JP2005135109A - Data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a data transfer end interrupt in proper timing during data transfer in a bus system having a plurality of buses. <P>SOLUTION: In the bus system having a plurality of buses 4, 8, and 11, DMA transfer between bus masters 2, 3, 6, and 9 and a memory 12 is performed by using a communication packet 20. The bus master 2, 3, 6, or 9 serving as the transmission source of the communication packet 20 decreases a number set in the communication packet 20 when the communication packet 20 passes through the bus masters 2, 3, 6, and 9, bridges 7 and 10 and a memory 12. When the number set in the communication packet 20 reaches 0, a notice of the end of the transfer is given to the bus masters 2, 3, 6, or 9 serving as the transmission source of the communication packet 20. Consequently, the bus master 2, 3, 6, or 9 generates a transfer end interrupt to a CPU 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transfer system for transferring data between devices connected to a bus in a bus system having a plurality of buses.

  Conventionally, in a bus system having a plurality of buses, when data is transferred from a bus master to a memory or the like, is a data transfer end interrupt issued to the CPU when data is received on a bus directly connected to the bus master? Alternatively, when the memory, which is the final data transfer destination, accepts data, the end of data transfer is notified from the memory, etc. to the bus master, and a data transfer end interrupt is issued from the bus master to the CPU. .

For example, Patent Document 1 below discloses a FIFO (First In First Out) memory for temporarily storing data in order to prevent a burst transfer end interrupt signal generation circuit from erroneously giving a burst transfer end interrupt signal to a processor. The memory empty signal is ON, the data transfer end signal indicating that the DMA (Direct Memory Access) control circuit indicates the end of burst transfer is ON, and the write signal given to the FIFO memory by the DMA control circuit is set for a certain time by the delay of the timer. A burst transfer end interrupt signal generation circuit is described that outputs an interrupt signal from an AND circuit to a processor when the three conditions that a timer output signal indicating nonexistence is turned on are satisfied.
Japanese Patent Laid-Open No. 5-28093

  However, in the above background art, when an interrupt occurs before data is actually transferred to the data transfer destination, and other bus masters access the same area, the desired data is still written. It can happen that there is no. In the latter background art, an interrupt is not yet notified even when a stage in which racing does not occur for data transfer, so that the start of data transfer from another bus master is delayed more than necessary. Further, the above patent document does not describe the case of data transfer over a plurality of buses.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transfer system capable of efficiently transferring data by interrupting the end of data transfer at a suitable timing.

  A data transfer system according to claim 1 is a data transfer system that is connected by a bus connection device and transfers data between a main transfer device and a slave transfer device via a plurality of buses, and is connected to one of the plurality of buses. Is connected to the bus to which the central processing unit is connected in the path when the main transfer device transfers data from the main transfer device to the slave transfer device. Transmission means for transmitting bus connection number information based on the number of bus connection devices located between the bus connection device on the slave transfer device side and the master transfer device to the slave transfer device, When the bus connection device receives the bus connection number information, the bus connection device changes the bus connection number information based on the fact that the bus connection number information has passed through the bus connection device; and the bus connection device If the predetermined value indicating that the device is a bus connection device on the slave transfer device side and the bus connection number information match, a notification that the data transfer has been completed is sent to the main transfer device. And a notification means for transmitting.

  A data transfer system according to a second aspect is the data transfer system according to the first aspect, wherein the changing unit lowers the bus connection number information by 1 when the bus connection number information is received. .

  The data transfer system according to claim 3 is the data transfer system according to claim 1 or 2, wherein the changing unit acquires the bus use right when transmitting the bus connection number information. The number information is decremented by one.

  The data transfer system according to claim 4 is the data transfer system according to claims 1 to 3, wherein the main transfer device generates an interrupt to the central processing unit when the notification is received from the bus connection device. It is further characterized by further comprising an interrupting means.

  The data transfer system according to claim 5 is the data transfer system according to claims 1 to 4, wherein all the bus connection devices connected to the plurality of buses and an end notification connected to the main transfer device Further comprising an intermediary device, wherein the transmission means transmits identification information for specifying the main transmission device, and the end notification mediation device receives the identification information together with the notification from the notification means; And a notification transmission unit configured to transmit the notification to the main transfer device indicated by the identification information.

  According to the first aspect of the present invention, in the main transfer device, when data transfer is performed between the main transfer device and the slave transfer device, data transfer performed between the central processing unit and the slave transfer device; The bus connection located between the bus connection device and the main transfer device as information for the bus connection device to recognize that the transmission from the main transfer device has arrived at the bus connection device in a position where no conflict occurs. Bus connection number information based on the number of devices is transmitted to the slave transfer device by the transmission means, and in the bus connection device, the bus connection number information is changed based on having passed through the bus connection device by the changing means, When the bus connection number information matches a predetermined value indicating that the bus connection device is a bus connection device at a position where the contention does not occur, data transfer is performed by the notification means. Since the notification of completion is transmitted to the main transfer device, when the bus connection device receives the bus connection number information, the data transfer performed between the main transfer device and the slave transfer device has already been performed by the central processing unit. If there is no conflict between the data transfer and the data transfer performed by the slave transfer device, the transfer end notification can be performed, and the transfer end notification is prevented from being performed at the time when the conflict can still occur. In addition, it is possible to prevent the transfer completion notification from being performed until the data transfer is completed even though the data transfer conflict does not occur. As a result, a transfer end notification is sent to the main transfer device at a suitable timing. As a result, a data transfer end interrupt to the central processing unit can be performed at a suitable timing, and the efficiency of data transfer can be improved.

  According to the second aspect of the present invention, when the bus connection number information is received, it is decremented by one by the changing means. Therefore, in the bus connection device in a position where the contention does not occur, a predetermined value such as 0 is set in advance. By setting the bus connection number information in the main transfer device so as to become a value, the bus connection device compares the coincidence with the predetermined value in the bus connection device, so that the bus connection device is in a position where the contention does not occur. It can be determined whether or not it is a connection device.

  According to a third aspect of the present invention, the bus connection number information is decremented by one when the right to use the bus related to transmission of this information is acquired, so that the bus connection at a position where the contention does not occur. By setting the bus connection number information in the main transfer device so as to have a predetermined value such as 0 in the device, the bus connection device compares the coincidence with the predetermined value in the bus connection device. It is possible to determine whether or not the bus connection device is in a position where the contention does not occur.

  According to the fourth aspect of the present invention, when the main transfer device receives notification from the bus connection device that the data transfer has been completed, the interrupt means causes the central processing device to generate an interrupt. A data transfer end interrupt can be performed at a suitable timing, and the central processing unit can reduce waiting for the data transfer end more than necessary, thereby improving the efficiency of data transfer.

  According to the fifth aspect of the present invention, identification information for identifying the main transfer device is transmitted by the transmission means in the main transfer device, and the identification information is transmitted to the end notification mediating device by the notification means in the slave transfer device. Since the identification information is received by the notification receiving means in the end notification mediating apparatus, and the notification is transmitted to the main transfer apparatus indicated by the identification information by the notification transmitting means, the main transfer is performed from the slave transfer apparatus without using the bus. The notification can be made to the apparatus, and the notification can be made quickly.

  Hereinafter, a data transfer system in a bus system having a plurality of buses according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of the configuration of a bus system according to an embodiment of the present invention. Buses 4, 8, and 11 are three buses in this system. The configuration of signal lines in each bus need not be the same. The bus master 2 and the bus master 3 have a DMA (Direct Memory Access) function to the memory 12 and are connected to the bus 4. The bus master 6 has a DMA function to the memory 12 and is connected to the bus 8. The bus master 9 has a DMA function to the memory 12 and is connected to the bus 11. The bridge 7 is a circuit that connects the bus 4 and the bus 8 and converts and transfers signals on the bus between the two buses. The bridge 10 is a circuit that connects the bus 8 and the bus 11.

  A CPU (Central Processing Unit) 5 is connected to the bus 8 and controls the operation of the entire system. The memory 12 is also accessed. The memory 12 is, for example, a RAM (Random Access Memory) connected to the bus 11. The decoder 1 is connected to all devices (bus masters 2, 3, 6, 9, bridges 7, 10, memory 12) other than the CPU 5, and notifies the end of data transfer in the DMA received from the bridges 7, 10 or memory 12 (hereinafter, The bus master identification information (for example, a number assigned to the bus master) is decoded and notified to the bus master performing the DMA. The bus master is a device that can obtain the right to use the bus. For example, in an image forming apparatus such as a copying machine, a data compression / decompression apparatus is the bus master. The bus master obtains the right to use the bus and designates a target device (for example, the memory 12) to perform data transfer. Transferring data from the bus master to the target device (memory) is called writing, and transferring data from the target device (memory) to the bus master is called reading.

  FIG. 2 is a diagram showing a packet for data transfer used for DMA transfer by the bus master. FIG. 2A shows a basic format. In FIG. 2A, an ID area 21 is an area for storing information for identifying the bus master of the transmission source, and stores numbers assigned to each bus master, for example. The count information area 22 is count information for counting when the device that transfers this packet acquires the right to use the bus and when the device receives this packet, thereby notifying the transmission source bus master of the transfer end. Get time. The R / W information area 23 is used to transfer data from the bus master to the memory or the like (hereinafter referred to as “write”), or to transfer data from the memory or the like to the bus master (hereinafter referred to as “read”). ) Is an area for storing information indicating the type of one used. This type is represented by R (read) or W (write), for example. The address area 24 is an area for storing a write destination / read destination address of data transferred by the packet. The data area 25 is an area for storing data to be transferred or the address of the transmission source bus master. In the present embodiment, the data area 25 has a predetermined size and a fixed length.

  FIG. 2B is a diagram showing the contents of information stored in a packet in the case of writing. The ID area 21 stores identification information of the transmission source bus master. The count information area 22 stores the count information described above. However, if the transfer data is divided into a plurality of times and transmitted, other than the last packet, a sufficiently large number that does not become 0 even if the packet arrives at the memory or the like is stored as the count information. In the R / W information area 23, “W” is stored. The address area 24 stores the start address of a memory area to which data to be stored in the data area 25 is written. The data area 25 stores data to be transferred (data to be written to a memory or the like). In the case of writing, only the packet is transmitted from the bus master to the memory, and no packet is returned from the memory to the bus master.

  FIG. 2C is a diagram showing the contents of information stored in a transmission (when transmitting from the bus master to the memory) packet (read request packet) in the case of reading. The ID area 21 stores identification information of the transmission source bus master. The count information area 22 stores the count information described above. “R” is stored in the R / W information area 23. The address area 24 stores the start address of the memory area to be read. The address of the bus master that is the transmission source of the packet is stored in the first half portion 25a of the data area 25. In the latter half portion 25b of the data area 25, the size of data to be read is stored.

  FIG. 2D is a diagram showing the contents of information stored in a reply (when transmitting from the memory to the bus master) packet (read packet) in the case of reading. The ID area 21 stores the identification information of the transmission source bus master stored in the ID area 21 of the read request packet. In the count information area 22, a sufficiently large number that does not become zero even when a packet arrives at the bus master is stored as count information. “R” is stored in the R / W information area 23. The address area 24 stores the start address of a memory area from which data stored in the data area 25 is read. The data area 25 stores data to be transferred (data read from the memory).

  FIG. 3 is a block diagram showing the configuration of the functions of the bus masters 2, 3, 6, and 9. The bus masters 2, 3, 6, and 9 are a data transfer control unit 31, a packet creation unit 32, a packet transmission unit 33, a counter decrement unit 34, a packet reception unit 35, a data reception unit 36, a transfer end notification reception unit 37, and an interrupt transmission. The unit 38 is provided.

  The data transfer control unit 31 determines whether or not the bus master performs data transfer. In addition, when the transfer data is divided into a plurality of packets and transmitted, the control is performed. The packet creation unit 32 creates the write packet shown in FIG. 2B or the read request packet shown in FIG. 2C according to the type of data transfer (write or read). In the ID area 21, for example, a number assigned to the bus master is stored. In the count information area 22, a count value (number) determined for each target device, which is held in advance by the bus master, is stored as count information. This count value is determined by the configuration of the bus system (for example, the number of bridges to be passed from the bus master to the target device and the connection position of the CPU, etc.). When the bus system is configured, the bus master corresponds to each memory. Stored. R or W is set in the R / W information area 23 depending on whether the data transfer is a read or a write. The address area 24 stores a memory address for writing data to be stored in the data area 25 in the case of writing, and a memory address in which data to be read is stored in the case of reading. The data area 25 stores transfer data in the case of writing, and the address of the bus master and the size of data to be read in the case of reading.

  The packet transmission unit 33 transmits the packet created by the packet creation unit 32. When transmitting a packet, the packet transmission unit 33 first acquires the right to use the bus to which the bus master is connected. When the right to use the bus is acquired, the packet transmission unit 33 sends the count information described in the packet to the counter decrement unit 34. When this is done, the address of the target device (memory, etc.) recognized by the bus master is output to the address bus, and the packet is transmitted to the data bus in multiple times to transmit the packet. Do.

  The counter decrement unit 34 performs a process of decrementing the packet count information by one according to an instruction from the packet transmission unit 33. The packet receiving unit 35 receives the data by receiving the data constituting the packet via the bus to which the bus master is connected, and storing the data to construct the packet. The data receiving unit 36 takes out the transfer data from the data area of the received packet and passes it to a functional unit (not shown) that uses this data.

  The transfer end notification receiving unit 37 receives the transfer end notification transmitted from the memory 12 via the decoder 1. When the transfer end notification receiving unit 37 receives the transfer end notification, the transfer end notification receiving unit 37 notifies the interrupt transmitting unit 38 to that effect. The interrupt transmission unit 38 transmits an interrupt to the CPU 5 when notified from the transfer end notification receiving unit 37 that the transfer end notification has been received.

  FIG. 4 is a block diagram showing a configuration of functions provided in the bridges 7 and 10. The bridges 7 and 10 include a packet reception unit 41, a counter decrement unit 42, a transfer end notification unit 43, and a packet transmission unit 44.

  The packet receiver 41 receives a packet transmitted from a bus master or the like in the same manner as the packet receiver 35. The packet receiving unit 41 instructs the counter decrement unit 42 to decrement the received packet count information by one. The counter decrementing unit 42 performs a process of decrementing the packet count information by one according to an instruction from the packet receiving unit 41 or the packet transmitting unit 44. The transfer end notification unit 43 checks the packet count information 22 and, if the count information 22 is 0, transmits the ID information 21 described in the packet to the decoder 1 as a transfer end notification.

  The packet transmission unit 44 transfers the received packet. When transmitting a packet, the packet transmission unit 44 first acquires the right to use the bus not receiving the packet among the buses to which the bridge is connected. When the right to use the bus is acquired, the counter decrement unit 42 Is instructed to decrement the count information 22 described in the packet by one, and after this is done, the address bus information on the packet receiving side is output to the address bus on the transmitting side, and the packet is sent to the data bus multiple times. Packets are transmitted by outputting separately.

  FIG. 5 is a block diagram showing a configuration of functions provided in the memory 12. The memory 12 includes a packet receiver 51, a counter decrement unit 52, a transfer end notification unit 53, a data read / write unit 54, a packet creation unit 55, a packet transmission unit 56, a data transfer control unit 57, and a data storage unit 58.

  The packet receiving unit 51 receives packets transmitted from the bus master or the like in the same manner as the packet receiving units 35 and 41. The packet receiving unit 51 instructs the counter decrement unit 52 to decrement the received packet count information 22 by one. The counter decrement unit 52 performs a process of decrementing the packet count information by 1 according to an instruction from the packet reception unit 51 or the packet transmission unit 56. The transfer end notification unit 53 checks the packet count information 22 and, if the count information is 0, transmits the ID information 21 described in the packet to the decoder 1 as a transfer end notification.

  When the data read / write unit 54 receives a write packet (FIG. 2B), it extracts the transfer data from the data area 25 of the packet and the write address from the address area 24, and transfers the transfer data to the write address of the data storage unit 58. Is stored. When a read request packet (FIG. 2C) is received, the read address is extracted from the address area 24 and the size is extracted from the data area 25b, and the data for the size is transferred from the address in the data storage section 58 to the data transfer control section 57. In accordance with the instruction, the data amount stored in one packet is read out and transferred to the packet creation unit 55.

  The packet creation unit 55 creates a read packet (FIG. 2D) when a read request packet is received. The contents of the received packet are copied to the ID area 21. In the count information area 22, a sufficiently large number that does not become 0 even when a packet arrives at the bus master is entered (this is because the bus master does not need to issue a transfer end notification when the packet arrives). R is entered in the R / W area 23. In the address area 24, the head address of data stored in the data area is entered. In the data area 25, the data read from the data storage unit 58 and transferred from the data read / write unit 54 is stored.

  The packet transmission unit 56 transmits the packet created by the packet creation unit 55. The packet transmission unit 56 acquires a return address from the data area 25a of the received packet. When transmitting a packet, the packet transmission unit 56 first acquires the right to use the bus to which the bus master is connected. When the right to use the bus is acquired, the packet transmission unit 56 sends the count information 22 described in the packet to the counter decrement unit 52. After this is instructed, the packet is transmitted by outputting the acquired address to the address bus and outputting the packet in multiple times to the data bus.

  The data transfer control unit 57 performs control when the read data is transmitted by being divided into a plurality of packets. The data storage unit 58 stores data as a memory.

  FIG. 6 is a block diagram illustrating a configuration of functions included in the decoder 1. The decoder 1 includes a transfer end notification destination analysis unit 61 and a transfer end notification transmission unit 62. The transfer end notification destination analysis unit 61 selects a bus master corresponding to the ID information 21 based on the ID information 21 received from the memory. The transfer end notification transmission unit 62 transmits a transfer end notification to the bus master selected by the transfer end notification destination analysis unit 61.

  FIG. 7 is a flowchart showing a flow of processing relating to data transfer of the bus masters 2, 3, 6, and 9. The flow of processing related to data transfer of the bus master will be described below.

  In step S1, the data transfer control unit 31 determines whether or not to perform data transfer. If data transfer is to be performed (YES in step S1), the process proceeds to step S3. In step S3, the packet creation unit 32 creates a packet to be transmitted in accordance with the purpose such as R / W. In step S5, the packet transmission unit 33 repeats acquisition of the right to use until the right to use the bus to which the bus master is connected is obtained (NO in step S5). If the right to use the bus is acquired (YES in step S5), the process proceeds to step S7. In step S7, the packet transmission unit 33 instructs the counter decrement unit 34 to decrement the packet count information by 1, and the counter decrement unit 34 executes this. In step S9, the packet transmission unit 33 outputs the address of the target device (for example, the memory 12) to the address bus, divides the packet into a plurality of times, and outputs the packet to the data bus.

  In step S11, the data transfer control unit 31 determines whether or not all transfer data has been transmitted. If there is still transfer data to be transmitted (YES in step S11), the process returns to step S3, and the remaining transfer data is transferred. Send. If all the transfer data has been transmitted (NO in step S11), the process proceeds to step S13. In step S13, the data transmission unit 33 releases the bus. When it is determined that data transfer is not performed in the branch of step S1 (NO in step S1) and when the process of step S13 is completed, the process proceeds to step S15.

  In step S15, the packet receiver 35 checks whether or not a packet has been received. If a packet has been received (YES in step S15), the process proceeds to step S17. In step S17, the data receiving unit 36 takes out the address stored in the address area 24 of the packet and the data stored in the data area 25, and uses this data as read data from the address. If no packet is received in the branch of step S15 (NO in step S15) and if the process of step S17 is completed, the process proceeds to step S19.

  In step S19, the transfer end notification receiving unit 37 checks whether or not a transfer end notification is received from the decoder 1, and if a transfer end notification is received (YES in step S19), the process proceeds to step S21. In step S21, the interrupt transmission unit 38 issues a transfer end interrupt to the CPU 5. When the transfer end notification is not received in the branch of step S19 (NO in step S19) and when the process of step S21 is completed, the process returns to step S1 and the processes from step S1 are repeated.

  FIG. 8 is a flowchart showing the flow of processing of the bridges 7 and 10. The processing flow of the bridge will be described below.

  In step S31, the packet receiver 41 checks whether or not a packet is received until a packet is received (NO in step S31). If a packet has been received (YES in step S31), the process proceeds to step S33. In step S33, the packet reception unit 41 instructs the counter decrement unit 42 to decrement the packet count information 22 by one, and the counter decrement unit 42 executes this. In step S35, the transfer end notification unit 43 checks whether or not the packet count information 22 is zero. If the count information 22 is 0 (YES in step S35), the process proceeds to step S37. In step S37, the transfer end notification unit 43 transmits the packet ID information 21 to the decoder 1 as a transfer end notification.

  When the count information 22 is not 0 in the branch of step S35 (NO in step S35) and when the process of step S37 is completed, the process proceeds to step S39. In step S39, the packet transmitter 44 tries to acquire the right to use until the right to use the bus on the side opposite to the side that received the packet is acquired (NO in step S39). If the right to use the bus is acquired (YES in step S39), the process proceeds to step S41. In step S41, the packet transmission unit 44 instructs the counter decrement unit 42 to decrement the packet count information 22 by one, and the counter decrement unit 42 executes this. In step S43, the packet transmission unit 44 outputs the address of the target device (for example, the memory 12) to the address bus, divides the packet into a plurality of times, and outputs the packet to the data bus. In step S45, the packet transmission unit 44 releases the bus.

  FIG. 9 is a flowchart showing a flow of processing relating to data transfer in the memory 12. The flow of processing related to data transfer in the memory 12 will be described below.

  In step S51, the packet receiver 51 checks whether or not a packet has been received until a packet is received (NO in step S51). If a packet has been received (YES in step S51), the process proceeds to step S53. In step S53, the packet receiving unit 51 instructs the counter decrement unit 52 to decrement the packet count information 22 by one, and the counter decrement unit 52 executes this. In step S55, the transfer end notification unit 53 checks whether or not the packet count information 22 is zero. If the count information 22 is 0 (YES in step S55), the process proceeds to step S57. In step 57, the transfer end notification unit 53 transmits the packet ID information 21 to the decoder 1 as a transfer end notification.

  When the count information 22 is not 0 in the branch of step S55 (NO in step S55) and when the process of step S57 is completed, the process proceeds to step S59. In step S59, the data read / write unit 54 checks the R / W information 23 of the packet, and if it is W (YES in step S59), the process proceeds to step S61. In step S 61, the data read / write unit 54 extracts the address from the address area 24 of the packet and the transfer data from the data area 25, and writes the transfer data to the address in the data storage unit 58.

  If the R / W information is R in the branch of step S59 (NO in step S59), the process proceeds to step S63. In step S63, the packet transmission unit 56 takes out the packet return address (the address of the bus master that transmitted the packet) from the packet data area 25a. In step S65, the data read / write unit 54 extracts the size information of the data to be read from 25b after the read address of the memory from the packet address area 24 and the packet return address of the data area. In step S <b> 67, the data read / write unit 54 reads the data corresponding to the size or the amount transferred by the packet from the read address according to the instruction of the data transfer control unit 57 and passes the data to the packet creation unit 55.

  In step S69, the packet creation unit 55 creates a reply packet (FIG. 2 (d)). In step S71, the packet transmission unit 56 tries to acquire the usage right until it acquires the bus usage right (NO in step S71). If the right to use the bus is acquired (YES in step S71), the process proceeds to step S73. In step S73, the packet transmission unit 56 instructs the counter decrement unit 52 to decrement the packet count information 22 by one, and the counter decrement unit 52 executes this. In step S75, the packet transmission unit 56 outputs the return address 25a extracted from the received packet to the address bus, and outputs the packet to the data bus in a plurality of times.

  In step S77, the data transfer control unit 57 determines whether or not all transfer data has been transmitted. If there is still transfer data to be transmitted (YES in step S77), the process returns to step S67, and the remaining transfer data is transferred. Send. If all the transfer data has been transmitted (NO in step S77), the process proceeds to step S79. In step S79, the data transmission unit 33 releases the bus.

  FIG. 10 is a flowchart showing the flow of processing of the decoder 1. The processing flow of the decoder 1 will be described below.

  In step S81, the transfer end notification destination analysis unit 61 waits until receiving ID information 21, for example, an identification number, for identifying the bus master as a transfer end notification (NO in step S81). If the ID information is received (YES in step S81), the process proceeds to step S83. In step S83, the transfer end notification destination analysis unit 61 decodes the received ID information and selects a signal line to the corresponding bus master. In step S85, the transfer end notification transmitter 62 transmits a transfer end notification to the corresponding bus master by turning on the selected signal line.

  FIG. 11 is a diagram showing the flow of processing when the bus master 3 writes to the memory 12. In this flowchart, the processes of the same device are arranged in a vertical column. This flow will be described below.

  In step S91, the bus master 3 creates a packet in which 3 is stored in the ID information 21 and 4 is stored in the count information 22, and the right to use the bus 4 is acquired. In step S93, the bus master 3 decrements the count information 22 by one. In step S 95, the bus master 3 outputs the packet to the bus 4 and transmits it to the memory 12. In step S97, the bridge 7 receives the packet. In step S99, the bridge 7 decrements the count information 22 by 1. In step S101, the bridge 7 acquires the right to use the bus 8. In step S103, the bridge 7 decrements the count information 22 by 1. In step S <b> 105, the bridge 7 outputs the packet to the bus 8 and transmits it to the memory 12.

  In step S107, the bridge 10 receives the packet. In step S109, the bridge 10 decrements the count information 22 by 1 to zero. In step S111, the bridge 10 transmits the number “3” stored in the ID information 21 to the decoder 1 as a transfer end notification. In step S113, the bridge 10 acquires the right to use the bus 11. In step S115, the bridge 10 decrements the count information 22 by 1 to “−1”. In step S117, the bridge 10 outputs the packet to the bus 11 and transmits it to the memory 12. In step S119, the memory 12 receives the packet and writes the transfer data in the packet to the designated address.

  On the other hand, in step S121, the decoder 1 receives the number “3” from the bridge 10 as a transfer end notification. In step S123, the decoder 1 decodes “3” and turns on the signal line to the bus master 3, thereby giving a transfer end notification. In step S125, the bus master 3 receives a transfer end notification. In step S127, the bus master 3 generates a transfer end interrupt to the CPU 5.

  FIG. 12 is a diagram showing the flow of processing when the bus master 9 writes to the memory 12. This flow will be described below.

  In step S131, the bus master 9 creates a packet in which 9 is stored in the ID information 21 and 2 is stored in the count information 22, and the right to use the bus 11 is acquired. In step S133, the bus master 9 decrements the count information 22 by 1. In step S <b> 135, the bus master 9 outputs the packet to the bus 11 and transmits it to the memory 12. In step S137, the memory 12 receives the packet. In step S139, the memory 12 decrements the count information 22 by one. In step S141, the memory 12 transmits the number “9” stored in the ID information 21 to the decoder 1 as a transfer end notification. On the other hand, in step S143, the decoder 1 receives the number “9” from the memory 12 as a transfer end notification. In step S145, the decoder 1 performs the transfer end notification by decoding “9” and turning on the signal line to the bus master 9. In step S147, the bus master 9 receives a transfer end notification. In step S149, the bus master 9 generates a transfer end interrupt to the CPU 5.

  As described above, according to the present embodiment, for example, in the DMA transfer (for example, write) performed by the bus master 3 to the memory 12, the transfer end notification is sent via the decoder when the packet transmitted from the bus master 3 arrives at the bridge 10. The bus master 3 that has received the request interrupts the CPU 5. For example, in the DMA transfer (for example, write) performed by the bus master 9 to the memory 12, when the packet transmitted from the bus master 9 arrives at the memory 12, a transfer end notification is transmitted to the bus master 9 via the decoder. The bus master 9 having received this interrupts the CPU 5. As described above, the transfer end notification to the bus master related to data transfer is transmitted when contention for the data transfer does not occur (when the packet arrives at a timing at which the data transfer from the CPU is not overtaken). It is possible to prevent the transfer end notification from being performed at the time when the conflict can occur, and to prevent the transfer end notification from being performed until the data transfer is completed even though the data transfer conflict does not occur. be able to. As a result, a data transfer end interrupt can be performed at a suitable timing, and the efficiency of data transfer can be improved.

  Note that the timing for transmitting the transfer end notification in the case of reading is the same as that in the case of writing. This is because if the read request packet is not overtaken by another packet, even if a write packet to the same area comes later, the write packet that has read the data before being written can be returned. When data related to DMA transfer is divided into a plurality of packets and transmitted, the packet arrives at the destination device in the count information 22 of the packet other than the last packet (packet storing the end of the transfer data). A sufficiently large number that does not become zero is stored. This is because the transfer end notification is not performed even if a packet other than the final packet arrives at the destination device.

  In the present embodiment, the count information 22 is decremented by 1 when the device that transmits the packet acquires the right to use the bus and when the device receives the packet. Only when a packet is received, the count information 22 may be decremented by one.

  In this embodiment, the data area 25 has a fixed length, but may have a variable length. In this case, a data size area may be provided in front of the data area to store the size of the data stored in the data area.

It is a block diagram which shows the structure of the bus system in one Embodiment of this invention. FIG. 4 is a diagram illustrating an example of a packet in an embodiment of the present invention, where (a) is a basic format, (b) is a write packet, (c) is a read request packet, and (d) is a read packet. It is a block diagram which shows the function structure of the bus master in one Embodiment of this invention. It is a block diagram which shows the function structure of the bridge | bridging in one Embodiment of this invention. It is a block diagram which shows the function structure of the memory in one Embodiment of this invention. It is a block diagram which shows the function structure of the decoder in one Embodiment of this invention. It is a flowchart which shows the flow of the process which concerns on the data transfer of a bus master. It is a flowchart which shows the flow of a process of a bridge | bridging. It is a flowchart which shows the flow of the process which concerns on the data transfer of a memory. It is a flowchart which shows the flow of a process of a decoder. 6 is a flowchart showing a flow of processing when data is written from the bus master 3 to the memory 12. 6 is a flowchart showing a flow of processing when data is written from the bus master 9 to the memory 12.

Explanation of symbols

1 Decoder (end notification mediation device)
2, 3, 6, 9 Bus master (main transfer device)
4,8,11 Bus 5 CPU (Central processing unit)
7,10 bridge (bus connection device)
12 Memory (secondary transfer device)
32 packet generator 33 packet transmitter (transmission means)
35 Packet receiver 38 Interrupt transmitter (interrupt)
42 Counter lowering section (changing means)
43 Transfer end notification section (notification means)
61 Transfer end notification destination analysis unit (notification receiving means)
62 Transfer end notification transmitter (notification transmission means)

Claims (5)

A data transfer system for transferring data between a main transfer device and a slave transfer device via a plurality of buses connected by a bus connection device,
A central processing unit is connected to one of the plurality of buses,
The main transfer device is a device on the slave transfer device side of the bus connection devices connected to the bus to which the central processing unit is connected in a path when transfer is performed from the main transfer device to the slave transfer device. Transmission means for transmitting to the slave transfer device bus connection number information based on the number of the bus connection devices located between the bus connection device and the master transfer device;
The bus connection device changes the bus connection number information based on the fact that the bus connection number information has passed through the bus connection device when the bus connection number information is received; and
If the predetermined value indicating that the bus connection device is a bus connection device on the slave transfer device side matches the bus connection number information, a notification that the data transfer has been completed is sent to the main transfer. A data transfer system comprising: notification means for transmitting to a device.   2. The data transfer system according to claim 1, wherein the changing unit lowers the bus connection number information by 1 when the bus connection number information is received.   3. The data transfer system according to claim 1, wherein the changing unit decrements the bus connection number information by 1 when a bus use right related to transmission of the bus connection number information is acquired.   4. The data transfer system according to claim 1, wherein the main transfer device further includes an interrupt unit that generates an interrupt to the central processing unit when the notification is received from the bus connection device. An end notification intermediary device connected to all the bus connection devices connected to the plurality of buses and the main transfer device;
The transmission means transmits identification information for specifying the main transmission device;
The end notification mediating apparatus includes a notification receiving unit that receives the identification information together with the notification from the notification unit;
The data transfer system according to claim 1, further comprising notification transmission means for transmitting the notification to the main transfer device indicated by the identification information.

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