JP2005130286A - Video signal processing method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily perform a detection of a video signal converted from film and a conversion processing when the video signal is film signal. <P>SOLUTION: This video signal processing method comprises: a first selection processing for obtaining signals of four horizontal lines of a first, a second, a third and a fourth mutually delayed by every horizontal scanning period from the inputted video signal and selectively replacing the signal of the fourth horizontal line with the signal of the second horizontal line; a second selection processing for selectively replacing the signal of the second horizontal line with the signal of the fourth horizontal line; a timing matching processing for matching the signals of the four horizontal lines each other; a determination processing for comparing the signals of the four horizontal lines matching in the timing and determining whether or not a fixed pattern corresponding to the film signal is detected; and a control processing for controlling the first selection processing and the second selection processing based on the determination processing. The signals of respective horizontal lines matching in the timings are defined as input for performing a predetermined signal processing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a video signal processing method and apparatus, for example, and relates to a technique for performing video processing such as double speed conversion on the video signal when there is a video signal generated from a film signal, for example.

  Conventionally, when a video recorded on a film of 24 frames per second (that is, a video of 24 Hz) is a video signal with a field frequency of 60 Hz, so-called 3-2 pull-down processing is performed, and when a video signal of 50 Hz is obtained, A so-called 2-2 pull-down process is performed. The 3-2 pull-down process and the 2-2 pull-down process convert the field frequency of the video recorded on the film by adjusting the number of times the same field is repeated.

  By the way, in recent years, when a video signal is received and processed by a television receiver or the like, the field frequency is doubled, or double-speed conversion is performed to double the number of horizontal lines in one field, and so on. There are many cases where images are displayed. When this double speed conversion process is performed, a converted video signal of one field may be generated from video signals of a plurality of adjacent fields. Here, in the case of a video signal obtained by converting the above-mentioned film video, if a field created from the video of different frames is mixed and a video signal of one field after conversion is generated by the double speed conversion processing, it is generated. The field image will be difficult to see. For this reason, if the input video signal of the double speed conversion process is a video signal obtained by converting a film video, and if it is a film video, the double speed conversion is performed from the field made from the same frame. There is a need to.

  FIG. 10 is a diagram showing a configuration for detecting a conventional film image subjected to 3-2 pull-down processing. The 3-2 pull-down process is a process applied to a video signal having a field frequency of 60 Hz. The video signal input to the input terminal 1 is delayed by one field period by the first field memory 2, and further, the delayed signal is delayed by one field period by the second field memory 3, and the current signal (Cur) A signal of three field periods of a signal (1FD) one field before and a signal (2FD) two fields before is simultaneously obtained for the signal and input to the signal processing circuit 5 via the film detection circuit 4. In the signal processing circuit 5, double-speed conversion processing is performed using video signals of three field periods input simultaneously. When film image detection processing is not necessary, signals in three field periods may be input to the signal processing circuit 5 as they are. However, when the input video signal is a film video signal, the first switching is performed. The field period is switched by the switch 4b and the second switch 4c.

  That is, the film detection circuit 4 supplies the current signal (Cur) and the signal (2FD) two fields before to the film determination unit 4a, and determines whether both signals having a difference of one frame are the same signal. Then, from the pattern of the determination result, it is determined whether or not the video signal has been subjected to 3-2 pull-down processing (that is, whether or not it is a film video). Based on the determination result, switching of the two change-over switches 4b and 4c in the film detection circuit 4 is controlled. The second changeover switch 4c is a switch for changing over the current signal (Cur) and the signal (2FD) two fields before. The first changeover switch 4b is a switch for changing over the current signal (Cur) and the output of the second changeover switch 4c. Then, the signal selected by the first changeover switch 4 b is supplied as an input of the current signal (Cur) of the signal processing circuit 5. As for the input of the signal (1FD) before one field period of the signal processing circuit 5, the output of the first field memory 2 is supplied as it is. For the input of the signal (2FD) before the two-field period of the signal processing circuit 5, the signal selected by the second changeover switch 4c is supplied.

  An example of the operation of the film detection circuit 4 is shown in the table of FIG. In this example, the number of fields is counted in a 5-field cycle in the film determination unit 4a, and different pixel amounts are detected based on the difference between frames of the current signal (Cur) and the signal (2FD) two fields before. Depending on the amount, the film determination is performed depending on whether or not a pattern with a difference determination of 11011 is detected. In FIG. 11, what is shown before SW is the supply timing of a signal obtained by delaying the video signal input to the input terminal 1 by the first and second field memories 2 and 3, and is a film video. In this case, since it is a 3-2 pull-down signal, field A, field A ′, field A, field B, field B ′, field C, field C ′, field C, field D, field D ′ are provided for each field. ,... Are repeated alternately in the 3 field period and the 2 field period. Note that field A and field A ′ indicate an odd field and an even field of video having the same contents.

  Here, when the 3-2 pull-down signal is detected in this way, a field switching signal is generated as shown in FIG. 11, and switching processing is performed in a five-field cycle by the first and second switching switches 4b and 4c. Thus, the signal shown as after SW is obtained by replacing the signal shown as before SW, and the video of the field period with the same contents is obtained at any timing. That is, for example, at the timing when the current signal (Cur) of the second field from the left side of FIG. 11 is field A ′, the signal (2FD) before two fields is the field Z before that, but the signal shown as after SW , The signal (2FD) two fields before is also replaced with the field A ′, and the three fields input to the signal processing circuit 5 become the field A or the field A ′ having the same contents. Similarly, in the other field periods, the three fields are aligned with the same content field.

  By switching in this way, when the input video signal is a film video, the signals of the three fields input to the signal processing circuit 5 are aligned to the same content, and the same even if double speed conversion is performed. Double-speed conversion is performed only from the field made from frames, and optimal signal processing is performed.

  FIG. 12 is a diagram showing a configuration for detecting a conventional film image subjected to 2-2 pull-down processing. The 2-2 pull-down process is a process applied to a video signal having a field frequency of 50 Hz. The video signal input to the input terminal 1 is delayed by one field period by the first field memory 2, and further, the delayed signal is delayed by one field period by the second field memory 3, and the current signal (Cur) A signal processing circuit 5 that simultaneously obtains signals in three field periods, ie, a signal (1FD) one field before and a signal (2FD) two fields before, and performs double-speed conversion processing via the film detection circuit 6 To input. The configuration of the film detection circuit 6 is different from that in the 3-2 pull-down process.

  That is, the film detection circuit 6 supplies the current signal (Cur) and the previous signal (1FD) to the film determination unit 6a to determine whether or not both signals having a difference of one field are the same signal. From the pattern of the determination result, it is determined whether or not the video signal has been subjected to the 2-2 pull-down process (that is, whether or not it is a film video). Based on the determination result, switching of the two change-over switches 6b and 6c in the film detection circuit 6 is controlled. The second changeover switch 6c is a switch for changing over the current signal (Cur) and the signal (2FD) two fields before. The first changeover switch 6b is a switch for changing over the current signal (Cur) and the output of the second changeover switch 6c. Then, the signal selected by the first changeover switch 6 b is supplied as the input of the current signal (Cur) of the signal processing circuit 5. As for the input of the signal (1FD) before one field period of the signal processing circuit 5, the output of the first field memory 2 is supplied as it is. For the input of the signal (2FD) before the two-field period of the signal processing circuit 5, the signal selected by the second changeover switch 6c is supplied.

  An example of the operation of the film detection circuit 4 is shown in the table of FIG. In this example, the number of fields is counted in a 4-field cycle in the film determination unit 6a, and a different pixel amount is detected by the difference between fields of the current signal (Cur) and the previous signal (1FD). Film determination is performed depending on whether or not a pattern with a difference determination of 0101 is detected according to the amount. In FIG. 13, what is shown before SW shows the supply timing of a signal obtained by delaying the video signal input to the input terminal 1 by the first and second field memories 2 and 3, and is a film video. In this case, since it is a 2-2 pull-down signal, the same contents as field A, field A ′, field B, field B ′, field C, field C ′, field D, field D ′,. Are alternately repeated in two field periods. Note that field A and field A ′ indicate an odd field and an even field of video having the same contents.

  Here, when the 2-2 pull-down signal is detected in this manner, a field switching signal is generated as shown in FIG. 13, and switching processing is performed in a four-field cycle by the first and second switching switches 6b and 6c. Thus, the signal shown as after SW is obtained by replacing the signal shown as before SW, and the video of the field period with the same contents is obtained at any timing. That is, for example, at the timing when the current signal (Cur) of the second field from the left side of FIG. 13 is field A ′, the signal (2FD) two fields before is the field Z before it, but the signal shown as after SW , The signal (2FD) two fields before is also replaced with the field A ′, and the three fields input to the signal processing circuit 5 become the field A or the field A ′ having the same contents. Similarly, in the other field periods, the three fields are aligned with the same content field.

  By switching in this way, even when the 2-2 pull-down signal is applied to a video signal with a field frequency of 50 Hz, if the input video signal is a film video, it is input to the signal processing circuit 5. Even if the signals of the three fields are aligned to the same content and double-speed conversion is performed, the double-speed conversion is performed only from the field formed from the same frame, and optimal signal processing is performed.

Patent Document 1 discloses a circuit for detecting a pull-down signal.
JP 2003-189260 A

  By the way, as an actual input configuration to the signal processing circuit 5 shown in FIGS. 10 and 12, a relatively large capacity memory such as SDRAM is prepared in the previous stage, and a signal read from the memory is supplied to the signal processing circuit 5. May be configured to be input. That is, for example, as shown in FIG. 14, the video signal obtained at the input terminal 11 is written into a relatively large capacity RAM 12 for at least one field period, and necessary lines are stored from the RAM 12 for several lines. The data is read out from the memory 13 and read out line by line from the memory 13 under the control of the timing controller 14 and supplied to the signal processing circuit 5 through the buffers 15a, 15b and 15c. In general, the current signal (Cur), the signal one field before (1FD), and the signal two fields before (2FD) are used.

  If the input configuration of the signal processing circuit shown in FIG. 14 is prepared and the film detection circuit shown in FIG. 10 or 12 is simply connected, the control configuration for signal switching is complicated. In addition, there is a problem that the circuit for timing adjustment and its control configuration are also complicated, and there is a problem that it is not possible to easily perform film detection and process switching processing based on the detected signal state. .

  The present invention has been made in view of such a point, and an object thereof is to easily detect a film signal.

  The present invention obtains signals of the first horizontal line and the second, third and fourth horizontal lines delayed from the first horizontal line by one horizontal scanning period from the input video signal, A first selection process for selectively exchanging the signal of the fourth horizontal line with the signal of the second horizontal line; and a second selection process for selectively exchanging the signal of the second horizontal line with the signal of the fourth horizontal line. The selection processing, the timing matching processing for matching the timings of the signals of the four horizontal lines, and the signals of the four horizontal lines that match the timings are compared to determine whether or not a certain pattern corresponding to the film signal is detected. In order to perform predetermined signal processing on the signals of the four horizontal lines whose timings coincide with each other, the determination processing to be performed and the control processing to control the first selection processing and the second selection processing based on the determination processing of To the force.

  By doing in this way, it determines whether it is a film signal based on the signal after making the timing of the signal of four horizontal lines correspond, Based on the determination result, the 1st, 2nd selection process By performing the above control, it is possible to perform a replacement process when a film signal is input only by a process of matching the timings of the signals of the four horizontal lines and a selection process before or after that, and performs a predetermined signal process. When the video signal input process is performed, the replacement process for the film signal can be performed at the same time.

  According to the present invention, when video signal input processing for performing predetermined signal processing is performed, replacement processing in the case of a film signal can be performed at the same time, so that the circuit scale can be simplified.

  For example, by performing so-called double speed conversion processing for converting the number of horizontal lines or the field frequency based on the signals of three horizontal lines input in the input processing, the film signal required in the previous stage for double speed conversion can be obtained. There is an effect that the switching process can be performed with a simple process and configuration.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In this example, in a video signal processing apparatus such as a television receiver, the input video signal (or received by a built-in tuner) is subjected to video processing such as double speed conversion. Further, here, a video signal having a field frequency of about 60 Hz is handled as a video signal. When the supplied video signal is a video signal obtained by converting a film signal, the video signal is a so-called 3-2 pull-down signal. Shall.

  FIG. 1 is a block diagram illustrating a configuration example of this example. A video signal is supplied to the input terminal 101 from the outside (or received by a built-in tuner), and a video signal for at least one field is stored in a RAM (field memory) 102. The video signal stored in the RAM 102 is read out to the memory 103 and is output from the memory 103 one horizontal line at a time under the control of the timing controller 104. In this example, the signals of four adjacent horizontal lines are output from different signal lines. That is, the signal of four horizontal lines of the current signal (Cur) and the signal (1FD) one field before the signal (2FD), the signal (2FD) two fields before, and the signal (3FD) three fields before the signal. obtain. The obtained four signals Cur, 1FD, 2FD, and 3FD are supplied to buffers 121, 122, 123, and 124, respectively, so that the output timings of the signals of the four horizontal lines are matched. Then, the signals of the three horizontal lines output from the buffers 122, 123, and 124 are supplied to the signal processing circuit 130. For example, the signal processing circuit 130 is configured as a circuit that performs video processing of so-called double speed conversion processing for converting the number of horizontal lines or the field frequency.

  In this example, the first changeover switch 111 is arranged between the memory 103 and the buffer 124, and the second changeover switch 112 is arranged between the memory 103 and the buffer 122. The first changeover switch 111 is a switch for selecting the output of the signal (3FD) three fields before and the output of the signal (1FD) one field before from the memory 103. The second changeover switch 112 is a switch that selects the output of the signal (1FD) one field period before from the memory 103 and the output of the first changeover switch 111. These first and second change-over switches 111 and 112 are switches in which one of the signals is selected by a control signal supplied from the change-over controller 115, and when the video signal is not a film signal, The changeover switch 111 always selects the signal (3FD) before three field periods, and the second changeover switch 112 always selects the signal (1FD) before one field period. And in the case of a film signal, the signal which switches periodically changes.

  Then, the output of the buffer 121 and the output of the buffer 123 are supplied to the film determination unit 113, and the film signal of the 3-2 pull-down signal is determined based on the difference between the signals separated by two field periods (one frame period). To determine. Then, the data of the determination result in the film determination unit 113 is supplied to the switching controller 115 via the delay circuit 114 that delays one field period, and the first and second change-over switches 111 and 112 based on the determination result. A control signal for controlling the selection of is generated. Details of the determination state in the film determination unit 113 and the selection state in the first and second change-over switches 111 and 112 will be described later.

  FIG. 2 is a diagram showing a signal reading state from the RAM 102 in the circuit of FIG. FIG. 2A shows a horizontal synchronization pulse, and data is sequentially read from the RAM 102 as shown in FIG. 2B in conjunction with the horizontal synchronization pulse. The read data is sequentially output from the memory 103 by the read enable signals 1, 2, 3, and 4 shown in FIGS. 2C, D, E, and F. As shown in FIGS. 2G, H, I, and J, The two buffers 121, 122, 123, and 124 are sequentially stored. Of the data stored in the four buffers 121 to 124, the data stored in the three buffers 122 to 124 are temporally aligned and supplied to the signal processing circuit 130 as shown in FIG. The

  Also, when the lines read for each field are spatially shown, the state shown in FIG. 4 is obtained. In this example, since the film signal that may be input is a 3-2 pull-down signal, the film determination unit 113 uses the current signal (Cur) and the signal (2FD) two fields before. A film signal is detected from the difference between frames. When a 2-2 pull-down signal described in another embodiment, which will be described later, is input, a film signal is detected from the inter-field difference between the current signal (Cur) and the signal (1FD) one field before. To do.

  FIG. 5 is a diagram illustrating an operation example based on the determination of the film determination unit 113 in the circuit configuration illustrated in FIG. In this example, since a 3-2 pull-down signal is detected, the film determination unit 113 counts the number of fields at a period of 5 fields, and between frames of the current signal (Cur) and the signal 2 fields previous (2FD). Different pixel amounts are detected based on the difference, and film determination is performed depending on whether or not a pattern with a difference determination of 11011 is detected according to the detected amount. In FIG. 5, what is shown before SW indicates the output timing of the video signal from the memory 103, and in the case of a film video, it is a 3-2 pull-down signal. The same contents as field A ′, field A, field B, field B ′, field C, field C ′, field C, field D, field D ′,... Are alternately repeated in the three field period and the two field period. . Note that field A and field A ′ indicate an odd field and an even field of video having the same contents.

  Here, when the 3-2 pull-down signal is detected in this way, a field switching signal is generated as shown in FIG. 5, and the field switching signal is supplied to the switching controller 115 after being delayed by the delay circuit 114 for one field period. Then, at the timing delayed by one field, the first and second changeover switches 111 and 112 perform the switching process in the five-field cycle, and the signal shown as after SW is obtained by replacing the signal shown as before SW. At any timing, the three signals (1FD, 2FD, and 3FD) input to the signal processing circuit 130 are images in the field period with the same content. In this case, in this example, the first and second changeover switches 111 and 112 are switched at the previous stage of input to each of the buffers 121 to 124, but the field changeover signal is changed at a timing delayed by one field period by the delay circuit 114. Thus, when the signal is input to the signal processing circuit 130, the input of the signals of the three fields coincides.

  With this configuration, when the video signal read from the RAM 102, which is a field memory, is supplied to the signal processing circuit 130 that performs double speed conversion, the input timing to the signal processing circuit 130 is aligned. By performing film determination before and after the buffers 121 to 124 and performing signal replacement based on the determination result, film determination and processing based on the result can be performed with a simple configuration. Simplification is possible.

  Next, a second embodiment of the present invention will be described with reference to FIGS. In this example, the film signal processing of the 3-2 pull-down signal and the film signal processing of the 2-2 pull-down signal are configured to be executed by a common circuit, and FIG. In FIG. 1, the same circuit blocks as those in FIG. 1 described in the first embodiment are denoted by the same reference numerals.

  Hereinafter, the configuration will be described with reference to the block diagram of FIG. 6. The video signal obtained at the input terminal 101 is stored in the RAM 102 for at least one field, and the video signal stored in the RAM 102 is read into the memory 103. 1 to the configuration for outputting one horizontal line at a time under the control of the timing controller 104.

  Then, the current signal (Cur), which is a signal of four adjacent horizontal lines read from the memory 103, the signal (1FD) one field period before the signal, the signal (2FD) two field periods before, 3 The signal (3FD) before the field period is supplied to the buffers 151, 152, 153, and 154, respectively, so that the output timings of the signals of the four horizontal lines are matched. Then, the signals of the three horizontal lines output from the buffers 152, 153, and 154 are supplied to the signal processing circuit 130. For example, the signal processing circuit 130 is configured as a circuit that performs video processing of so-called double speed conversion processing for converting the number of horizontal lines or the field frequency.

  In this example, the first changeover switch 141 is arranged between the memory 103 and the buffer 154, and the second changeover is made between the buffer 152 and the signal (1FD) input portion of the signal processing circuit 130. A switch 142 is arranged. The first changeover switch 141 is a switch for selecting the output of the signal (3FD) three fields before and the output of the signal (1FD) one field before from the memory 103. The second changeover switch 142 is a switch that selects the output of the buffer 154 and the output of the buffer 152. These first and second change-over switches 141 and 142 are switches for selecting one of the signals according to the control signal supplied from the change-over controller 147, and when the video signal is not a film signal, The changeover switch 141 always selects the signal (3FD) before three field periods, and the second changeover switch 142 always selects the signal (1FD) before one field period output from the buffer 152. And when it is a film signal, the signal which switches periodically changes. However, the switching pattern differs between the case of the 3-2 pull-down signal and the case of the 2-2 pull-down signal.

  Then, the output of the buffer 151 and the output of the buffer 152 are supplied to the third changeover switch 143. The third change-over switch 143 is a switch that switches between a case where a 3-2 pull-down signal is detected and a case where a 2-2 pull-down signal is detected. When the output is selected and the 2-2 pull-down signal is detected, the output of the buffer 152 is selected. The signal selected by the third changeover switch 143 is supplied to the film determination unit 144 together with the output of the buffer 153 to determine whether it is a film signal. When a 3-2 pull-down signal is detected, it is determined whether or not it is a film signal from the difference between signals separated by two field periods (one frame period). When a 2-2 pull-down signal is detected, one field is detected. It is determined whether or not it is a film signal from the difference between signals separated by a period.

  Then, the data of the determination result in the film determination unit 144 is directly supplied to the fourth changeover switch 146 and supplied to the fourth changeover switch 146 via the delay circuit 145 that delays one field period. Either one of the unprocessed signal and the delayed signal is selected. This selection is switched between when the 3-2 pull-down signal is detected and when the 2-2 pull-down signal is detected. When the 3-2 pull-down signal is detected, the delayed signal is selected. When detecting a pull-down signal, a signal that is not delayed is selected.

  The signal selected by the fourth changeover switch 146 is supplied to the changeover controller 147 to generate a control signal for controlling selection by the first and second changeover switches 141 and 142 based on the film determination result.

  FIG. 7 is a diagram illustrating an operation example when the 2-2 pull-down signal is processed with the circuit configuration illustrated in FIG. 6. When processing the 2-2 pull-down signal, the third changeover switch 143 selects the output side of the buffer 152, and the film determination unit 144 uses different pixels depending on the difference between the signal (1FD) and the signal (2FD). An amount is detected, and film determination is performed depending on whether or not the difference determination has detected a constant pattern of four field periods according to the detected amount. In addition, the fourth changeover switch 146 selects a signal that is not delayed, and the changeover controller 147 controls the changeover of the first and second changeover switches 141 and 142. In FIG. 7, the output timing of the video signal from the memory 103 is shown as before SW, and in the case of film video, it is a 2-2 pull-down signal. The same contents as field A ′, field B, field B ′, field C, field C ′, field D, field D ′,... Are repeated for two field periods.

  Here, when the 2-2 pull-down signal is detected in this way, a field switching signal is generated as shown in FIG. 7, and the field switching signal is supplied to the switching controller 147. The change-over switches 141 and 142 perform the switching process in a four-field cycle, and the signal shown as after SW is obtained by replacing the signal shown as before SW, and is input to the signal processing circuit 130 at any timing. The two signals (1FD, 2FD, and 3FD) to be displayed are images of the same field period.

  In the example of FIG. 6, since the second changeover switch 142 is provided at the subsequent stage of the buffers 152 and 154, it is possible to prevent erroneous detection of the inter-field difference when detecting the 2-2 pull-down signal. In the example of FIG. 6, the process is switched to a process when a 2-3 pull-down signal is input by switching the third and fourth changeover switches 143 and 146 and switching the determination state in the film determination unit 144. Thus, the video signal circuit that handles the 2-2 pull-down signal and the video signal circuit that handles the 2-3 pull-down signal can be shared. In this case, when processing the 2-3 pull-down signal, the second changeover switch 142 is positioned downstream of the buffers 152 and 154 as compared with the configuration of FIG. .

  Next, a third embodiment of the present invention will be described with reference to FIGS. In this example, the film signal processing of the 3-2 pull-down signal and the film signal processing of the 2-2 pull-down signal are configured to be executed by a common circuit, and further input to the signal processing circuit simultaneously. The number of lines is increased so that more advanced video signal processing can be performed by the signal processing circuit. That is, as the signal processing circuit 130 ′ for performing the double speed conversion process, the current signal (Cur), the signal (1FD) one field period before the signal (1FD), the signal (2FD) two field periods before, and the three field periods before Signal (3FD), and signals (1FD_2), (2FD_2), and (3FD_2) of adjacent horizontal lines on the same field as the delayed signals (1FD), (2FD), and (3FD). This is a configuration to be made.

  That is, as shown in FIG. 9, when the signal of a predetermined horizontal line of the current signal (Cur) is represented by 0, not only the signals 1, 2 and 3 of the horizontal line at substantially the same position of 1FD, 2FD and 3FD, The signals 1 ', 2', 3 'on the adjacent horizontal lines on the same field as the signals 1, 2, 3 are also input to the signal processing circuit 130', and these signals surrounded by a frame in FIG. The structure is such that double speed conversion processing is performed from 1, 2, 3, 1 ', 2', 3 '. Here, the configuration for processing the current signal (Cur) and the signals (1FD, 2FD, 3FD) before one field period, two field periods, and three field periods is the same as the configuration shown in FIG. The same configuration can be applied to the configuration in which the signal is determined and controlled by the switching controller.

  The signals (1FD_2), (2FD_2), and (3FD_2) on adjacent horizontal lines on each field are input to the signal processing circuit 130 'via the buffers 155, 156, and 157, and other signals and input timings are input. It is made to match.

  Further, with respect to the input signals to the buffers 155 and 157, the fifth and sixth changeover switches 148 and 149, which can select the signal (1FD_2) and the signal (3FD_2), respectively, by the field switching signal from the switching controller 147 are provided. Since it is provided and can be replaced when it is a film signal, it is possible to input a signal with the same timing to the signal processing circuit 130 ′ similarly to the signals (1 FD, 2 FD, 3 FD). Become.

  As can be seen from the circuit configuration of FIG. 8 compared with the configuration of FIG. 6 described as the second embodiment, the number of lines required by the signal processing circuit is increased. It is only necessary to add a selector switch that performs the same selection process to the front stage of the buffer, and a common configuration can be applied to the configuration for controlling the selector switch, which can be easily dealt with.

It is a block diagram which shows the structural example by the 1st Embodiment of this invention. It is explanatory drawing which showed the example of the process timing by the 1st Embodiment of this invention. It is explanatory drawing which showed the example of the input processing state by the 1st Embodiment of this invention. It is explanatory drawing which showed each line processed by the 1st Embodiment of this invention spatially. It is explanatory drawing which showed the example of the signal replacement state by the 1st Embodiment of this invention. It is a block diagram which shows the structural example by the 2nd Embodiment of this invention. It is explanatory drawing which showed the example of the signal replacement state by the 2nd Embodiment of this invention. It is a block diagram which shows the structural example by the 3rd Embodiment of this invention. It is explanatory drawing which showed each line processed by the 3rd Embodiment of this invention spatially. It is the block diagram which showed the example of a switching structure of the film signal of the conventional 3-2 pulldown. It is explanatory drawing which showed the example of the signal replacement state of the example of FIG. It is the block diagram which showed the example of a switching structure of the film signal of the conventional 2-2 pulldown. It is explanatory drawing which showed the example of the signal replacement state of the example of FIG. It is the block diagram which showed the example of an input structure to a signal processing circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Input terminal, 102 ... RAM, 103 ... Memory, 104 ... Timing controller, 111 ... 1st changeover switch, 112 ... 2nd changeover switch, 113 ... Film determination part, 114 ... Delay circuit, 115 ... Switch controller, 121, 122, 123, 124 ... buffer, 130 ... signal processing circuit, 141 ... first changeover switch, 142 ... second changeover switch, 143 ... third changeover switch, 144 ... film judgment unit, 145 ... delay circuit 146: 4th changeover switch, 147: changeover controller, 151, 152, 153, 154 ... buffer, 201 ... first changeover switch, 202 ... second changeover switch, 203 ... third changeover switch, 204 ... Fourth switch 205, fifth switch 206, film determination unit 207, slow Circuit, 208 ... sixth selector switch, 209 ... switching controller, 211,212,213,214,215,216,217 ... buffer, 220 ... signal processing circuit

Claims (10)

From the input video signal, signals of the first horizontal line and the second, third and fourth horizontal lines delayed by one horizontal scanning period from the first horizontal line are obtained,
A first selection process for selectively replacing the signal of the fourth horizontal line with the signal of the second horizontal line;
A second selection process for selectively replacing the signal of the second horizontal line with the signal of the fourth horizontal line;
A timing matching process for matching the timings of the signals of the four horizontal lines after the first and second selection processes are selectively executed;
Whether a certain pattern corresponding to the film signal is detected by comparing the signal of the first horizontal line and the signal of the third horizontal line among the signals of the four horizontal lines having the same timing. A determination process for determining whether or not
A control process for controlling the first selection process and the second selection process at a timing delayed by at least one horizontal scanning period based on the determination process;
An input process in which at least the signals of the second, third and fourth horizontal lines among the signals of the four horizontal lines having the same timing in the timing matching process are input to perform predetermined signal processing; A video signal processing method. The video signal processing method according to claim 1,
A video signal processing method for performing signal processing for converting the number of horizontal lines or the field frequency based on the signals of the second, third, and fourth horizontal lines input in the input processing. The video signal processing method according to claim 1,
The timing matching process is performed on signals of four horizontal lines after only the first selection process is selectively executed,
For the second selection process, the second and fourth horizontal lines after the timing coincidence in the timing coincidence process is selected from the signals, and the selected signal is selected in the second horizontal line in the input process. Video signal processing method to input as a signal. From the input video signal, signals of the first horizontal line and the second, third and fourth horizontal lines delayed by one horizontal scanning period from the first horizontal line are obtained,
A first selection process for selectively replacing the signal of the fourth horizontal line with the signal of the second horizontal line;
A timing matching process for matching timings of signals of four horizontal lines after the first selection process is selectively executed;
A second selection process of selectively replacing a signal of a second horizontal line with a signal of a fourth horizontal line among the signals of four horizontal lines having the same timing;
Whether a certain pattern corresponding to the film signal is detected by comparing the signal of the second horizontal line and the signal of the third horizontal line among the signals of the four horizontal lines having the same timing. A determination process for determining whether or not
A control process for controlling the first selection process and the second selection process based on the determination process;
An input process in which at least the signals of the second, third and fourth horizontal lines among the signals of the four horizontal lines having the same timing in the timing matching process are input to perform predetermined signal processing; A video signal processing method. The video signal processing method according to claim 4, wherein
A video signal processing method for performing signal processing for converting the number of horizontal lines or the field frequency based on the signals of the second, third, and fourth horizontal lines input in the input processing. Input means for obtaining from the input video signal a first horizontal line and signals of the second, third and fourth horizontal lines delayed from the first horizontal line by one horizontal scanning period;
First switching means for selectively replacing the signal of the fourth horizontal line obtained by the input means with the signal of the second horizontal line;
Second switching means for selectively replacing the signal of the second horizontal line obtained by the input means with the signal of the fourth horizontal line;
Timing matching means for matching the timings of the signals of the four horizontal lines after the selection by the first and second switching means is performed;
Of the four horizontal line signals output by the timing matching means, the first horizontal line signal and the third horizontal line signal are compared to detect a certain pattern corresponding to the film signal. Film determination means for determining whether or not,
Control means for controlling the first and second switching means at a timing delayed by at least one horizontal scanning period based on the determination result of the film determination means;
Video processing means for performing predetermined video processing using at least the signals of the second, third and fourth horizontal lines among the signals of the four horizontal lines whose timings are matched by the timing matching means as a video Signal processing device. The video signal processing apparatus according to claim 6, wherein
The video processing means is a means for performing video signal processing for converting the number of horizontal lines or the field frequency. The video signal processing apparatus according to claim 6, wherein
The timing matching means receives as input the signals of four horizontal lines after only the first switching means is selectively executed.
The second switching means is configured to select the signals of the second and fourth horizontal lines after the timing is matched by the timing matching means, and the signal selected by the second switching means is the video signal. A video signal processing apparatus that uses a signal of a second horizontal line to be input to the processing means. Input means for obtaining, from the input video signal, signals of the first horizontal line and the signals of the second, third and fourth horizontal lines delayed from the first horizontal line by one horizontal scanning period;
First switching means for selectively replacing the signal of the fourth horizontal line obtained by the input means with the signal of the second horizontal line;
Timing matching means for matching the signals of the four horizontal lines after the selection by the first switching means is performed;
Second switching means for selectively replacing the signal of the second horizontal line among the signals of the four horizontal lines whose timings are matched by the timing matching means;
Whether a certain pattern corresponding to the film signal is detected by comparing the signal of the second horizontal line and the signal of the third horizontal line among the signals of the four horizontal lines having the same timing. Film determination means for determining whether or not
Control means for controlling the first and second switching means based on the determination result in the film determination means;
Video processing means for performing predetermined video predetermined by inputting at least signals of the second, third and fourth horizontal lines among the signals of the four horizontal lines whose timings are matched by the timing matching means. Signal processing device. The video signal processing apparatus according to claim 9, wherein
The video processing means is a means for performing video signal processing for converting the number of horizontal lines or the field frequency.

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