JP2005129901A - Redundancy repaired yield calculation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable calculation of the yield of a memory cell array to which a redundancy repair is provided. <P>SOLUTION: The product of a probability that failure-related defects in the number equal to or smaller than the number of redundancy repairs occur in one layer included in a memory cell array, and the probability that no failure-related defect occurs in layers other than one layer included in a memory cell array, is used in the calculation of the yield. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for calculating a yield when redundant relief is applied to a memory cell array.

  In recent years, circuits have become more complicated with higher integration and higher performance of integrated circuits, and as a result, it has become impossible to calculate yield based only on chip size as in the past. Therefore, for example, a method of calculating the yield by calculating the defect distribution for each mask layer and calculating the yield of the entire product using the product of the yields calculated for each layer, or the target yield of the product for each process target A method of decomposing into yield has been proposed (see Non-Patent Document 1 and Non-Patent Document 2, for example).

  For example, according to the Poisson distribution model, the yield (hereinafter referred to as Y) can be expressed by the following equation.

Y = exp (−DD × A)
Here, DD is the number of defects per critical unit area, and A is the critical area.

Specifically, after obtaining DD for each main mask process, in other words, after obtaining DD for each layer 1 (L1), layer 2 (L2),... Formed by each main mask process, The yield is calculated for each main mask process. Thereafter, by obtaining the product of the yields calculated for each mask process, that is, by obtaining the product of the yields calculated for each layer, the overall yield of the process can be obtained. Here, layer 1 (L1), layer 2 (L2),... Correspond to mask process 1, mask process 2,. That is, if the total yield of the process is Ytotal, and the yield calculated for each layer is Y (L1), Y (L2),.
Ytotal = Y (L1) × Y (L2) ×.
It is.
Lee Jacobson (National Semiconductor Corp.) et al., Development of Dynamic Tool PID / PWP Limits to Achieve Product Defect Density Goal, 1997 IEEE / SEMIAdvanced Semiconductor Manufacturing Conference, Page 144-145 Fred Lakhani (SEMATECH) et al., Design and Validation of 0.25um Integrated Circuit Yield Model, ISSM 1997 San Francisco, California, October 1997 Jitendra khare et al., Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.28, NO.2, Page 146-156, February 1993

  However, in the yield calculation method of Non-Patent Document 1 or 2 described above, since the yield is expressed as a product of the yield rate (yield) of all layers, SRAM (static random access memory) or DRAM (dynamic random access) With regard to memory) and the like, there is a problem that the yield can be calculated when redundancy relief is not performed, but the yield cannot be calculated when redundancy relief is performed. Furthermore, as the capacity of each cell constituting the memory cell array increases, the difference in yield between the case where redundancy relief is not performed and the case where redundancy relief is performed increases. That is, in the conventional yield calculation method, although the actual yield is 90% due to the redundancy relief, the yield when the redundancy relief is performed cannot be predicted, so the yield is 70%, for example. There arises a problem that it is underestimated.

  On the other hand, Non-Patent Document 3 proposes a method for predicting yield in consideration of redundant relief for each block of an integrated circuit device. In this method, for example, as shown in FIG. 8, when the integrated circuit device 10 is configured by a plurality of blocks 11 to 15, the yield considering redundancy relief is calculated for each of the blocks 11 to 15. The yield of the integrated circuit device 10 as a whole is calculated by calculating the product of the yield for each of the blocks 11 to 15. However, according to the method of Non-Patent Document 3, since the yield prediction is performed for each block, in other words, since the defect occurrence probability is not calculated for each layer, the yield prediction result is fed back to process development, or the yield prediction It is difficult to readjust the layer layout based on the result.

  In view of the foregoing, it is an object of the present invention to calculate the yield of a memory cell array subjected to redundancy repair in consideration of the defect occurrence probability for each layer.

  In order to achieve the above object, a redundant relief yield calculation method according to the present invention is a method for calculating a yield of a memory cell array having redundant relief, and is less than the number of redundant reliefs in one layer in the memory cell array. The yield is calculated by using the product of the probability that a defective defect will occur and the probability that a defective defect will not occur in another layer other than one layer in the memory cell array.

  Specifically, when there is one redundant relief and the memory cell array has the first layer and the second layer, the probability that one defective defect occurs in the first layer, The first product of the probability that no defective defect occurs in the second layer is obtained, the probability that one defective defect occurs in the second layer, and no defective defect occurs in the first layer The yield may be calculated by obtaining a second product with the probability and using the sum of the first product and the second product.

  Further, when there is one redundant relief and the memory cell array has n (n is an integer of 3 or more) layers, the m-th layer (m is an arbitrary integer from 1 to n) is considered defective. Each of the cases where m is an integer from 1 to n, the product of the probability that one defect will occur and the probability that no defect that is defective in any other layer other than the mth layer will occur. And the yield may be calculated by using the sum of each product.

  Further, when there are two redundant reliefs and the memory cell array has the first layer and the second layer, the probability that two defective defects occur in the first layer, and the second layer The first product of the probability that no defective defect occurs in the first layer, the probability that one defective defect occurs in the first layer, and the probability that one defective defect occurs in the second layer And the third product of the probability that two defective defects occur in the second layer and the probability that no defective defect occurs in the first layer, The yield may be calculated by using the sum of the product, the second product, and the third product.

  If there are two redundant reliefs and the memory cell array has n (n is an integer of 3 or more) layers, the m-th layer (m is an arbitrary integer from 1 to n) is considered defective. M is an integer from 1 to n, the first product of the probability that two defects will occur and the probability that no defect other than the mth layer will be defective. In each of the cases, p (p is an arbitrary integer from 1 to n) th and q (q is an arbitrary integer from 1 to n and p ≠ q) th defect is defective. A second product of the probability of occurrence of one and the probability of occurrence of a defective defect in any other layer other than the p-th and q-th layers, p and q being integers from 1 to n And use the sum of each first product and each second product. By Rukoto, it may calculate the yield.

  In addition, when the number of redundant repairs is s (s is an integer of 3 or more) and the memory cell array has the first layer and the second layer, s defective defects are generated in the first layer. The first product of the probability of failure and the probability that no defective defect occurs in the second layer is obtained, the probability that (s−1) defective defects occur in the first layer, and the second The yield may be calculated by obtaining a second product with the probability that one defect that is defective in the layer will occur and using at least the first product and the second product.

  Further, when the redundant relief is s (s is an integer of 3 or more) and the memory cell array has n (n is an integer of 3 or more) layers, m (m is an arbitrary number from 1 to n). (Integer) The first product of the probability that s defective defects occur in the 1st layer and the probability that no defect other than the mth layer occurs will be 1 For each of the integers from n to n, the probability that (s−1) defects that are defective in the mth layer will occur, and defects in any of the other layers other than the mth layer A second product with the probability of occurrence of one defect is obtained for each case where m is an integer from 1 to n, and at least using each first product and each second product The yield may be calculated.

  According to the redundancy repair yield calculation method of the present invention, in the yield calculation, there is a probability that a defect that is less than the number of redundancy repairs occurs in one layer and a probability that a defect that does not occur in another layer does not occur. Use product. Therefore, according to the number of redundant relief settings, the distribution probability of the defects can be calculated while considering the number of defects in which the entire memory does not become defective. Therefore, the yield when redundant relief is applied can be calculated. it can. That is, even when the size of the SRAM block or DRAM block is large, the product yield can be calculated with high accuracy.

  In the redundant relief yield calculation method of the present invention, the yield may be calculated separately depending on whether the redundant relief is bit relief or word relief.

  Further, in the redundant relief yield calculation method of the present invention, if the yield is calculated separately for each layer, the yield for each layer in consideration of redundant relief can also be calculated, so by changing the layout or the like for each layer Measures to improve yield can be taken.

  Note that what is calculated in the redundant relief yield calculation method of the present invention is an increase in yield due to the provision of redundant relief. Therefore, by using the probability that no defective defect occurs in all the layers of the memory cell array, the yield when there is no redundant relief is calculated, and by calculating the sum of the yield and the increase in the yield, The overall yield of the memory cell array can be calculated.

  In addition, according to the redundant relief yield calculation method of the present invention, the relationship between the number of redundant reliefs applied to the memory cell array and the yield can be easily predicted. An appropriate number of redundant remedies to be determined can be determined. That is, since the yield can be predicted in consideration of redundancy relief before the product is manufactured, it is possible to determine in advance how much redundancy relief should be prepared for the memory cell array.

  According to the present invention, in the yield calculation, the product of the probability that a defect that is less than the number of redundant repairs occurs in a predetermined layer and the probability that a defect that fails in other layers does not occur is used. Therefore, according to the number of redundant relief settings, the distribution probability of the defects can be calculated while considering the number of defects in which the entire memory does not become defective. Therefore, the yield when redundant relief is applied can be calculated. it can. That is, even when the size of the SRAM block or the like is large, the product yield can be calculated with high accuracy.

  Further, according to the present invention, the relationship between the number of redundant remedies to be given to the memory cell array and the yield can be easily predicted, so that an appropriate redundant remedy to be actually given to the memory cell array based on the relationship can be predicted. The number of can be determined. That is, since the yield can be predicted in consideration of redundancy relief before the product is manufactured, it is possible to determine in advance how much redundancy relief should be prepared for the memory cell array.

(First embodiment)
Hereinafter, a redundant relief yield calculation method and a redundant relief yield calculation apparatus according to a first embodiment of the present invention will be described with reference to the drawings.

  In the present embodiment, the yield after redundancy repair is performed on a memory cell array such as an SRAM is calculated. For example, a Poisson distribution model is used in the calculation of the yield. Hereinafter, although the case where the Poisson distribution model is used will be described, a negative binomial distribution model, a Γ distribution model, or the like may be used instead of the Poisson distribution model.

  According to the Poisson distribution model, the yield Y of the memory cell array is expressed as follows.

  Y = exp (−DD × A)

Here, A is an area (critical area (unit: cm ² )). Further, DD is the number of defects per unit area (more precisely, the number of defects per critical unit area (unit: number / cm ² )), and can be expressed as the following equation.

Here, DD (x) is the number of defects per unit area for a defect whose size is x, and x _min is the minimum dimension of the pattern in the memory cell array.

  A yield calculation method using the Poisson distribution model and DD and A will be described with reference to the graphs shown in FIGS.

FIG. 1A shows a defect distribution curve with the defect size x on the horizontal axis and the number of defects DD (x) (unit: number / cm ² ) on the vertical axis. As shown in FIG. 1A, there are few defects having a large size, while there are many defects having a small size. Here, the defect is, for example, a particle. That is, when the particles fall between the wirings, a short circuit occurs and the particles become defects.

FIG. 1B shows the dependency of the critical area A (x) on the defect size x, with the defect size x on the horizontal axis and the critical area A (x) (unit: cm ² ) on the vertical axis. Is shown. Here, the critical area A (x) is a critical area for a defect whose size is x. As shown in FIG. 1B, the critical area A (x) increases as the defect size x increases. The “critical area” means “the area of a portion that becomes defective when a defect exists”. Therefore, it means that the larger the “critical area”, the more likely it becomes a “defective defect”. In other words, as the defect size increases, the probability of becoming a “defective defect” increases.

  Further, the yield calculation formula based on the aforementioned Poisson distribution model: DD × A in Y = exp (−DD × A) can be expressed as follows using DD (x) and A (x). it can.

  That is, the yield Y can be calculated using DD (x) shown in FIG. 1 (a) and A (x) shown in FIG. 1 (b). As shown in FIG. 1C, even if the defects have the same size, the critical area is larger when the layout is dense than when the layout is sparse.

  In the present embodiment, based on the yield calculation method using this Poisson distribution model, the yield in the case where redundant relief is performed is predicted. Hereinafter, in order to make the description easy to understand, a case of a three-layer (L1, L2, L3) configuration using three masks will be described as an example. Here, each of the layer 1 (L1), the layer 2 (L2), and the layer 3 (L3) is a mask 1 (for source / drain structure creation) for producing a memory cell array having a cross-sectional configuration as shown in FIG. Mask), mask 2 (first wiring structure creation mask), and mask 3 (second wiring structure creation mask). That is, as shown in FIG. 2, L1 is a layer of the source / drain structure of the transistor, L2 is a layer of the first wiring structure connected to the source / drain structure, and L3 is connected to the first wiring structure. The second wiring structure layer.

  FIG. 3 is a diagram illustrating an example of the configuration of the redundant relief yield calculation apparatus according to the first embodiment. As shown in FIG. 3, the apparatus 100 according to the present embodiment includes a main control unit (CPU: central processing unit) 101, pattern layout data 103 including each pattern layout of layer 1, layer 2, and layer 3, and yield information. And a storage device 102 for storing 104. The main control unit 101 reads out the pattern layout data 103 from the storage device 102 as a calculation means, and executes the redundant relief yield calculation method of the present embodiment described later using the read pattern layout data 103. Further, the main control unit 101 outputs, as output means, yield information 104 when redundant relief is provided, which is a calculation result obtained by executing the redundant relief yield calculation method of the present embodiment, to the storage device 102. . The yield information 104 includes a yield Yn (Li) for each layer i (i = 1, 2, 3) when the number of defects is n, a yield Ym when the number of redundant remedies is m, and a comprehensive yield. Yield Y is included.

  Hereinafter, the redundant relief yield calculation method of this embodiment will be described in detail.

  The yield Y (L1) in L1 corresponding to the mask 1 is expressed by the following equation from the Poisson distribution model.

  Y (L1) = exp (−DD (L1) × A (L1))

  Here, A (L1) is a critical area in L1, and DD (L1) is the number of defects per unit area in L1.

  DD (L1) is calculated by using data obtained from the wafer defect inspection apparatus for each process.

  A (L1) is calculated using the layout of the mask 1. Specifically, the critical area A is calculated based on the actual layout density. That is, if the layout is dense, the critical area A becomes large because even a small particle becomes a defective defect. On the other hand, if the layout is sparse, even a slightly larger particle does not become a defective defect, and the critical area A becomes smaller.

  As described above, the yield Y (L1) of L1 can be obtained. Further, based on the same concept, the yields Y (L2) and Y (L3) for L2 and L3 can be calculated as follows.

Y (L2) = exp (−DD (L2) × A (L2))
Y (L3) = exp (−DD (L3) × A (L3))

  It should be noted that both DD and A are layer functions, and each numerical value varies depending on the layer. Therefore, the yield calculation method in the case of the three-layer (L1, L2, L3) configuration can be expressed as the flow in FIG.

  Hereinafter, a specific yield calculation method will be described for each case where no redundant relief is provided in the memory cell array, one redundant relief is provided, and two redundant reliefs are provided.

<When no redundant relief is provided>
First, the yield in the case where redundant relief is not provided in the memory cell array will be described. In this case, the number of defects that become defective in each of L1, L2, and L3 must be zero. In other words, since no remedy is taken, it is not a non-defective product unless there are zero defects in all layers.

  In this case, since the yield is equal to the probability that each of the three layers has no defect, the yield Y0 when no redundant relief is provided can be obtained as follows.

Y0 = Y0 (L1) × Y0 (L2) × Y0 (L3)
= Exp (-DD (L1) * A (L1)) * exp (-DD (L2) * A (L2)) * exp (-DD (L3) * A (L3))

<When providing one redundant relief>
Next, the yield in the case where one redundant relief is provided in the memory cell array will be described by taking as an example the case where there is “one” redundant relief in the bit line of the memory cell constituting the 32 kbit SRAM. In this case, even if there is “one defect”, it becomes a non-defective product and yield is improved. In other words, even if one defect occurs in the bit line, by replacing the defective bit line with a redundant bit line provided as a redundant relief, the defect does not become defective due to the defect. Can improve the yield.

  At this time, in the calculation of the yield (increase) Y1 when one redundant relief is provided, for example, in order to prevent a defect even if there is one defect in L1, the number of defects in the other layers L2 and L3 is Take into account that it must be zero. That is, since there is only one redundant remedy, if a defect occurs in a plurality of bits, it cannot be made “good” by the redundant remedy.

  Similarly, in order for L2 to have no defect even if there is one defect, the number of defects in other layers L1 and L3 must be zero, and even if there is one defect in L3 Consider that the number of defects in the other layers L1 and L2 must be zero in order not to be.

  Considering the above, the yield “Y1” when the redundant relief is “1” is expressed as shown in FIG.

Y1 = Y1 (L1) × [Probability that the number of defective defects in L2 and L3 is zero] + Y1 (L2) × [Probability that the number of defective defects in L1 and L3 is zero]
+ Y1 (L3) × [Probability that the number of defective defects in L1 and L2 is zero]
= Y1 (L1) × (Y0 (L2) × Y0 (L3))
+ Y1 (L2) × (Y0 (L1) × Y0 (L3))
+ Y1 (L3) × (Y0 (L1) × Y0 (L2))

  Here, for example, Y1 (L1) is the probability that one defect will occur in L1, and for example, (Y0 (L2) × Y0 (L3)) is the probability that the number of defects in each of L2 and L3 will be zero. is there.

In the case of the Poisson distribution model, the probability that n (n is an integer) defects exist in a predetermined layer is
Yn = ((DD × A) ⁿ / n!) × exp (−DD × A)
And the probability for a single defect is
Y1 = (DD × A) × (exp (−DD × A))
And the probability for zero defects is
Y0 = exp (−DD × A)
It is expressed.

  As described above, the yield Y1 (increase) when one redundant relief is provided in the memory cell array can be obtained. Therefore, in this case, the overall yield Y is calculated by Y = Y0 + Y1.

<When two redundant reliefs are provided>
Next, the yield Y2 when two redundant reliefs are provided in the memory cell array will be described. In this case, the number of defective defects is allowed up to two, but if it exceeds that, it cannot be made “good” by redundant relief. Therefore, considering the probability that up to two defects that are defective in L1 to L3 are distributed, the yield (increase) “Y2” when the redundant relief is “2” is expressed as shown in FIG. .

  As shown in FIG. 5, when there are “two” redundant remedies, even if two defects exist in any one of L1 to L3, it does not become defective. In addition, when two defects are dispersed one by one in any two layers of L1 to L3, it does not become a defect. In other words, L1 and L2 each have one defect and L3 has zero defect, L1 and L3 each have one defect and L2 has zero defect, or L2 and Even if one defect exists in each of L3 and the defect of L1 is zero, it is not a failure.

  When the probabilities in the above cases are calculated, they are expressed as shown in FIG.

[Probability of two defects in L1 and zero defects in L2 and L3]
= Y2 (L1) × Y0 (L2) × Y0 (L3)
[Probability that L1 and L2 have one defect and L3 has zero defect]
= Y1 (L1) × Y1 (L2) × Y0 (L3)
[Probability that there is one defect in each of L1 and L3 and zero defect in L2]
= Y1 (L1) × Y0 (L2) × Y1 (L3)
[Probability of two defects in L2 and zero defects in L1 and L3]
= Y0 (L1) × Y2 (L2) × Y0 (L3)
[Probability that there is one defect each in L2 and L3 and zero defect in L1]
= Y0 (L1) × Y1 (L2) × Y1 (L3)
[Probability that there are two defects in L3 and zero defects in L1 and L2]
= Y0 (L1) × Y0 (L2) × Y2 (L3)
Here, for example, Y0 (L1) is the probability that the number of defects in L1 is zero,
Y0 (L1) = exp (−DD (L1) × A (L1))
And
For example, Y1 (L1) is the probability that one defect will occur in L1,
Y1 (L1) = (DD (L1) × A (L1))
× (exp (−DD (L1) × A (L1)))
And
For example, Y2 (L1) is the probability that two defects will occur in L1,
Y2 (L1) = ((DD (L1) × A (L1)) 2/2)
× (exp (−DD (L1) × A (L1)))
It is expressed.

  Using the probability in each case calculated as described above, the yield (increase) Y2 when two redundant reliefs are provided in the memory cell array is calculated as follows.

  Y2 = Y2 (L1) * Y0 (L2) * Y0 (L3) + Y1 (L1) * Y1 (L2) * Y0 (L3) + Y1 (L1) * Y0 (L2) * Y1 (L3) + Y0 (L1) * Y2 (L2) * Y0 (L3) + Y0 (L1) * Y1 (L2) * Y1 (L3) + Y0 (L1) * Y0 (L2) * Y2 (L3)

  Therefore, in this case, the overall yield Y is calculated by Y = Y0 + Y1 + Y2.

  As described above, according to the first embodiment, in the yield calculation, the probability that a defect that is less than the number of redundant remedies occurs in a predetermined layer and the defect that becomes a defect in other layers occur. Use the product with the probability of not. Therefore, according to the number of redundant relief settings, the distribution probability of the defects can be calculated while considering the number of defects in which the entire memory does not become defective. Therefore, the yield when redundant relief is applied can be calculated. it can. That is, the yield of products can be calculated with high accuracy even when the size of the SRAM block is large.

  Further, according to the first embodiment, since the relationship between the number of redundant reliefs to be given to the memory cell array and the yield can be easily predicted, an appropriate value to be actually given to the memory cell array based on this relationship. The number of redundant remedies can be determined. That is, since the yield can be predicted in consideration of redundancy relief before the product is manufactured, it is possible to determine in advance how much redundancy relief should be prepared for the memory cell array.

  In the first embodiment, the case where there are three layers of the memory cell array (that is, the case where there are three masks) has been described as an example. However, the present embodiment is applicable even when there are other than three layers. The same idea can be applied. For example, when there is one redundant relief and two memory cell array layers, the probability of one defective defect occurring in the first layer and the defective defect occurring in the second layer A first product of the probability of not occurring is obtained, and a second product of the probability of occurrence of one defective defect in the second layer and the probability of no defective defect occurring in the first layer is obtained. The yield may be calculated by using the sum of the first product and the second product. Also, for example, when there are two redundancy reliefs and two memory cell array layers, the probability that two defective defects occur in the first layer and the second layer becomes defective. A first product of the probability of no defect occurring is obtained, and the second of the probability that one defective defect occurs in the first layer and the probability that one defective defect occurs in the second layer And the third product of the probability that two defective defects occur in the second layer and the probability that no defective defect occurs in the first layer, and the first product and the first The yield may be calculated by using the sum of the product of 2 and the third product.

  In the first embodiment, the case where the number of redundant remedies is one or two has been described as an example. Needless to say, the number of redundant remedies may be three or more. However, if the number of redundant remedies is increased too much, there is a demerit that the area of the memory cell becomes large. Therefore, it is not preferable to increase the number of redundant remedies indefinitely.

  In the first embodiment, the case where the memory cell array is an SRAM has been described as an example. Needless to say, the memory cell array may be another memory such as a DRAM.

  In the first embodiment, the case where the redundant relief is a redundant bit line has been described as an example. Needless to say, the redundant relief may be a redundant word line. That is, the yield calculation may be performed separately depending on whether the redundant relief is bit relief or word relief.

  Further, in the first embodiment, for the sake of simplification, the description has been made on the assumption that the yield of redundant relief cells, fuses, and the like is 100%. However, these yields are also actually used. In some cases, a calculation formula may be created and the calculation formula may be used in the redundant relief yield calculation method of the present invention.

(Modification of the first embodiment)
Hereinafter, a redundant relief yield calculation method according to a modification of the first embodiment of the present invention will be described. This modification is different from the first embodiment in that the number of redundant remedies in the first embodiment is one or two, whereas in this modification, three or more redundant remedies are used. This is a case where the case is provided. Needless to say, an apparatus similar to the redundant repair yield calculation apparatus according to the first embodiment shown in FIG. 3 can be used to implement the redundant repair yield calculation method according to the present embodiment.

  Now, assuming that the number of layers of the memory cell array is n (n is an integer of 2 or more), the yield of one layer (hereinafter referred to as layer 1) can be expressed by the following equation.

Here, D ₀₁ is the number of defects per unit area in layer 1, A _c1 is the critical area in layer 1, and D _0i is the number of defects per unit area in the i-th layer (hereinafter referred to as layer i). A _ci is a critical area in layer i, D _0j is the number of defects per unit area in the j-th layer (hereinafter referred to as layer j), and A _cj is a critical area in layer j.

Specifically, in the case where the number of redundant remedies is 3, for example, when calculating the yield of layer 1 (corresponding layer), the failure occurrence probability (0 to 2 redundant remedies) considered in the first embodiment is used. In addition to the probability of failure occurrence in some cases)
[Probability of 3 defects in the corresponding layer] x [Probability that other layers are non-defective]
+ [Probability that two defects occur in the corresponding layer] x [Probability that one defect occurs in one of the other layers and the remaining layers are non-defective]
+ [Probability that one defect occurs in the corresponding layer] × [Probability that two defects occur in one of the other layers and the remaining layers are non-defective]
+ [Probability that one defect occurs in the corresponding layer] x [Probability that one defect occurs in two of the other layers and the remaining layers are non-defective]
Need to be considered.

  Here, for simplification of yield calculation, it may be assumed that only one defect (exactly, a defect that becomes a defect) occurs in other layers other than the corresponding layer (that is, the third equation in the above equation). The term does not have to be considered). Under this assumption, the defect distribution state for each layer when the number of layers is n and the number of redundant repairs is m (m is an integer equal to or less than n) can be expressed as shown in FIG. Although the number of defect distribution states, that is, the types of redundant repair conditions, can be increased as much as possible in the calculation, in practice, depending on the size of the memory cell array, there is one defect in other layers other than the corresponding layer as a redundant repair condition. It is often efficient to assume that only one occurs.

Further, the yield of layer 1 is the sum of the probabilities obtained for all redundant repair conditions shown in FIG. However, the probability obtained for the redundant repair condition at the top of each column in FIG. 6 must be divided by the number of layers in which defects exist. That is, when the yield of the layer 1 and Y _1, the following expression holds.

Y ₁ = (sum of probabilities in the first column) + (probability in the uppermost row in the second column) / 2 + (probability in the uppermost row in the third column) / 3 +... + (Probability in the uppermost row in the Nth column ) / N + (sum of probabilities of other stages in second column) + (sum of probabilities of other stages of third column) +... + (Sum of probabilities of other stages of N column)

  Further, (sum of probabilities for the redundant repair condition in the first column) can be expressed as the following equation.

  Further, (sum of probabilities for the redundant repair condition in the second column) can be expressed as the following equation.

  Further, (sum of probabilities for the redundant repair condition in the third column) can be expressed as the following equation.

  Further, (sum of probabilities for the redundant repair condition in the Nth column) can be expressed as the following equation.

Here, D ₀₁ is the number of defects per unit area in layer 1, A _c1 is the critical area in layer 1, D _0i is the number of defects per unit area in layer i, and A _ci is in layer i. D _0l is the number of defects per unit area in layer 1, A _cl is the critical area in layer 1, D _0j is the number of defects per unit area in layer j, and A _cj is the layer j is the critical area in j, D _0j1 is the number of defects per unit area in layer j1, A _cj1 is the critical area in layer j1, D _0j2 is the number of defects per unit area in layer j2, and A _cj2 Is a critical area in layer j2.

  That is, in the present modification, when the number of redundant reliefs is m (m is an integer of 3 or more) and the memory cell array has layers 1 and 2 (the number of layers is two), layer 1 The first product of the probability that m defective defects will occur and the probability that no defective defects will occur in layer 2, and the probability that (m-1) defective defects occur in layer 1 Then, the second product of the probability of occurrence of one defective defect in layer 2 is obtained, and the yield is calculated by using at least the first product and the second product.

  Further, in this modification, when the number of redundant reliefs is m (m is an integer of 3 or more) and the memory cell array has n (n is an integer of 3 or more) layers, i (i is 1). A first product of the probability that m defective defects occur in the first layer i and the probability that no defective defect occurs in any other layer other than layer i, A second product of the probability that (m−1) defects that become defective in layer i occur and the probability that one defect that occurs in any one of the other layers other than layer i occurs, layer i The third product of the probability that (m−2) defects that become defective will occur and the probability that one defect that occurs in any two layers other than layer i will occur one by one,... , Any one of the other layers other than layer i and the probability that a defect which becomes defective in layer i occurs ( -1) respectively obtained the product of the first N of the probability that a defect which becomes defective pieces is generated one by one by using the at least first product to the product of the N, we calculate the yield.

  According to this modification described above, the same effects as those of the first embodiment can be obtained.

(Second Embodiment)
The redundant relief yield calculation method according to the second embodiment of the present invention will be described below. The present embodiment is different from the first embodiment in that the first embodiment is intended for calculating the yield of the entire memory cell array, whereas the present embodiment is for each layer constituting the memory cell array. This is a point that is intended for the calculation of the yield. Needless to say, an apparatus similar to the redundant repair yield calculation apparatus according to the first embodiment shown in FIG. 3 can be used to implement the redundant repair yield calculation method according to the present embodiment.

  Specifically, the yield Y (L1) limited to L1 in the same three-layer (L1, L2, L3) configuration as in the first embodiment can be calculated by the following equation.

Y (L1) = [Probability that the number of defective defects in L1 is zero]
+ [Probability that there is a defect only in L1]

  Here, considering the yields Y0, Y1, and Y2 shown in FIG. 5, Y (L1) is expressed by the following equation.

  Y (L1) = Y0 (L1) + Y1 (L1) × Y0 (L2) × Y0 (L3) + Y2 (L1) × Y0 (L2) × Y0 (L3) + (Y1 (L1) × Y1 (L2) × Y0 (L3) + Y1 (L1) × Y0 (L2) × Y1 (L3)) / 2

  That is, in the previous equation, the yield when no redundant relief is provided is Y0 (L1). In addition, the yield (increase) in the case where one redundant relief is provided takes into consideration the probability that only L1 becomes a target of redundant relief and becomes a non-defective product, in other words, the probability that only one defect exists in L1 ( In other words, Y1 (L1) × Y0 (L2) × Y0 (L3) in consideration of the probability that there is no defect in other layers other than L1. Furthermore, the yield (increase) when two redundant reliefs are provided is, specifically, the probability that L1 has two defects only in L1 in consideration of the probability that L1 becomes a target of redundant relief and becomes a non-defective product. Y2 (L1) × Y0 (L2) × Y0 (L3) + (Y1 () in consideration of the probability that one defect exists in L1 and one defect exists in other layers other than L1. L1) * Y1 (L2) * Y0 (L3) + Y1 (L1) * Y0 (L2) * Y1 (L3)) / 2. Here, the probability that two defects exist only in L1 is Y2 (L1) × Y0 (L2) × Y0 (L3). In addition, the probability that one defect exists in L1 and one defect exists in other layers other than L1 is the probability that one defect exists in L1 and one defect exists in L2. Is the sum of the probability that one defect exists in L3 and one defect also exists in L3, so (Y1 (L1) × Y1 (L2) × Y0 (L3) + Y1 (L1) × Y0 (L2) × Y1 (L3)) / 2. However, in this case, there is one defect in L2 and one defect in L1 (which contributes to the yield of L2), or one defect in L3 and one defect in L1. In some cases (contributing to the yield of L3), the aforementioned sum is divided by two.

  The yield Y (L2) or Y (L3) limited to the layer 2 (L2) or the layer 3 (L3) can also be calculated in the same manner as Y (L1).

  According to the second embodiment, instead of the yield of the entire memory cell array in the case where redundancy relief is provided, the yield of a specific layer considering redundancy relief can be calculated. For this reason, it is possible to take measures to improve the yield by adjusting the layout or the like for each layer.

  In the second embodiment, the case where the number of redundant remedies is one or two has been described as an example. However, as in the modification of the first embodiment, the number of redundant remedies is three or more. Needless to say, it may be. However, if the number of redundant remedies is increased too much, there is a demerit that the area of the memory cell becomes large. Therefore, it is not preferable to increase the number of redundant remedies indefinitely.

  Further, in the first embodiment, the modified example thereof, or the second embodiment, the probability calculation in the case where at least one defect exists in at least one layer (for example, “two defects exist only in L1 in this embodiment” When calculating “probability to perform” = Y2 (L1) × Y0 (L2) × Y0 (L3), etc.), the yield calculation accuracy is further improved by multiplying the probability obtained by the calculation by a predetermined rescue rate. be able to. Hereinafter, the relief rate will be described with reference to the drawings.

  FIGS. 7A and 7B are views showing the concept of the bit (Word) relief rate and the word (Word) relief rate when the redundancy relief is a redundancy bit line or a redundancy word line, respectively. In FIGS. 7A and 7B, the unit cell region is surrounded by a broken line. 7A and 7B, the vertical direction of the drawing is the bit line direction, and the horizontal direction of the drawing is the word line direction.

  As shown in FIGS. 7A and 7B, a plurality of gate electrodes (GA) 201 are formed on a semiconductor substrate 200, and contacts (contacts on GA) 202a and 202b are formed on each gate electrode 201. Is formed. Here, each of the GA upper contacts 202a (three) is entirely present in the unit cell region. On the other hand, each of the GA upper contacts 202b (two) has a half in the unit cell region. That is, the number of each GA upper contact 202b in the unit cell region is ½. Therefore, the total number of the GA upper contacts 202a and 202b in the unit cell region is four.

  7A and 7B, an impurity diffusion layer (OD) is formed on the semiconductor substrate 200, and contacts (contacts on OD) 203a and 203b are formed on the impurity diffusion layer. Is formed. Here, each of the on-OD contacts 203a (four) is entirely present in the unit cell region. On the other hand, half of each OD contact 203b (six) exists in the unit cell region. That is, the number of contacts on each OD 203b in the unit cell region is ½. Therefore, the total number of the GA upper contacts 203a and 203b in the unit cell region is seven.

  As shown in FIG. 7A, in the case where a total of seven OD contacts 203a and 203b are provided in a unit cell, when bit repair is possible and word repair is impossible, contact on OD 203a and Since both of 203b can repair Bit, the total number of contacts that can be Bit repaired is seven. Therefore, the Bit relief rate is 1. On the other hand, when Bit repair is not possible and Word repair is possible, as shown in FIG. 7A, the OD on-contact 203b cannot be repaired. In other words, only the on-OD contact 203a is repaired by Word. Since this is possible, the total number of contacts that can be relieved by Word is four. Therefore, the Word relief rate is 4/7.

  Further, as shown in FIG. 7B, when there are a total of four on-GA contacts 202a and 202b in the unit cell, if the bit relief is possible and the word relief is not possible, the on-GA contact Since 202b cannot repair the bit, in other words, only the contact 202a on the GA can repair the bit, so the total number of contacts that can repair the bit is three. Therefore, the bit relief rate is 3/4. On the other hand, when bit repair is impossible and word repair is possible, both the contacts on the GA 202a and 202b can repair the word, so the total number of contacts that can be repaired is four. Therefore, the Word relief rate is 1.

  The present invention relates to a method for calculating the yield of a memory cell array, and is particularly useful when used in a memory cell array having redundant relief.

(A)-(c) is a figure for demonstrating the yield calculation method using the Poisson distribution model used in the redundant relief yield calculation method which concerns on the 1st Embodiment of this invention. FIG. 3 is a diagram showing a cross-sectional configuration of a memory cell array to which the redundant relief yield calculation method according to the first embodiment of the present invention is applied. It is a figure which shows an example of a structure of the redundant relief yield calculation apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart of the redundant relief yield calculation method which concerns on the 1st Embodiment of this invention. It is a figure which shows the yield calculation formula used according to the number of redundant relief in the redundant relief yield calculation method concerning the 1st Embodiment of this invention. It is a figure which shows the defect distribution condition according to layer in the redundant relief yield calculation method which concerns on the modification of the 1st Embodiment of this invention. (A) And (b) is a figure which shows the idea of the relief rate used in the redundant relief yield calculation method which concerns on 1st and 2nd embodiment (a modification is included) of this invention. It is sectional drawing which shows schematic structure of the integrated circuit device used as the application object of the conventional yield prediction method.

Explanation of symbols

L1 layer 1
L2 layer 2
L3 layer 3
100 Redundant Rescue Yield Calculation Device 101 Main Control Unit 102 Storage Device 103 Pattern Layout Data 104 Yield Information 200 Semiconductor Substrate 201 Gate Electrodes 202a and 202b GA Contacts 203a and 203b Contacts on OD

Claims (11)

A method of calculating a yield of a memory cell array with redundant relief,
The probability that a defect that is less than or equal to the number of redundancy remedies occurs in one layer in the memory cell array and the probability that a defect that fails in another layer other than the one layer in the memory cell array does not occur A redundant relief yield calculation method, wherein the yield is calculated by using a product. The redundant relief is one,
The memory cell array has a first layer and a second layer;
Obtaining a first product of a probability that one defective defect occurs in the first layer and a probability that a defective defect does not occur in the second layer;
Obtaining a second product of the probability of one defective defect occurring in the second layer and the probability of no defective defect occurring in the first layer;
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using a sum of the first product and the second product. The redundant relief is one,
The memory cell array has n (n is an integer of 3 or more) layers,
The probability that one defective defect occurs in the m-th layer (m is an arbitrary integer from 1 to n) and no defective defect occurs in any other layer other than the m-th layer. Find the product of the probabilities for each case where m is an integer from 1 to n,
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using a sum of the products. The redundant relief is two,
The memory cell array has a first layer and a second layer;
Obtaining a first product of a probability that two defective defects occur in the first layer and a probability that a defective defect does not occur in the second layer;
Obtaining a second product of the probability of one defective defect occurring in the first layer and the probability of generating one defective defect in the second layer;
Obtaining a third product of the probability of two defective defects occurring in the second layer and the probability of no defective defects occurring in the first layer;
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using a sum of the first product, the second product, and the third product. The redundant relief is two,
The memory cell array has n (n is an integer of 3 or more) layers,
The probability that two defective defects occur in the m-th layer (m is an arbitrary integer from 1 to n) and the defect that does not occur in any other layer other than the m-th layer does not occur. Find a first product with the probability for each of the cases where m is an integer from 1 to n;
the probability that one defective defect occurs in each of the pth (p is an arbitrary integer from 1 to n) th and q (q is an arbitrary integer from 1 to n and p ≠ q) th layer; , The second product of the probability that a defect that is defective in any of the layers other than the p-th and q-th layers does not occur, and p and q are integers from 1 to n. Ask for each,
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using a sum of the first products and the second products. The redundant relief is s (s is an integer of 3 or more),
The memory cell array has a first layer and a second layer;
Obtaining a first product of the probability of occurrence of s defective defects in the first layer and the probability of no defective defects occurring in the second layer;
Obtaining a second product of the probability that (s−1) defects that are defective in the first layer occur and the probability that one defect that is defective in the second layer occurs;
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using at least the first product and the second product. The redundant relief is s (s is an integer of 3 or more),
The memory cell array has n (n is an integer of 3 or more) layers,
The probability that s defective defects occur in the mth layer (m is an arbitrary integer from 1 to n) th layer, and no defective defect occurs in any other layer other than the mth layer. Find a first product with the probability for each of the cases where m is an integer from 1 to n;
The second of the probability that (s−1) defects that are defective in the m-th layer occur and the probability that one defect occurs in any other layer other than the m-th layer. For each case where m is an integer from 1 to n,
2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated by using at least each first product and each second product.   2. The redundant relief yield calculation method according to claim 1, wherein the yield is calculated separately according to whether the redundant relief is bit relief or word relief.   The redundant relief yield calculation method according to claim 1, wherein the yield is calculated separately for each layer. A yield calculation method using the redundant relief yield calculation method according to any one of claims 1 to 7,
By using the probability that a defective defect does not occur in all the layers of the memory cell array, the first yield when there is no redundant relief is calculated,
By using the redundant relief yield calculation method, the second yield when there is redundant relief is calculated,
A yield calculation method, comprising: calculating a total yield of the memory cell array by calculating a sum of the first yield and the second yield. A method for determining the number of redundant remedies using the redundant remedy yield calculation method according to any one of claims 1 to 7,
Determining the number of redundant reliefs actually applied to the memory cell array based on the relationship between the number of redundant reliefs applied to the memory cell array and the yield calculated by using the redundant relief yield calculation method. A method for determining the number of redundant reliefs as a feature.

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