CN110970085B

CN110970085B - DRAM yield analysis system

Info

Publication number: CN110970085B
Application number: CN201811163264.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-30
Filing date: 2018-09-30
Publication date: 2021-08-13
Anticipated expiration: 2038-09-30
Also published as: CN110970085A

Abstract

The invention relates to the field of integrated circuits, and provides a DRAM yield analysis system which is used for analyzing electrical failure data of a DRAM chip and obtaining possible failure reasons, wherein a plurality of failure templates are stored in a storage module, each failure template corresponds to at least one possible failure reason, after the data input module obtains the electrical failure data of the DRAM chip, a graphic module can process the electrical failure data and mark the electrical failure data in a grid map, and the analysis module can compare the marked grid map with the failure templates to obtain at least one failure template matched with the marked grid map, so that the possible failure reasons corresponding to the marked grid map can be obtained. By utilizing the DRAM yield analysis system, possible failure reasons can be obtained in time from electrical failure data of the DRAM chip, so that the yield of the DRAM chip is favorably and rapidly improved.

Description

DRAM yield analysis system

Technical Field

The invention relates to the field of integrated circuits, in particular to a DRAM yield analysis system.

Background

In modern integrated circuit manufacturing processes, chip processing needs to go through a series of process links related to cleaning, film formation, etching, heat treatment and the like, and various defects may be introduced in each process. The losses due to device defects are extremely costly. Under the condition, the chip on the wafer is tested, failure reasons are analyzed, and factors influencing the yield of the chip are obtained to reduce the defects of the device, namely, the yield analysis becomes an important link in the manufacture of the integrated circuit.

Taking a Dynamic Random Access Memory (DRAM) as an example, a DRAM chip generally includes a plurality of memory cells arranged in an array, and an electrical failure condition of the DRAM chip can be known by testing a formed memory cell array. In order to further know the cause of the electrical failure to improve the yield of the chip, the electrical test result needs to be further analyzed, and a commonly used method at present is to adjust the test conditions, such as the voltage value, timing (timing) and other parameters, to find out the specific cause of the failure or the possible processes.

However, it is time consuming to adjust the test conditions to find out the specific cause of failure or the analysis process of the possible process, and the experience requirements of the operator are high, so that it is difficult to obtain the analysis result in time in the face of a large amount of test data, the overall efficiency of yield analysis is low, and the yield of DRAM chip products is not improved.

Therefore, it is desirable to develop a tool that can timely obtain the failure cause through the electrical failure condition of the DRAM chip, so as to improve the yield of the DRAM chip.

Disclosure of Invention

The invention provides a DRAM yield analysis system, which aims to timely obtain failure reasons from the electrical failure condition of a DRAM chip so as to improve the yield of the DRAM chip.

The DRAM yield analysis system provided by the invention is used for analyzing electrical failure data of a DRAM chip and obtaining possible failure reasons, the DRAM chip comprises a plurality of active regions and an isolation region for limiting the active regions, the DRAM chip also comprises a plurality of word lines and a plurality of bit lines, every two word lines extend along a first direction and intersect with the corresponding active regions, every bit line extends along a second direction different from the first direction and intersects with the corresponding active regions, each active region is provided with two storage units, and the DRAM yield analysis system comprises:

a storage module for storing a plurality of failure templates, each of the failure templates corresponding to at least one possible failure cause; the data input module is used for acquiring electrical failure data of the DRAM chip; the graphic module is used for processing the electrical failure data and marking the electrical failure data in a grid graph, wherein a plurality of grids in the grid graph correspond to a plurality of storage units on the DRAM chip one by one; an analysis module, configured to compare the marked grid map with the plurality of failure templates to obtain at least one failure template matching the marked grid map, and obtain a possible failure cause corresponding to the marked grid map; and an output module for outputting a possible failure cause corresponding to the marked grid map.

Optionally, the electrical failure data includes location information of failed portions of the storage units on the DRAM chip, the graphic module marks portions of the grids corresponding to the failed portions of the storage units in the grid map, and a coordinate system is provided on the grid map to determine a location of each grid.

Optionally, in the marked grid map, a part of the grid corresponding to the failed part of the storage unit is filled with color blocks.

Optionally, the analysis module includes:

a calculation unit for calculating the number of marked grids in the marked grid map and the coordinates of the marked grids in the coordinate system; and the comparison unit is used for obtaining at least one failure template matched with the marked grid graph according to the number of the marked grids and the coordinates in the coordinate system.

Optionally, a first memory array is disposed on the DRAM chip, the first memory array includes a plurality of memory cells arranged in m rows and 2n columns, and the grid map includes a plurality of grids arranged in m rows and 2n columns; coordinates of two storage units arranged in the same active region in the coordinate system are (x, 2y) and (x, 2y +1), respectively, where m, n, x, and y are integers greater than or equal to 0, and 0 ≦ x ≦ m, and 0 ≦ y ≦ n.

Optionally, a first failure template is stored in the storage module, and possible failure causes corresponding to the first failure template include bit line contact failure; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y) and (x, 2y +1), respectively, the marked grid map matches the first failure template.

Optionally, the storage module stores a second failure template, and the possible failure cause corresponding to the marked grid map includes word line isolation failure; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, y ') and (x +1, y '), respectively, the marked grid map matches the second failure template, where y ' is an integer greater than or equal to 0.

Optionally, a third failure template is stored in the storage module, and possible failure reasons corresponding to the third failure template include a diagonal bit line short circuit failure; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y +1) and (x +1, 2y), respectively, the marked grid map matches the third failure template.

Optionally, a fourth failure template is stored in the storage module, and possible failure reasons corresponding to the fourth failure template include active area isolation failure; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y +1) and (x +1, 2y +2), respectively, the marked grid map matches the fourth failure template.

Optionally, a fifth failure template and a sixth failure template are stored in the storage module, where a possible failure cause corresponding to the fifth failure template includes a word line disconnection failure, and a possible failure cause corresponding to the sixth failure template includes a bit line disconnection failure; and when the grids in the same column in the marked grid map are all marked, the marked grid map is matched with the fifth failure template; when the grids in the same row in the marked grid map are marked, the marked grid map is matched with the sixth failure template.

Optionally, a seventh failure template is stored in the storage module, and a possible failure cause corresponding to the seventh failure template includes a word line short circuit failure; when two adjacent columns of grids in the marked grid map are marked, the marked grid map is also matched with the seventh failure template.

Optionally, an eighth failure template is stored in the storage module, and a possible failure cause corresponding to the eighth failure template includes a bit line short circuit failure; when two adjacent rows of grids in the marked grid map are both marked, the marked grid map is also matched with the eighth failure template.

Optionally, a ninth failure template is stored in the storage module, and a possible failure cause corresponding to the ninth failure template includes a cross short failure; when the same row and column of grids in the marked grid map are both marked, the marked grid map is also matched with the ninth failure template.

Optionally, a second memory array is further disposed on the DRAM chip, the second memory array includes a plurality of memory cells arranged in m' rows and 2n columns, n controllers are disposed between the first memory array and the second memory array, and each controller connects two word lines of a corresponding column of the first memory array and the second memory array; the grid map includes a plurality of the grids arranged in (m + m ') rows and 2n columns, m' being an integer greater than or equal to 0.

Optionally, a tenth failure template is stored in the storage module, and a possible failure cause corresponding to the tenth failure template includes connection failure of a controller and a word line; when grids which are positioned in the same column and continuously exceed a first preset value in the marked grid map are marked, the marked grid map is also matched with the tenth failure template, and the first preset value is larger than m.

Optionally, an eleventh failure template is stored in the storage module, and a possible failure cause corresponding to the eleventh failure template includes short circuit failure between controllers; when the grids in the marked grid map at the spacing columns are all marked, the marked grid map is also matched with the eleventh failure template.

Optionally, a twelfth failure template is stored in the storage module, and a possible failure cause corresponding to the twelfth failure template includes a storage unit open circuit failure; when the marked grid map comprises adjacent grids, the number of which exceeds a second preset value, which are marked, the marked grid map is matched with the twelfth failure template, wherein the coordinates of the marked grids are (x ', y "), wherein x ' and y ' are integers greater than 0, and 1 ≦ x ≦ m-2, and 1 ≦ y ≦ 2 n-2.

The DRAM yield analysis system provided by the invention is used for analyzing the electrical failure data of the DRAM chip and obtaining possible failure reasons, wherein the storage module stores a plurality of failure templates, each failure template corresponds to at least one possible failure reason, after the data input module obtains the electrical failure data of the DRAM chip, the graphic module can process the electrical failure data and mark the electrical failure data in a grid map, the marked grid map can be compared with the plurality of failure templates through the analysis module to obtain at least one failure template matched with the marked grid map, and therefore the possible failure reasons corresponding to the marked grid map can be obtained and output through the output module. By utilizing the DRAM yield analysis system, possible failure reasons can be obtained in time from electrical failure data of the DRAM chip, so that the yield of the DRAM chip is favorably and rapidly improved.

Drawings

FIG. 1 is a schematic plan view of a DRAM chip in one embodiment of the invention.

FIG. 2 is a schematic plan view of a DRAM chip according to another embodiment of the present invention.

FIG. 3 is a diagram illustrating a DRAM yield analysis system according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a grid diagram corresponding to a DRAM chip in one embodiment of the invention.

FIG. 5 is a relational diagram of a failure template, possible failure causes, and a labeled grid graph in one embodiment of the invention.

Description of reference numerals:

100-DRAM chips; 101-an active region; 102-an isolation region; 110-word lines; 120-bit line; 130-a storage capacitor; 10-a first storage array; 20-a second storage array; 30-a controller; 31-a metal layer;

200-grid graph; 201-a first failure template; 202-a second failure template; 203-a third failure template; 204-a fourth failure template; 205-fifth failure template; 206-a sixth failure template; 207-seventh failure template; 208-eighth failure template; 209-ninth failure template; 210-a tenth failure template; 211-eleventh failure template; 212-twelfth failure template;

300-DRAM yield analysis system; 310-a storage module; 320-a data input module; 330-a patterning module; 340-an analysis module; 341-a calculation unit; 342-a comparison unit; 350-output module.

Detailed Description

The following describes the DRAM yield analysis system in further detail with reference to the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Meanwhile, the terms used herein are for the purpose of illustrating embodiments and are not intended to limit the present invention. In this specification, the singular forms should be understood to include the plural forms unless otherwise specified. The use of the terms "comprising" and/or "including" in the specification does not preclude the addition of one or more other compositions, components, steps, operations and/or elements to the specified compositions, components, steps, operations and/or elements.

As used herein, a "unit" or "module" refers generally to a component of the invention, such as logically separable software (computer program), hardware, or an equivalent. Thus, the units in the embodiments of the present invention include not only units in a computer program but also units in a hardware configuration. Thus, this embodiment can also be used as a description of a computer program containing instructions, which can be a program for executing each step in a computer, a program for forming a computer function into each tool, or a program for causing a computer to realize each of the functions, systems, or methods, wherein the computer program starts "unit" or "module". As used herein, the term "apparatus" and/or "system" may include a plurality of computers, hardware, apparatuses, etc. interconnected by a communication unit, such as a network, having a one-to-one corresponding communication connection, or a single computer, hardware, apparatus, etc. having a process for implementing the invention.

The embodiment of the invention provides a DRAM yield analysis system, which is used for analyzing electrical failure data of a DRAM chip and obtaining possible failure reasons so as to improve the yield of the DRAM chip. FIG. 1 is a schematic plan view of a DRAM chip in one embodiment of the invention. Referring to fig. 1, a DRAM chip 100 includes a plurality of active regions 101 and isolation regions 102 for defining the plurality of active regions 101, the DRAM chip 100 further includes a plurality of word lines 110 and a plurality of bit lines 120, each two of the word lines 110 extends along a first direction AB and intersects with a corresponding active region 101, each of the bit lines 120 extends along a second direction a 'B' different from the first direction AB and intersects with a corresponding active region 101, and two memory cells M are disposed corresponding to each of the active regions 101 (the position of each memory cell M is shown by a dashed circle in fig. 2).

In particular, the memory cells M formed in each active area 101 may comprise an access transistor in which the gate electrode is connected to a corresponding word line 110, one of the source/drain regions being connected to a corresponding bit line 120, and the other source/drain region being connected to a corresponding storage capacitor 130, which storage capacitor 130 is typically used for storing charge representative of stored information. As shown in fig. 1, a plurality of memory cells M formed on the DRAM chip 100 may form a first memory array 10, the first memory array 10 may include a plurality of memory cells M arranged in M rows and 2n columns, M and n are integers greater than 0 (hereinafter, values of M and n are the same as those herein), and specific values of M and n may be determined by the size and specific design of the DRAM chip 100.

The DRAM chip 100 of the embodiment of the present invention may also be provided with one or more memory cell arrays. FIG. 2 is a schematic plan view of a DRAM chip according to another embodiment of the present invention. Referring to fig. 2, in another embodiment, a DRAM chip 100 includes a first memory array 10 and a second memory array 20, where the first memory array 10 includes a plurality of memory cells M arranged in M rows and 2n columns, the second memory array 20 includes a plurality of memory cells M arranged in M 'rows and 2n columns, M' is an integer greater than or equal to 0 (hereinafter, values regarding M 'are the same as those herein), and M' and M may be the same or different. For clarity, elements in the second memory array 20 have been given the same reference numerals as the first memory array 10. In other embodiments, a plurality of memory arrays are disposed on the DRAM chip 100, and each memory array may include a different number of rows and/or columns of memory cells, and the structure of the memory cells in each memory array may not be identical.

As shown in fig. 2, in this embodiment, n controllers 30 are disposed between the first memory array 10 and the second memory array 20, the n controllers 30 are disposed corresponding to the multiple columns of the active regions 101 and are respectively electrically connected to the memory cells M of the corresponding columns, that is, each controller 30 is connected to the word lines 110 of the corresponding columns of the first memory array 10 and the second memory array 20, and specifically, each controller 30 is electrically connected to the word lines 110 of the corresponding columns through the metal layer 31 to control the memory cells M of the corresponding columns. The n controllers 30 are isolated from each other. The arrangement of the DRAM chip 100 of the present invention is not limited to the above description, and the DRAM chip 100 may also be arranged with reference to the disclosed technology.

FIG. 3 is a diagram illustrating a DRAM yield analysis system according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a grid diagram corresponding to a DRAM chip in one embodiment of the invention. Referring to fig. 3 and 4, a DRAM yield analysis system 300 according to an embodiment of the present invention includes one or more of the following modules:

a storage module 310 for storing a plurality of failure templates, each of the failure templates corresponding to at least one possible failure cause;

a data input module 320 for acquiring electrical failure data of the DRAM chip 100;

the graphic module 330 is configured to process and mark the electrical failure data in a grid map 200, where a plurality of grids M' in the grid map 200 correspond to a plurality of memory cells M on the DRAM chip 100 one by one;

an analysis module 340, configured to compare the marked grid map 200 with the plurality of failure templates to obtain at least one failure template matching the marked grid map 200, and obtain a possible failure cause corresponding to the marked grid map 200; and

an output module 350 for outputting a possible reason for failure corresponding to the marked grid map 200.

The data input module 320 is used for acquiring electrical failure data of the DRAM chip 100. The electrical failure data refers to information about failed memory cells M in the test result obtained after the electrical test of the DRAM chip 100, wherein the electrical test can obtain information about whether each memory cell M on the DRAM chip 100 has failed by testing the electrical signal applied to the memory cell M. Preferably, the data input module 320 in this embodiment obtains the location information of the failed part of the memory cells M on the DRAM chip 100, so as to obtain the distribution of the failed part of the memory cells M on the DRAM chip 100, so as to compare the distribution with the corresponding failure template to obtain the possible failure cause.

Referring to fig. 4, corresponding to the DRAM chip provided with the first memory array 10, a corresponding grid map 200 includes a plurality of grids M' arranged in M rows and 2n columns, and the grid map 200 may also be stored in the memory module 310. Grid M' in grid diagram 200 may be represented using squares, circles, ovals, triangles, pentagons, hexagons, and the like. The graphic module 330 is used for processing the electrical failure data acquired by the data input module 320 and marking the electrical failure data in the grid map 200. Specifically, the graphic module 330 processes the electrical failure data to obtain the location information of the failed memory cell M on the DRAM chip 100, and then marks the corresponding partial grid M' in the grid map 200, thereby forming the marked grid map 200 (or referred to as an electrical failure map). For example, in the marked grid map 200, the part of the grid corresponding to the failed part of the storage unit is filled with color blocks for identification.

In order to determine the corresponding location of the failed portion of the memory cells M, a coordinate system may be disposed on the grid map 200 to determine the location of each grid M'. Each grid M 'in the grid map 200 may correspond to a defined coordinate, for example, the origin of coordinates O of the grid map 200 may be located at the upper left corner, the abscissa may gradually increase in the left-to-right direction, the ordinate may gradually increase in the top-to-bottom direction, and the coordinate of each grid M' may be defined by the row-column position in the grid map 200. For example, the coordinates of the grid M' corresponding to two memory cells M of the same active region 101 on the DRAM chip 100 are represented as (x, 2y) and (x, 2y +1), respectively, where x, y are integers greater than or equal to 0, and 0 ≦ x ≦ M-1, 1 ≦ 2y +1 ≦ 2n-1 (hereinafter, values for x, y are the same here).

The analysis module 340 is configured to compare the marked grid map 200 with the plurality of failure templates to obtain at least one failure template matching the marked grid map 200, and obtain a possible failure cause corresponding to the marked grid map 200. Specifically, referring to fig. 3, the analysis module 340 may further include a calculation unit 341 and a comparison unit 342, where the calculation unit 341 is configured to calculate the number of marked grids M ' in the marked grid map 200 and the coordinates of the marked grids M ' in the grid map 400, and the comparison unit 342 obtains at least one failure template matching the marked grid map according to the number of marked grids M ' obtained by the calculation unit 341 and the coordinates in the coordinate system, so as to obtain the possible failure cause corresponding to the electrical failure pattern.

The storage module 310 in the embodiment of the present invention is configured to store a plurality of failure templates, each of the failure templates corresponding to at least one possible failure cause. FIG. 5 is a relational diagram of a failure template, possible failure causes, and a labeled grid graph in one embodiment of the invention. The disabling template in the embodiment of the present invention is described in further detail below with reference to fig. 3 and 5.

The plurality of storage templates stored in the storage module 310 may include a first failure template 201, and a possible failure cause corresponding to the first failure template 201 includes a bit contact failure (bit contact fail). Correspondingly, when the marked grid map 200 includes two marked grids M 'and the coordinates of the two marked grids M' in the coordinate system are (x, 2y) and (x, 2y +1), respectively (corresponding to two memory cells M of the same active area), the marked grid map 200 matches with the first invalidation template 201. Thus, it can be concluded that possible causes of failure corresponding to the marked grid map 200 at this time include bit line contact failure, where "bit line contact failure" refers to a malfunctioning bit line contact between two memory cells M corresponding to the two marked grids M'.

The plurality of memory templates stored in the memory module 310 may include a second failure template 202, and the possible failure cause corresponding to the second failure template 202 includes word line's STI fail. Correspondingly, when the marked grid map includes two marked grids M ' and the coordinates of the two marked grids M ' in the coordinate system are (x, y ') and (x +1, y '), respectively, where y ' is an integer greater than or equal to 0 (the value of y ' is the same as here below), for example, the value of y ' may be 2y or 2y +1 (no odd or even columns are defined), the marked grid map 200 is matched with the second failure template 202. Thus, it can be seen that possible causes of failure corresponding to the marked grid map 200 at this time include word line isolation failure, where "word line isolation failure" refers to poor functioning of the isolation region 102 between the two memory cells M corresponding to the two marked grids M', e.g., too many air bubbles in the isolation medium formed by the isolation region 102, resulting in two memory cell isolation failures.

The plurality of storage templates stored in the storage module 310 may include a third failure template 203, and a possible failure cause corresponding to the third failure template 203 includes a diagonal bit line short failure (bit binary fail). Correspondingly, when the marked grid map includes two marked grids M ' and the coordinates of the two marked grids M ' in the coordinate system are (x, 2y +1) and (x +1, 2y), respectively, the marked grid map 200 matches with the third failure template 203, and thus, it can be found that the possible failure cause corresponding to the marked grid map 200 at this time includes a bit line diagonal short failure, where "bit line diagonal short failure" refers to a short circuit occurring between two memory cells M corresponding to the two marked grids M ' located in the corresponding diagonal direction.

The plurality of storage templates stored in the storage module 310 may include a fourth failure template 204, and the possible failure cause corresponding to the fourth failure template 204 includes an active area isolation failure (ground STI fail), and correspondingly, when the marked grid map 200 includes two marked grids M ' and the coordinates of the two marked grids M ' in the coordinate system are (x, 2y +1) and (x +1, 2y +2), respectively, the marked grid map 200 is matched with the fourth failure template 204, so that the possible failure cause corresponding to the marked grid map 200 at this time may be determined to include an active area isolation failure, where "active area isolation failure" refers to a failure of the isolation area 102 between two storage units M corresponding to the marked two grids M ' located in corresponding diagonal directions.

In some embodiments, the marked grid map 200 may include a case where grids M' located in the same row and/or the same column are all marked, and the storage module 310 in this embodiment further stores a storage template corresponding to such marked grid map 200, which is described in detail below.

The memory module 310 may store a fifth failing template 205 and a sixth failing template 206, where possible failure causes corresponding to the fifth failing template 205 include a word line break failure (word line break failure), and possible failure causes corresponding to the sixth failing template 206 include a bit line break failure (bit line break failure).

Correspondingly, when the same row of grids M ' in the marked grid map 200 are all marked, for example, when the marked grid M ' includes (0, y '), (1, y '), (2, y '),. once., (M-1, y ') in the coordinates of the coordinate system, the marked grid map 200 is matched with the fifth failure template 205, and thus, it can be found that the possible failure causes corresponding to the marked grid map 200 at this time include a word line disconnection failure, where "word line disconnection failure" means that the word line 210 corresponding to the corresponding row of grids M ' has a disconnection problem.

When the same row of grid M 'in the marked grid map 200 is marked, for example, the coordinates of the marked grid M' in the coordinate system include (x, 0), (x, 1), (x, 2),. ·, (x, 2n-1), the marked grid map 200 matches the sixth failure template 206. Thus, it can be seen that the possible failure causes corresponding to the marked grid map 200 at this time include bit line break failures (bit line break failures), where "bit line break failure" means that the bit lines 220 corresponding to the corresponding row grid M' have a broken line problem.

In some embodiments, the marked grid M 'in the marked grid map 200 has more than one row, for example, the grid map 200 may include a case where the grids M' in two adjacent rows and/or two columns are marked, and the storage module 310 in this embodiment also includes a failure template corresponding to such a case.

Specifically, the storage module 310 may further store a seventh failure template 207, where a possible failure cause corresponding to the seventh failure template includes a word line short failure (word line short fail). Correspondingly, when two adjacent columns of the grid M 'in the marked grid map 200 are marked, for example, the coordinates of the marked grid M' in the marked grid map 200 in the coordinate system include (0, y '), (1, y'), (2, y '), (M-1, y') and (0, y '+1), (1, y' +1), (2, y '+1),. lograph., (M-1, y' +1), the marked grid map 200 is further matched with the seventh failure template 204. Thus, it can be seen that the possible reasons for failure corresponding to the marked grid map 200 at this time also include word line short failure, where "word line short failure" means that a short problem has occurred between two word lines 210 corresponding to the respective two columns of grid M'.

The storage module 310 may further store an eighth failure template 208, and possible failure causes corresponding to the eighth failure template 208 include bit line short fail (bit line short fail). When two adjacent rows of grid M 'in the marked grid map 200 are marked, for example, the marked grid M' in the marked grid map 200 includes (x, 0), (x, 1), (x, 2), (1.), (x, 2n-1) and (x +1, 0), (x +1, 1), (x +1, 2), (x +1, 2n-1) in the coordinate system, the marked grid map 200 is further matched with the eighth failure template 208. Thus, it can be seen that the possible reasons for the failure corresponding to the marked grid map 200 at this time also include a bit line short failure, where "bit line short failure" means that a short problem is generated between two bit lines 220 corresponding to the respective two rows of grids M'.

The storage module 310 may further store a ninth failure template 209, and possible failure causes corresponding to the ninth failure template 209 include cross short failures (cross fail). Correspondingly, when the same row and the same column of grids in the marked grid map 200 are marked, for example, the coordinates of the marked grid M ' in the marked grid map 200 in the coordinate system include (0, y '), (1, y '), (2, y '),. once., (M-1, y ') and (x, 0), (x, 1), (x, 2),. once., (x, 2n-1), the marked grid map 200 is further matched with the ninth failure template 209. Thus, it can be seen that the possible causes of failure corresponding to the marked grid map 200 at this time also include cross-short failures, where "cross-short failure" means that the bit lines 220 corresponding to the respective row grid M 'and the word lines 210 corresponding to the respective column grid M' both create a short problem.

In another embodiment of the present invention, referring to fig. 2, in a DRAM chip 100 that can be provided with more than one array, for example, a first memory array 10 and a second memory array 20, the electrical failure data to be analyzed further includes electrical failure data related to a memory cell M in the second memory array 20, and the grid map 200 of the embodiment of the present invention can also include a plurality of grids M 'corresponding to the plurality of memory cells M in the second memory array 20 one by one, specifically, corresponding to the first memory array 10 and the second memory array 20, and the grid map 200 can include a plurality of grids M' arranged in (M + M ') rows and 2n columns, where the grids M' correspond to the plurality of memory cells M one by one. Between the (M-1) th row and the (M) th row, word lines 210 in the two memory arrays corresponding to the grid M' of the spaced columns are connected to each other through the controller 30. The memory module 310 of embodiments of the present invention may further include a failure template associated with a connection between a plurality of memory arrays, as described in more detail below.

The storage module 310 may further store a tenth failure template 210, where possible failure reasons corresponding to the tenth failure template 210 include a single word line fail (single word line fail) of the controller. Correspondingly, when the grids M' located in the same column and continuously exceeding the first preset value in the marked grid map 200 are all marked, for example, when the coordinates of the marked grid M ' in the above-mentioned coordinate system include (0, y '), (1, y '), (2, y '),. once., (M-1, y '),. once., (x ', y '), wherein x 'is an integer greater than 0 and m-1 ≦ x' ≦ m + m '-1 (hereinafter, values for x' are the same as here), the marked grid map 200 is also matched with the tenth failure template 210, so that the possible failure reasons corresponding to the marked grid map 200 at this time can be obtained to further include a controller and word line connection failure, where "controller and word line connection failure" refers to a problem that a connection failure (i.e., open circuit) is generated in the metal layer 31 process between the word line 210 and the controller 30 corresponding to the corresponding column grid M'. Wherein the first preset value can be set by an input module (component) additionally provided in the DRAM yield analysis system 300, and the first preset value is generally larger than M (i.e. the number of marked grids M' of the corresponding columns exceeds the number of rows of the first memory array 10) for the case that the marked grid map 200 corresponds to a plurality of arrays.

The storage module 310 may further store an eleventh failure template 211, where a possible failure cause corresponding to the eleventh failure template 211 includes a short circuit failure (local line fail) between controllers. Correspondingly, when the grids M' located in the spaced columns in the marked grid map 200 are all marked, for example, when the coordinates of the marked grid M ' in the marked grid map 200 in the above coordinate system include (0, y '), (1, y '), (2, y '),. talka., (M-1, y '),. talka., (x ', y ') and (0, y ' +2), (1, y ' +2), (2, y ' +2),. talka., (M-1, y ' +2),. talka., (x ', y ' +2), the marked grid map 200 also matches the eleventh failure template 211, and thus, it can be seen that the possible reasons for failure corresponding to the labeled grid map 200 at this time also include inter-controller short circuit failure, where "inter-controller short circuit failure" refers to a problem in which a short circuit is generated between the controllers 30 corresponding to the respective two (or more) columns of the grid M'.

In addition, in this embodiment, the storage module 310 may further store a twelfth failure template 212, and a possible failure cause corresponding to the twelfth failure template 212 includes a block fail (open failure) of a storage unit. Correspondingly, when the marked grid map 200 includes adjacent grids M 'whose number exceeds the second predetermined value, the marked grid map is matched with the twelfth failure template, wherein coordinates of the marked grid M' in the marked grid map 200 in the coordinate system are (x ", y"), where x "and y" are both integers greater than 0, and 1 ≦ x "≦ M-2, 1 ≦ y" ≦ 2 n-2. The possible failure causes corresponding to the marked grid pattern 200 include open circuit failure of memory cells, and the term "open circuit failure of memory cells" refers to a problem that when a capacitor of a DRAM chip is manufactured, a barrier layer at the bottom of an opening area of the capacitor is not completely etched, so that a plurality of adjacent memory cells are opened and fail.

Corresponding to the twelfth failure template 212, the memory cells M corresponding to the grid M' located at least one turn around the outer periphery of the grid map 200 are not included in the calculation range, so as to exclude the case where the entire memory cells are failed (which may correspond to the seventh failure template or the eighth failure template). The second preset value may be set by an input module (component) additionally provided in the DRAM yield analysis system 300, and is usually set to a value greater than 2, and more preferably, the second preset value includes the number of marked grids M 'distributed in both directions of the horizontal axis and the vertical axis of the coordinate system, and further, the number of marked grids M' in both directions may be set to be greater than 2.

The arrangement of the memory cells M of the DRAM chip 100 that fail after electrical testing may include various forms, and correspondingly, the arrangement of the marked grids M' in the grid map 200 may not be limited to the above listed types, and the failure templates and the corresponding possible failure reasons corresponding to the marked grid map 200 obtained by the DRAM yield analysis system 300 of the present invention are not limited to the above description. In some embodiments, the distributions of the corresponding marked grids M' in the storage templates may be superimposed, and the marked grid map 200 may be matched with the various storage templates, so that more than one possible failure cause corresponding to the marked grid map 200 may be obtained by the analysis module 340.

The output module 350 is used for outputting the possible failure reasons corresponding to the marked grid map obtained by the analysis module 340. The output module 350 may output the possible reasons for failure corresponding to the marked grid map to a terminal, such as a display or a computer system having a display. The possible failure reasons corresponding to the electrical failure patterns can be displayed in one or more forms of characters, images or voice. The output module 350 may also output the electrical failure data acquired by the data input module 320 and the marked grid map 200 processed by the graphic module 330 to the terminal, so that an operator can intuitively know the failure condition of the memory cell on the DRAM chip and the corresponding possible failure reason.

The DRAM yield analysis system can improve the data analysis efficiency and timely obtain the possible failure reasons by acquiring the electrical failure data of the DRAM chip, carrying out graphical processing, calculation and analysis and outputting the corresponding possible failure reasons. For operators with less experience, the DRAM yield analysis system can also obtain possible failure reasons of the DRAM chip from a large amount of electrical failure data, and is favorable for popularization and application in production and experiments. In addition, the electrical failure data of the DRAM chip are analyzed and possible failure reasons are obtained in time, so that the efficiency of process improvement and verification is improved, and the yield of the DRAM chip is improved rapidly.

The implementation of the DRAM yield analysis system in the above embodiments is generally implemented in a software program manner in cooperation with a device or an apparatus, however, all (or a part) of them may also be implemented in an electronic hardware manner, and whether in a software or hardware manner, individual parts thereof may be implemented by persons skilled in the electronic and software arts, and therefore, the details thereof are not repeated in this specification.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims

1. A DRAM yield analysis system for analyzing electrical failure data of a DRAM chip and obtaining possible failure reasons, wherein the DRAM chip comprises a plurality of active regions and isolation regions for limiting the active regions, the DRAM chip further comprises a plurality of word lines and a plurality of bit lines, every two word lines extend along a first direction and intersect with the corresponding active regions, every bit line extends along a second direction different from the first direction and intersects with the corresponding active regions, each active region is provided with two memory cells, the DRAM yield analysis system comprises:

a storage module for storing a plurality of failure templates, each of the failure templates corresponding to at least one possible failure cause;

the data input module is used for acquiring electrical failure data of the DRAM chip;

the graphic module is used for processing the electrical failure data and marking the electrical failure data in a grid graph, wherein a plurality of grids in the grid graph correspond to a plurality of storage units on the DRAM chip one by one;

an analysis module, configured to compare the marked grid map with the plurality of failure templates to obtain at least one failure template matching the marked grid map, and obtain a possible failure cause corresponding to the marked grid map; and

an output module for outputting a possible reason for failure corresponding to the marked grid map.

2. The DRAM yield analysis system of claim 1, wherein the electrical failure data comprises location information of failed memory cells on the DRAM chip, the graphics module marks the grid corresponding to the failed memory cells in the grid map, and a coordinate system is disposed on the grid map to determine a location of each grid.

3. The DRAM yield analysis system of claim 2, wherein the grid corresponding to the failed memory cell in the marked grid map is filled with color blocks.

4. The DRAM yield analysis system of claim 2, wherein the analysis module comprises:

a calculation unit for calculating the number of marked grids in the marked grid map and the coordinates of the marked grids in the coordinate system; and

and the comparison unit is used for obtaining at least one failure template matched with the marked grid graph according to the number of the marked grids and the coordinates in the coordinate system.

5. The DRAM yield analysis system of claim 2, wherein a first memory array is disposed on the DRAM chip, the first memory array comprising a plurality of the memory cells arranged in m rows and 2n columns, the grid map comprising a plurality of grids arranged in m rows and 2n columns; coordinates of two storage units arranged in the same active region in the coordinate system are (x, 2y) and (x, 2y +1), respectively, where m, n, x, and y are integers greater than or equal to 0, and 0 ≦ x ≦ m, and 0 ≦ y ≦ n.

6. The DRAM yield analysis system of claim 5, wherein the storage module stores a first failure template, and the possible failure causes corresponding to the first failure template comprise bit line contact failures; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y) and (x, 2y +1), respectively, the marked grid map matches the first failure template.

7. The DRAM yield analysis system of claim 5, wherein the memory module has stored therein a second failure template, wherein the possible causes of failure corresponding to the marked grid map include word line isolation failures; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, y ') and (x +1, y '), respectively, the marked grid map matches the second failure template, where y ' is an integer greater than or equal to 0.

8. The DRAM yield analysis system of claim 5, wherein the storage module stores a third failure template, and the possible failure causes corresponding to the third failure template comprise diagonal bit line short circuit failures; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y +1) and (x +1, 2y), respectively, the marked grid map matches the third failure template.

9. The DRAM yield analysis system of claim 5, wherein the storage module stores a fourth failure template, and possible failure causes corresponding to the fourth failure template include active area isolation failures; when the marked grid map includes two marked grids and the coordinates of the two marked grids are (x, 2y +1) and (x +1, 2y +2), respectively, the marked grid map matches the fourth failure template.

10. The DRAM yield analysis system of claim 5, wherein the memory module stores a fifth failure template and a sixth failure template, wherein the possible failure cause corresponding to the fifth failure template comprises a word line disconnection failure, and the possible failure cause corresponding to the sixth failure template comprises a bit line disconnection failure; and the number of the first and second electrodes,

when the grids in the same column in the marked grid map are marked, the marked grid map is matched with the fifth failure template;

when the grids in the same row in the marked grid map are marked, the marked grid map is matched with the sixth failure template.

11. The DRAM yield analysis system of claim 10, wherein the memory module has a seventh failure template stored therein, wherein the possible causes of failure corresponding to the seventh failure template include word line short failures; when two adjacent columns of grids in the marked grid map are marked, the marked grid map is also matched with the seventh failure template.

12. The DRAM yield analysis system of claim 10, wherein the memory module stores an eighth failure template, and the possible causes of failure corresponding to the eighth failure template include bit line short circuit failures; when two adjacent rows of grids in the marked grid map are both marked, the marked grid map is also matched with the eighth failure template.

13. The DRAM yield analysis system of claim 10, wherein the storage module stores a ninth failure template, and the possible failure cause corresponding to the ninth failure template comprises a cross-short failure; when the same row and column of grids in the marked grid map are both marked, the marked grid map is also matched with the ninth failure template.

14. The DRAM yield analysis system of claim 5, wherein a second memory array is further disposed on the DRAM chip, the second memory array comprising a plurality of the memory cells arranged in m' rows and 2n columns, wherein n controllers are disposed between the first memory array and the second memory array, each controller connecting two of the word lines of a corresponding column of the first memory array and the second memory array; the grid map includes a plurality of the grids arranged in (m + m ') rows and 2n columns, m' being an integer greater than or equal to 0.

15. The DRAM yield analysis system of claim 14, wherein the memory module has a tenth failure template stored therein, and wherein the possible causes of failure corresponding to the tenth failure template include a failure in connection between the controller and a word line; when grids which are positioned in the same column and continuously exceed a first preset value in the marked grid map are marked, the marked grid map is also matched with the tenth failure template, and the first preset value is larger than m.

16. The DRAM yield analysis system of claim 14, wherein an eleventh failure template is stored in the storage module, and wherein the possible causes of failure corresponding to the eleventh failure template include short circuit failure between controllers; when the grids in the marked grid map at the spacing columns are all marked, the marked grid map is also matched with the eleventh failure template.

17. The DRAM yield analysis system of claim 5, wherein the memory module stores a twelfth failure template, and the possible failure causes corresponding to the twelfth failure template comprise open circuit failures of memory cells; when the marked grid graph comprises adjacent grids, the number of which exceeds a second preset value, and the marked grid graph is marked, the marked grid graph is matched with the twelfth failure template, wherein the coordinates of the marked grid graph are (x '', y ''), wherein x '' and y '' are integers larger than 0, and 1 ≦ x '' ≦ m-2, and 1 ≦ y '' ≦ 2 n-2.