JP2005122529A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a capacity of a RAM storing logical-physical translation table and to maximize an effectively available data area in a non-volatile memory in a mass storage semiconductor memory device. <P>SOLUTION: The non-volatile memory 103 is divided into four physical areas A-D to be controlled. The logical-physical translation tables used for translating a logical address into a physical address in a plurality of logical address ranges matching the respective physical areas are stored in logical-physical translation table blocks 104-107 in the respective physical areas. A volatile memory 101 stores at least one of a plurality of logical-physical translation tables. A control part 503 performs translation to the physical address by using the logical-physical translation table within the logical address area matching a given logical address. In this process, the logical address area (2007block) managed by the logical-physical translation table is decided as a value securing a predetermined good block ratio (98% or more, for example) for each physical area. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory device using a semiconductor, and more particularly to a semiconductor memory device such as a memory card using a nonvolatile memory (flash memory or the like) as a semiconductor memory.

  A conventional semiconductor memory device generally includes a controller 506 and a non-volatile memory 507 as shown in FIG. 4, and reads / writes data in accordance with a read / write instruction from the host 501. The controller 506 includes a host interface 502, a nonvolatile memory interface 505, a control unit 503 that performs read / write control, a conversion table that converts a logical address to a physical address of the nonvolatile memory 507 (hereinafter referred to as a logical-physical conversion table, And a volatile memory (RAM) 504 that stores a conceptual diagram corresponding to FIG. The logical address is an address designated by the host 501 and designates a storage location in the logical space. The physical address designates a physical storage location defined on the nonvolatile memory 507. To do. In addition, the logical-physical conversion table is provided in order to avoid rewriting concentration (rewriting only a specific physical address) with respect to rewriting restrictions (usually about 100,000 times of life) of the nonvolatile memory (flash memory) 507. It has been. By the way, this avoidance is called wear leveling. As illustrated in FIG. 5, the logical-physical conversion table 601 associates actual physical addresses on the nonvolatile memory with logical addresses 0 to 8027 with 13 bits b0 to b12. Here, although the physical space of the nonvolatile memory has 8192 blocks, 8028 blocks are allocated as the logical space. The reason will be described below.

  In general, a non-volatile memory includes a block that is already defective when shipped from the factory and a block that becomes defective due to subsequent use. The probability of occurrence varies depending on the flash memory, but here the entire nonvolatile memory is assumed to be, for example, 2% or less. The defective block is subjected to substitution processing that is managed by replacing it with the good block. Therefore, it is necessary to secure a block for alternative processing as a margin.

  Therefore, in the example shown in FIGS. 4 and 5, the margin of 8192 blocks × 0.02≈164 blocks is secured, and the number of usable blocks is 8192-164 = 8028 blocks.

  On the other hand, with the recent increase in capacity of memory cards, the size of the logical / physical conversion table for managing the non-volatile memory (flash memory) has become a cost issue. A method that can reduce the size of the memory (RAM) 504 has been proposed (see, for example, Patent Document 1).

  FIG. 6 shows the points of the invention described in Patent Document 1. A significant difference from the semiconductor memory device shown in FIG. 4 is that a logical / physical conversion table (logical / physical conversion table blocks 304 to 307) is stored in a nonvolatile memory (flash memory) 303 for each logical address range in the logical space. The logical-physical conversion table in the physical area corresponding to the logical address instructed by the host 501 is read into the volatile memory (RAM) 301 and converted, and then the desired data is stored in the nonvolatile memory. The data is stored in a desired physical address of (flash memory) 303. Each logical address range is divided into a nonvolatile memory (flash memory) 303 corresponding to the physical area A ′ to the physical area D ′. The size of the volatile memory (RAM) 301 can be reduced by dividing and managing the nonvolatile memory (flash memory) 303 for each logical address range. Here, the physical address is a physical address of an erase block which is an erase unit, and one block is 16 KB. The total size of the nonvolatile memory (flash memory) 303 is 128 MB. Therefore, when the physical space is represented by the number of blocks, it is 8192 blocks, and the size of each of the physical area A ′ to the physical area D ′ is 2048 blocks. In consideration of a margin for a defective block, the number of logical blocks is 1883 with respect to the number of physical blocks (2048 blocks) in the physical area A ′ to the physical area D ′.

Accordingly, as shown in FIG. 7, in the logical-physical conversion table 401, 11-bit physical addresses b0 to b10 are associated with logical addresses 0 to 1882. Therefore, the logical-physical conversion table 601 shown in FIG. 5 is 8028 × 13 bits, whereas the logical-physical conversion table 401 can be significantly reduced to 1883 × 11 bits.
JP 2001-142774 A

  However, by dividing and managing the nonvolatile memory as in the conventional semiconductor memory device shown in FIGS. 6 and 7, the size of the logical-physical conversion table can be reduced, and the volatile memory (RAM) for storing it can be reduced. There is a problem that the logical space of the nonvolatile memory for storing data becomes small. The reason will be described below.

  For example, in the entire nonvolatile memory (flash memory) 303, it is assumed that the occurrence rate of defective blocks is 2% or less. That is, there is a possibility that a maximum of 2% of the total number of blocks will be defective blocks by the rewrite life (usually about 100,000 cycles). In order to avoid such a state, generally, a means for replacing a defective block, that is, a means for rewriting a block determined to be a defective block at the time of writing into a good block is taken. The area of this alternative block may be provided in a specific physical fixed area (not shown) in the nonvolatile memory (flash memory) 303. Since the frequency of rewriting increases and this is not preferable in terms of wear leveling, it is preferable to perform alternative management for each of the physical areas A ′ to D ′. For this reason (because the margin of the alternative block is taken), the number of physical blocks in the physical area A ′ to physical area D ′ is 2048 and the number of logical blocks is as small as 1883. Here, the calculation standard is 1883. In the case where 2% is guaranteed for the entire nonvolatile memory (flash memory) 303, for example, only 2% of the defective blocks are generated only in the physical area A ′. Therefore, the logical address size corresponding to each physical area is equal to the number of blocks obtained as 8192 blocks × 0.02≈164 blocks. A margin is taken in the physical area, resulting in 1883 blocks (2048- (164 + 1) = 1888). Note that the addition for one block requires a data area corresponding to the number of blocks for the logical-physical conversion table. As a result, the data area (logical space for storing data), which is 8028 blocks in the example shown in FIG. 4, becomes 1883 × 4 = 7532 blocks.

  An object of the present invention is to provide a semiconductor memory device in which a logical space for storing data is increased while reducing the size of a logical-physical conversion table.

  In order to achieve the above object, the present invention provides a semiconductor memory device for controlling a nonvolatile memory by dividing it into a plurality of physical areas, wherein physical addresses are physically allocated in a plurality of logical address ranges corresponding to the plurality of physical areas. A plurality of logical-physical conversion tables used for conversion to an address and stored in each physical area; a volatile memory in which an area for storing at least one of the plurality of logical-physical conversion tables is secured; and a logical address Logical-address range logical-physical conversion table corresponding to the logical address range, and a logical-physical conversion means for converting the physical address into a physical address. The logical address range is determined by the good block rate guaranteed for each physical area. Is.

  According to the present invention, a logical block range (number of logical blocks) determined so as to guarantee a predetermined good block rate is associated with each physical area obtained by dividing the nonvolatile memory (flash memory). Can be made larger than the desired value, and the logical space of the nonvolatile memory (flash memory) for storing data can be made larger.

According to a first aspect of the present invention, there is provided a semiconductor memory device for controlling a nonvolatile memory by dividing it into a plurality of physical areas, wherein a logical address is assigned in a plurality of logical address ranges corresponding to the plurality of physical areas. A plurality of logical-physical conversion tables used for conversion into physical addresses and stored in each physical area; a volatile memory in which an area for storing at least one of the plurality of logical-physical conversion tables is secured; Logical-to-physical conversion means for converting into a physical address using a logical-to-physical conversion table corresponding to a logical address range when a logical address is given,
The logical address range is determined by a good block rate guaranteed for each physical area.

  The invention according to claim 2 is characterized in that, in the above invention, the plurality of physical areas have substantially the same size, and the replacement processing of the defective block is performed within each logical address range.

  In the invention according to claim 3, in the above invention, when the number of blocks in the physical area is PB, the guaranteed bad block rate is R, and the coefficient is α, the logical address range is approximately PB × (1− R × α), and the coefficient α is characterized in that the number of blocks in the entire physical space / PB = N >> α ≧ 1, and is determined based on the defective block distribution in the entire physical space.

  As a result, the logical address range in consideration of the defective block distribution can be obtained while reducing the size of the logical-physical conversion table, so that the logical space for storing data can be expanded.

  Hereinafter, semiconductor memory devices according to embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device according to this embodiment includes a controller 102 and a nonvolatile memory 103, and data is read and written in accordance with instructions from the host 501.

  The controller 102 uses a volatile memory (RAM) 101 that stores at least one logical-physical conversion table, a host interface 502 that transmits / receives commands and data to / from the host 501, a read / write control based on commands, and a logical-physical conversion table. A control unit 503 that operates as a conversion unit that converts a logical address into a physical address, and a nonvolatile memory interface 505 that transmits and receives data to and from the nonvolatile memory 103.

  The nonvolatile memory 103 is managed by being divided into a plurality of physical areas. In the example of FIG. 1, all the physical space 8192 blocks of the nonvolatile memory 103 are equally divided into four 2048 blocks of physical areas (sections separated by broken line arrows on the physical space side). The physical / physical conversion table blocks 104 to 107 are allocated to each physical area. In FIG. 1, a section divided into four by broken line arrows on the logical space side is a logical address range, and is a range managed by one logical-physical conversion table. Further, each physical area is a guaranteed range of good blocks, and substitution processing performed when a defective block exists is performed within each logical address range.

  FIG. 2 is a conceptual diagram showing the format of the logical / physical conversion table stored in the logical / physical conversion table blocks 104 to 107. Reference numeral 201 denotes a logical-physical conversion table, and 11 bits (b0 to b10) of physical addresses are assigned corresponding to logical addresses of 0 to 2006.

  The non-volatile memory 103 is divided into four physical areas (physical area A to physical area D), and the defective block rate is less than or equal to a predetermined value (for example, 2% or less) for each physical area. Guaranteed. In other words, if the flash memory manufacturer divides into areas where the defective block rate can guarantee 2% or less, for example (in this case, 4 divisions), one area becomes 2048 physical block addresses. When a defective block is generated by a writing process or the like in these areas, the replacement process is performed for each of the physical areas A to D as described above. Therefore (because the margin of the substitute block is taken), the number of physical blocks in the physical area A to physical area D is 2048, and the number of logical blocks is 2007.

  That is, when the number of blocks in the target physical area PB = 2048, the guaranteed bad block rate R = 0.02 (2%), and the coefficient α = 1, the logical address range (the number of logical blocks) is PB X (1−R × α) = 2048 × (1−0.02 × 1) ≈2007. The coefficient α is the number of blocks in the entire physical space / PB = N >> α ≧ 1, and is determined based on the defective block distribution in the entire physical space. In the example shown in FIG. 1, N = 8192/2048 = 4 >> α ≧ 1, and takes a value of 1 or more and less than 4.

  This α is determined based on the defective block distribution. For example, as shown in (a) to (c) of FIG. 3, the defective block ratio that can be guaranteed in each physical area is 1% in all areas, although the average defective block ratio is 2% or less. ,to differ greatly. Therefore, the coefficient α is determined in consideration of this defective block distribution. In FIG. 3A, since the defect rate of one physical area is greatly deviated to be slightly less than 8%, α≈4 is approximately the worst value, and the difference from the conventional one is reduced. On the other hand, in FIG. 3B, since the dispersion is medium, it is possible to determine the logical address range to be guaranteed with α≈1.5. Further, in FIG. 3C, since averaging is performed, α≈1 can be set. This coefficient is determined by the type of flash memory manufacturer, flash memory, and the like.

  As described above, according to the present embodiment, a logical address range determined to guarantee a predetermined good block rate (bad block rate = 2%) for each physical area obtained by dividing the nonvolatile memory 103 into four. Therefore, the logical space of the non-volatile memory 103 for storing data can be increased from the conventional 1883 block to the 2007 block while the good block ratio is set to a desired value or more.

  In FIG. 1, the logical address range (the range managed by one logical-physical conversion table) and the physical area are associated one-to-one, but one logical address range may be associated with a plurality of physical areas. Further, an area for a logical-physical conversion table may be provided separately.

  The semiconductor memory device according to the present invention is particularly useful for a memory card or the like using a large-capacity nonvolatile memory (flash memory), and the size of a volatile memory (RAM) for storing a logical-physical conversion table is reduced. This contributes to the maximization of the logical space (effective use area) of the nonvolatile memory (flash memory).

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. Conceptual diagram showing a logical-physical conversion table of the semiconductor memory device Conceptual diagram showing an example of a defective block distribution considered when determining the logical address range of the semiconductor memory device The block diagram which shows the structure of the conventional semiconductor memory device Conceptual diagram showing a logical-physical conversion table of a conventional semiconductor memory device The block diagram which shows the structure of the conventional semiconductor memory device Conceptual diagram showing a logical-physical conversion table of a conventional semiconductor memory device

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Volatile memory 102 Controller 103 Non-volatile memory 104-107 Logical-physical conversion table block 501 Host 502 Host interface 503 Control part 505 Non-volatile memory interface

Claims (3)

A semiconductor memory device for controlling a nonvolatile memory by dividing it into a plurality of physical areas,
A plurality of logical-physical conversion tables used when converting logical addresses into physical addresses in a plurality of logical address ranges corresponding to the plurality of physical areas, and stored in each physical area;
A volatile memory in which an area for storing at least one of the plurality of logical-physical conversion tables is secured;
Logical-to-physical conversion means for converting into a physical address using a logical-to-physical conversion table corresponding to a logical address range when a logical address is given,
The semiconductor memory device, wherein the logical address range is determined by a good block rate guaranteed for each physical area. 2. The semiconductor memory device according to claim 1, wherein the plurality of physical areas have substantially the same size, and the replacement processing of a defective block is performed within each logical address range. When the number of blocks in the physical area is PB, the guaranteed bad block rate is R, and the coefficient is α, the logical address range is approximately PB × (1−R × α), and the coefficient α is the total physical space. 3. The semiconductor memory device according to claim 1, wherein the number of blocks / PB = N >> α ≧ 1 and is determined based on a defective block distribution in the entire physical space.

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