JP2005117680A - Image signal coding method and device, image signal transmission method and decoding method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remove error of DCT (Discrete Cosine Transformation) process or the like due to real number calculation and enable reversible encoding. <P>SOLUTION: An input picture signal is predictively coded with a calculation section 53, is applied with a DCT process in a DCT circuit 56, is quantized in a quantization circuit 57, and is variable-length-coded in a variable-length coding circuit 58 to extract an output bit stream. And a signal S2 obtained by reverse-quantizing the output from the quantization circuit 57 in a reverse-quantization circuit 60 and by reverse-DCT processing it with an IDCT circuit 61 is subtracted from a signal S1 before the DCT process, and the obtained subtraction output is variable-length-coded in a variable-length coding circuit 71 to be extracted as a subtraction bit stream. When decoding, a signal decoded from the output bit stream is added with a signal decoded from the subtraction bit stream to obtain a highly accurate original image picture signal to realize the reversible encoding. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image signal encoding method and apparatus, an image signal transmission method, an image signal decoding method and apparatus, and a recording medium, and in particular, records a moving image signal on a recording medium such as a magneto-optical disk or a magnetic tape, Alternatively, an image signal encoding method and apparatus, an image signal transmission method, an image signal decoding method and apparatus, and a recording medium that are suitable for use when the moving image signal is transmitted through a transmission path and the moving image signal is reproduced. About.

  For example, in a system that transmits a moving image signal to a remote place such as a video conference system and a video phone system, in order to efficiently use a transmission path, the line correlation of video signals and the correlation between frames are used. An image signal is compressed and encoded.

  When line correlation (two-dimensional correlation) is used, signal power can be concentrated on a specific frequency component by, for example, DCT (Discrete Cosine Transform) processing of an image signal, and can be compressed thereby. .

  In addition, when the correlation between frames (or fields) is used, the image signal can be further compressed and encoded. That is, since images of frames that are temporally adjacent do not have such a large change, when the difference between them is calculated, the difference signal has a small value. Therefore, if this difference signal is encoded, the code amount can be compressed.

  However, if only the differential signal is transmitted, the original image cannot be restored. Therefore, the image of each frame is set to any one of three types of pictures of I picture, P picture, and B picture, and the image signal is compressed and encoded.

  Such a compression technique is used as an MPEG (Moving Picture Image Coding Experts Group) encoding standard. MPEG is discussed in ISO-IEC / JTC1 / SC2 / WG11 and proposed as a standard proposal, which combines motion-compensated prediction coding and discrete cosine transform (DCT) coding. It is a hybrid system. For example, it is proposed in the specification and drawings of US application USP 5,155,593 (DATE OF PATENT: October 13, 1992) by the present applicant.

  For example, an image signal of 17 frames from frames F1 to F17 is a group of picture (hereinafter referred to as GOP), and this is a unit of processing. The image signal of the first frame F1 is encoded as an I picture, the second frame F2 is encoded as a B picture, and the third frame F3 is encoded as a P picture. Hereinafter, the fourth and subsequent frames F4 to F17 are alternately processed as a B picture or a P picture.

  As an image signal encoded as an I picture, the image signal for one frame (or field) is transmitted as it is. On the other hand, an image signal encoded as a P picture basically transmits a difference from an image signal of an I picture or P picture preceding in time. Further, for an image signal encoded as a B picture, basically, a difference from an average value of both a temporally preceding frame and a succeeding frame is obtained, and the difference is encoded.

  As described above, when a moving image signal is encoded, the first frame F1 is processed as an I picture, and thus is transmitted as transmission data to a transmission path as it is (intra-image encoding). In contrast, since the second frame F2 is processed as a B picture, basically, the difference between the temporally preceding frame F1 and the average value of the temporally following frame F3 is calculated. The difference is transmitted as transmission data.

  However, there are four types of encoding processing as a B picture in more detail. The first process is to transmit the original frame F2 data as it is as transmission data (intra coding, intra-picture prediction coding), and is the same process as in the case of an I picture. The second process is to calculate a difference from a temporally subsequent frame F3 and transmit the difference (backward predictive coding). The third process is to transmit a difference from the temporally preceding frame F1 (forward predictive coding). Further, the fourth process is to generate a difference between the average value of the temporally preceding frame F1 and the succeeding frame F3 and transmit this as transmission data (bidirectional predictive coding).

  Of these four methods, the method with the least amount of transmission data is employed.

  When the difference data is transmitted, the motion vector x1 (the motion vector between the frames F1 and F2 in the case of forward prediction) between the frame image (predicted image) whose difference is to be calculated, or x2 ( In the case of backward prediction, the motion vector between frames F3 and F2) or both x1 and x2 (in the case of bidirectional prediction) are transmitted along with the difference data.

  Also, a frame F3 of a P picture basically uses a temporally preceding frame F1 as a predicted image, a difference signal from this frame, and a motion vector x3 are calculated and transmitted as transmission data (forward prediction) Coding).

  However, there are two types of encoding processing as the P picture. The first process is to transmit a difference from the temporally preceding frame F1 as described above (forward prediction coding). In the second process, the data of the original frame F3 is transmitted as transmission data as it is (intra coding, intra-picture prediction coding). Which method is used for transmission is selected, as in the case of a B picture, where transmission data is smaller.

JP 63-045684 A Japanese Patent Laid-Open No. 01-305666 Japanese Patent Laid-Open No. 06-343171

  By the way, according to the conventional image signal encoding and decoding method and apparatus, transform coding using transform such as DCT (Discrete Cosine Transform) is performed. This DCT process is a real number calculation, but when an actual DCT circuit is used, the calculation is terminated with a finite word length. Therefore, in the DCT circuit and the IDCT (Inverse Discrete Cosine Transform) circuit, when the IDCT process is performed after the DCT process, part of the original signal information is lost.

  Therefore, when real number arithmetic such as DCT is used in the encoding / decoding device, lossless encoding cannot be realized. Lossless encoding is a technique required when a highly accurate image signal is required.

  The present invention has been made in view of such a situation, and makes it possible to realize lossless encoding even in image signal encoding / decoding using real number arithmetic such as DCT.

  According to the present invention, in order to solve the above-described problem, in an image signal encoding method for quantizing a signal obtained by performing an encoding process with real number operation on an image signal and outputting the quantized signal The feature is that the locally decoded data of the encoded data is compared with the data before the real number calculation and the difference is extracted.

  That is, the image signal encoding method according to the present invention involves a real number operation for an input image signal in an image signal encoding method for outputting a signal obtained by performing an encoding process with a real number operation on an image signal. Comparing the step of performing encoding processing and generating encoded data, the step of locally decoding the encoded data and generating data by local decoding, and the local decoded data and the image data before performing the real number operation And a step of calculating the difference.

  An image signal encoding apparatus according to the present invention is an image signal encoding apparatus that outputs a signal obtained by performing an encoding process with a real number operation on an image signal. Comparing means for performing encoding processing and generating encoded data, means for locally decoding the encoded data and generating data by local decoding, and the local decoded data and the image data before performing the real number operation And means for calculating the difference.

  In addition, an image signal transmission method according to the present invention is an image signal transmission method for transmitting a signal obtained by performing an encoding process with a real number operation on an image signal, and encoding an input image signal with a real number operation. Performing a process to generate encoded data, comparing the step of locally decoding the encoded data and generating data by local decoding, and comparing the local decoded data and the image data before performing the real number operation, A step of calculating the difference and transmitting difference data.

  The recording medium according to the present invention is a recording medium decodable by a decoding device, wherein the recording medium records a recording signal decodable by the decoding device, and the recording signal is a real number operation on an input image signal. A process of generating encoded data by performing an encoding process, a process of locally decoding the encoded data and generating data by local decoding, and comparing the local decoded data with the data before the real number operation is performed And the difference data is obtained by calculating the difference and generating difference data.

  In addition, the image signal decoding method according to the present invention includes encoded data obtained by performing an encoding process with real number operation on an image signal, local decoded data of the encoded data, and an image before the real number operation is performed. In an image signal decoding method for decoding original image data from the encoded data and the difference data, a difference data signal obtained by a difference operation with data is supplied, and the encoded data is subjected to the encoding process. The method includes a step of decoding according to a corresponding decoding process to generate decoded data, and a step of adding the difference data and the decoded data.

  In addition, the image signal decoding apparatus according to the present invention provides encoded data obtained by performing an encoding process involving real number operation on an image signal, local decoded data of the encoded data, and an image before performing the real number operation. In the image signal decoding apparatus for decoding the original image data from the encoded data and the difference data, the difference data signal obtained by the difference calculation with the data is supplied, and the encoded data is subjected to the encoding process. It has a means for decoding according to a corresponding decoding process and generating decoded data, and means for adding the difference data and the decoded data.

  That is, in image signal coding for performing a real number operation such as discrete cosine transform (DCT) processing, at the time of local decoding, the local decoded data is compared with predetermined data before performing the real number operation, a difference is obtained, transmitted, and an image signal In the decoding device, the transmitted difference signal is added to the decoded data, and the signal is corrected, whereby lossless encoding can be realized.

  According to the present invention, in an image signal encoding method for quantizing a signal obtained by performing an encoding process with a real number operation on an image signal and outputting the quantized signal, local decoding data of encoded data and Since the difference is extracted by comparing the data before the real number calculation, lossless encoding can be realized by adding the difference signal to the decoded data and correcting the signal. By enabling this lossless encoding, it is possible to realize encoding / decoding of a highly accurate image signal.

  Further, for each predetermined block, the representative value data and the quantization width of the image data are determined, the difference between the image data and the representative value data is calculated, the difference is quantized based on the quantization width, and the first quantum Generate data. Then, a predetermined conversion process is performed on the first quantized data, the conversion coefficient is quantized to generate second quantized data, and the representative value data, the quantized width, and the second quantized data are Encode. Therefore, an image can be encoded and decoded by converting its bit precision.

  Hereinafter, some preferable image signal encoding method and apparatus, image signal transmission method, image signal decoding method and apparatus, and a recording medium on which a recording signal decodable by the image signal decoding apparatus or method is recorded according to the present invention. Embodiments will be described with reference to the drawings.

  FIG. 1 shows the configuration of an image signal encoding apparatus as a first embodiment of the present invention.

  In the embodiment of FIG. 1, a signal S <b> 1 before DCT processing supplied to a DCT (Discrete Cosine Transform) circuit 56 is sent to an adder 70. Further, the signal S 2 obtained by the DCT circuit 56, the quantization circuit 57 and the inverse quantization circuit 60 and subjected to the IDCT process by the IDCT (Inverse Discrete Cosine Transform) circuit 61 is sent to the subtractor 70. Then, the signal S2 subjected to the IDCT processing is subtracted from the signal S1 before the DCT processing to obtain a difference signal S3, the difference signal S3 is subjected to variable length encoding processing by the variable length encoding circuit 71, and the transmission buffer 73 is set. Output as a differential bit stream.

  In the image signal encoding apparatus shown in FIG. 1, image data to be encoded is input to the motion vector detection circuit 50 in units of macroblocks. The motion vector detection circuit 50 processes the image data of each frame as an I picture, P picture, or B picture according to a predetermined sequence set in advance. It is determined in advance which picture of each frame that is sequentially input is processed as I, P, or B picture.

  Here, the macroblock is composed of vertical and horizontal luminance signals of 16 × 16 dots on the screen, and is divided into four blocks Y [1] to Y [4] having 8 × 8 dots as a unit. The 16 × 16 dot luminance signal corresponds to an 8 × 8 dot Cb signal and an 8 × 8 dot Cr signal.

  Image data of a frame processed as an I picture is transferred from the motion vector detection circuit 50 to the front original image portion 51a of the frame memory 51 and stored. Image data of a frame processed as a B picture is transferred to and stored in the original image unit 51b. Image data of a frame processed as a P picture is transferred to and stored in the rear original image portion 51c.

  Further, when an image of a frame to be processed as a B picture or a P picture is input at the next timing, the image data of the first P picture that has been stored in the rear original image unit 51 c until then is the front original image. Is transferred to the unit 51a. Then, the image data of the next B picture is stored (overwritten) in the original image portion 51b, and the image data of the next P picture is stored (overwritten) in the rear original image portion 51c. Such an operation is sequentially repeated.

  The signal of each picture stored in the frame memory 51 is read from the picture signal, supplied to the motion vector detection circuit 50, and also supplied to the frame / field prediction mode switching circuit 52. In the prediction mode switching circuit 52, frame prediction mode processing or field prediction mode processing is performed. Further, under the control of the prediction determination circuit 54, the calculation unit 53 performs calculation for intra prediction, forward prediction, backward prediction, or bidirectional prediction. Which of these processes is performed is determined corresponding to a prediction error signal (a difference between a reference image to be processed and a predicted image corresponding thereto). For this reason, the motion vector detection circuit 50 generates the absolute value sum (or sum of squares) of the prediction error signal used for this determination.

  Here, the frame prediction mode and the field prediction mode in the prediction mode switching circuit 52 will be described.

  When the frame prediction mode is set in the prediction mode switching circuit 52, the prediction mode switching circuit 52 converts the four luminance blocks Y [1] to Y [4] supplied from the motion vector detection circuit 50, The data is output as it is to the calculation unit 53 in the subsequent stage. On the other hand, when the field prediction mode is set, the prediction mode switching circuit 52 selects the luminance blocks Y [1] and Y [2] out of the four luminance blocks, for example, for the odd field lines. The other two luminance blocks Y [3] and Y [4] are constituted by even-numbered line data and output to the calculation unit 53. In this case, one motion vector corresponds to the two luminance blocks Y [1] and Y [2], and the other two luminance blocks Y [3] and Y [4]. Thus, one other motion vector is associated.

  The motion vector detection circuit 50 outputs the sum of absolute values of prediction errors in the frame prediction mode and the sum of absolute values of prediction errors in the field prediction mode to the prediction mode switching circuit 52. The prediction mode switching circuit 52 compares the absolute value sum of the prediction errors in the frame prediction mode and the field prediction mode, performs a process corresponding to the prediction mode having a small value, and outputs the data to the calculation unit 53.

  However, such processing may be performed by the motion vector detection circuit 50. That is, the motion vector detection circuit 50 compares the absolute value sum of the prediction errors in the frame prediction mode and the field prediction mode, and outputs a signal having a configuration corresponding to the mode having a small value to the prediction mode switching circuit 52. The switching circuit 52 outputs the signal as it is to the calculation unit 53 in the subsequent stage. Actually, this processing is performed by the latter, that is, the motion vector detection circuit 50.

  Note that, in the frame prediction mode, the color difference signal is supplied to the arithmetic unit 53 in a state where the odd field line data and the even field line data coexist. In the field prediction mode, the upper half (four lines) of the color difference blocks Cb and Cr is used as the odd-field color difference signal corresponding to the luminance blocks Y [1] and Y [2], and the lower half (four lines). ) Is the color difference signal of the even field corresponding to the luminance blocks Y [3], Y [4].

  In addition, the motion vector detection circuit 50 calculates the absolute value of the prediction error for determining whether the prediction determination circuit 54 performs prediction in the image, forward prediction, backward prediction, or bidirectional prediction as follows. Generate a value sum.

  That is, as the sum of the absolute values of the prediction errors of the intra-picture prediction, the sum Σ | Aij | of the absolute value | ΣAij | of the sum ΣAij of the macroblock signal Aij of the reference picture and the absolute value | Aij | of the macroblock signal Aij Find the difference. Also, as the sum of the absolute values of the prediction errors of the forward prediction, the sum Σ | Aij− of the absolute value | Aij−Bij | of the difference Aij−Bij between the macroblock signal Aij of the reference image and the macroblock signal Bij of the predicted image Bij | is obtained. Also, the absolute value sum of the prediction errors of the backward prediction and the bidirectional prediction is obtained in the same manner as in the forward prediction (by changing the prediction image to a prediction image different from that in the forward prediction).

  These sums of absolute values are supplied to the prediction determination circuit 54. The prediction determination circuit 54 selects the smallest one of the absolute value sums of the prediction errors of the forward prediction, the backward prediction and the bidirectional prediction as the absolute value sum of the prediction errors of the inter prediction. Further, the absolute value sum of the prediction error of the inter prediction and the absolute value sum of the prediction error of the intra prediction are compared, and the smaller one is selected, and the mode corresponding to the selected absolute value sum is set as the prediction mode. select. That is, if the sum of the absolute values of the prediction errors of intra prediction is smaller, the intra prediction mode is set. If the absolute value sum of the prediction errors of inter prediction is smaller, the mode in which the corresponding absolute value sum is the smallest is set among the forward prediction, backward prediction, and bidirectional prediction modes.

  In addition, the motion vector detection circuit 50 performs the same operation as the prediction determination circuit 54 described above, and selects the mode in which the absolute value sum of the prediction errors in each mode is the smallest among the four prediction modes, and selects the selected mode. A motion vector corresponding to the selected mode is output.

  In this way, the motion vector detection circuit 50 has the configuration corresponding to the mode selected by the prediction mode switching circuit 52 out of the frame or field prediction mode, as the macro block signal of the reference image, and the prediction mode switching circuit 52 And the motion vector between the prediction image corresponding to the prediction mode selected by the prediction determination circuit 54 and the reference image among the four prediction modes is detected, and the variable-length encoding circuit 58 is detected. And output to the motion compensation circuit 64. As described above, the motion vector having the minimum absolute value sum of the corresponding prediction errors is selected.

  The prediction determination circuit 54 sets an intra-frame (image) prediction mode (a mode in which motion compensation is not performed) as a prediction mode when the motion vector detection circuit 50 reads image data of an I picture from the front original image portion 51a. Then, the switch 53d of the calculation unit 53 is switched to the contact a side. As a result, the image data of the I picture is input to the DCT mode switching circuit 55.

  This DCT mode switching circuit 55 has the data of the four luminance blocks in either a state where odd-numbered field lines and even-numbered field lines are mixed (frame DCT mode) or separated (field DCT mode). In this state, the signal is output to the DCT circuit 56.

  In other words, the DCT mode switching circuit 55 compares the coding efficiency when DCT processing is performed with mixed odd-numbered field data and even-numbered field data, and the coding efficiency when DCT processing is performed in a separated state. Choose a good mode.

  For example, the input signal has a configuration in which odd-numbered field and even-numbered field lines coexist, and the difference between the odd-numbered and even-numbered adjacent-field signal is calculated, and the sum of the absolute values (Or sum of squares). In addition, the input signal has a configuration in which the odd field and even field lines are separated, and the difference between the signals of the odd field lines adjacent to each other and the signal difference between the even field lines are calculated. Find the sum (or sum of squares) of the absolute values of. Furthermore, both (absolute value sum) are compared, and a DCT mode corresponding to a small value is set. That is, if the former is smaller, the frame DCT mode is set, and if the latter is smaller, the field DCT mode is set.

  Then, data having a configuration corresponding to the selected DCT mode is output to the DCT circuit 56, and a DCT flag indicating the selected DCT mode is output to the variable length coding circuit 58 and the motion compensation circuit 64. Further, data (signal S1) from the DCT mode switching circuit 55 is sent to the adder 70 for taking out the difference.

  As is apparent from a comparison between the prediction mode in the prediction mode switching circuit 52 and the DCT mode in the DCT mode switching circuit 55, regarding the luminance block, the data structures in both modes are substantially the same.

  Further, when the frame prediction mode (mode in which odd lines and even lines are mixed) is selected in the prediction mode switching circuit 52, the frame DCT mode (mode in which odd lines and even lines are mixed) also in the DCT mode switching circuit 55. ) Is selected, and when the field prediction mode (the mode in which the data of the odd field and the even field are separated) is selected in the prediction mode switching circuit 52, the field in the DCT mode switching circuit 55 is selected. There is a high possibility that a DCT mode (a mode in which data of odd and even fields are separated) is selected.

  However, this is not always the case. In the prediction mode switching circuit 52, the mode is determined so that the absolute value sum of the prediction errors is small, and in the DCT mode switching circuit 55, the coding efficiency is good. The mode is determined so that

  The I-picture image data output from the DCT mode switching circuit 55 is input to the DCT circuit 56, subjected to DCT (discrete cosine transform) processing, and converted to DCT coefficients. The DCT coefficients are input to the quantization circuit 57, quantized at a predetermined quantization step (quantization scale), and then input to the variable length encoding circuit 58. In the case of the present embodiment, as will be described later, the input data is quantized with a quantization scale 1.

  The variable length encoding circuit 58 corresponds to the quantization step (scale) supplied from the quantization circuit 57, and converts the image data supplied from the quantization circuit 57 (in this case, I picture data), for example, It is converted into a variable length code such as a Huffman code and output to the transmission buffer 59.

  The variable-length encoding circuit 58 also has a quantization step (scale) set by the quantization circuit 57 and a prediction mode (intra-picture prediction, forward prediction, backward prediction, or bidirectional prediction) set by the prediction determination circuit 54. ), A motion vector from the motion vector detection circuit 50, a prediction flag (a flag indicating whether the frame prediction mode or the field prediction mode is set) from the prediction mode switching circuit 52, and a DCT mode switching circuit 55. A DCT flag (a flag indicating whether the frame DCT mode or the field DCT mode is set) is input, and these are also variable-length encoded.

  The transmission buffer 59 temporarily stores the input data, and the data stored in the transmission buffer 59 is read at a predetermined timing and output as transmission data. The transmission data is then supplied to, for example, the transmission path 74 and transmitted to the receiving side via the transmission path 74 or recorded on the recording medium 75 via the recording transmission system.

  On the other hand, the I picture data output from the quantization circuit 57 is input to the inverse quantization circuit 60 and inversely quantized corresponding to the quantization step supplied from the quantization circuit 57. The output of the inverse quantization circuit 60 is input to an IDCT (inverse DCT) circuit 61, subjected to inverse DCT processing, and then supplied to an adder 62 via an adder 72 and a DCT block rearrangement circuit 66. The output of the adder 62 is supplied to the frame memory 63 and stored in the forward predicted image unit 63a. The output from the IDCT circuit 61 (signal S2) is sent to the subtractor 70, and the difference between the output from the IDCT circuit 61 (signal S2) and the output from the DCT mode switching circuit 55 (signal S1) is calculated. The difference data is supplied to the variable length coding circuit 71. The difference data is supplied to the adder 72, details of which will be described later.

  The motion vector detection circuit 50, when processing the image data of each frame sequentially input as, for example, pictures of I, B, P, B, P, B. After the image data is processed as an I picture, the image data of the next input frame is further processed as a P picture before the image of the next input frame is processed as a B picture. This is because a B picture is accompanied by backward prediction, and therefore cannot be decoded unless a P picture as a backward predicted image is prepared first.

  Therefore, the motion vector detection circuit 50 starts processing the image data of the P picture stored in the rear original image portion 51c after the processing of the I picture. As in the case described above, the absolute value sum of the inter-frame difference (prediction error) in units of macroblocks is supplied from the motion vector detection circuit 50 to the prediction mode switching circuit 52 and the prediction determination circuit 54. The prediction mode switching circuit 52 sets the frame / field prediction mode corresponding to the absolute value sum of the prediction errors of the macroblock of the P picture. Further, the prediction determination circuit 54 sets a prediction mode for intra-picture prediction, forward prediction, backward prediction, or bidirectional prediction, corresponding to the sum of the absolute values of the prediction errors of the macroblock of the P picture.

  When the in-picture prediction mode is set, the calculation unit 53 switches the switch 53d to the contact a side as described above. Accordingly, this data is output via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59, similarly to the I picture data. The data is supplied to the frame memory 63 via the inverse quantization circuit 60, the IDCT circuit 61, the adder 72, the DCT block rearrangement circuit 66, and the adder 62, and is stored in the backward predicted image unit 63b. .

  In addition, when the forward prediction mode is set, the switch 53d is switched to the contact point b, and image (I-picture image in this case) data stored in the forward prediction image portion 63a of the frame memory 63 is read. The read image data is motion-compensated by the motion compensation circuit 64 corresponding to the motion vector output from the motion vector detection circuit 50. That is, when the setting of the forward prediction mode is instructed by the prediction determination circuit 54, the motion compensation circuit 64 sets the read address of the forward prediction image unit 63a to the position of the macro block currently output by the motion vector detection circuit 50. Data is read out from the corresponding position by the amount corresponding to the motion vector, and predicted image data is generated.

  The predicted image data output from the motion compensation circuit 64 is supplied to the subtractor 53a. The subtractor 53a subtracts the prediction image data corresponding to the macroblock supplied from the motion compensation circuit 64 from the macroblock data of the reference image supplied from the prediction mode switching circuit 52, and the difference (prediction error). ) Is output. The difference data is output via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59. The difference data is locally decoded by the inverse quantization circuit 60 and the IDCT circuit 61 and input to the adder 62 via the adder 72 and the DCT block rearrangement circuit 66.

  The adder 62 is also supplied with the same data as the predicted image data supplied to the subtractor 53a. The adder 62 adds the predicted image data output from the motion compensation circuit 64 to the difference data output from the IDCT circuit 61. As a result, image data of the original (decoded) P picture is obtained. The image data of the P picture is supplied to and stored in the backward predicted image unit 63b of the frame memory 63.

  As described above, the motion vector detection circuit 50 stores the data of the I picture and the P picture in the forward predicted image unit 63a and the backward predicted image unit 63b, respectively, and then executes the process of the B picture. The prediction mode switching circuit 52 sets the frame / field mode corresponding to the magnitude of the sum of absolute values of inter-frame differences in units of macroblocks, and the prediction determination circuit 54 sets the prediction mode to the intra-picture prediction mode. , Forward prediction mode, backward prediction mode, or bidirectional prediction mode.

  As described above, in the intra prediction mode or the forward prediction mode, the switch 53d is switched to the contact point a or b, respectively. At this time, the same processing as in the case of the P picture is performed, and data is transmitted.

  On the other hand, when the backward prediction mode or the bidirectional prediction mode is set, the switch 53d is switched to the contact c or d, respectively.

  In the backward prediction mode in which the switch 53d is switched to the contact c, image (in this case, P picture image) data stored in the backward predicted image unit 63b is read. The read image data is motion-compensated by the motion compensation circuit 64 corresponding to the motion vector output from the motion vector detection circuit 50. That is, when the setting of the backward prediction mode is instructed by the prediction determination circuit 54, the motion compensation circuit 64 sets the read address of the backward prediction image unit 63b to the position of the macroblock currently output by the motion vector detection circuit 50. Data is read out from the corresponding position by the amount corresponding to the motion vector, and predicted image data is generated.

  The predicted image data output from the motion compensation circuit 64 is supplied to the subtractor 53b. The subtractor 53b subtracts the predicted image data supplied from the motion compensation circuit 64 from the macroblock data of the reference image supplied from the prediction mode switching circuit 52, and outputs the difference. The difference data is output via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59.

  In the bidirectional prediction mode in which the switch 53d is switched to the contact point d, the image (in this case, the image of I picture) data stored in the forward predicted image unit 63a and the backward predicted image unit 63b are stored. Image (in this case, P picture image) data is read out. These image data are motion-compensated by the motion compensation circuit 64 corresponding to the motion vector output from the motion vector detection circuit 50. That is, in the motion compensation circuit 64, when the setting of the bidirectional prediction mode is instructed by the prediction determination circuit 54, the motion vector detection circuit 50 now outputs the read addresses of the forward prediction image unit 63a and the backward prediction image unit 63b. The data is read out from the position corresponding to the position of the macroblock being read by shifting the motion vector by the amount corresponding to the motion vector (in this case, the motion vector is for the forward prediction image and the backward prediction image), and prediction image data is generated. To do.

  The predicted image data output from the motion compensation circuit 64 is supplied to the subtractor 53c. The subtractor 53c subtracts the average value of the predicted image data supplied from the motion compensation circuit 64 from the macroblock data of the reference image supplied from the motion vector detection circuit 50, and outputs the difference. The difference data is output via the DCT mode switching circuit 55, the DCT circuit 56, the quantization circuit 57, the variable length coding circuit 58, and the transmission buffer 59.

  The B picture image is not stored in the frame memory 63 because it is not a predicted image of another image.

  Note that, in the frame memory 63, the forward predicted image unit 63a and the backward predicted image unit 63b are subjected to bank switching as necessary, and those stored in one or the other with respect to a predetermined reference image It can be switched and output as a predicted image or a backward predicted image.

  In the above description, the luminance block is mainly described, but the color difference block is similarly processed and transmitted in units of macroblocks. As the motion vector for processing the color difference block, the motion vector of the corresponding luminance block is halved in the vertical direction and the horizontal direction.

  Next, a detailed description will be given of the configuration and operation related to the extraction of error during DCT processing, which is the main part of the embodiment of the present invention.

  As a configuration for this purpose, the above-described subtractor 70, adder 72, variable length coding circuit 71, and transmission buffer 73 are provided.

  The image signal (in the case of I picture) and the difference signal (in the case of B and P pictures) output from the Frame / Field DCT mode switching circuit 55 are output to the DCT circuit 56 and the adder 70. The signal input to the DCT circuit 56 is subjected to DCT processing as in the prior art.

  The signal subjected to DCT processing by the DCT circuit 56 is input to the quantization circuit 57. The quantization circuit 57 quantizes the quantization scale at 1. That is, the quantization circuit 57 outputs the input signal as it is without performing any processing. Then, this output signal is supplied to the variable length coding circuit 58 and the inverse quantization circuit 60. Similarly, the inverse quantization circuit 60 performs inverse quantization at the quantization scale 1.

The signal S2 output from the IDCT circuit 61 is output to the subtracter 70 and the adder 72. The subtractor 70 calculates a difference S3 between the signal S1 from the Frame / Field DCT mode switching circuit 55 and the signal S2 from the IDCT circuit 61. That is, the following calculation S3 = S1-S2
Is output to the variable length encoding circuit 71 and the adder 72.

  The variable length coding circuit 71 performs variable length coding on the difference signal S3 from the adder 70 and outputs the output bit stream (difference bit stream) via the transmission buffer 73. The data output from the transmission buffer 73 is then supplied as transmission data, for example, to the transmission path 74 and transmitted to the receiving side via the transmission path 74 or recorded on the recording medium 75 via the recording transmission system. Is done.

  The adder 72 adds the signal S2 from the IDCT circuit 61 and the signal S3 from the adder 70, and outputs the result to the adder 62 as a signal S4.

  Here, the principle of realizing lossless encoding with this image signal encoding device will be described. The signal S1 is an original signal not subjected to DCT processing or quantization processing. That is, it is a signal for storing all information of the original image. When DCT processing is performed on this signal, some information of the original signal is lost even when quantization processing is not performed (quantization scale is 1). This is because the DCT processing is a real number operation, whereas the DCT circuit and the IDCT circuit abort the operation to a finite word length.

  Therefore, in order to realize lossless encoding, it is necessary to separately transmit information lost by this DCT processing.

  Some information is lost in the output signal S2 of the IDCT circuit 61 by the DCT and IDCT processing. The subtractor 70 calculates the difference between the signals S1 and S2 and extracts information lost by the DCT process. This is signal S3. By adding the signal S3 to the signal S2 in the adder 72, the original signal S1 can be restored.

  Next, an image signal decoding apparatus for decoding the signal obtained from the image signal encoding apparatus shown in FIG. 1 as described above will be described with reference to FIG.

  FIG. 2 is a block diagram showing a configuration of an image signal decoding apparatus corresponding to the image signal encoding apparatus according to the first embodiment of the present invention.

  In FIG. 2, the encoded image data output from the encoding apparatus shown in FIG. 1 and transmitted via the transmission path 74 or recorded on the recording medium 75 is received by a receiving circuit (not shown). The data is received or reproduced by a reproduction device, temporarily stored in the reception buffer 81, and then supplied to the variable length decoding circuit 82 of the decoding circuit 90. The variable length decoding circuit 82 performs variable length decoding on the data supplied from the reception buffer 81, and the motion vector, prediction mode, prediction flag, and DCT flag are supplied to the motion compensation circuit 87, and the quantization step is an inverse quantization circuit. The decoded image data is output to the inverse quantization circuit 83.

  The inverse quantization circuit 83 converts the image data supplied from the variable length decoding circuit 82 into a quantization step (in this case, the quantization step (quantization scale) is 1) also supplied from the variable length decoding circuit 82. Inverse quantization is performed according to (1), and the result is output to the IDCT circuit 84. The data (DCT coefficient) output from the inverse quantization circuit 83 is subjected to inverse DCT processing by the IDCT circuit 84 and supplied to the adder 85 via the adder 93 and the DCT block rearrangement circuit 89. The adder 93 is for adding an error due to the operation word length limitation during the above-described DCT processing, and details thereof will be described later.

  When the image data supplied from the IDCT circuit 84 is I picture data, the data is output from the adder 85, and the predicted image of the image data (P or B picture data) input to the calculator 85 later. For data generation, the data is supplied to the frame memory 86 and stored in the forward predicted image unit 86a. The output data from the adder is taken out as an output reproduction image, and is output to a subsequent stage, for example, a format conversion circuit (not shown).

  When the image data supplied from the IDCT circuit 84 is P picture data having the image data of the previous frame as predicted image data and is data in the forward prediction mode, the forward predicted image portion 86a of the frame memory 86 is used. The image data of one frame before (I picture data) stored in is read out. The read image data is subjected to motion compensation corresponding to the motion vector output from the variable length decoding circuit 82 by the motion compensation circuit 87. The adder 85 adds the image data after the motion compensation and the image data (difference data) supplied from the IDCT circuit 84, and outputs the added data as an output reproduction image. This added data, that is, decoded P picture data, is supplied to the frame memory 86 in order to generate predicted picture data of picture data (B picture or P picture data) to be input to the adder 85 later. And stored in the backward predicted image unit 86b.

  Even in the case of P picture data, the data in the intra prediction mode is stored in the backward predicted image unit 86b as it is without any particular processing in the adder 85, like the I picture data.

  Since this P picture is an image to be displayed next to the next B picture, at this point of time, it is not yet output to a format conversion circuit (not shown) (as described above, the P picture input after the B picture) Are processed and transmitted before the B picture).

  When the image data supplied from the IDCT circuit 84 is B picture data, it is stored in the forward predicted image unit 86a of the frame memory 86 corresponding to the prediction mode supplied from the variable length decoding circuit 82. I-picture image data (in the forward prediction mode), P-picture image data stored in the backward prediction image portion 86b (in the backward prediction mode), or both image data (in the bidirectional prediction mode) Is read out. The read image data is subjected to motion compensation corresponding to the motion vector output from the variable length decoding circuit 82 in the motion compensation circuit 87, and a predicted image is generated. However, when motion compensation is not required (in the case of intra-picture prediction mode), a predicted image is not generated.

  Thus, the data subjected to motion compensation in the motion compensation circuit 87 is added to the output of the IDCT circuit 84 in the adder 85. This added output is then output to a format conversion circuit (not shown).

  However, since this addition output is B picture data and is not used for generating a predicted image of another image, it is not stored in the frame memory 86.

  After the B picture image is output, the P picture image data stored in the backward predicted image unit 86 b is read out and supplied to the adder 85 through the motion compensation circuit 87. However, motion compensation is not performed at this time.

  The decoder 31 does not show circuits corresponding to the prediction mode switching circuit 52 and the DCT mode switching circuit 55 in the encoder of FIG. 1, but processes corresponding to these circuits, that is, an odd field and an even field. The motion compensation circuit 87 executes a process of returning the configuration in which the signals of the first line are separated to the original mixed configuration as necessary.

  In the above description, the processing of the luminance signal has been described, but the processing of the color difference signal is similarly performed. However, in this case, the motion vector used is a luminance signal halved in the vertical and horizontal directions.

  Next, the decoding process of the differential bit stream that has been variable-length encoded in the variable-length encoding circuit 71 of the image signal encoding device of FIG. 1 described above will be described.

The differential bit stream that has been variable-length encoded by the variable-length encoding circuit 71 of FIG. 1 and extracted through the transmission buffer 73 is transmitted from the transmission path 74 or reproduced from the recording medium 75 to obtain the difference bit stream of FIG. Input to the reception buffer 91. The variable length decoding circuit 92 reads the corrected bit stream from the reception buffer and decodes the variable length code from the bit stream. The variable length decoding circuit 92 is paired with the variable length encoding circuit 71 in the image signal encoding apparatus and performs the reverse operation.
The output signal S3 ′ of the variable length decoding circuit 92 matches the signal S3 in the encoding device. The output signal S2 ′ of the IDCT circuit 84 coincides with the signal S2 in the encoding device.

  The adder 93 adds the output S3 'of the variable length decoding circuit 92 and the output signal S2' of the IDCT circuit 84, and outputs a signal S1 '. This corresponds to the signal S1 in the encoding device.

  As described above, lossless encoding can be realized in an image signal encoding / decoding device using DCT processing.

  Next, referring to FIG. 3 regarding the form of the image signal encoding apparatus according to the second embodiment of the present invention, and also about the form of the image signal decoding apparatus corresponding to the image encoding apparatus according to the second embodiment. This will be described with reference to FIG.

  FIG. 3 shows an image signal encoding apparatus according to the second embodiment of the present invention.

The image signal encoding apparatus shown in FIG. 3 is the same as the image signal encoding apparatus in the example of FIG. 1 except for the operations of the subtractor 70, the adder 72, and the variable length encoding circuit 71. Description of the portion is omitted.

  The motion vector detection circuit 50 of FIG. 3 outputs the output S1 to the Frame / Field prediction mode switching circuit 52 and the adder 70. The signal input to the Frame / Field prediction mode switching circuit 52 is processed in the same manner as in the example of FIG.

  The quantization circuit 57 quantizes the quantization scale at 1. That is, the quantization circuit 57 outputs the input signal as it is without performing any processing. This output signal is supplied to the variable length coding circuit 58 and the inverse quantization circuit 60. Similarly, the inverse quantization circuit 60 performs inverse quantization at the quantization scale 1.

The signal S2 output from the adder 62 is output to the subtractor 70 and the adder 72. The subtracter 70 calculates a difference S3 between the signal S1 from the motion vector detection circuit 50 and the signal S2 from the adder 62. That is, the following calculation S3 = S1-S2
Is output to the variable length encoding circuit 71 and the adder 72.

  The variable length coding circuit 71 performs variable length coding on the difference signal S3 from the subtractor 70 and outputs the output bit stream (correction bit stream) via the transmission buffer 73.

  The adder 72 adds the signal S2 from the adder 62 and the signal S3 from the subtractor 70 and outputs the result.

  Here, the principle of realizing lossless encoding with this image signal encoding device will be described. The signal S1 is an original signal that has not been subjected to DCT processing or quantization processing. That is, it is a signal for storing all information of the original image. When DCT processing is performed on this signal, some information of the original signal is lost even when quantization processing is not performed (quantization scale is 1). This is because the DCT processing is a real number operation, whereas the DCT circuit and the IDCT circuit abort the operation to a finite word length.

  Therefore, in order to realize lossless encoding, it is necessary to separately transmit information lost by this DCT processing.

  Some information is lost in the output signal S2 of the adder 62 by the DCT and IDCT processing. The subtractor 70 calculates the difference between S1 and S2 and extracts information lost by the DCT process. This is signal S3.

  In the adder 72, the signal S3 can be added to the signal S2 to restore the original signal S1.

  Other operations in the image signal encoding apparatus are the same as those of the image signal encoding apparatus in the example of FIG.

  FIG. 4 shows an image signal decoding apparatus corresponding to the image encoding apparatus of the second embodiment.

  4 is the same as the image signal decoding apparatus shown in FIG. 2 except for the reception buffer 91, the variable length decoding circuit 92, and the adder 93. Therefore, the description of the same parts is omitted.

  The corrected bit stream variable-length encoded in the variable-length encoding circuit 71 of the image signal encoding device is transmitted from the transmission path or reproduced from the recording medium and input to the reception buffer 91. The variable length decoding circuit 92 reads the corrected bit stream from the reception buffer and decodes the variable length code from the bit stream. The variable length decoding circuit 92 is paired with the variable length coding circuit 71 in the image signal coding apparatus, and performs the reverse operation.

  The output signal S3 'of the variable length decoding circuit 92 coincides with S3 in the image signal encoding device. The output signal S2 'of the adder 85 coincides with S2 in the encoding device. The adder 93 adds the output S3 'of the variable length decoding circuit 92 and the output signal S'2 of the adder 85, and outputs the result as an output signal S1'. This corresponds to S1 in the image signal encoding device.

  3 and 4 as described above, it is possible to realize lossless encoding in an image signal encoding / decoding apparatus using DCT processing.

  Next, the form of the image signal encoding apparatus according to the third embodiment of the present invention will be described with reference to FIGS.

  In the third embodiment, for each predetermined block, m-bit, for example, 10-bit representative value data and quantization width of 10-bit image data are determined, and the difference between the image data and the representative value data is determined. calculate. Then, the difference data is quantized based on the quantization width to generate first quantized data. Furthermore, a predetermined conversion process is performed on the first quantized data, a conversion coefficient is generated, the conversion coefficient is quantized, and second quantized data is generated. Then, the representative value data, the quantization width, and the second quantization data are encoded, and the quantization error is set so that the representative value comes to the center of the quantization width at the time of the first quantization. Is decreasing. Further, the memory can be reduced by performing motion compensation of m bits, for example, 10-bit images, by n bits, for example, 8 bits. This is equivalent to sending the lower bits not subjected to motion prediction by intra. In addition, when encoding an m-bit image, for example, a 10-bit image, high-definition images can be losslessly compressed by adaptively switching between lossless compression encoding and lossy compression encoding. Further, the second quantization is performed based on the quantization width in the first quantization, and an image with uniform image quality can be obtained.

  FIG. 5 is a block diagram showing an image signal encoding apparatus as a third embodiment of the present invention.

  The image signal encoding apparatus shown in FIG. 5 will be described on the assumption that image data having a bit accuracy higher than 8-bit accuracy, for example, 10-bit accuracy, is input to the apparatus. In this example, a specific example of a 10-bit image signal is shown, but this can be similarly applied to an image signal having a bit accuracy of 10 bits or more.

  The field memory group 1 can store 10-bit precision image data. For example, the field memory group 1 temporarily stores digital image data (image pixel data) divided into blocks of 16 × 16 pixels or the like, and is generated by the field memory controller 16 corresponding to the synchronization signal of the input image. Based on the timing control signal, a block of image data with 10-bit accuracy is output to the arithmetic unit 3.

  As described above, the motion prediction circuit 2 uses a motion compensation mode (intra-picture prediction mode, forward prediction, backward prediction, or bidirectional prediction mode) for a block of image data as a reference image stored in the field memory group 1. And a motion vector between the predicted image and the reference image corresponding to the set motion compensation mode is detected and output to the motion compensation circuit 14 and the VLC circuit 15. Further, the motion prediction circuit 2 sets the motion compensation mode to the intra-block representative value calculation circuit 5 and the block quantization width calculation via the motion compensation circuit 14 in addition to the motion compensation circuit 14 and the VLC circuit (variable length coding circuit) 15. Supply to circuit 6.

  Note that the motion prediction circuit 2 in FIG. 5 is configured in the same manner as in FIG. 1, and thus is configured so that 8-bit precision image data can be input to the motion prediction circuit 2. Therefore, all the connection lines from the field memory group 1 cannot be connected.

  Therefore, among the connection lines corresponding to the 10-bit precision image data from the field memory group 1, connection lines other than the lower 2 bits are connected to the motion prediction circuit 2.

  In other words, the motion prediction circuit 2 is inputted with 8-bit precision image data obtained by discarding the lower 2 bits of the 10-bit precision image data.

  When a block of 10-bit precision image data as a reference image stored in the field memory group 1 is read from the block and supplied to the computing unit 3, it is further set in the computing unit 3 by the motion prediction circuit 2. A predicted image corresponding to the motion compensation mode is supplied from the motion compensation circuit 14 via the field memory group 13.

  The arithmetic unit 3 performs the subtraction process corresponding to the motion compensation mode as described above (when the motion compensation mode is the intra-picture prediction mode, the 10-bit precision image data from the field memory group 1 is processed. If the block is output as it is and the motion compensation mode is an inter-picture prediction mode (either forward prediction, backward prediction or bidirectional prediction mode), a block of 10-bit precision image data from the field memory group 1; The difference (prediction error) from the predicted image from the motion compensation circuit 14 is calculated), and a 10-bit precision calculation output is the signal S1, the calculator 4, the intra-block representative value calculation circuit 5, and the block quantization width calculation circuit 5 and the subtractor 70.

  An intra-block representative value calculation circuit (hereinafter referred to as a representative value calculation circuit) 5 outputs the calculation output of the calculator 3 in accordance with the motion compensation mode supplied from the motion prediction circuit 2 via the motion compensation circuit 4. The representative value data is calculated as described later and output to the subtracter 4. A block quantization width calculation circuit (hereinafter referred to as a quantization width calculation circuit) 6 corresponds to the motion compensation mode supplied from the motion prediction circuit 2 via the motion compensation circuit 4 and outputs the computation output of the computing unit 3. The quantization width Q to be quantized by the block quantizer 7 is calculated as described later, and is output to the block quantizer 7 and the block inverse quantizer 10.

  Here, in this specification, the quantization width determined by the quantization width calculation circuit 6, the quantum in the differential signal encoder 8, the differential signal decoder 9, and the differential signal decoder 22 in FIG. The quantization widths are distinguished by describing them as quantization widths Q and S, respectively.

  The difference between the calculation output of the calculator 3 and the representative value data output from the representative value calculation circuit 5 in the subtractor 4 is calculated, and the difference data is output to the block quantizer 7. In the block quantizer 7, the operation output of the subtractor 4 is quantized by the quantization width Q, that is, divided by the quantization width Q and output to the differential signal encoder 8.

  The differential signal encoder 8 includes a DCT circuit 111 and a quantizer 112. The DCT circuit 111 performs DCT (Discrete Cosine Transform) processing on the quantized data from the block quantizer 7 and converts it into DCT coefficients. The DCT coefficient is input to the quantizer 112, quantized with a predetermined quantization width S, and then input to the VLC circuit 15. In the present embodiment, the quantization width S is set to 1.

  Here, as described above, the DCT circuit 111 of the differential signal encoder 8 indicates that 8-bit precision image data, that is, 8 bits from 0 to 255 when the motion compensation mode is the intra-picture prediction mode. When the motion compensation mode is an inter-picture prediction mode (forward prediction, backward prediction, or bidirectional prediction mode), the image data that can be represented can be represented by 9 bits from −255 to 255, which is 8 bits plus a sign bit. It is necessary to input image data.

  That is, it is necessary to convert the bit accuracy of the block of image data input to the image signal encoding device from 10-bit accuracy to 8-bit accuracy, and input to the differential signal encoder 8.

  Therefore, when the motion compensation mode is the intra-picture prediction mode, the representative value calculation circuit 5 has the maximum value of the calculation output of the calculator 3 (in this case, a block of 10-bit precision image data from the field memory group 1). The minimum value is detected and, for example, the minimum value is output to the calculators 4 and 11 as representative value data of a block of 10-bit precision image data output from the calculator 3.

  In this case, the representative value data of the block may not be the minimum value of the block. However, when the motion compensation mode is the intra prediction mode, it is necessary to represent the image data with 8 bits from 0 to 255. Therefore, when the block representative value data is set to the minimum value of the block, it will be described later. The dynamic range of the block can be maximized.

  Then, in the computing unit 4, the block of 10-bit precision image data output from the computing unit 3 (each pixel data in the block) and the representative value data of the block output from the representative value calculation circuit 5, that is, the minimum of the block The difference from the value is calculated and output to the block quantizer 7.

  Therefore, in this case, the block quantizer 7 outputs a block of image data having a minimum value of 0 to the block quantizer 7.

That is, when the motion compensation mode is the intra prediction mode, for example, as shown in FIG. 6A, the maximum value or the minimum value of the block of 10-bit precision image data output from the computing unit 3 is 500 respectively. If 300, the block of image data having a value in the range of 0 (= 300-300) to 200 (= 500-300) obtained by subtracting the minimum value 300 as representative value data from the block of image data is calculated. Is output from the unit 4 to the block quantizer 7. For example, as shown in FIG. 7A, if the maximum value or the minimum value of the block of 10-bit precision image data output from the computing unit 3 is 1000 or 300, respectively, the block of the image data A block of image data having a value in the range of 0 (= 300-300) to 700 (= 1000-300) obtained by subtracting the minimum value 300 as representative value data is output from the computing unit 4 to the block quantizer 7. become.

  At the same time, in this case, the quantization width calculation circuit 6 detects the maximum value and the minimum value of the arithmetic output of the arithmetic unit 3 (in this case, a block of 10-bit precision image data from the field memory group 1), and the difference between them is detected. The dynamic range is calculated.

  In this specification, the dynamic range of a signal means the difference between the maximum value and the minimum value of the signal.

  Then, the quantization width calculation circuit 6 determines whether or not the dynamic range of the block of 10-bit precision image data from the field memory group 1 is within 8 bits that can be expressed in the range of 0 to 255. When it is determined that the dynamic range is within 8 bits, the quantization width Q is determined to be 1 and output to the block quantizer 7.

  Therefore, when the motion compensation mode is the intra prediction mode, if the dynamic range of the block of 10-bit precision image data output from the computing unit 3 is within 8 bits (for example, FIG. From the encoder 7, the image data from the arithmetic unit 4 is output to the differential signal encoder 8 as it is.

  That is, when the motion compensation mode is the intra prediction mode, when the dynamic range of the block of 10-bit precision image data output from the calculator 3 is within 8 bits, the image data output from the calculator 3 The bit accuracy of the block is substantially 8 bits, and this block of image data with an 8-bit accuracy is output to the differential signal encoder 8.

  Further, when the motion compensation mode is the intra-picture prediction mode, the dynamic range of the block of 10-bit precision image data from the field memory group 1 exceeds 8 bits in the quantization width calculation circuit 6 (256 or more). ), The quantization width Q is determined so that the dynamic range of the quantization output of the block quantizer 7 is within 8 bits (255), and is output to the block quantizer 7.

  That is, when the dynamic range of the block of 10-bit precision image data from the field memory group 1 is, for example, 256 or more and less than 512, the quantization width Q is determined to be 2. Further, when the dynamic range is, for example, 512 or more and less than 768, the quantization width Q is determined to be 3, and when the dynamic range is, for example, 768 or more and less than 1024, the quantization width Q is determined to be 4. .

  Next, a quantization method in the block quantizer 7 will be described. When the quantization width Q is 1, the block quantizer 7 does not perform any processing and the image data from the arithmetic unit 4 is output to the differential signal encoder 8 as it is.

  When the quantization width Q is 2, the image data from the computing unit 4 is divided by the quantization width 4. However, at this time, the decimal point is rounded down.

When the quantization width Q is 3, the image data x from the computing unit 4 is quantized with the quantization width 3 according to the following equation (X). However, at this time, the decimal point is rounded down.
(When x ≧ 0) X = (x + 1) / 3
(When x <0) X = (x−1) / 3
When the quantization width Q is 4, the image data x from the computing unit 4 is quantized to a quantization output X with the quantization width 4 according to the following expression. However, at this time, the decimal point is rounded down.
(When x ≧ 0) X = (x + 1) / 4
(When x <0) X = (x−1) / 4
When the quantization width Q is 4, as a modification, the quantization can be performed as follows.
(When x ≧ 0) X = (x + 2) / 4
(When x <0) X = (x−2) / 4
However, these cannot be used together.

  As described above, when the motion compensation mode is the intra-picture prediction mode, when the dynamic range of the block of 10-bit precision image data from the computing unit 4 exceeds 8 bits (256 or more), the block quantum In the coder 7, the block of 10-bit precision image data from the computing unit 4 is converted into a block of 8-bit precision image data and output to the differential signal coder 8.

  On the other hand, when the motion compensation mode is the inter-picture prediction mode (forward prediction, backward prediction, or bidirectional prediction mode), the representative value calculation circuit 5 outputs the calculation output of the calculator 3 (in this case, the field memory group 1 The maximum value and the minimum value of the difference data between the block of 10-bit precision image data from the image and the predicted image) are detected, for example, the average value (= (maximum value + minimum value) / 2, but rounded down to the nearest decimal point) Are output to the calculators 4 and 11 as representative value data of a block of 10-bit precision image data output from the calculator 3.

  In this case, the representative value data of the block is not the average value of the maximum value and the minimum value of the block (pixels in the block) (hereinafter referred to as the average value of the block), for example, the minimum value of the block or 0 can do. However, when the motion compensation mode is the inter-picture prediction mode, it is necessary to represent the image data with 9 bits in the range of −255 to 255 as described above. However, the maximum dynamic range of the block can be obtained.

  Then, in the subtractor 4, the block of 10-bit precision image data output from the calculator 3 (each pixel data in the block) and the block representative value data output from the representative value calculation circuit 5, that is, the average of the blocks The difference from the value is taken and output to the block quantizer 7.

  Therefore, in this case, the block quantizer 7 outputs a block of image data having the same absolute value of the maximum value and the minimum value to the block quantizer 7.

  That is, when the motion compensation mode is the inter-picture prediction mode, for example, as shown in FIG. 6B, the maximum value or the minimum value of the block of 10-bit precision image data output from the computing unit 3 is − If it is 155 or 355, an average value 100 (= (− 155 + 355) / 2) as representative value data is subtracted from the image data block, −255 (= −155-100) to 255 (= 355-100). A block of image data having a value in the range is output from the computing unit 4 to the block quantizer 7. For example, as shown in FIG. 7B, if the maximum value or the minimum value of the block of 10-bit precision image data output from the computing unit 3 is 1000 or −1000, respectively, the average value 0 (= A block of image data having a value in the range of (−1000 + 1000) / 2), −1000 (= −1000−0) to 1000 (= 1000−0) is output to the block quantizer 7.

  At the same time, in this case, in the quantization width calculation circuit 6, the maximum value of the calculation output of the calculator 3 (in this case, the difference data between the block of 10-bit precision image data from the field memory group 1 and the predicted image) and The minimum value is detected, and the dynamic range as the difference is calculated.

  In the quantization width calculation circuit 6, the dynamic range of the 10-bit precision image data block from the field memory group 1 is within 9 bits including 1 sign bit that can be expressed in the range of −255 to 255. When it is determined whether or not the dynamic range is within 9 bits, the quantization width Q is determined as 1 and output to the block quantizer 7.

  Therefore, when the motion compensation mode is the inter-picture prediction mode, if the dynamic range of the block of 10-bit precision image data (difference data) output from the computing unit 3 is within 9 bits (for example, FIG. )), The block quantizer 7 outputs the image data from the arithmetic unit 4 to the differential signal encoder 8 as it is.

  That is, when the motion compensation mode is the inter-picture prediction mode, when the dynamic range of the block of 10-bit precision image data output from the arithmetic unit 3 is within 9 bits, the image data output from the arithmetic unit 3 The bit accuracy of the block is substantially 8 bits, and this block of image data with an 8-bit accuracy is output to the differential signal encoder 8.

  Further, when the motion compensation mode is the inter-picture prediction mode, the dynamic range of the 10-bit precision image data block from the field memory group 1 exceeds 9 bits in the quantization width calculation circuit 6 (−255 to 255). The quantization width Q is set so that the dynamic range of the quantization output of the block quantizer 7 is 9 bits or less (less than 511) (within the range of -255 to 255). It is determined and output to the block quantizer 7.

  That is, when the dynamic range of a block of 10-bit precision image data from the field memory group 1 is, for example, 512 or more and less than 1024, the quantization width Q is determined to be 2. Further, when the dynamic range is, for example, 1024 or more and less than 1536, the quantization width Q is determined to be 3, and when the dynamic range is, for example, 1536 or more and less than 2048, the quantization width Q is determined to be 4. .

  Even when the motion compensation mode is the inter-picture prediction mode, the block quantizer 7 performs the same operation. The quantization method is the same.

  As described above, when the motion compensation mode is the inter-picture prediction mode, when the dynamic range of the block of 10-bit precision image data from the subtractor 4 exceeds 9 bits (512 or more), the block quantum In the encoder 7, the block of 10-bit precision image data from the subtractor 4 is converted into a block of 8-bit precision image data and output to the differential signal encoder 8.

  As described above, when a block of 10-bit precision image data is input to the image signal encoding apparatus, an 8-bit precision image data block is input to the differential signal encoder 8. In the subtractor 4 and the block quantizer 8, the image data is converted into a block of 10-bit precision image data and a block of 8-bit precision image data.

  By the way, when an image having a bit accuracy higher than an 8-bit accuracy, for example, a 10-bit accuracy, is divided into small blocks such as 8 × 8 pixels and 16 × 16 pixels, the dynamic range in each block is generally Not large (when the motion compensation mode is the intra prediction mode, the block dynamic range is within 8 bits, and when the motion compensation mode is the inter picture prediction mode, the block dynamic range is within 9 bits). Many. Further, when the motion compensation mode is the inter-picture prediction mode, since the difference between the block of the image data and the predicted image is obtained by the computing unit 3, the dynamic range of the block of the difference hardly exceeds 9 bits.

  Therefore, by subtracting the representative value data from the block of image data in the arithmetic unit 4, in most cases, 10-bit precision image data can be converted to 8-bit precision image data without loss of information. .

  That is, even if the apparatus is configured without providing the quantization width calculation circuit 6 and the block quantizer 7, the 10-bit precision image data can be converted into 8-bit precision image data without damaging the image. Can do.

  When the dynamic range of the block of image data is large (when the motion compensation mode is the intra prediction mode, the block dynamic range exceeds 8 bits, and when the motion compensation mode is the inter prediction mode, the block dynamic range is As described above, when the image data is quantized by the block quantizer 7 and is decoded, the resolution is somewhat deteriorated.

  However, for example, in a portion with a large dynamic range, such as a contour portion of an image, the luminance discrimination degree of the human eye is low. Therefore, the lowering (degradation) of the resolution in the level direction due to the above-mentioned quantization has little influence on the viewer. It is not considered.

  The image data converted from the 10-bit precision to the 8-bit precision is supplied to the differential signal encoder 8. Then, in the differential signal encoder 8, DCT processing is performed, and the signal is further quantized and supplied to the VLC circuit 15.

  In the VLC circuit 15, the representative value data or the quantization width Q of the block other than the block of the image data subjected to DCT processing by the differential signal encoder 8 and further quantized is represented by the representative value calculation circuit 5 or the quantization width. The motion vector and motion compensation mode are supplied from the calculation circuit 6 and supplied from the motion prediction circuit. Further, the VLC circuit 15 is supplied with the quantization width S in the differential signal encoder 8. The VLC circuit 15 then changes the block of image data whose bit precision is converted from 10-bit precision to 8-bit precision, the representative value data of the block, the quantization width Q, S, the motion vector, and the motion compensation mode to a variable length. Encode and output via a transmission buffer (not shown).

  Here, in this case, the VLC circuit 15 adds the representative value data or the quantization width Q of the block to the header of each block of the encoded image data.

  Note that the representative value data or quantization width Q of a block is not added to the header of the block as described above, but the macro is added to the header of the macroblock layer or the picture layer as a higher layer than the block. It can be added together with representative value data and quantization width Q of other blocks belonging to the block or picture layer.

  A bit stream as an encoder output signal is output from the VLC circuit 15.

  Further, the image data that has been subjected to DCT processing and further quantized by the differential signal encoder 8 is supplied to the differential signal decoder 9 when it is I or P picture data.

  The differential signal decoder 9 includes an inverse quantizer 113 and an inverse DCT circuit 114, in which data from the differential signal encoder 8 (quantized DCT data) is converted into the differential signal encoder 8. Inverse quantization is performed with the same quantization width as the quantization width S in FIG.

  The image data output from the differential signal decoder 9 is input to the block inverse quantizer 10, where it is the same as the quantization width Q in the block quantizer 7 output from the quantization width calculation circuit 6. Inverse quantization with quantization width. That is, in the block inverse quantizer 10, the image data output from the differential signal decoder 9 is multiplied by the same quantization width Q as the quantization width Q in the block quantizer 7 and output to the computing unit 11. The

  In the adder 11, the image data output from the block inverse quantizer 10 is the same as the representative value data output from the representative value calculation circuit 5 and subtracted from the calculation output of the calculator 3 in the subtractor 4. The representative value data is added, and the added data is supplied to the adder 70 and the adder 72.

  As a result, the subtracter 70 and the adder 72 are identical to the block of image data with 10-bit accuracy before being converted into the block of image data with 8-bit accuracy by the subtractor 4 and the block quantizer 7 (exactly). Since a quantization error is included, almost the same block of image data is supplied.

The signal S2 output from the adder 11 is output to the subtracter 70 and the adder 72. In the subtractor 70, the difference S3 between the signal S1 from the calculator 3 and the signal S2 from the adder 11 is calculated as follows: S3 = S1-S2
The difference signal S3 is output to the variable length coding circuit 71 and the adder 72.

  The variable length coding circuit 71 performs variable length coding on the difference signal S3 from the subtractor 70, and outputs the output bit stream (correction bit stream) as transmission data via the transmission buffer 73. The transmission data is transmitted through the transmission path 74. Is transmitted to the receiving side through the recording medium or recorded on the recording medium 75.

  The adder 72 adds the signal S2 from the computing unit 11 and the signal S3 from the subtractor 70, and outputs this addition signal to the adder 12.

  Through the above processing, information lost by the DCT processing and the processing of converting the 10-bit image signal into the 8-bit image signal is corrected, and a signal that matches the original signal S1 is input to the arithmetic unit 12.

  The adder 12 is also supplied with a predicted image that has already been decoded and motion-compensated by the motion compensation circuit 14, where the predicted image and the image data from the computing unit 11 are added to obtain the original 10-bit accuracy. Image data (image data with 10-bit accuracy before encoding). The decoded 10-bit precision image data is supplied to and stored in the field memory group 13.

  The field memory group 13 can store 10-bit precision image data. The already decoded 10-bit image data stored in the field memory group 13 is read based on the timing control signal generated by the field memory controller 16 corresponding to the synchronization signal of the input image. The read image signal is motion-compensated in the motion compensation circuit 14 corresponding to the motion vector from the motion prediction circuit 2 and supplied to the computing units 3 and 12. That is, the predicted image is supplied to the calculator 3 and the adder 12.

  As described above, since the 10-bit precision image data is converted to the 8-bit precision image data, the motion prediction circuit 2, the differential signal encoder 8, and the differential signal decoding for the 8-bit precision image data. An image encoding device using the encoder 9 or the like can losslessly encode a 10-bit precision image without degrading the image quality.

  Next, FIG. 8 is a block diagram showing a configuration of an example of an image signal decoding apparatus corresponding to the image signal encoding apparatus of the third embodiment of the present invention.

  The image signal decoding apparatus shown in FIG. 8 can decode the image encoded by the image signal encoding apparatus shown in FIG.

  The encoded image data encoded by the image signal encoding device of FIG. 5 and transmitted via the transmission path 74 or recorded on the recording medium 75 is received by a receiving circuit (not shown), The data is reproduced from the recording medium by the reproduction device and supplied to the variable length decoding (inverse VLC) circuit 21. The inverse VLC circuit 21 performs variable length decoding on the bit stream of the encoded image data, and adds the representative value data or the quantization width Q of the image data added to the header of each block, for example, to the adder 24 or the block The motion vector and motion compensation mode are supplied to the motion compensation circuit 27 while being supplied to the inverse quantizer 23. Further, the inverse VLC circuit 21 supplies the differential signal decoder 22 with the block (quantized width S) of the decoded (variable length decoded) image data.

  Further, the inverse VLC circuit 21 outputs a timing pulse to the memory controller 28 every time the variable length decoding of data corresponding to one image (one screen) is completed. In the memory controller 28, a timing control signal is supplied to the field memory group 26 in response to this timing pulse, whereby the timing of reading image data from the field memory group 26 is controlled. It is made like that.

  The differential signal decoder 22 includes an inverse quantizer 121 and an inverse DCT circuit 122, similarly to the differential signal decoder 9 of FIG. The inverse quantizer 121 inversely quantizes the image data supplied from the inverse VLC circuit 21 according to the quantization width S also supplied from the inverse VLC circuit 21, and outputs it to the inverse DCT circuit 122. The data (DCT coefficient) output from the inverse quantizer 121 is subjected to inverse DCT processing by the inverse DCT circuit 122.

  Here, since the image data to be input / output to / from the differential signal decoder 22 has been converted into 8-bit precision, the differential signal decoder 22 uses the same as in FIG. Bit-quantized image data can be inversely quantized and further subjected to inverse DCT processing.

  The block of image data output from the differential signal decoder 22 is input to the block inverse quantizer 23, where it is quantized by the block quantizer 7 (FIG. 5) output from the inverse VLC circuit 21. Inverse quantization is performed with the same quantization width as the quantization width Q. That is, the block inverse quantizer 23 multiplies the image data output from the differential signal decoder 22 by the same quantization width as the quantization width Q when quantized by the block quantizer 7. .

  As a result, the dynamic range of the block of image data is converted to the same (substantially the same) value as that before encoding by the image signal encoding device of FIG.

  The block of image data dequantized by the block dequantizer 23 is supplied to the adder 24. In the adder 24, the representative value data from the inverse VLC circuit 21 and the block of image data (each pixel data in the block) from the block inverse quantizer 23 are added, and this added data is passed through the adder 93. Are output to the arithmetic unit 25.

  The differential bit stream that is variable length encoded in the variable length encoding circuit 71 of the image signal encoding device of FIG. 5 and supplied from the transmission path 74 or recorded on the recording medium 75 is input to the reception buffer 91. The variable length decoding circuit 92 reads the differential bit stream from the reception buffer 91 and decodes the variable length code from the bit stream. The variable length decoding circuit 92 is paired with the variable length encoding circuit 71 in the image signal encoding device of FIG. 5 and performs the reverse operation.

  The output signal S3 'of the variable length decoding circuit 92 coincides with S3 in the image signal encoding device. The output signal S2 'from the adder 24 matches S2 in the image signal encoding device. The adder 93 adds the output S3 'from the variable length decoding circuit 92 and the output signal S2' from the adder 24, and outputs the result as a signal S1 '. This coincides with S1 in the image signal encoding device of FIG.

  The adder 25 is also supplied with a predicted image in which image data of an already decoded I or P picture is motion compensated by the motion compensation circuit 27, where the predicted image and the image data from the adder 24 are received. Addition is performed and the original 10-bit precision image data (decoded 10-bit precision image data) is decoded. The decoded 10-bit precision image data is supplied to the field memory group 26 and stored therein.

  The field memory group 26 can store 10-bit precision image data, and stores the decoded 10-bit precision image data from the computing unit 25. Of the already decoded 10-bit image data stored in the field memory group 26, the image data of the I or P picture is used as a timing control signal generated by the field memory controller 28 corresponding to the synchronization signal of the input image. Read based on. The read image data is motion-compensated in the motion compensation circuit 14 corresponding to the motion vector from the motion prediction circuit 2 and supplied to the calculator 25. That is, the predicted image is supplied to the calculator 25.

  The image data stored in the field memory group 26 is output to the output terminal based on a timing control signal from the field memory controller 28. The image data output to the output terminal is subjected to predetermined processing such as D / A conversion processing, and is supplied to and displayed on a display (not shown).

  As described above, the image decoding apparatus using the differential signal decoder 22 for image data with 8-bit accuracy and the like encoded by the image encoding apparatus in FIG. An image with 10-bit accuracy can be decoded, and the image completely matches the original image.

  In the image signal encoding device shown in FIG. 5 and the image signal decoding device shown in FIG. 8, not only an image with a bit accuracy of 10 bits but also an image with an accuracy of 9 bits or 11 bits, for example ( Decryption).

  Next, a fourth embodiment of the present invention will be described with reference to FIGS.

  FIG. 9 shows an image signal encoding apparatus as a fourth embodiment of the present invention.

  The image signal encoding apparatus shown in FIG. 9 will be described on the assumption that image data having a bit accuracy higher than 8-bit accuracy, for example, 10-bit accuracy, is input to the apparatus. In this example, a specific example of a 10-bit image signal is shown, but this can be similarly applied to an image signal having a bit accuracy of 10 bits or more.

  The image signal encoding device shown in FIG. 9 has substantially the same configuration as that of the image signal encoding device shown in FIG. 5 described above. Omitted.

  The 10-bit image data read from the field memory group 1 in FIG. 9 is output to the subtracter 70 together with the calculator 3 as a signal S1. The adder 70 is supplied with the output signal S2 from the adder 12.

  Here, the output signal S2 from the computing unit 11 is directly supplied to the adder 12 without going through the adder 72 as shown in FIG. 5, and the adder 12 receives 8 bits by the subtracter 4 and the block quantizer 7. A block of image data that is the same as the block of image data of 10-bit accuracy before being converted to a block of accurate image data (to be exact, almost the same because a quantization error is included) is supplied. . The adder 12 is supplied with a predicted image that has already been decoded and motion-compensated by the motion compensation circuit 14, where the predicted image and the image data from the computing unit 11 are added to obtain the original 10-bit accuracy. Image data (image data with 10-bit accuracy before encoding).

  The decoded 10-bit precision image data is supplied to a subtracter 70 and an adder 72 in the example of FIG.

The subtractor 70 calculates the difference S3 between the signal S1 input to the calculator 3 and the signal S2 from the adder 12 by performing the following calculation.
S3 = S1-S2
The difference data S3 is output to the variable length encoding circuit 71 and the adder 72.

  The variable length coding circuit 71 performs variable length coding on the difference signal S3 from the adder 70 and outputs the output bit stream (corrected bit stream) via the transmission buffer 73.

  The adder 72 adds the signal S2 from the adder 12 and the signal S3 from the subtractor 70 and outputs the result to the adder 12.

  With the above processing, the information lost by the DCT processing and the processing for converting the 10-bit image signal into the 8-bit image signal can be corrected, and the signal S1 matching the original signal is supplied to the field memory group 13 And memorized.

  The field memory group 13 can store 10-bit precision image data. The already decoded 10-bit image data stored in the field memory group 13 is read based on the timing control signal generated by the field memory controller 16 corresponding to the synchronization signal of the input image. The read image data is motion-compensated in the motion compensation circuit 14 in accordance with the motion vector from the motion prediction circuit 2 and supplied to the calculators 3 and 12. That is, the predicted image is supplied to the calculators 3 and 12.

  As described above, since the 10-bit precision image data is converted to the 8-bit precision image data, the motion prediction circuit 2, the differential signal encoder 8, and the differential signal decoding for the 8-bit precision image data. An image encoding device using the encoder 9 or the like can losslessly encode a 10-bit precision image without degrading the image quality.

  Next, FIG. 10 is a block diagram showing a configuration of an example of an image signal decoding apparatus corresponding to the image signal encoding apparatus of the fourth embodiment of the present invention.

  In FIG. 10, portions corresponding to the respective portions in FIG. 8 are given the same reference numerals and description thereof is omitted. The image signal decoding apparatus shown in FIG. 10 can decode an image encoded by the image signal encoding apparatus shown in FIG.

  In the image signal decoding apparatus shown in FIG. 10, the difference from the configuration of FIG. 8 is the insertion position of the adder 93, and the output from the adder 24 is sent directly to the calculator 25. The output signal S2 ′ is sent to the adder 93. The adder 93 adds the difference signal S3 ′ from the inverse VLC circuit 92 and the output signal S2 ′ from the calculator 25. The output signal S1 'from the adder 93 is sent to the field memory group 26.

  That is, the block of image data inversely quantized by the block inverse quantizer 23 is supplied to the adder 24. The adder 24 adds the representative value data from the inverse VLC circuit 21 and the block of image data from the block inverse quantizer 23 (each pixel data in the block), and outputs the addition data to the calculator 25.

  The computing unit 25 is also supplied with a predicted image in which the image data of the already decoded I or P picture is motion compensated by the motion compensation circuit 27, where the predicted image and the image data from the adder 24 are received. Addition is performed and the original 10-bit precision image data (decoded 10-bit precision image data) is decoded. The decoded 10-bit precision image data is input to the adder 93.

  The differential bit stream that is variable length encoded in the variable length encoding circuit 71 of the image signal encoding apparatus of FIG. 9 and supplied from the transmission path 74 or recorded on the recording medium 75 is stored in the reception buffer 91 of FIG. Entered. The variable length decoding circuit 92 reads the differential bit stream from the reception buffer 91 and decodes the variable length code from this bit stream. The variable length decoding circuit 92 is paired with the variable length coding circuit 71 in the image signal coding apparatus, and performs the reverse operation.

  Here, the output signal S3 'of the variable length decoding circuit 92 coincides with the signal S3 in the encoding device of FIG. The output signal S2 'from the arithmetic unit 24 coincides with the signal S2 in the encoding device of FIG. The adder 93 adds the output S3 'of the variable length decoding circuit 92 and the output signal S2' of the arithmetic unit 24, and outputs the result as a signal S1 '. This coincides with the signal S1 in the encoding device of FIG.

  The output signal of the adder 93 is supplied to the field memory group 26 and stored. The field memory group 26 can store 10-bit precision image data, and stores the decoded 10-bit precision image data from the computing unit 25. Of the decoded 10-bit image data stored in the field memory group 26, the image data of the I or P picture is used as the timing control signal generated by the field memory controller 28 corresponding to the synchronization signal of the input image. Read based on. The read image data is motion compensated in the motion compensation circuit 14 in accordance with the motion vector from the motion prediction circuit 2 and supplied to the computing unit 25. That is, the predicted image is supplied to the calculator 25.

  The image data stored in the field memory group 26 is output to the output terminal based on a timing control signal from the field memory controller 28. The image data output to the output terminal is subjected to predetermined processing such as D / A conversion processing, and is supplied to and displayed on a display (not shown).

  As described above, the image signal decoding apparatus using the differential signal decoder 22 for image data with 8-bit accuracy and the like encoded with the image signal encoding apparatus in FIG. An image with 10-bit accuracy can be decoded, and the image completely matches the original image.

  Note that the image signal encoding device shown in FIG. 9 and the image signal decoding device shown in FIG. 10 encode not only images with a bit accuracy of 10 bits, but also images with, for example, 9 bits or 11 bits. And decryption.

  Note that the present invention is not limited to the above-described embodiment. For example, in each of the above-described embodiments, lossless encoding is realized by transmitting a signal for correcting information lost by DCT processing. Although an example of an image signal encoding / decoding device to be performed is shown, the present invention can also be applied to degradation factors other than DCT processing. For example, although the quantization scale is set to 1 in the embodiment, the present invention can be similarly applied to cases where the quantization scale is other than 1. Of course, various modifications can be made without departing from the scope of the present invention.

  According to the above-described embodiment of the present invention, in an image signal encoding method for quantizing a signal obtained by performing an encoding process with a real number operation on an image signal and outputting the quantized signal, Since the local decoded data of the encoded data is compared with the data before the real number operation is performed and the difference is extracted, the difference signal is added to the decoded data, and the signal is corrected to perform lossless encoding. It can be realized. By enabling this lossless encoding, it is possible to realize encoding / decoding of a highly accurate image signal.

  Further, for each predetermined block, the representative value data and the quantization width of the image data are determined, the difference between the image data and the representative value data is calculated, the difference is quantized based on the quantization width, and the first quantum Generate data. Then, a predetermined conversion process is performed on the first quantized data, the conversion coefficient is quantized to generate second quantized data, and the representative value data, the quantized width, and the second quantized data are Encode. Therefore, an image can be encoded and decoded by converting its bit precision.

It is a block diagram which shows the structure of the image signal encoding apparatus as the 1st Embodiment of this invention. It is a block diagram which shows the structure of the image signal decoding apparatus corresponding to the image signal encoding apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the image signal encoding apparatus as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the image signal decoding apparatus corresponding to the image signal encoding apparatus of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the image signal encoding apparatus as the 3rd Embodiment of this invention. It is a figure which shows an example of the dynamic range of the block of image data. It is a figure which shows the other example of the dynamic range of the block of image data. It is a block diagram which shows the structure of the image signal decoding apparatus as the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the image signal encoding apparatus as the 4th Embodiment of this invention. It is a block diagram which shows the structure of the image signal decoding apparatus corresponding to the image signal encoding apparatus of the 4th Embodiment of this invention.

Explanation of symbols

50 motion vector detection circuit, 52 prediction mode switching circuit, 53 operation unit, 55 DCT mode switching circuit, 56 DCT circuit, 57 quantization circuit, 58, 71 variable length coding circuit, 60, 83 inverse quantization circuit, 61, 84 IDCT circuit, 70, 72, 93 adder, 82, 92 variable length decoding circuit

Claims (20)

In an image signal encoding method for outputting a signal obtained by performing an encoding process with a real number operation on an image signal,
Performing an encoding process with a real number operation on the input image signal to generate encoded data;
A step of locally decoding the encoded data and generating data by local decoding;
An image signal encoding method comprising: a step of comparing the local decoded data with image data before the real number calculation and calculating a difference therebetween. The image signal encoding method according to claim 1, wherein the real number calculation is a discrete cosine transform process. The image signal encoding method according to claim 1, wherein the local decoded data is data immediately after the real number calculation process. The encoding process is a process of performing a real number operation after predictive encoding,
The image signal encoding method according to claim 1, wherein the local decoded data is data after decoding after the prediction signal of the prediction encoding is added. The encoding process is a process of performing a real number operation on a difference between representative value data determined for each predetermined block of input image data and original input image data. An image signal encoding method. In an image signal encoding apparatus that outputs a signal obtained by performing an encoding process with a real number operation on an image signal,
Means for performing encoding processing with real number operation on the input image signal and generating encoded data;
Means for locally decoding the encoded data and generating data by local decoding;
An image signal encoding apparatus comprising: means for comparing the local decoded data and the image data before the real number calculation, and calculating a difference between them. The image signal encoding apparatus according to claim 6, wherein the real number calculation is a discrete cosine transform process. The image signal encoding apparatus according to claim 6, wherein the local decoded data is data immediately after the real number calculation process. The encoding process is a process of performing a real number operation after predictive encoding,
The image signal encoding apparatus according to claim 6, wherein the local decoded data is data after decoding after the prediction signal of the prediction encoding is added. The encoding process is a process of performing a real number operation on a difference between the representative value data determined for each predetermined block of the input image data and the original input image data. Image signal encoding apparatus. In an image signal transmission method for transmitting a signal obtained by performing an encoding process with a real number operation on an image signal,
Performing an encoding process with a real number operation on the input image signal to generate encoded data;
A step of locally decoding the encoded data and generating data by local decoding;
A method of transmitting an image signal, comprising: comparing the local decoded data with image data before the real number calculation, calculating a difference thereof, and transmitting the difference data. The image signal transmission method according to claim 11, wherein the real number calculation is discrete cosine transform processing. The image signal transmission method according to claim 11, wherein the local decoded data is data immediately after the real number calculation process. The encoding process is a process of performing a real number operation after predictive encoding,
12. The image signal transmission method according to claim 11, wherein the local decoded data is decoded data after the prediction signal of the predictive encoding is added. The encoding process is a process of performing a real number operation on a difference between representative value data determined for each predetermined block of input image data and original input image data. Image signal transmission method. In a recording medium decodable by a decoding device,
The recording medium records a recording signal that can be decoded by the decoding device.
A process of performing an encoding process with a real number operation on the input image signal to generate encoded data;
A step of locally decoding the encoded data and generating data by local decoding;
A step of comparing the local decoded data with the data before the real number calculation and calculating the difference to generate difference data, and including the encoded data and the difference data obtained by Image signal recording medium. A differential data signal obtained by performing a differential operation between encoded data obtained by performing an encoding process with a real number operation on an image signal, and local decoded data of the encoded data and the image data before the real number operation is performed. In an image signal decoding method for decoding original image data from the encoded data and the difference data,
Decoding the encoded data according to a decoding process corresponding to the encoding process to generate decoded data;
An image signal decoding method comprising: adding the difference data and the decoded data. The image signal decoding method according to claim 17, wherein the decoding process includes at least an inverse discrete cosine transform process. A differential data signal obtained by performing a differential operation between encoded data obtained by performing an encoding process with a real number operation on an image signal, and local decoded data of the encoded data and the image data before the real number operation is performed. In the image signal decoding apparatus for decoding the original image data from the encoded data and the difference data,
Means for decoding the encoded data according to a decoding process corresponding to the encoding process, and generating decoded data;
An image signal decoding apparatus comprising: means for adding the difference data and the decoded data. The image signal decoding apparatus according to claim 19, wherein the decoding process includes at least an inverse discrete cosine transform process.

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