JP2005117146A - Modulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a modulator capable of properly carrying out DC offset adjustment. <P>SOLUTION: A level adjustment unit 11 adjusts a level of an input signal, a low pass filter 12 extracts a signal with a first required frequency band from an output signal of the level adjustment unit 11, and an A/D converter 14 converts the signal into a digital signal. A DC component elimination unit 21 eliminates a DC component of the digital signal through digital signal processing. A modulation processing section 15 modulates the signal from which the DC component is eliminated by digital signal processing. A D/A converter 16 converts the modulated signal into an analog signal and a band pass filter 17 extracts a signal with a second required frequency band. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a modulator corresponding to each modulation method such as DSB (Double Side Band) modulation, SSB (Single Side Band) modulation, ISB (Independent Side Band) modulation and the like.

FIG. 6 is a block diagram showing a configuration of a conventional modulator.
The conventional modulator shown in FIG. 6 includes a level adjuster 11, a low-pass filter 12, a DC offset adjuster 13, an A / D converter 14, a modulation processing unit 15, a D / A converter 16, and a band-pass filter. 17 is included.

  The low frequency signal to be modulated is input to the level adjuster 11. The signal level of the low frequency signal is adjusted by the level adjuster 11 with respect to the signal component in the required band (for example, about 100 Hz to about 3 kHz). The output signal of the level adjuster 11 is band-limited by the low-pass filter 12. The DC signal is removed from the output signal of the low-pass filter 12 by the DC offset adjuster 13. Modulation schemes such as DSB, SSB, and ISB are modulation schemes that use a modulated signal in which a carrier signal component is suppressed compared to general AM modulation or the like in order to increase power efficiency. For this reason, the carrier signal component remaining without being removed is recognized as an unnecessary wave. On the other hand, when the DC component is included in the low frequency signal, the carrier wave signal remains in the process of modulation. For this reason, the DC offset adjustment is performed so that the DC component is not included in the low frequency signal.

  The output signal of the DC offset adjuster 13 is converted from an analog signal to a digital signal by the A / D converter 14. The output signal of the A / D converter 14 is subjected to modulation processing such as DSB, SSB, or ISB by the modulation processing unit 15. The output signal of the modulation processing unit 15 is converted from a digital signal to an analog signal by the D / A converter 16.

  From the output signal of the D / A converter 16, harmonics, sampling clock components, aliasing noise at the time of D / A conversion, and the like are removed by the band pass filter 17. The output signal of the band pass filter 17 becomes a modulation signal obtained by this modulator.

An A / D conversion device having a DC component removal function is known (see, for example, Patent Document 1).
Also, a method of digitally processing a Weber type SSB modulation process is known (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 9-261052 JP2000-223953

  In the conventional modulator shown in FIG. 6, since the DC offset adjustment is performed by analog signal processing, the characteristics of the DC offset adjustment are caused by the fluctuation of the characteristics of the analog parts alone or the fluctuation of the characteristics of the parts due to the change of the ambient temperature. There is a risk of deterioration. In order to suppress such deterioration of characteristics, measures such as single component evaluation at the time of analog component selection and circuit design in consideration of the result are generally taken. There is a problem that the circuit becomes higher or the circuit becomes complicated. In addition, since it is common that the removal amount in the DC offset adjustment can be adjusted by a variable resistor or the like, the adjustment of this portion is indispensable, and this adjustment man-hour is required.

  Even the techniques disclosed in Patent Document 1 and Patent Document 2 cannot solve the above-described problems associated with DC offset adjustment.

  The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide a modulator capable of appropriately performing DC offset adjustment.

  In order to achieve the above object, the present invention provides level adjusting means for adjusting the level of an input signal, low-pass filtering means for extracting a signal of a first required frequency band from an output signal of the level adjusting means, Digitizing means for digitizing the output signal of the low-pass filtering means, DC removing means for removing a DC component from the output signal of the digitizing means by digital signal processing, and output signal of the DC removing means as a digital signal Modulating means for modulating by processing, analogizing means for analogizing the output signal of the modulating means, and band filtering means for extracting a signal of the second required frequency band from the output signal of the analogizing means .

  By taking such measures, the input signal is digitized after level adjustment and low-pass filtering. The DC component removal and modulation processing is performed by digital signal processing on the digitized signal. The modulated signal is analogized and then banded.

The present invention also includes the following technical concepts.
[Concept 1]
The direct current removing means of the present invention comprises:
Means for adding the output signal of the digitizing means and the first signal to output a second signal;
Delay means for latching the second signal for each sampling period and outputting it as a third signal;
Means for multiplying the third signal by a first constant and outputting the first signal;
Means for multiplying the third signal by a second constant to output a fourth signal;
A modulator comprising: means for subtracting the fourth signal from the output signal of the digitizing means.

[Concept 2]
The direct current removing means of the present invention comprises:
Delay means for subtracting the first signal from the output signal of the digitizing means and outputting a second signal;
Means for adding the second signal and the third signal to output a fourth signal;
Means for latching the fourth signal for each sampling period and outputting it as the third signal;
A modulator comprising: means for multiplying the third signal by a constant and outputting the first signal.

[Concept 3]
The DC removal means calculates a DC component in the absence of the input signal, stops the calculation in the presence of the input signal, and removes the DC component using the value of the DC component calculated immediately before the stop. The modulator according to any one of the concept 1 and the concept 2 according to the present invention.

[Concept 4]
The modulator according to Concept 1, wherein the delay unit stops latching in the presence of the input signal, and outputs a value latched immediately before stopping as a third signal for each sampling period.

[Concept 5]
3. The modulator according to concept 2, wherein the delay unit stops latching in a state where the input signal is present, and outputs a value latched immediately before stopping as a second signal for each sampling period.

  Since the removal of the DC component is performed by digital signal processing, the modulator can perform the DC offset adjustment appropriately.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a modulator according to an embodiment of the present invention. The same parts as those in FIG. 6 are denoted by the same reference numerals.

  The modulator of this embodiment includes a level adjuster 11, a low-pass filter 12, an A / D converter 14, a modulation processing unit 15, a D / A converter 16, a band-pass filter 17, and a DC component removal unit 21. .

  A low frequency signal to be modulated is input to the level adjuster 11. The level adjuster 11 adjusts a signal level with respect to a signal component (for example, about 100 Hz to 3 kHz) in a required band included in the low frequency signal. This level adjustment is performed when a low-frequency signal of a specified level (for example, 0 dBm) is input, this signal is input to an appropriate level (for example, the saturation input of the A / D converter 14) at the input terminal of the A / D converter 14. (About one half of the level).

  The low-pass filter 12 limits the band of the output signal of the level adjuster 11. This band limitation is used for the purpose of preventing an unnecessary signal from being folded back and added to the required band when performing A / D conversion, that is, for the purpose of so-called anti-aliasing, and the amplitude in the required band is Designed to be flat.

  The A / D converter 14 converts the output signal of the low-pass filter 12 from an analog signal to a digital signal.

  The DC component removing unit 21 removes the DC component from the output signal of the A / D converter 14 by digital signal processing. The DC component removal unit 21 receives a low frequency input determination signal. This low-frequency input determination signal is a signal indicating whether or not there is a low-frequency signal input to the level adjuster 11. For example, a PTT (Press To Talk) signal used in a half-duplex communication system communication device. Is available. The DC component removal unit 21 turns ON / OFF the adjustment operation of the removal amount of the DC component according to the low frequency input determination signal.

  The modulation processing unit 15 corresponds to any one of the DSB modulation method, the SSB modulation method, and the ISB modulation method. The modulation processing unit 15 performs modulation processing on the output signal of the DC component removal unit 21.

  The D / A converter 16 converts the output signal of the modulation processing unit 15 from a digital signal to an analog signal.

  The band pass filter 17 removes harmonics, sampling clock components, aliasing noise during D / A conversion, and the like from the output signal of the D / A converter 16. The output signal of the band pass filter 17 is a modulation signal obtained by the modulator of this embodiment.

  The DC component removing unit 21 and the modulation processing unit 15 can be configured using a DSP, FPGA, a dedicated device (such as an ASIC), and the like. Even if any one of these devices is used, a plurality of different components can be used. A combination of devices may be used.

  The low-pass filter 12 and the band-pass filter 17 can be easily configured by using a ceramic filter or the like (when the signal is several hundred kHz) according to the frequency of the signal.

FIG. 2 is a block diagram showing an internal configuration of the direct current component removing unit 21.
As shown in FIG. 2, the DC component removing unit 21 includes an adder 211, a one sample delay unit 212, a multiplier 213, a multiplier 214, and a subtracter 215.

  The adder 211 receives an output signal from the A / D converter 14 (hereinafter referred to as signal a) and an output signal from the multiplier 213 (hereinafter referred to as signal d). The adder 211 outputs a signal having a sum of the value of the signal a and the value of the signal d (hereinafter referred to as a signal b).

  The 1-sample delay device 212 receives the signal b and the low-frequency input determination signal g. The one-sample delay unit 212 delays the signal b by one sample only when the low-frequency input determination signal g indicates that there is no low-frequency signal. Here, it is assumed that the signal g is at L level when there is no low frequency signal. The one-sample delay unit 212 does not newly latch the signal b when the low-frequency input determination signal g indicates that there is a low-frequency signal, that is, when the low-frequency input determination signal g is at the H level. The already latched value is output repeatedly.

  The multiplier 213 receives the output signal of the 1-sample delay device 212 (hereinafter referred to as signal c) and a constant A. The multiplier 213 outputs a signal having a product value of the value of the signal c and the constant A as the signal d.

  The multiplier 214 receives the signal c and the constant B. Multiplier 214 outputs a signal having a product value of signal c and constant B (hereinafter referred to as signal e).

  A signal a and a signal e are input to the subtracter 215, respectively. The subtractor 215 outputs a signal (hereinafter referred to as a signal f) having a difference value between the signal a and the signal e. This signal f is input to the modulation processing unit 15 as an output signal of the DC component removal unit 21.

Next, the operation of the modulator configured as described above will be described.
FIG. 3 is a timing chart showing the flow of calculation in the DC component removal unit 21. FIG. 3 shows, in chronological order, changes in the signals b, c, d, e, and f with respect to the input of the signal a and the low-frequency input determination signal g. The constant A and the constant B are values “0.999” and “0.001”, respectively, and an impulse signal having a value “1.0” is input to the signal a for the sake of simplicity. In addition, the DC component is calculated and updated when the low-frequency input determination signal g is at the logic level L level. The sampling clock in FIG. 3 is a digital signal update cycle. Every time the sampling clock rises (strictly, from the time immediately after the rise to the time immediately before the next rise), the digital signal processing for one sample of data is completed. The sampling clock is numbered for convenience, and the period from immediately after the sampling clock of number “0” (referred to as sampling clock (0)) rises to just before the sampling clock of number “1” rises is referred to as “state 0”. (Same for other periods) The signal a in state 0 is denoted as signal a (0) (the same applies to other signals). By the way, although a sampling clock is not described in FIGS. 1 and 2, it is omitted because it is a common-sense signal in digital signal processing. Strictly speaking, digital signal processing is performed in synchronization with the sampling clock. Done.

  In FIG. 3, the values of the respective parts in the initial state (state 1) are all set to the value “0”, and the impulse is input at the timing of state 0. The operation of each part at the rising edge of the sampling clock will be briefly described as follows.

  First, the operation of the one sample delay unit 212 will be described. The one-sample delay device 212 latches the value of the signal b and outputs it as the signal c when the low frequency input determination signal g is at the L level. When the value of the low-frequency input determination signal g is H level, the one-sample delay device 212 does not latch the value of the signal b and does not update the signal c. The 1-sample delay unit 212 performs a latch operation at the rising timing of the sampling clock. Therefore, the signal c is not latched in a state where the sampling clock is fixed at the L or H level or a state where the sampling clock falls. The value is not updated.

  Next, operations of the adder 211, the multiplier 213, the multiplier 214, and the subtractor 215 will be described. The adder 211 starts adding the signal a and the signal d immediately after the rising edge of the sampling clock, ends the adding process immediately before the rising edge of the next sampling clock, and outputs the signal b. The multiplier 213 starts multiplication of the signal c and the constant A immediately after the rising edge of the sampling clock, ends the multiplication processing immediately before the next rising edge of the sampling clock, and outputs the signal d. The multiplier 214 starts the multiplication of the signal c and the constant B immediately after the rising edge of the sampling clock, ends the multiplication processing immediately before the rising edge of the next sampling clock, and outputs the signal e. The subtracter 215 starts subtracting the signal e from the input signal a immediately after the rising edge of the sampling clock, ends the subtraction process immediately before the rising edge of the next sampling clock, and outputs the output signal f.

When the above operation is executed from the sampling clock (0) to the sampling clock (6) in FIG. 3, the following processing is performed.
First, the sampling clock (0) to (2) is as follows. Since the low frequency input determination signal g during this period is at the L level, the 1-sample delay device 212 executes a delay operation.
[Sampling clock (0)]
Signal c (0) = signal b (-1) = 0
Signal d (0) = Signal c (0) × 0.999 = 0 × 0.999 = 0
Signal b (0) = input signal a (0) + signal d (0) = 1.0 + 0 = 1.0
Signal e (0) = Signal c (0) × 0.001 = 0 × 0.001 = 0
Signal f (0) = input signal a (0) signal e (0) = 1.0−0 = 1.0
[Sampling clock (1)]
Signal c (1) = signal b (0) = 1.0
Signal d (1) = Signal c (1) x 0.999 = 1.0 x 0.999 = 0.999
Signal b (1) = input signal a (1) + signal d (1) = 0 + 0.999 = 0.999
Signal e (1) = Signal c (1) x 0.001 = 1.0 x 0.001 = 0.001
Signal f (1) = input signal a (1) −signal e (1) = 0−0.001 = −0.001
[Sampling clock (2)]
Signal c (2) = Signal b (1) = 0.999
Signal d (2) = Signal c (2) x 0.999 = 0.999 x 0.999 = 0.998001
Signal b (2) = Input signal a (2) + Signal d (2) = 0 + 0.998001 = 0.998001
Signal e (2) = Signal c (2) x 0.001 = 0.999 x 0.001 = 0.000999
Signal f (2) = input signal a (2) −signal e (2) = 0−0.001 = −0.000999
Subsequently, the sampling clocks (3) to (6) are as follows. Since the low frequency input determination signal g from the sampling clocks (3) to (5) is at the H level, the one sample delay unit 212 holds the value one sample before without executing the delay operation. Since the low frequency input determination signal g of the sampling clock (6) is at the L level, the one sample delay unit 212 executes a delay operation.
[Sampling clock (3)]
Signal c (3) = Signal c (2) = 0.998001
Signal d (3) = Signal c (3) × 0.999 = 0.998001 × 0.999 = 0.997002999
Signal b (3) = input signal a (3) + signal d (3) = 0 + 0.99700299 = 0.997002999
Signal e (3) = Signal c (3) × 0.001 = 0.998001 × 0.001 = 0.000998001
Signal f (3) = input signal a (3) −signal e (3) = 0−0.001 = 0.000998001
[Sampling clock (4)]
Signal c (4) = Signal c (3) = 0.998001
Signal d (4) = Signal c (4) × 0.999 = 0.998001 × 0.999 = 0.997002999
Signal b (4) = input signal a (4) + signal d (4) = 0 + 0.99700299 = 0.997002999
Signal e (4) = Signal c (4) × 0.001 = 0.998001 × 0.001 = 0.000998001
Signal f (4) = input signal a (4) signal e (4) = 0−0.001 = −0.000998001
[Sampling clock (5)]
Signal c (5) = Signal c (4) = 0.998001
Signal d (5) = Signal c (5) × 0.999 = 0.998001 × 0.999 = 0.997002999
Signal b (5) = input signal a (5) + signal d (5) = 0 + 0.99700299 = 0.997002999
Signal e (5) = Signal c (5) × 0.001 = 0.998001 × 0.001 = 0.000998001
Signal f (5) = input signal a (5) signal e (5) = 0−0.001 = −0.000998001
[Sampling clock (6)]
Signal c (6) = Signal b (5) = 0.997002999
Signal d (6) = Signal c (6) × 0.999 = 0.997002999 × 0.999 = 0.996005996
Signal b (6) = input signal a (6) + signal d (6) = 0 + 0.996005996 = 0.996005996
Signal e (6) = Signal c (6) × 0.001 = 0.997002999 × 0.001 = 0.000997003
Signal f (6) = input signal a (6) signal e (6) = 0−0.001 = −0.000997003
In this way, the adder 211, the one sample delay unit 212, the multiplier 214, and the multiplier 213 perform the weighted addition process of the signal a. When the signal a is an AC signal such as an audio signal, for example, a signal equivalent to a DC component can be obtained by weighted addition processing. That is, a signal e equivalent to the direct current component is extracted. Then, the signal e is subtracted from the signal a by the subtractor 215 to remove the DC component from the signal e.

  FIG. 4 is a diagram showing the DC component removal characteristics of the DC component removal unit 21 when “0.999” is given to the constant A and “0.001” is given to the constant B. FIG. 4 shows frequency characteristics of the signal f when the horizontal axis is the frequency [Hz] and the vertical axis is the amplitude [dB], and the impulse is input as the signal a.

  It can be seen from the characteristics shown in FIG. 4 that a large attenuation is obtained at a low frequency of several tens of Hz. This characteristic varies depending on the values of constant A and constant B. That is, since the direct current component removal characteristic of the direct current component removing unit 21 can be adjusted by changing the values of the constant A and the constant B, the performance required for the modulator is appropriately selected from the constant A and the constant B. Can be achieved.

  When a low frequency signal is input to the level adjuster 11, the level of the low frequency signal is adjusted by the level adjuster 11, the band is limited by the low pass filter 12, and the DC component is still included. The signal is converted into a digital signal by the A / D converter 14. Then, the output signal of the A / D converter 14 is input to the DC component removing unit 21 as the signal a, so that the DC component is removed by the above-described action. The output signal of the DC component removing unit 21, that is, the signal after the DC component is removed, is subjected to modulation processing by the modulation processing unit 15. The output signal of the modulation processing unit 15 is converted from a digital signal to an analog signal by the D / A converter 16, and then harmonics, sampling clock components, aliasing noise at the time of D / A conversion, or the like by the band pass filter 17. Is output as a modulated signal.

  As described above, according to the modulator of the present embodiment, the direct current component removing unit 21 removes the direct current component by digital processing. Therefore, unlike the analog processing, the deterioration of characteristics due to the ambient temperature and the aging of the components is not caused. Since it does not occur, a more stable DC component removal operation can be realized. In the past, in order to satisfy the DC component removal characteristics under ambient temperature conditions, more expensive analog parts and complicated compensation circuits were provided to cope with this problem. Even if a component is generated, it can be removed by subsequent digital signal processing, so that the cost of the analog component can be reduced. Furthermore, since there is no need to adjust the removal amount of the direct current component, a commonly used variable resistor is not required, which contributes to reduction of component costs and manufacturing man-hours (adjustment man-hours).

  Further, according to the modulator of the present embodiment, the update of the weighted addition process can be stopped by controlling the one-sample delay unit 212 according to the state of the low-frequency input determination signal g. For this reason, since it is possible to perform processing only when there is no signal input to the input signal a, weighted addition processing can be realized by a method that handles a smaller amplitude value than when there is signal input. It is possible to reduce the circuit scale (calculation bit length) required for the operation. For example, when the standard input level of the signal a is 0 dBm, the amplitude is 774 mVrms when the input impedance is 600Ω. On the other hand, the amplitude when there is no signal at the input is about 6 mVrms or less. Even if the DC component is added by 10 mV in the processing from the level adjuster 11 to the A / D converter 14, the amplitude is 50 minutes. Therefore, it is possible to reduce the circuits necessary for the weighted addition process.

  Control of the DC component removing unit 21 using such a low frequency input determination signal g is useful because it is considered that the fluctuation of the DC offset is small if transmission is performed for a relatively short time. However, in the case of a system that continues to transmit continuously for a long time, the DC removal is not performed for a long time, and there is a possibility that the DC offset may fluctuate during this time. In this case, the DC offset removal process is operated regardless of the presence or absence of an input signal.

  The present invention is not limited to the above embodiment. For example, the specific configuration of the DC component removing unit 21 can be variously changed.

FIG. 5 is a block diagram showing a modified configuration example of the DC component removing unit 21. In addition, the same code | symbol is attached | subjected to the same part as FIG.
5 includes a subtractor 215, an adder 216, a one-sample delay unit 217, and a multiplier 218.

  The adder 216 receives the signal f output from the subtracter 215 and the output signal of the 1-sample delay unit 217 (hereinafter referred to as signal i). The adder 216 outputs a signal (hereinafter referred to as a signal j) having a sum value of the value of the signal f and the value of the signal i.

  The 1-sample delay device 217 receives the signal h and the low frequency input determination signal g. The one-sample delay unit 217 delays the signal h by one sample only when the low-frequency input determination signal g indicates that there is no low-frequency signal. The one-sample delay unit 212 does not newly latch the signal h when the low-frequency input determination signal g indicates that there is a low-frequency signal, that is, when the low-frequency input determination signal g is at the H level. The already latched value is output repeatedly.

  The multiplier 218 receives the signal i and the constant A. The multiplier 213 outputs a signal having a product value of the value of the signal i and the constant A as the signal e. The constant A is a value smaller than 1.0.

  The DC component removing unit 21 shown in FIG. 5 performs cumulative addition processing in the adder 216, the one sample delay unit 217, and the multiplier 218 in synchronization with the rising timing of the sampling clock, as in the first embodiment. Thus, a signal e equivalent to the DC component is generated. The DC component is removed from the signal a by subtracting the signal e from the signal a by the subtractor 215.

  In short, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

The block diagram which shows the structure of the modulator which concerns on one Embodiment of this invention. The block diagram which shows the internal structure of the direct-current component removal part 21 in FIG. The timing chart which showed the flow of calculation in the direct-current component removal part 21 shown in FIG. The figure which shows the DC component removal characteristic of the DC component removal part 21 shown in FIG. The block diagram which shows the modification structural example of the direct-current component removal part 21 in FIG. The block diagram which shows the structure of the conventional modulator.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Level adjuster, 12 ... Low pass filter, 13 ... DC offset adjuster, 14 ... A / D converter, 15 ... Modulation processing part, 16 ... D / A converter, 17 ... Band pass filter, 21 ... DC component remover, 211, 216 ... adder, 212, 217 ... 1 sample delay, 213, 214, 218 ... multiplier, 215 ... subtractor.

Claims (1)

Level adjusting means for adjusting the level of the input signal;
Low-pass filtering means for extracting a signal of a first required frequency band from the output signal of the level adjusting means;
Digitizing means for digitizing the output signal of the low-pass filtering means;
DC removing means for removing a DC component from the output signal of the digitizing means by digital signal processing;
Modulating means for modulating the output signal of the direct current removing means by digital signal processing;
Analogizing means for analogizing the output signal of the modulating means;
A modulator comprising: band filtering means for extracting a signal of a second required frequency band from the output signal of the analogization means.

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