JP2005115925A - Circuit design verification method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit design verification method of a semiconductor integrated circuit capable of executing verification of driving capability in a realistic execution condition at a full-chip level to the semiconductor integrated circuit including a large-scale analog circuit. <P>SOLUTION: This circuit design verification method comprises: an on-resistance extraction process for extracting a driver circuit for driving an internal signal node from a net list for describing all the circuits for every internal signal node to extract on-resistance in a driving path of the driver circuit for every internal signal node; a load capacity extraction process for extracting driving load capacity to be driven from the net list for every internal signal node; and a time constant extraction process for extracting the product of the driving load capacity and the on-resistance as a time constant for every internal signal node. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit design verification method for a semiconductor integrated circuit. More specifically, the present invention relates to a drive capability for an internal signal node driven by each of a plurality of driver circuits included in all circuits of the semiconductor integrated circuit. The present invention relates to a circuit design verification method for a semiconductor integrated circuit to be verified for all.

  Normally, when performing a transistor level circuit simulation of a large scale integrated circuit, all designed circuit diagrams are read. In this case, since the current flowing through each transistor varies depending on the voltage applied to the transistor based on the IV characteristics of each transistor, simulation is performed at an analog level while detecting a subtle difference in voltage. Therefore, in the circuit simulation at the transistor level, the computation load applied to the computer is great, and the time required for the simulation is also long.

In logic simulations using only digital circuits, the signal level (voltage value) is only detected at two levels, 0 or 1. Therefore, the amount of data required for the simulation is small, and it is possible to perform simulations much faster than transistor-level simulations. It is. Therefore, all signal patterns related to the circuit operation can be confirmed by simulation. On the other hand, in a circuit simulation including an analog circuit, for example, an intermediate value until the signal level transitions from 0 to 1 needs to be finely divided and verified in an analog manner. The accuracy of simulation depends on the way of division. As the data is divided finely, the amount of data increases and the simulation execution time also increases. Therefore, since it takes at least 10 times as long as the logic simulation just to check the operation of one signal pattern, it is very difficult to check the circuit operation for all the signal patterns related to the circuit operation. In addition, in order to verify how many circuit elements are connected to one wiring and how much the wiring parasitic capacitance affects the operation, the driving capability verification using the predicted wiring capacitance before creating layout data Verification of drive capability using the actual wiring capacitance after layout data creation is performed at the standard cell level or gate level of a logic circuit or the like. The following Patent Document 1 discloses an example of circuit verification in such a logic circuit or the like. FIG. 6 shows a flow of the circuit verification. In this circuit verification flow, since all are based on circuit data of logic design, and the signal delay on the signal line of the circuit is calculated based on the fan-out information of the gate, the verification is extremely rough.
Japanese Patent Laid-Open No. 5-102306

  As the integration of semiconductor integrated circuits increases, high-speed verification of the entire chip is performed in consideration of functional limitations, timing-specific verification, and drive check in consideration of wiring load. However, in the case of an analog circuit, since continuous current and voltage are processed, not only logic verification of 1 and 0 but also simulation at the transistor level is required. The transistor level simulation of a semiconductor integrated circuit including a large-scale analog circuit is extremely difficult to realize at a full chip level including all circuits due to restrictions on computer capabilities and verification tools. Even if it can be executed, there is a high possibility that it will not end in a realistic time. In particular, when the wiring parasitic capacitance is taken into account, the number of elements becomes large due to the capacitance element, so that dynamic simulation is almost impossible.

  Accordingly, it is desired that even in a semiconductor integrated circuit including a large-scale analog circuit, driving capability verification (drive check) at a full chip level can be performed under realistic execution conditions.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to verify the driving capability of a semiconductor integrated circuit including a large-scale analog circuit under a realistic execution condition at a full chip level. An object is to provide a circuit design verification method for a semiconductor integrated circuit that can be executed.

  In order to achieve this object, a semiconductor integrated circuit circuit design verification method according to the present invention (hereinafter referred to as “method of the present invention”) is driven by a plurality of driver circuits included in all the circuits of the semiconductor integrated circuit. A circuit design verification method for a semiconductor integrated circuit for verifying the drive capability for an internal signal node for all of the internal signal nodes, comprising: a driver circuit for driving the internal signal node from a netlist describing the entire circuit; An on-resistance extraction step of extracting for each internal signal node and extracting an on-resistance of the drive path of the driver circuit for each internal signal node, and a drive load capacity to be driven for each internal signal node from the net list A time constant extraction step for extracting a product of the drive load capacity and the on-resistance as a time constant for each of the internal signal nodes and the load capacity extraction step to be extracted The first characterized by a step.

  With the above characteristic configuration, the drive capability of the drive path of the driver circuit that drives the load capacitance of the internal signal node is set as a time constant for all of the internal signal nodes that are driven by the plurality of driver circuits included in the entire circuit. A comprehensive evaluation is possible. As a result, it is possible to easily and quickly verify the location where the driving capability is insufficient over the entire circuit. In particular, according to the above-described feature configuration, it is possible to evaluate the driving capability even for an analog circuit having no attribute information regarding the driving capability such as fan-out used for logic circuit design. However, it is difficult to perform the simulation, and it is possible to easily and quickly verify the driving capability over the entire circuit. The on-resistance in the first characteristic configuration may be a relative value instead of an absolute value. For example, the same evaluation is possible even when the on-resistance ratio is based on the on-resistance of a standard transistor.

  Furthermore, in addition to the above-described characteristic configuration, the method of the present invention has a second characteristic that the driver circuit is extracted from a specific gate circuit in the on-resistance extraction step. With such a characteristic configuration, the driver circuit can be extracted easily and quickly even in a large-scale circuit, and the load on the computer used for verification can be reduced and the verification time can be shortened.

  In addition to the above-described characteristic configuration, the method of the present invention further includes a transistor that extends from the internal signal node to the power supply line or the ground line via the one or more transistors for each internal signal node in the on-resistance extraction step. Searching for all transistor paths that do not pass through the gate electrode of the transistor in the path, and extracting a circuit composed of a group of transistors included in the searched transistor path as a driver circuit for driving the internal signal node is third. It is characterized by. With such a characteristic configuration, the driver circuit included in the entire circuit is extracted without being limited to the gate level circuit. Furthermore, the search for the driver circuit can be performed using either circuit diagram data that maintains a hierarchical structure or data that does not have a hierarchical structure, which is suitable for analog circuit design that does not have an attribute as a gate.

  Further, according to the method of the present invention, in addition to any one of the above-described features, in the on-resistance extraction step, the on-resistance is a sum of on-resistances of circuit elements existing in a drive path of the driver circuit. It is a fourth feature that it is extracted by calculating from the circuit constants of the circuit elements included in. With this feature configuration, the on-resistance of the drive path can be accurately extracted from the circuit information in the netlist, so that accurate drive capability evaluation can be performed easily and quickly.

  Furthermore, in addition to any one of the above-described features, the method of the present invention extracts the maximum value of the on-resistance of the drive path as the maximum on-resistance for each internal signal node in the on-resistance extraction step, In the time constant extracting step, a fifth feature is that a maximum time constant using the maximum on-resistance is extracted for each internal signal node. With this characteristic configuration, one driving path with the weakest driving capability is extracted for each internal signal node, so that the number of extracted time constants is limited to the number of internal signal nodes, and the internal capacity where the driving capability is insufficient among them. Signal nodes can be extracted efficiently.

  Further, according to the method of the present invention, in addition to any one of the above feature configurations, the load capacity extraction step extracts a receiver circuit connected to the internal signal node from the net list for each internal signal node, and A first load capacitance extracting step for extracting a load capacitance of the receiver circuit for each signal node; and a first step of extracting a wiring capacitance caused by a wiring portion of the internal signal node from layout data or the netlist corresponding to all the circuits. A second load capacity extracting step, wherein the drive load capacity is calculated as the sum of the load capacity of the receiver circuit and the wiring capacity for each internal signal node. With this feature configuration, the drive load capacitance can be extracted with high accuracy in a state close to an actual device by dividing the load capacitance parasitic on the receiver circuit side and the load capacitance parasitic on the wiring. Here, as the load capacitance parasitic on the receiver circuit side, for example, the gate capacitance of the transistor existing in the input stage of the receiver circuit, the junction capacitance of the drain or the source, etc. are obtained or calculated from the attribute information related to the transistor of the netlist. can do. Further, the wiring capacity can be calculated from the dimension information about the wiring pattern in the layout data, the positional relationship information with other wirings, and the like. Alternatively, if it has already been extracted as a capacitive element on the net list, the information may be used.

  Furthermore, in the sixth feature configuration, a layout matching step of performing one-to-one association between the internal signal node on the net list and the internal signal node on layout data corresponding to all the circuits. In the second load capacitance extracting step, it is preferable that the wiring capacitance is calculated based on wiring pattern information of the internal signal node on the layout data. This enables collation between the created layout data and the netlist corresponding to all the designed circuits, so that the correspondence between the layout data and the designed circuits can be verified, and based on the verified layout data The wiring capacity of the internal signal node having a corresponding relationship with the netlist can be calculated with high accuracy from the dimension information regarding the wiring pattern of the layout data, the positional relationship information with other wirings, and the like. As a result, in the final design stage after the layout is completed, both verification with the layout circuit diagram and more reliable driving capability verification based on the completed layout data can be performed simultaneously.

  Further, according to the method of the present invention, in addition to any one of the above feature configurations, the netlist is a non-hierarchical netlist generated by hierarchically expanding circuit diagram data having a hierarchical structure describing the entire circuit. This is the seventh feature. With such a feature configuration, for example, in analog circuit design, there are cases where the circuit diagram and layout data at the full chip level do not have the same hierarchical structure or cell structure. It is possible to eliminate the difficulty in associating with signal nodes and extracting wiring capacities over multiple layers. Here, by expanding the hierarchy to flat data, redundancy increases and the amount of data increases. However, the amount of data increases by deleting unnecessary data while leaving only the information necessary for driving capability evaluation. Can be suppressed.

  Further, according to the method of the present invention, in addition to any one of the first to sixth feature configurations, the net list is a non-hierarchical net list generated from layout data corresponding to all the circuits. Eight features. With this feature configuration, it is possible to extract the driver circuit and its on-resistance, and the driving load capacity consisting of the wiring capacity and the load capacity of the receiver circuit, in a form close to an actual device based on the layout data, and highly accurate driving capability verification Is possible.

  Furthermore, the method of the present invention includes a display step of identifying and displaying the corresponding internal signal node that exceeds a predetermined value of the time constant extracted in the time constant extraction step in addition to any one of the above-described feature configurations. The ninth feature is to have. The method of the present invention further includes a display step of specifying and displaying the internal signal nodes corresponding to the order of the time constants extracted in the time constant extraction step in addition to any of the above-described feature configurations. Is a tenth feature. Such a characteristic configuration makes it easier to identify an internal signal node with insufficient driving capability.

  Furthermore, in addition to any of the ninth or tenth feature configurations, the method of the present invention multiplies the time constant by a predetermined delay coefficient for each internal signal node, and sets the drive delay time of the drive path. A delay time calculating step for calculating, wherein in the display step, the driving delay time corresponding to the displayed time constant is displayed in addition to the time constant or in place of the time constant. And With such a characteristic configuration, it is possible to more specifically grasp the degree of deficiency in the driving capability of the extracted internal signal node having insufficient drivability.

  An embodiment of a circuit design verification method for a semiconductor integrated circuit according to the present invention (hereinafter referred to as “the present invention method” as appropriate) will be described with reference to the drawings.

  Normally, logic circuits, timing simulations, and drive checks (driving capability verification) such as fan-out are performed in the logic circuit, but similar verifications need to be performed in the analog circuit. In particular, since an analog circuit takes time for simulation, it is difficult to cover all the timing verification in every part of the circuit. However, with respect to internal signal nodes on all the circuits, load capacitance connected to each internal signal node, for example, device capacitance such as capacitance parasitic to the gate, drain, source, etc. of the transistor, and signals constituting the internal signal node If it is possible to obtain all the wiring capacitance parasitic on the wiring, etc., and verify whether the driver circuit that drives the load capacitance to satisfy the circuit operation is properly assigned under the worst condition, No driving ability verification can be realized. In the method of the present invention, how to realize such a leak-free driving capability verification will be described below. Here, “inside” of the internal signal node means a signal node inside the semiconductor integrated circuit. Therefore, the driver circuit in the method of the present invention does not originally verify the drive capability of the output stage such as an output driver for driving an external device. Note that the driving capability of the output driver can be verified by virtually setting the load capacity.

  In the method of the present invention, in order to perform a simulation in a form as close to an actual device as possible, the driving capability verification is performed by hierarchically combining a first netlist extracted from layout data and all circuit diagrams in which all circuits are described hierarchically. Execution is performed using the second netlist that is expanded and made hierarchical. However, in the first netlist extracted from the layout data, signal names are not assigned to all signal wirings, so that the target signal is an appropriate signal that differs from the signal name on the circuit diagram by the layout tool. Since a name (node name) is allocated, even if an attempt is made to confirm the result by simulation, it is difficult to analyze the simulation result because correspondence with the circuit diagram cannot be obtained. If the simulation is performed using the signal name of the circuit diagram data, the output result can be easily confirmed.

  Therefore, in order to extract the first netlist from the layout and use the circuit name data as the signal name, the wiring name of the wiring of the layout data and the wiring name of the wiring of the circuit diagram data are used as the wiring connection information. The layout data wiring is given signal name information of the wiring of the circuit diagram data in a one-to-one correspondence while checking whether the connection is correct. Then, a first net list is extracted from the layout data, and a first net list using the signal name of the circuit diagram data as a signal name is created.

  Furthermore, if the parasitic capacitance in the signal wiring is also extracted at the same time, the verification closer to the actual device becomes possible. Since the parasitic capacitance of the signal wiring is parasitic not only between the internal signal node corresponding to the signal wiring and the substrate but also between the wirings, it exists beyond the hierarchy of layout data and circuit diagram data. Therefore, it is not preferable to extract the net list while maintaining the original hierarchy. Therefore, the netlist is expanded in a flat state.

  The driving capability is represented by a relative relationship between a load of a driven circuit (referred to as “receiver circuit”) and a driving circuit (referred to as “driver circuit”). An internal signal node is formed at the connection point between the output terminal of the driver circuit and the input terminal of the receiver circuit. One driver circuit may drive a plurality of receiver circuits, and one receiver circuit may be driven by a plurality of driver circuits. Therefore, for each internal signal node, the load of the receiver circuit and the driving of the driver circuit are performed. Examine the relative relationship between abilities.

  First, the load on the receiver circuit will be described. FIG. 2 shows an example of a receiver circuit and a driver circuit connected to each internal signal node in a flat state. In FIG. 2, DR, C1, RV, and Nd represent a driver circuit, a wiring capacitor, a receiver circuit, and an internal signal node, respectively. The driving load capacitance C of the receiver circuit RV driven by the driver circuit DR is calculated as the sum of the wiring capacitance C1 of the internal signal node Nd and the load capacitance C2 parasitic to the receiver circuit RV in the manner shown in the following formula 1. . Here, the load capacitance C2 of the receiver circuit RV is calculated as the sum of the gate capacitance Cg of the transistor at the input stage of the receiver circuit RV connected to the internal signal node Nd and the junction capacitance Cj of the drain and source. Usually, the parasitic capacitance of the same type as the load capacitance C2, particularly the junction capacitance Cj, is also present on the driver circuit DR side, and these are added to the load capacitance C2. For example, when a plurality of driver circuits are connected to the internal signal node Nd, a load capacitance C2 is generated in the plurality of driver circuits.

(Equation 1)
C = C1 + C2 = C1 + Cg + Cj

  It should be noted that in the extraction of the drive load capacitance C, an internal signal node whose absolute value is equal to or smaller than a predetermined value is excluded, or when the junction capacitance Cj has only one of the N type and the P type, the driver circuit is searched later. Treatments that are excluded in advance may be added.

  Next, the driving capability of the driver circuit will be described. The driving capability of the driver circuit DR that drives the receiver circuit RV is such that one or a plurality of driving paths (internal signals) are used for both driving the internal signal node to the power supply potential and driving to the ground potential (ground potential). On-resistance when a transistor, which is a circuit element having a resistance component existing between a node and a power supply line or a ground line, is turned on is attribute information of the transistor (in the case of MOSFET, channel length, If there are multiple transistors in the same drive path, the on-resistances are summed, and if there are multiple drive paths as the combined on-resistance of the drive path, The on-resistance of the drive path having the largest on-resistance value is the drive capability of the driver circuit. In order to obtain the driving capability of the driver circuit, the following processing is performed.

  First, a driver circuit is identified and extracted from the first or second netlist. Recognition as a driver circuit is limited to a gate level circuit. Here, the gate level search is performed using circuit diagram data maintaining a hierarchical structure. For example, when the drains or sources of, for example, 2 or more and 7 or less transistors are connected to a specific node in the same instance of the lowermost circuit cell, the set of these transistors is recognized as the gate level. Therefore, even if a transistor level circuit design is made in the circuit cell, the gate level can be recognized. That is, it corresponds to an analog circuit design having no attribute as a gate. Here, an intermediate node in the circuit recognized as the driver circuit is excluded from the subsequent search targets, and the search time is shortened. Here, an instance refers to a state in which circuit components (circuit elements such as circuit cells and transistors) are specifically arranged on a circuit diagram and have individuality. Accordingly, even if there are a plurality of the same circuit components, each is a different instance.

  Further, as a method for identifying and extracting a driver circuit from the first or second netlist, it is preferable that the driver circuit is not limited to a gate level circuit but is recognized for all circuits. A method for searching for driver circuits for all circuits will be described in detail. The internal signal nodes are sequentially read from the netlist, and among the transistor paths from each internal signal node to the power supply line and the ground line, only the current path between the drain and source of the transistor from a specific node is passed through in series. One or a plurality of transistor paths to the same are searched. Similarly, one or a plurality of transistor paths that pass through only the current path between the drain and source of the transistor from the same node and reach the ground line in series are searched. A circuit formed of a transistor group included in the transistor path is recognized as a driver circuit that drives the internal signal node. Therefore, a transistor path that reaches the power supply line or the ground line via the gate (gate electrode) of the transistor is excluded. Here, an intermediate node in the circuit recognized as the driver circuit is excluded from the subsequent search targets, and the search time is shortened. According to the above-described driver circuit search method for all circuits, transistor search can be performed using either circuit diagram data that maintains a hierarchical structure or data that does not have a hierarchical structure. That is, it is suitable for an analog circuit design having no attribute as a gate.

  Next, for each extracted driver circuit, all current paths from the internal signal node in each driver circuit to the power supply line or ground line are extracted as drive paths, and the on-resistance is calculated for each drive path. For example, in the case of the 2-input NAND gate drive circuit DR illustrated in FIG. 2, the on-resistance is calculated by the following equation (2). The first equation of Formula 2 is a calculation formula of the on-resistance R1 of the first drive path composed of a series circuit of NMOS transistors N1 and N2, and the second formula is the on-resistance R2 of the second drive path from the PMOS transistor P1. The third equation represents a calculation equation for the on-resistance R3 of the third drive path from the PMOS transistor P2. Subsequently, the maximum on-resistance of each drive path is obtained by the calculation formula shown in Formula 3, and the maximum on-resistance Rd is used as the extracted drive capability index of the driver circuit. In the method according to the present invention, the on-resistance (specifically, the relative on-resistance) is used as a driving capability index. Therefore, the lower the on-resistance, the higher the driving capability.

(Equation 2)
R1 = α _N × L _N1 / W _N1 + α _N × L _N2 / W _N2
R2 = α _P × L _P1 / W _P1
R3 = α _P × L _P2 / W _P2

(Equation 3)
Rd = max (R1, R2, R3)

In Equation 2, L and W represent the channel length and channel width of each transistor, and values extracted from layout data or transistor attribute values at the time of designing circuit diagram data are used. alpha _N and alpha _P, the type of the transistor represents a different resistance coefficient (P-type, distinguished the N-type). When each of the on-resistances R1 to R3 in Expression 2 represents the absolute value of the on-resistance, the resistance coefficients α _N and α _P represent the on-resistance values of the transistors per unit length and unit width, respectively. . When determining the on-resistance of the drive path, even if the transistor size is the same, the on-resistance of the transistor differs depending on the type of transistor (P-type or N-type distinction). Even if a relative value is used for the on-resistance, it is possible to make a temporary evaluation, for example, to extract a candidate for a node with insufficient driving capability. In the present embodiment, the resistance coefficient (α _N ) of one type of transistor (for example, enhancement type NMOS transistor) is 1, and the resistance coefficient (α _P ) of the other type of transistor (for example, enhancement type PMOS transistor). Is calculated by dividing the on-resistance (absolute value) of a PMOS transistor of a certain transistor size (channel length L and channel width W) by the on-resistance (absolute value) of an NMOS transistor of the same transistor size. To calculate the relative on-resistance. The on-resistance (absolute value) of each transistor for calculating the resistance coefficient (α _P ) of the PMOS transistor is obtained by circuit simulation. Here, as shown in FIG. 3, the transistor sizes L and W used for calculating the resistance coefficient (α _P ) of the PMOS transistor are the channel lengths L and N of both N-type and P-type transistors included in all driver circuits. Of the transistor sizes common to the distribution range of the channel width W, the minimum channel length L _MIN and the maximum channel width W _MAX are calculated, and the ON resistance (absolute value) of the transistor having the transistor size is calculated. For example, the resistance coefficient of the NMOS transistor is α _N = 1, whereas the resistance coefficient of the PMOS transistor is given as α _P = 3.445826. That is, when the transistor size is the same, the NMOS transistor has a driving capability of 3.45826.

For example, in the case of each instance of the NMOS transistor and the PMOS transistor illustrated in FIG. 4, the transistor sizes are L _N = 0.8 (μm), W _N = 20 (μm), and L _N = 0.9 (μm). _), since it is W N = 40 (μm), the on-resistance _{R N} and _{R P} in an instance of each transistor becomes as the following numbers 4. The notation of each instance in FIG. 4 includes the instance name, drain terminal name, gate terminal name, source terminal name, back gate terminal name, transistor type, channel length, channel width, drain area, drain peripheral length, source area, The attribute information is shown in the order of the source perimeter.

(Equation 4)
R _N = α _N × L _N / W _N = 1 × 0.8 / 20 = 0.04
R _P = α _P × L _P1 / W _P1 = 3.445826 × 0.9 / 40 = 0.0778176

  Next, a method for narrowing down the location (internal signal node) where the driving capability is insufficient will be described. The greater the product (time constant) Rd × C of the maximum on-resistance Rd and drive load capacitance C in the drive path of the driver circuit, the greater the possibility that the receiver circuit drive is hindered. Starting with the above time constant, maximum on-resistance Rd, drive load capacitance C, wiring capacitance C1, load capacitance C2, gate capacitance Cg, junction capacitance Cj, the number of circuit elements connected to the internal signal node, the total gate area of the transistor, etc. A tabular file that lists information by internal signal node is generated in a tabular format as shown in FIG. 5, for example. Then, for example, by sorting and displaying the above list display in the order of internal signal nodes having a large time constant, the circuit designer can verify the driving capability as compared with the circuit design specifications.

  Furthermore, a delay constant determined depending on the manufacturing process for converting the time constant into an actual signal delay time and the type of transistor is obtained in advance by simulation, and the product of the time constant and the delay constant is obtained. Signal delay time can be expressed. This further simplifies the verification of the driving ability.

  For the internal node where the driver circuit is not recognized, only existing information among the drive load capacitance C, wiring capacitance C1, load capacitance C2, gate capacitance Cg, and junction capacitance Cj is stored in a separate file. By displaying the list in descending order of the capacity C, the circuit designer can also verify the internal node as compared with the design specification of the circuit.

  The processing procedure of the method of the present invention will be described below with reference to the flowchart shown in FIG.

<Step 1>
A first netlist is extracted from the layout data, and a second netlist is extracted from all circuit diagram data. In the extraction of the first netlist, circuit elements such as transistors and resistors and their connection relations are extracted, and attribute information of circuit elements such as transistors is also extracted. At this point, the node names of the first netlist are automatically assigned at the time of extraction. Further, in the extraction of the second netlist, the hierarchical structure of the original circuit diagram data is expanded to obtain a flat non-hierarchical state. As a result, a specific node can be easily narrowed down from the second netlist, and analysis is also facilitated. In addition, since the first netlist is also extracted in a state where the hierarchy is expanded, it is possible to associate nodes between the first and second netlists in the next step 2.

<Step 2>
Next, collation between the first and second netlists is performed to verify whether the electrical connection relationship on the layout data is in accordance with the circuit diagram data (corresponding to the layout collation process). At the same time as this collation, the correspondence of node names is taken. Based on the correspondence, the node name of the first netlist is replaced with the node name on the circuit diagram data side as much as possible. Here, when the parasitic correspondence or the parasitic diode is extracted from the first netlist, and there is a flaw in the correspondence between the nodes, the parasitic resistance or the parasitic diode is transferred to the following steps 3 and 4. Ignored in the capacitance calculation, the nodes at both ends of the parasitic resistance are treated as the same node.

<Step 3>
The wiring capacitance C1 parasitic to each node of the first netlist is extracted from the layout data and given to each node of the first netlist (corresponding to the second load capacitance extraction step of the load capacitance extraction step). Here, not only the capacitance with respect to the substrate but also the capacitance between wirings is extracted. As a result, the extraction of the drive load capacity is simplified.

<Step 4>
Next, the load capacitance C2 of the transistor connected to each node is exhaustively extracted (corresponding to the first load capacitance extraction step of the load capacitance extraction step). As the load capacitance C2, the gate capacitance Cg of the gate of the transistor connected to each node and the junction capacitance Cj of the drain and source are calculated separately. Here, for calculating the gate capacitance Cg and the junction capacitance Cj, attribute information such as a transistor size acquired at the time of extracting the first netlist is used. As a result, it is possible to calculate the load capacity in a state closer to an actual device. For each node, the driving load capacity C is extracted by summing the wiring capacity C1 extracted in step 3 and the load capacity C2 extracted in step 4 (corresponding to a load capacity extraction process). Usually, a part of transistors connected to each node, in particular, a part of transistors connected to a gate constitute a part of an input stage of a receiver circuit driven by a driver circuit. In addition, if step 4 is performed about one node, it will transfer to the following steps 5-7.

<Step 5>
Next, the driver circuit is extracted. Referring to the node name in which the history of hierarchical expansion created when the second netlist is expanded hierarchically is described (the original hierarchical structure is described in the node name), the same group of nodes connected to that node All the circuit elements (transistors, resistors, diodes, etc.) at the hierarchical level are extracted. Then, a lump of circuit elements at the same hierarchical level are examined to determine whether they have a drive structure. As an example of the drive structure, when a CMOS process is assumed as a manufacturing process, the extracted circuit element includes at least one PMOS transistor and NMOS transistor, and their drains or sources are connected to the node. In this case, it is determined that a driver structure is formed.

<Step 6>
If it is determined that the node to be processed is connected to the driver circuit, the node is registered as an internal signal node, the node in the driver circuit is excluded from the internal signal node, and the target of the subsequent step 5 To reduce the processing time. When registered as an internal signal node, the drive path of the extracted driver circuit is extracted. As the drive path, a current path from the internal signal node in each driver circuit to the power supply line or the ground line is assigned one by one. Then, for each of the extracted drive paths, a calculation formula similar to the calculation formula shown in Equation 2 is created to obtain a relative on-resistance. Steps 5 and 6 correspond to an on-resistance extraction process.

<Step 7>
Next, the drive path having the highest on-resistance among all the extracted drive paths is extracted. The on-resistance of the drive path is referred to as the maximum on-resistance (Rd) and is defined as a drive capability index of the internal signal node.

  If the driver circuit is not extracted in step 5, the node is not registered as an internal signal node, and steps 6 and 7 are not executed. However, the node name and each capacity extracted in step 4 are not changed. Save it so that it can be easily used for analysis. Steps 4 to 7 are repeated for all the nodes continuously for each node. Steps 4 to 7 are repeatedly executed for all the nodes, and when extraction of all the internal signal nodes, the corresponding drive load capacitance C and the maximum on-resistance Rd is completed, the process proceeds to Step 8.

<Step 8>
Next, for each internal signal node, a time constant defined by the product of the drive load capacitance C and the maximum on-resistance Rd is calculated (corresponding to a time constant extraction step). Here, the higher the on-resistance in the driving path of the driver circuit and the larger the driving load capacity, the more disadvantageous the driving condition of the receiver circuit is. Therefore, by using the time constant using the maximum on-resistance Rd, the internal signal node Each worst case can be verified.

  The calculated time constant is the maximum on-resistance Rd, drive load capacitance C, wiring capacitance C1, load capacitance C2, gate capacitance Cg, junction capacitance Cj, the number of circuit elements connected to the internal signal node, the total gate area of the transistor, etc. Are registered in a predetermined tabular file. In addition, the registered time constants are sorted and displayed in the order of the internal signal nodes having the largest time constants (corresponding to the display process), so that the circuit designer compares the circuit design specifications with the driving capability. Can be verified. In the list display, it is also preferable to selectively display only internal signal nodes having a time constant exceeding a predetermined threshold.

<Step 9>
Next, for each internal signal node, the delay time is calculated by multiplying the time constant by the above-mentioned delay constant, and the driver circuit with insufficient driving capability is discovered and analyzed using this delay time (in the delay time calculation step). Equivalent). As for the delay time, the circuit designer can verify the driving capability as compared with the design specification of the circuit by sorting and displaying the list in the order of the internal signal nodes having the larger time constants.

  As described above, according to the method of the present invention, even if the circuit scale is large, it is possible to narrow down the deficiencies in the driving capability in a short time using the net list extracted from the layout data or the circuit diagram data. Therefore, it becomes possible to perform a static drive check after layout at the final stage of the design, which has been difficult or impossible until now.

  Hereinafter, another embodiment will be described.

  <1> In the above embodiment, the first netlist extracted from the layout data and the second netlist obtained by hierarchically expanding all circuit diagrams in which all circuits are described hierarchically are used. Only one of the first and second netlists may be used as the netlist. For example, when the first netlist extracted from the layout data is used, when extracting the driver circuit, refer to the node name in which the history of hierarchical expansion created when the second netlist is hierarchically expanded is described. Instead, the same drive structure determination method and reference as in the above embodiment may be used.

  In addition, the method of the present invention may be carried out using the second netlist in which all circuit diagrams are hierarchically developed even during the design stage where layout data is not completed. In this case, standard values derived from virtually input attribute information or other attribute information may be used for the attribute information of the signal wiring and the transistor.

  <2> In the above embodiment, in the flowchart shown in FIG. 1, after extracting the wiring capacitance C1 for all the nodes in step 3, the load capacitance C2 and the driving load capacitance C are extracted in step 4 for each node. The driver circuit is extracted, the internal signal node is specified, and the on-resistance and the maximum on-resistance are sequentially extracted in steps 6 and 7, but instead, the driver circuit is extracted first. After specifying the internal signal node, the wiring capacitance C1, the load capacitance C2, and the drive load capacitance C may be extracted from the internal signal node. The execution order of the steps can be changed as appropriate within the scope of the technical idea of the method of the present invention.

6 is a flowchart showing a processing procedure in an embodiment of a circuit design verification method for a semiconductor integrated circuit according to the present invention. 1 is a circuit diagram showing an example of a receiver circuit and a driver circuit connected to an internal signal node in an embodiment of a circuit design verification method for a semiconductor integrated circuit according to the present invention. (A) is a circuit diagram in gate notation, and (B) is a circuit diagram in transistor notation. The figure explaining how to obtain | require the resistance coefficient in one Embodiment of the circuit design verification method of the semiconductor integrated circuit which concerns on this invention. The figure which shows an example of the attribute information of the transistor in one Embodiment of the circuit design verification method of the semiconductor integrated circuit which concerns on this invention. The figure which shows the example of a display of the verification result in one Embodiment of the circuit design verification method of the semiconductor integrated circuit which concerns on this invention. The flowchart which shows the circuit verification flow of the conventional logic circuit.

Explanation of symbols

C: Drive load capacitance C1: Wiring capacitance C2: Load capacitance DR: Driver circuit RV: Receiver circuit Nd: Internal signal nodes N1, N2: NMOS transistors P1, P2: PMOS transistors R1 to R3: On resistance Rd: Maximum on resistance

Claims (12)

A circuit design verification method for a semiconductor integrated circuit for verifying the drive capability of each of the internal signal nodes driven by a plurality of driver circuits included in all the circuits of the semiconductor integrated circuit with respect to all of the internal signal nodes,
On-resistance extraction that extracts the driver circuit that drives the internal signal node for each internal signal node from the net list that describes the entire circuit, and extracts the on-resistance of the drive path of the driver circuit for each internal signal node Process,
A load capacity extraction step of extracting a drive load capacity to be driven for each internal signal node from the netlist;
A circuit design verification method for a semiconductor integrated circuit, comprising: a time constant extraction step for extracting a product of the driving load capacitance and the on-resistance as a time constant for each internal signal node.   2. The circuit design verification method for a semiconductor integrated circuit according to claim 1, wherein in the on-resistance extraction step, the driver circuit is extracted from a specific gate circuit.   In the on-resistance extraction step, for each internal signal node, all transistors that do not go through the gate electrode of the transistor in the transistor path from the internal signal node to the power supply line or the ground line through one or more transistors. 2. The circuit design verification method for a semiconductor integrated circuit according to claim 1, wherein a path is searched and a transistor group included in the searched transistor path is extracted as a driver circuit for driving the internal signal node.   In the on-resistance extraction step, the on-resistance is extracted by calculating a total of on-resistances of circuit elements existing in a drive path of the driver circuit from circuit constants of the circuit elements included in the netlist. The circuit design verification method for a semiconductor integrated circuit according to any one of claims 1 to 3. In the on-resistance extraction step, for each internal signal node, the maximum value of the on-resistance of the drive path is extracted as the maximum on-resistance,
5. The circuit of a semiconductor integrated circuit according to claim 1, wherein, in the time constant extraction step, a maximum time constant using the maximum on-resistance is extracted for each internal signal node. Design verification method. The load capacity extraction step includes
A first load capacity extracting step of extracting a receiver circuit connected to the internal signal node from the netlist for each internal signal node, and extracting a load capacity of the receiver circuit for each internal signal node;
A second load capacitance extraction step of extracting a wiring capacitance caused by a wiring portion of the internal signal node from the layout data corresponding to the entire circuit or the net list,
6. The semiconductor integrated circuit according to claim 1, wherein the driving load capacitance is calculated as a sum of a load capacitance of the receiver circuit and the wiring capacitance for each internal signal node. Circuit design verification method. A layout matching step for performing a one-to-one correspondence between the internal signal nodes on the netlist and the internal signal nodes on layout data corresponding to all the circuits;
7. The circuit design verification method for a semiconductor integrated circuit according to claim 6, wherein, in the second load capacitance extraction step, the wiring capacitance is calculated based on wiring pattern information of the internal signal node on the layout data. .   8. The netlist according to claim 1, wherein the netlist is a non-hierarchical netlist generated by hierarchically expanding circuit diagram data having a hierarchical structure describing all the circuits. Circuit design verification method for semiconductor integrated circuit.   7. The circuit design verification method for a semiconductor integrated circuit according to claim 1, wherein the net list is a non-hierarchical net list generated from layout data corresponding to all the circuits. .   10. The display step of specifying and displaying the internal signal node corresponding to a value exceeding a predetermined value of the time constant extracted in the time constant extraction step. 2. A circuit design verification method for a semiconductor integrated circuit according to 1.   11. The display method according to claim 1, further comprising: a display step of specifying and displaying the internal signal nodes corresponding to the order of the time constant extracted in the time constant extraction step. Circuit design verification method for semiconductor integrated circuit. A delay time calculating step of calculating a drive delay time of the drive path by multiplying the time constant by a predetermined delay coefficient for each internal signal node;
12. The display step according to claim 10, wherein the driving delay time corresponding to the displayed time constant is displayed in addition to the time constant or in place of the time constant. Circuit design verification method for semiconductor integrated circuit.

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