JP2007073838A - Method of analyzing electrostatic noise tolerance of semiconductor integrated circuit device, and method of optimizing design of the semiconductor integrated circuit device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten time required for analyzing electrostatic noise tolerance and optimizing design in a semiconductor integrated circuit device having an increased number of terminals due to improvement of integration. <P>SOLUTION: The method for analyzing electrostatic noise tolerance of the semiconductor integrated circuit device largely shortens the analysis time compared with conventional ones; as the semiconductor integrated circuit device can be divided into regions, and a location with a relatively weaker tolerance to electrostatic noise can be detected from impedance information acquired in each region. As a result, the time required for optimizing the design of the device is also shortened. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrostatic noise resistance analysis method for a semiconductor integrated circuit device, and a design optimization method using the same, and more particularly to electrostatic noise resistance of a large-scale semiconductor integrated circuit device against electrostatic discharge (ESD). The present invention relates to a noise tolerance analysis method for analyzing the above and a design optimization method for a semiconductor integrated circuit device using this method.

  In this specification, electrostatic noise can be defined as an inflow of electric charges generated by static electricity, and electrostatic noise resistance can be defined as an index of whether or not a transistor is easily destroyed by static electricity.

  With the widespread use of portable devices, one of the recent trends of LSI (Large Scale Semiconductor Integrated Circuit Device) is low power consumption. In order to reduce power consumption, power supply stop or voltage reduction by power supply separation is used, but this makes the resistance to electrostatic noise weak. For this reason, analysis of electrostatic noise resistance of a semiconductor integrated circuit device is indispensable.

  Usually, when analyzing the resistance to electrostatic noise of a semiconductor integrated circuit, it is necessary to input electrostatic noise to all terminals and specify the location where the semiconductor integrated circuit is destroyed.

  However, the improvement in the degree of integration has increased the number of terminals, and the analysis of the resistance to electrostatic noise of semiconductor integrated circuits has taken a long time.

  Therefore, it is a critical requirement to analyze the resistance to electrostatic noise in a short time and with high accuracy, and various methods have been proposed.

  As a conventional method, equivalent conversion of a semiconductor integrated circuit into a circuit having only a resistor and a capacitor is performed, a power supply voltage is applied to each terminal, and a potential distribution of each element is simulated, so that there is a high possibility that breakdown due to electrostatic discharge occurs. A method of specifying a location is used, and a method of performing this for all terminals has been proposed (see Patent Document 1).

In this method, it is possible to easily identify a portion having low resistance to electrostatic noise, and the analysis time is shortened to some extent.
JP-A-10-54865 ([0007]-[0010] FIG. 1-2)

  However, in the conventional method, since a transistor level simulation is executed for each terminal, it takes a very long time. Further, as the degree of integration increases, the number of external terminals of the semiconductor integrated circuit device increases, and if electrostatic noise resistance is verified at the level of one chip, 500 terminals would take more than a month and would be very inefficient. Conceivable.

  Therefore, the present inventors pay attention to the fact that the resistance to electrostatic noise is high in a region where the value of resistance R is high and the value of capacitance C is large, and resistance to electrostatic noise is determined using the resistance value and the capacitance value. Invented a method to evaluate

  By using the present invention, it is possible to analyze the electrostatic noise resistance of the semiconductor integrated circuit device in a short time, and it is only necessary to perform the electrostatic noise verification on the terminal related to the weak resistance from the analysis result. Target terminals can be greatly reduced.

  In view of the above, it is an object of the present invention to provide a semiconductor integrated circuit device having a good operation characteristic based on the shortening of the electrostatic noise verification time and the verification result.

  (1) An electrostatic noise resistance analysis method for a semiconductor integrated circuit device according to a first aspect of the present invention is based on a step of dividing an internal circuit of a semiconductor integrated circuit device into a plurality of blocks, and impedance information of each of the plurality of blocks. And a step of analyzing resistance to electrostatic noise.

  In the method of the present invention, it is possible to classify a portion having relatively weak electrostatic noise resistance only by evaluation using impedance information without performing verification for a long time by a conventional simulation.

    (1A) It is preferable that the impedance information is obtained by equivalently converting the internal circuit of the block into an RC circuit including a resistor and a capacitor and performing the equivalent conversion on the RC circuit.

    (1B) It is preferable to degenerate the RC circuit into a single RC circuit between the power source and the ground.

  (1C) It is preferable that the degeneration is performed by approximating the impedance of the RC circuit only with a resistance component when the operating frequency is high, and is degenerated by approximating only the capacitance component when the operating frequency is low.

  (1D) It is preferable that an RC multiplication value is calculated from the resistance value and the capacitance value in the approximate single RC circuit, and a block having low electrostatic noise resistance is detected from the RC multiplication value.

  (1E) Based on a result of comparing the RC multiplication value of the input / output circuit including the protection circuit and the RC multiplication value of each of the plurality of blocks, the detection is performed to determine a block having low electrostatic noise resistance and a strong block. It is preferable to do so.

 (2) An electrostatic noise resistance analysis method for a semiconductor integrated circuit device according to a second aspect of the present invention includes a step of dividing an internal circuit of the semiconductor integrated circuit device into a region connected to a signal terminal and other regions, and the signal terminal Equivalent conversion of the internal circuit of the connected region to an RC circuit composed of a resistor and a capacitor, a step of calculating an RC multiplication value in the equivalently converted RC circuit, and a region of the region connected to the signal terminal from the RC multiplication value And a step of detecting electrostatic noise resistance.

  In the second aspect of the present invention, it is preferable that the RC circuit obtained by equivalently converting the internal circuit in the region connected to the signal terminal is degenerated into a single RC circuit.

  In the second aspect of the present invention, the detection is performed based on the result of comparing the RC multiplication value of the input / output circuit including the protection circuit and the RC multiplication value of the region connected to the signal terminal. This is preferably performed by determining noise resistance.

  In the second aspect of the present invention, when it is impossible to degenerate the internal circuit in the region connected to the signal terminal to a single RC circuit, the internal circuit in the other region is degenerated into a single RC circuit. It is preferable to evaluate electrostatic noise resistance by simulation.

  In the second aspect of the present invention, the region connected to the signal terminal is preferably a region connected to the input signal terminal or the output signal terminal.

  In the second aspect of the present invention, in the region connected to the output signal terminal, electrostatic noise is applied between the power source and the ground, and the RC multiplication value in each path through which the charge flows by this application is calculated by the RC multiplication of the input / output circuit including the protection circuit. One of the region connected to the signal terminal and between the signal and ground, the region connected to the signal terminal and between the signal and the power source, and the other region based on the comparison. It is preferable to determine resistance to electrostatic noise.

 (3) In the third method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to the present invention, the internal circuit of the semiconductor integrated circuit device is divided into a region (S) connected to all signal terminals and another region (Z). Dividing the region (S) connected to all the signal terminals into regions (S1, S2,...) Connected to the signal terminals and other regions (Z1, Z2,. The step of modeling the internal circuit of region (S1, S2,...), Region (Z1, Z2,...), Region (Z) into an RC circuit, and the internal circuit of the semiconductor integrated circuit device as region (X1) = region ( S1 + Z1 + Z), region (X2) = region (S2 + Z2 + Z), and so on. In the analysis of electrostatic noise resistance of each region (X1), region (X2),. ) Is characterized by reusing the model That.

 (4) A fourth method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to the present invention includes a step of dividing an internal circuit of a semiconductor integrated circuit device into a plurality of regions, and equivalently converting each of the plurality of regions into an RC circuit. A step, a step of applying electrostatic noise to each of the plurality of regions, a step of obtaining an impedance in each of the plurality of regions when the electrostatic noise is applied, from a frequency of electrostatic noise, and a protection circuit. Comparing the impedance of the input / output circuit with the determined impedances of the plurality of regions, and determining electrostatic noise resistance for the plurality of regions based on the comparison result, To do.

 (5) According to a fifth aspect of the present invention, there is provided a fifth method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device, comprising: extracting a block composed only of standard cells from an internal circuit of the semiconductor integrated circuit device; A step of obtaining, and a step of determining electrostatic noise resistance of the block from the area information.

  In the fifth aspect of the present invention, it is preferable that the block is extracted from layout information of the semiconductor integrated circuit device.

  In the fifth aspect of the present invention, the area information of the block is obtained by collecting the capacitance values obtained in advance corresponding to the area as a correspondence table, and the block area is associated with the correspondence table to obtain the capacitance value of the block. It is preferable that an RC multiplication value is calculated from the capacitance value and the resistance value of the block, and the electrostatic noise resistance of the block is determined based on the calculated RC multiplication value.

   (6) In the electrostatic noise resistance analysis method for a semiconductor integrated circuit device according to the sixth aspect of the present invention, the electrostatic noise resistance analysis method of any one of the above (1) to (5) is used. A step of detecting a region, a step of extracting a terminal connected to the detected region having low resistance to electrostatic noise, and a step of performing an electrostatic noise verification simulation on the extracted terminal. It is characterized by.

    (7) According to a seventh method of optimizing the design of a semiconductor integrated circuit device of the present invention, a step of detecting a path with low electrostatic noise resistance using an electrostatic noise resistance analysis method and the detected low resistance to electrostatic noise Obtaining impedance information on the path, and increasing the impedance of the detected path with low electrostatic noise resistance based on the impedance information to reinforce the electrostatic noise resistance of the path. Is.

  (8) A method for optimizing the design of a semiconductor integrated circuit device according to an eighth aspect of the present invention includes a step of detecting a path with low electrostatic noise resistance using an electrostatic noise resistance analysis method, and the detected low resistance to electrostatic noise. Obtaining impedance information in the path and lowering the impedance of the path parallel to the detected path with low electrostatic noise resistance based on the impedance information to reinforce the electrostatic noise resistance for the path with low electrostatic noise resistance And the step of performing.

  (9) As described above, according to the present invention, it is possible to detect a relatively weak block of electrostatic noise resistance in a semiconductor integrated circuit device to be analyzed. However, detection using DC analysis is also possible instead of RC multiplication value evaluation.

  As described above, according to the present invention, in the electrostatic noise resistance analysis of the semiconductor integrated circuit device, the circuit is divided into elements, and the resistance value and the capacitance value in each divided area are used to determine whether the electrostatic noise resistance is strong or weak. Therefore, it is possible to detect a weakly resistant portion in a short time. Further, if hierarchical processing is performed using the electrostatic noise resistance analysis, even more detailed portions can be specified.

  In addition, since it is sufficient to perform electrostatic noise verification only for the portion with low electrostatic noise resistance, the time can be significantly reduced when performing one-chip simulation.

  Further, the design optimization of the semiconductor integrated circuit device can be easily performed based on the result of the electrostatic noise resistance analysis.

  Hereinafter, an electrostatic noise resistance analysis method and a design optimization method according to the present invention will be described in detail with reference to the drawings. The resistance described below includes power supply resistance and wiring resistance, and the capacity includes wiring-to-wiring capacity, gate capacity, drain-gate capacity, and source-gate capacity.

(Embodiment 1)
As a first embodiment of the present invention, a method of dividing a semiconductor integrated circuit device into blocks and evaluating electrostatic noise resistance using resistance values and capacitance values in the respective blocks will be described. FIG. 1 is a flowchart of the present embodiment.

  First, in step S1, as shown in FIG. 2, the semiconductor integrated circuit device is divided into blocks 4 to 9 for each power supply system according to the layout information.

  Next, in step S2, each of the divided blocks 4 to 9 is equivalently converted into a circuit having only resistors and capacitors. For this equivalent conversion, for example, a net list obtained by extracting a parasitic element from a semiconductor integrated circuit at the gate level is used. This netlist is composed of a power supply / wiring resistance and a parasitic capacitance between macros and cells, and the cell and macro are approximated in advance to a cell macro linear circuit composed of resistance and capacitance. As an example, as shown in FIG. 3, the circuit elements in the block 10 are modeled using a circuit 11 between the power source and the ground.

  Using this cell / macro linear circuit and the netlist of each block divided in step S1, an equivalent netlist is created. From this equivalent netlist, equivalent R and equivalent C can be estimated.

  Here, the case where the PMOS transistors 12 to 13 are in the ON state and the NMOS transistors 14 to 15 are in the OFF state is considered, but the same applies to the case where the PMOS transistors 12 to 13 are in the OFF state and the NMOS transistors 14 to 15 are in the ON state. Can be expressed.

  As described above, the circuit 11 can be equivalently converted to an RC circuit like the circuit 16. However, since there are various known methods for converting to an equivalent circuit, any method may be used.

  It is possible to model similarly between the signal and the power source and between the signal and the ground.

  Next, in step S3, the RC circuit generated by the equivalent conversion in step S2 is degenerated. From the actual measurement, when the frequency is 1 GHz or less, since the LSI is represented as an RC circuit, the impedance can be represented as Z = R + 1 / jωC (ω = 2πf). Here, it can be approximated as Z = R when the operating frequency is high, and Z = 1 / jωC when the operating frequency is low. Since the LSI is composed of a parallel circuit of transistors (z = r + 1 / jωc), it is expressed as a parallel circuit of z = r when the operating frequency is high, and as a parallel circuit of z = 1 / ωc when the operating frequency is low. Therefore, the impedance can be expressed as Z = (1 / Σ (1 / r)) + (1 / jω (Σc)).

  As described above, the circuit 16 shown in FIG. 3 is shown again as the circuit 17 in FIG. In the circuit 17 shown in FIG. 4, when the operating frequency is high, it can be expressed as a circuit 29 including only resistors 18 to 25 as shown in FIG. 4, and when the operating frequency is low, capacitors 26 to 28 are used. The circuit 30 can be expressed as

  By estimating the combined resistance 31 from the circuit 29 and the combined capacitance 32 from the circuit 30, the circuit 17 can be reduced to a single RC circuit like the circuit 33. Here, it is considered that the combined resistance 31 indicates the resistance component of the circuit 17 and the combined capacitance 32 indicates the capacitance component of the circuit 17.

  Based on Kirchhoff's equation, the combined resistance can be obtained by performing a numerical analysis of the matrix using the voltage / current at each contact as a determinant. It is also possible to calculate the combined resistance from a voltage value applied to the equivalent circuit represented only by the resistance and a current value flowing through the equivalent circuit using a commercially available simulator.

  Next, in step S4, an RC multiplication value is calculated from the resistance value and the capacitance value in the blocks 4 to 9 in FIG. This RC multiplication value is represented by τ. Further, the RC multiplication value of the input / output circuit 2 including the protection circuit of FIG. 2 is obtained in the same manner as in steps S2 and S3.

  Here, since the RC multiplication value can be expressed as a time constant, transient characteristics can be examined by simulation and obtained from the result. The RC multiplication value obtained as described above is represented as t.

  Next, in step S5, τ and t are compared to determine the strength of electrostatic noise resistance (steps S6 to S7).

  As described above, since τ and t can be expressed as time constants, they represent the time until charge flows as shown in FIG. Therefore, as shown in FIG. 6, when electrostatic noise 42 is applied to the input / output circuit 35 including the protection circuit, the charge 43 caused by the electrostatic noise 42 flows through the input / output circuit 35 including the protection circuit and the internal circuit. It can be determined which of the paths 44 through the block 38 is taken.

  That is, when τ> t, it is indicated that charges due to electrostatic noise easily flow into the input / output circuit including the protection circuit. That is, it can be determined that the block to be compared has strong electrostatic noise resistance.

  On the other hand, when τ <t, it indicates that the charge due to electrostatic noise tends to flow into the block to be compared before the input / output circuit including the protection circuit. That is, it can be determined that the block has low electrostatic noise resistance. Further, without comparing with the input / output circuit, it is also possible to sort each block in order from the smallest RC multiplication value and relatively determine the strength of electrostatic noise resistance to obtain an evaluation result.

  As described above, it is possible to determine the strength of electrostatic noise resistance between the power source and the ground of the block divided for each power supply system.

(Embodiment 2)
Next, as a second embodiment of the present invention, a semiconductor integrated circuit device is divided into a region connected to a signal terminal and other regions, and a resistance value and a capacitance value in each region are evaluated for electrostatic noise resistance. Will be explained.

  FIG. 7 is a flowchart of the present embodiment.

  First, in step S8, the semiconductor integrated circuit device is divided into a region connected to the signal terminal and other regions, and each region is equivalently converted to an RC circuit in step S9.

  Here, as a region division method, CCC (channel connect component) connected to the signal terminal or CCC having a gate terminal connected to the signal terminal is referred to as “region connected to the signal terminal”, and other circuit elements between the power supply and the ground are expressed as “ A method of dividing as “other areas” is adopted. Note that CCC can be specifically defined as a group of transistors connected to each other via a source and a drain.

  At this time, since the gate is separated and divided, unless the gate is directly connected to the power supply line or the ground line, the current tolerance between the source and drain of the transistor is exceeded rather than being broken by the voltage applied to the gate itself. Assuming that it is faster, ignore the connection relationship for that gate.

  As a specific example, first, division for an input signal terminal is shown (see FIG. 8). When the gates of the inverters 45 to 48 are separated and separated based on the above-described conditions, the region connected to the signal terminal is the region 49, and the other regions are the regions 50.

  Here, the separated gate terminal is connected to the power supply line and the ground line as an execution capacity assuming an ideal state. When the regions 49 to 50 are equivalently converted to an RC circuit, they can be expressed as regions 51 to 52.

  Here, assuming that the PMOS transistor is in the ON state and the NMOS transistor is in the OFF state, the transistor in the ON state is converted into a resistor and the transistor in the OFF state is converted into a capacitor. Even if the NMOS transistor is in the ON state, the same model can be obtained.

  Next, the division for the output signal terminal will be described. (See FIG. 9). When the gates of the inverters 53 to 56 are separated and separated based on the above-described conditions, the region connected to the signal terminal is the region 57 and the other regions are the region 58.

  Here, the separated gate terminal is connected to the power supply line and the ground line as an execution capacity assuming an ideal state. When equivalently converting the regions 57 to 58 to the RC circuit, it is assumed that the PMOS transistor is turned on and the NMOS transistor is turned off, the transistor in the on state is converted into a resistor, and the transistor in the off state is converted into a capacitor. It can be expressed as 59 to 60. Conversely, assuming that the PMOS transistor is in an OFF state and the NMOS transistor is in an ON state, the regions 57 to 58 can be expressed as regions 62 to 63, respectively.

  As described above, it is necessary to consider two types of output signal terminals, model 61 and model 64. However, the region 60 and the region 63 are the same model.

  Next, in step S10, it is confirmed whether or not the region connected to the signal terminal can be degenerated into a single RC circuit.

  If degeneration is possible, the region connected to the signal terminal and other regions are degenerated into a single RC circuit in step S11. The degeneration method is as described in step S3 of the first embodiment.

  Next, in step S12, the RC multiplication value in each path is obtained, and in step S13, the RC multiplication value in each path is compared with the RC multiplication value of the input / output circuit including the protection circuit.

  As illustrated in FIG. 10, when electrostatic noise is applied between the signal of the circuit 65 and the ground, a path 71 and a path 72 are considered as paths through which charges due to the electrostatic noise flow.

  The resistance and capacitance in the path 71 can be expressed as R1 = (resistance 67) and C1 = (capacitance 69), and the resistance and capacity in the path 72 can be expressed as R2 = (resistance 66 + resistance 68) and C2 = (capacitance 70).

  From the above, RC multiplication values τ1 = R1C1 and τ2 = R2C2 in each path are obtained and compared with the RC multiplication value t of the input / output circuit including the protection circuit. If τ2> t> τ1, the path 71, that is, the area connected to the signal terminal and the area between the signal and the ground is determined to be an area having low resistance to electrostatic noise (step S14).

  In addition, the region including the region connected to the signal terminal and the region between the signal and the power source and the other region not connected to the signal terminal is determined as a region having strong electrostatic noise resistance (step S15).

  In step S10, if the region connected to the signal terminal cannot be reduced to a single RC circuit, only the other region is reduced to a single RC circuit in step S16. Next, in step S17, a simulation is performed for each region, and the electrostatic noise resistance is analyzed. In this case, since the other regions are degenerated, the simulation time is greatly shortened.

  Further, by applying the present embodiment to the block having low electrostatic noise resistance detected in step S6 of the first embodiment, it is possible to further narrow down the places having low electrostatic noise resistance.

(Embodiment 3)
Next, as a third embodiment of the present invention, a method in which a semiconductor integrated circuit device is divided into a region connected to a signal terminal and other regions, and models of the other regions are reused in electrostatic noise resistance analysis. explain.

  FIG. 11 is a flowchart of the present embodiment.

  First, in step S18, the area is divided into areas connected to signal terminals and other areas. In the present embodiment, unlike the second embodiment, as shown in FIG. 12, the area 73 is divided into an area 74 connected to all signal terminals and another area 75.

  Next, in step S18, the region 74 connected to all the signal terminals is divided for each signal terminal into a region connected to the signal terminal and other regions. For example, when the signal terminal 1 is divided, the region 74 connected to all signal terminals can be divided into a region 76 connected to the signal terminal 1 and a region 77 other than that as shown in FIG.

  Next, in step S19, the region 76 connected to the signal terminal 1 and the other region 77 are modeled into an RC circuit, which are referred to as models S1 and Z1, respectively. In step S20, the other region 75 is modeled as a model Z. The modeling method is as shown in step S11 of the second embodiment.

  Next, in step S21, the region connected to the signal terminal 1 and the other region are modeled as a model S1 and a model Z1 + Z, respectively. Since this modeling can be performed for each signal terminal, the model Z can be reused once it is modeled.

  Next, in step S22, electrostatic noise resistance evaluation with an RC multiplication value is performed using the result modeled in the previous step. The electrostatic noise tolerance determination with the RC multiplication value is as described in step S5 of the first embodiment.

  As described above, the electrostatic noise resistance can be determined by reusing the model of the other region 75. Further, since there are two types of models 61 and 64 in FIG. 9 for the region connected to the output signal terminal, when the signal terminal 1 is an output signal terminal, the region 75 + region 77 is used as one model. It is possible.

(Embodiment 4)
Next, as a fourth embodiment of the present invention, a method of dividing a semiconductor integrated circuit device into regions and determining electrostatic noise resistance from impedance information in each region will be described. FIG. 13 is a flowchart of the present embodiment.

  First, in step S23, the semiconductor integrated circuit device is divided, and each region divided in step S24 is equivalently converted to an RC circuit. For these, the method used in step S2 of the first embodiment or step S9 of the second embodiment may be used.

  Next, impedance information in each region is acquired in step S25. Assume that there are a region A and a region B as the divided regions. The impedance in the region A can be expressed as Za = Ra + 1 / (jωCa), and the impedance in the region B can be expressed as Zb = Rb + 1 / (jωCb). Since ω = 2πf, the impedance when electrostatic noise is applied can be obtained from the frequency of the electrostatic noise.

  Next, in step S26, the impedance in each region is compared with the impedance of the input / output circuit including the protection circuit, and in step S26, the strength of electrostatic noise resistance is determined.

  Here, consider a case where the impedance of the input / output circuit including the protection circuit is Z = R + 1 / (jωC). Here, when R≈Ra, it can be determined that the smaller the impedance, the stronger the electrostatic noise resistance. This is because, as described in the first embodiment, the larger the multiplication value of resistance and capacitance, the stronger the electrostatic noise resistance. In other words, if the resistance values are substantially the same, it can be determined that the one with the larger capacitance value, that is, the one with a smaller impedance has a higher resistance to electrostatic noise.

  Similarly, when C≈Ca, it can be determined that the larger the impedance, the stronger the electrostatic noise resistance. This is because if the capacitance values are substantially the same, it can be determined that the resistance value is larger, that is, the impedance is larger, the resistance to electrostatic noise is stronger. It is also possible to determine only the relative strength of electrostatic noise resistance by comparing only region A and region B.

  As described above, electrostatic noise resistance can be determined from impedance information.

(Embodiment 5)
Next, as Embodiment 5 of the present invention, a method of extracting a block composed only of standard cells from a semiconductor integrated circuit device and determining electrostatic noise resistance from area information in each block will be described. FIG. 14 is a flowchart of the present embodiment.

  First, in step S28, a block composed only of standard cells in the internal circuit of the semiconductor integrated circuit device is extracted. Since such a block can be identified from the layout information of the semiconductor integrated circuit device, it is extracted according to the layout information. As a result, it is assumed that block A and block B are extracted.

  Next, in step S29, the area information of the block A and the block B extracted in the previous step S28 is acquired. The area information can be acquired from the layout information of the semiconductor integrated circuit device.

  Here, it is assumed that the area of the block A is acquired as Sa and the area of the block B is acquired as Sb. Based on this area information, the size of a block composed of standard cells can be estimated.

  Next, in step S30, the strength of electrostatic noise resistance is relatively determined from the area information obtained in previous step S29. Here, if Sa> Sb, it can be determined that the block A is more resistant to electrostatic noise than the block B.

  As described above, when sorting is performed from blocks having a relatively small block area, the order of weakness in electrostatic noise resistance can be known.

  In addition, the method of judging based on the block area can be extended as follows. First, for various types, capacitance values corresponding to areas are obtained in advance using equivalent circuit conversion, and these are compiled into a correspondence table and prepared. The capacitance value is obtained from the block area and the correspondence table, and the resistance value from the terminal to the block entrance is obtained by equivalent circuit conversion.

  From the above results, a resistance value and a capacitance value are acquired for each block, an RC multiplication value is calculated, and comparison and ranking are performed.

  As described above, the resistance to electrostatic noise can be determined based on the block area with respect to the block composed of standard cells.

(Embodiment 6)
Next, as a sixth embodiment of the present invention, a method for performing an electrostatic noise verification simulation only for terminals related to portions having low electrostatic noise resistance based on the analysis results in the first to fifth embodiments will be described. FIG. 15 is a flowchart of the present embodiment.

  First, in step S33, a region having low resistance to electrostatic noise is detected in the semiconductor integrated circuit device. For this, the results shown in the first to fifth embodiments may be used. Here, it is assumed that only the path 71 in FIG. 10 has low electrostatic noise resistance, and that other areas and paths have high electrostatic noise resistance.

  Next, in step S34, the terminals connected to the area detected in the previous step S33 are extracted. Here, a signal terminal and a ground terminal in the circuit 65 of FIG. 10 are obtained as an extraction result.

  Next, in step S35, the electrostatic noise verification simulation is performed only for the terminals extracted in the previous step S34, and in step S36, it is confirmed whether or not the circuit is broken as a result of the simulation. In this case, a simulation may be performed in which electrostatic noise is applied between the signal and the ground, and the result may be confirmed.

  At this time, the other regions not connected to the corresponding signal terminals are degenerated into a single RC circuit for each power supply system.

  As described above, a simple evaluation of electrostatic noise resistance is performed using the first to fifth embodiments, and the minimum necessary simulation is performed based on the result. Therefore, the simulation is executed for all terminals of the semiconductor integrated circuit device. Rather than the overall analysis time.

(Embodiment 7)
Next, as a seventh embodiment of the present invention, a method for performing design optimization on a path with low electrostatic noise resistance based on the electrostatic noise resistance analysis results in the first to sixth embodiments will be described.

  FIG. 16 is a flowchart of the present embodiment.

  First, in step S37, a resistance value and a capacitance value of a portion where the electrostatic noise resistance of the semiconductor integrated circuit device is weak are acquired. Here, the route 71 in FIG. 10 is considered. Here, it is assumed that the resistance value of the resistor 67 is R1 = 0.09Ω, and the capacitance value of the capacitor 69 is C1 = 0.27 nF.

  Next, in step S38, the impedance is increased for a path with weak electrostatic noise resistance. Here, if the RC multiplication value τ in the path 71 is larger than the RC multiplication value t of the input / output circuit including the protection circuit, it can be determined that the resistance to electrostatic noise is strong.

  If it is known that t = 0.30 ns, it can be said that the resistance to electrostatic noise is enhanced when τ = RC = (0.09 + R) × 0.27 ns> 0.30 ns.

  From the above, the resistance to electrostatic noise can be reinforced by inserting the resistor 80 with R> 1.02Ω into the path 79 of the circuit 78 as shown in FIG.

  This is equivalent to inserting a resistor 80 in the path 82 of the original circuit 81 as shown in FIG.

  In addition to the resistor, the impedance can be increased by connecting a protection transistor in series with the target path. There is also a method in which a transistor in which breakdown occurs is replaced from salicide to non-salicide.

(Embodiment 8)
Next, as an eighth embodiment of the present invention, a method for performing design optimization on a path parallel to a path having a weak electrostatic noise resistance based on the electrostatic noise resistance analysis results in the first to sixth embodiments will be described. To do. FIG. 18 is a flowchart of the present embodiment.

  First, in step S39, a resistance value and a capacitance value of a portion where the electrostatic noise resistance of the semiconductor integrated circuit device is weak are acquired. Here, the route 71 in FIG. 10 is considered.

  Here, it is assumed that the resistance value of the resistor 67 is R1 = 0.09Ω, and the capacitance value of the capacitor 69 is C1 = 0.27 nF.

  Next, in step S40, the impedance is lowered for a path parallel to the path with weak electrostatic noise resistance.

  Here, if the RC multiplication value τ in the path 71 is larger than the RC multiplication value t of the input / output circuit including the protection circuit, it can be determined that the resistance to electrostatic noise is strong.

  Further, if it is known that t = 0.30 ns, it can be said that the resistance to electrostatic noise is enhanced if τ = RC = 0.09 × (0.27 + C) ns> 0.30 ns.

  From the above, it is possible to reinforce electrostatic noise resistance by inserting a capacitor 86 with C> 3.06 nF into the path 88 of the circuit 87 as shown in FIG.

  This is equivalent to inserting a capacitor 89 in the path 88 of the original circuit 87 as shown in FIG.

  The design optimization of the semiconductor integrated circuit device is performed as described above.

  As described above, according to the present invention, it is possible to analyze the resistance to electrostatic noise of a semiconductor integrated circuit device in a short time, and it is possible to perform design optimization so as to obtain a semiconductor integrated circuit device having high resistance to electrostatic noise from the analysis result. .

  The electrostatic noise resistance analysis method and the design optimization method according to the analysis result according to the present invention are useful as a method for shortening electrostatic noise verification at the LSI design stage.

FIG. 1 is a flowchart showing an electrostatic noise resistance analysis method using block division according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing modeled block division according to Embodiment 1 of the present invention. FIG. 3 is a diagram showing an example of modeling of the intra-block circuit according to the first embodiment of the present invention. FIG. 4 is a diagram showing an example of degeneration to a single RC circuit model according to the first embodiment of the present invention. FIG. 5 is a diagram showing an electrostatic noise tolerance determination method according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating an example of charge inflow due to electrostatic noise according to the first embodiment of the present invention. FIG. 7 is a flowchart showing an electrostatic noise resistance analysis method using area division according to the second embodiment of the present invention. FIG. 8 is a diagram showing an example of division of a region connected to the input signal terminal according to the second embodiment of the present invention. FIG. 9 is a diagram showing an example of division of a region connected to the output signal terminal according to the second embodiment of the present invention. FIG. 10 is a diagram showing an electrostatic noise resistance analysis method using area division according to Embodiment 2 of the present invention. FIG. 11 is a flowchart showing a modeling method for electrostatic noise resistance analysis according to the third embodiment of the present invention. FIG. 12 is a diagram illustrating an example of division and modeling of a region connected to the signal terminal according to the third embodiment of the present invention. FIG. 13 is a flowchart showing an electrostatic noise tolerance analysis method focusing on impedance information according to the fourth embodiment of the present invention. FIG. 14 is a flowchart showing an electrostatic noise resistance analysis method focusing on the block size according to the fifth embodiment of the present invention. FIG. 15 is a flowchart showing a method for shortening electrostatic noise verification according to the sixth embodiment of the present invention. FIG. 16 is a flowchart showing a design optimization method according to the seventh embodiment of the present invention. FIG. 17 is a diagram illustrating a model example used for design optimization according to the seventh embodiment of the present invention. FIG. 18 is a flowchart showing a design optimization method according to the eighth embodiment of the present invention. FIG. 19 is a diagram illustrating a model example used for design optimization according to the eighth embodiment of the present invention.

Explanation of symbols

S1 to S40 Each step of the flow in the present invention 1 Semiconductor integrated circuit device 2 Input / output circuit 3 of semiconductor integrated circuit device Internal circuit 4 to 10 of semiconductor integrated circuit device Block 11 divided by layout 11 Power supply-ground circuit model 12 13 to 13 PMOS transistors 14 to 15 NMOS transistors 16 to 17 Circuit models 18 to 25 equivalently converted to RC circuits 18 to 25 Resistors 26 to 28 Capacitance 29 Circuit model 30 when operating frequency is high 30 When operating frequency is low Circuit model 31 Degenerated resistor 32 Degenerated capacitor 33 Single RC circuit 34 composed of circuit elements between power supply and ground RC multiplication value 35 Input / output circuits 36 to 41 including protection circuit Power supply circuit block 42 Electrostatic noise Source 43 Flows to input / output circuit including protection circuit Current 44 Current flowing in the block 45 to 48 Inverter 49 Signal line connected area 50 Other area 51 Signal line connected area 52 Other area 53 to 56 Inverter 57 Signal line connected area 58 Other area 59 Signal line connected area 60 Other area 61 Modeling example of area connected to output signal terminal 62 Area connected to signal line 63 Other area 64 to 65 Modeling example of area connected to output signal terminal 66 to 68 Resistance 69 to 70 Capacitance 71 to 72 Charge A path 74 through which the signal flows 73 A region 74 in the semiconductor integrated circuit A region 75 connected to all signal terminals Other regions 76 A region 77 connected to the signal terminal 1 Other regions 78 Optimized circuit 79 A path 80 through which charges flow Inserted resistor 81 Optimal Circuit 82 charge flow path 83 inserted resistor 84 optimization The circuit 85 routes 86 inserted of flow of the charge capacity 87 optimized circuit 88 path 89 inserted volume of flow of the charge

Claims (20)

Dividing the internal circuit of the semiconductor integrated circuit device into a plurality of blocks;
Analyzing the resistance to electrostatic noise based on the impedance information of each of the plurality of blocks;
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, comprising:   2. The semiconductor integrated circuit device according to claim 1, wherein the impedance information is obtained by equivalently converting an internal circuit of the block into an RC circuit composed of a resistor and a capacitor, and obtaining the equivalent converted RC circuit. Electrostatic noise tolerance analysis method.   3. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 2, wherein the RC circuit is degenerated into a single RC circuit between a power source and a ground.   4. The degeneration is performed by approximating the impedance of the RC circuit only with a resistance component when the operating frequency is high, and degenerating by approximating only the capacitance component when the operating frequency is low. Electrostatic noise tolerance analysis method for semiconductor integrated circuit device of   5. The semiconductor according to claim 4, wherein an RC multiplication value is calculated from a resistance value and a capacitance value in the approximate single RC circuit, and a block having low resistance to electrostatic noise is detected from the RC multiplication value. Electrostatic noise resistance analysis method for integrated circuit device.   By detecting the detection based on the result of comparing the RC multiplication value of the input / output circuit including the protection circuit and the RC multiplication value of each of the plurality of blocks, a block having low electrostatic noise resistance and a strong block are determined. 6. The electrostatic noise resistance analysis method for a semiconductor integrated circuit device according to claim 5, wherein the method is performed. Dividing the internal circuit of the semiconductor integrated circuit device into a region connected to the signal terminal and another region;
Equivalently converting an internal circuit in a region connected to the signal terminal into an RC circuit composed of a resistor and a capacitor;
Calculating an RC multiplication value in the equivalently converted RC circuit;
Detecting electrostatic noise resistance in a region connected to the signal terminal from the RC multiplication value;
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, comprising:   8. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 7, wherein the RC circuit obtained by equivalently converting an internal circuit in a region connected to the signal terminal is degenerated into a single RC circuit.   The electrostatic noise resistance of the region connected to the signal terminal is determined based on a result of comparing the detection with the RC multiplication value of the input / output circuit including the protection circuit and the RC multiplication value of the region connected to the signal terminal. The method for analyzing electrostatic noise resistance of a semiconductor integrated circuit device according to claim 7 or 8, wherein   When the internal circuit in the region connected to the signal terminal cannot be reduced to a single RC circuit, the internal circuit in the other region is reduced to a single RC circuit, and each region is subjected to electrostatic noise by simulation. 9. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 8, wherein the resistance is evaluated.   11. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 7, wherein the region connected to the signal terminal is a region connected to an input signal terminal or an output signal terminal. .   In the region connected to the output signal terminal, electrostatic noise is applied between the power source and the ground, and the RC multiplication value in each path through which the charge flows by this application is compared with the RC multiplication value of the input / output circuit including the protection circuit. Based on the comparison, the electrostatic noise resistance of any one of the region connected to the signal terminal and between the signal and the ground, the region connected to the signal terminal and between the signal and the power source, and the other region is determined. 12. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 11, wherein: Dividing the internal circuit of the semiconductor integrated circuit device into a region (S) connected to all signal terminals and another region (Z);
Dividing the region (S) connected to all the signal terminals into regions (S1, S2,...) Connected to the signal terminals and the other regions (Z1, Z2,.
Modeling the internal circuit of the region (S1, S2,...), Region (Z1, Z2,...), Region (Z) into an RC circuit;
Modeling the internal circuit of the semiconductor integrated circuit device into region (X1) = region (S1 + Z1 + Z), region (X2) = region (S2 + Z2 + Z),
Have
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, wherein the model of the area (Z) is reused in the analysis of the electrostatic noise resistance of each area (X1), area (X2),. Dividing the internal circuit of the semiconductor integrated circuit device into a plurality of regions;
Equivalently converting each of the plurality of regions into an RC circuit;
Applying electrostatic noise to each of the plurality of regions;
Obtaining the impedance in each of the plurality of regions when the electrostatic noise is applied from the frequency of the electrostatic noise;
Comparing the impedance of the input / output circuit including a protection circuit with the determined impedances of the plurality of regions, and determining electrostatic noise resistance for the plurality of regions based on the comparison results;
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, comprising: Extracting a block composed of only standard cells from the internal circuit of the semiconductor integrated circuit device;
Obtaining area information of the block;
Determining electrostatic noise resistance of the block from the area information;
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, comprising:   16. The method for analyzing an electrostatic noise resistance of a semiconductor integrated circuit device according to claim 15, wherein the block is extracted from layout information of the semiconductor integrated circuit device.   Capacitance values obtained in advance corresponding to the areas are summarized as a correspondence table, and the block area is associated with the correspondence table to obtain a block capacitance value. 17. The semiconductor integrated circuit device according to claim 15, wherein an RC multiplication value is calculated from the resistance value, and electrostatic noise resistance of the block is determined based on the calculated RC multiplication value. 17. Electric noise tolerance analysis method. Detecting a region having low electrostatic noise resistance using the electrostatic noise resistance analysis method according to any one of claims 1 to 17,
Extracting a terminal connected to the detected area of weak electrostatic noise resistance;
Performing electrostatic noise verification simulation on the extracted terminals;
An electrostatic noise resistance analysis method for a semiconductor integrated circuit device, comprising: Detecting a path with low electrostatic noise resistance using the electrostatic noise resistance analysis method according to any one of claims 1 to 18,
Obtaining impedance information in the detected weak path of electrostatic noise resistance;
Increasing the impedance of the detected weak path of electrostatic noise resistance based on the impedance information to reinforce the electrostatic noise resistance of the path;
A method for optimizing the design of a semiconductor integrated circuit device. Detecting a path with low electrostatic noise resistance using the electrostatic noise resistance analysis method according to any one of claims 1 to 18,
Obtaining impedance information in the detected weak path of electrostatic noise resistance;
Reducing the impedance of the path parallel to the detected weak path of electrostatic noise resistance based on the impedance information to reinforce the electrostatic noise resistance for the path of weak electrostatic noise resistance;
A method for optimizing the design of a semiconductor integrated circuit device.

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