JP2005109983A - Operation amplifier, sample-hold circuit using it and filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a balance type operation amplifier by which in-phase signals can be sufficiently suppressed by using two gain stages suitable for use under a low power source voltage. <P>SOLUTION: The operation amplifier is provided with first and second input terminals IN1 and IN2 for respectively receiving first and second input signals which are differential with respect to each other, a first inverting amplifier circuit A1 for amplifying the first input signal, a second inverting amplifier circuit A2 for amplifying the second input signal, a third inverting amplifier circuit A3 for outputting a first output signal which is the result of multiplication of the output signal of the first inverting amplifier circuit A1 by the first gain and a second output signal which is the result of its multiplication by the second gain, a fourth inverting amplifier circuit A4 for outputting a third output signal which is the result of multiplication of the output signal of the second inverting amplifying circuit A2 by the first gain and a fourth output signal which is the result of its multiplication by the second gain and first and second noninverting amplifier circuits A5 and A6 which amplify quasi-in-phase output signals Voc which are obtained by summing the second output signal and the fourth output signal and feeding them back to the inputs of the third and fourth inverting amplifying circuits A3 and A4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an operational amplifier with a low power supply voltage that handles differential signals, and more particularly to an operational amplifier that achieves improved frequency characteristics and improved common-mode signal reduction.

  The progress of integrated circuits is remarkable, and the miniaturization of manufacturing processes is progressing year by year. With the miniaturization of the manufacturing process, the performance of a single transistor is improved, but the breakdown voltage, that is, the power supply voltage that can be applied to the transistor is low. When the power supply voltage is lowered, the amplitude of the voltage signal that can be handled in the integrated circuit becomes small, and it becomes difficult to realize a desired signal-to-noise ratio (S / N). In order to solve this, the operational amplifier realizes a signal amplitude that is double that of the single-phase signal by differentiating the input signal and the output signal.

  In an operational amplifier having a so-called balanced configuration that handles such input / output as a differential signal, it is necessary to suppress the in-phase signal, unlike an operational amplifier that handles a single-phase signal. For example, in the case of a filter using an integrator realized by an operational amplifier having a balanced configuration, the voltage range of the output signal is narrowed if the common-mode signal removal of the operational amplifier is not sufficient, and the differential output signal is distorted. Become. In particular, if the power supply voltage is lowered, the signal amplitude range that can be handled is reduced, and therefore suppression of the in-phase signal is essential.

  In a balanced operational amplifier, a method of using a differential pair in the input unit and the common mode feedback unit in order to suppress the common-mode signal has been proposed (see, for example, FIGS. 1 and 1 of Non-Patent Document 1). 3).

Mihai Banu, John M. Khoury, and Yannis Tsividis, “Fully differential operational amplifiers with accurate output balancing”, IEEE Journal of Solid-State Circuits, vol. 23, pp. 1410-1414, December 1988

  If a differential pair is used for common-mode signal suppression as in Non-Patent Document 1, at least three transistors are stacked vertically between the power supply and the ground, so when the power supply voltage is low However, there is a problem that the signal amplitude range that can be handled cannot be taken sufficiently.

  An object of the present invention is to provide an operational amplifier having a balanced configuration that can sufficiently suppress an in-phase signal by using two gain stages suitable for a low power supply voltage.

  According to an aspect of the present invention, first and second input terminals for inputting first and second input signals having a differential relationship with each other, and a first inverting amplifier circuit for amplifying the first input signal, A second inverting amplifier circuit for amplifying the second input signal, a first output signal obtained by multiplying the output signal of the first inverting amplifier circuit by a first gain, and a second output signal obtained by multiplying the second gain signal. , A third output signal obtained by multiplying the output signal of the second inverting amplifier circuit by a first gain, and a fourth output signal obtained by multiplying the second gain by a fourth gain. An inverting amplifier circuit; and first and second non-inverting amplifier circuits that amplify a sum signal of the second output signal and the fourth output signal and feed back to the inputs of the third and fourth inverting amplifier circuits. An operational amplifier is provided.

  According to the present invention, an in-phase signal can be sufficiently suppressed by an operational amplifier having a balanced configuration having two gain stages directed to a low power supply voltage. In addition, since the number of internal nodes in each path of the differential signal is one, the frequency characteristics can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 shows an operational amplifier with a balanced configuration according to a first embodiment of the present invention. Differential input signals, that is, first and second input signals having a differential relationship with each other are input to the first and second input terminals IN1 and IN2, respectively. The first input signal from the first input terminal IN1 is input to the + input terminal of the first inverting amplifier circuit A1, and the second input signal from the second input terminal IN2 is input to the second inverting amplifier circuit A2. Is input to the + input terminal.

  The negative output terminal of the first inverting amplifier circuit A1 is connected to the positive input terminal of the third inverting amplifier circuit A3. The negative output terminal of the second inverting amplifier circuit A2 is connected to the positive input terminal of the fourth inverting amplifier circuit A4. The third and fourth inverting amplifier circuits A3 and A4 each have two negative output terminals. The first -output terminal of the third inverting amplifier circuit A3 is connected to the first output terminal OUT1, and the first -output terminal of the fourth inverting amplifier circuit A4 is connected to the second output terminal OUT2. Is done. The second -output terminal of the third inverting amplifier circuit A3 and the second -output terminal of the fourth inverting amplifier circuit A4 are connected to each other.

  The common connection node of the second − output terminals of the third and fourth inverting amplifier circuits A3 and A4 is connected to the + input terminals of the non-inverting amplifier circuits A5 and A6. The non-inverting amplifier circuits A5 and A6 have positive output terminals connected to negative output terminals of the first and second inverting amplifier circuits A1 and A2, that is, positive input terminals of the third and fourth inverting amplifier circuits A3 and A4, respectively. Is done.

  Here, the inverting amplifier circuits A3 and A4 are configured by inverting amplifier circuits Aa1 and Aa2, for example, as shown in FIG. The + input terminals of the inverting amplifier circuits Aa1 and Aa2 are connected to each other. As shown in FIG. 3, each of the inverting amplifier circuits Aa1 and Aa2 includes a series circuit of a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) P1 and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) N1. That is, the source terminal of the PMOS transistor P1 is connected to the power supply Vdd, the gate terminal is connected to the bias source Vbias, the drain terminal is connected to the drain terminal of the NMOS transistor N1, and the output terminal OUT−. The source terminal of the NMOS transistor N1 is connected to the ground, and the gate terminal is connected to the input terminal IN +. The circuit in FIG. 3 has a simple configuration having no internal nodes other than the input terminal and the output terminal. That is, the inverting amplifier circuits A3 and A4 have no nodes inside.

  Next, the operation of the operational amplifier of FIG. 1 will be described. When the first and second input signals, which are differential input signals of the operational amplifier, are input from the first and second input terminals IN1 and IN2 to the first and second inverting amplifier circuits A1 and A2, The second inverting amplifier circuits A1 and A2 output the amplified output signals Vo1 and Vo2, respectively.

  The output signal Vo1 from the first inverting amplifier circuit A1 is input to the + input terminal of the third inverting amplifier circuit A3. The third inverting amplifier circuit A3 outputs the first output signal −αVo1 from the first −output terminal, and outputs the second output signal −βVo1 from the second −output terminal. Similarly, the output signal Vo2 from the second inverting amplifier circuit A2 is input to the + input terminal of the fourth inverting amplifier circuit A4. The fourth inverting amplifier circuit A4 outputs the third output signal -αVo2 from the first -output terminal, and outputs the fourth output signal -βVo2 from the second -output terminal.

Here, α is the first gain and β is the second gain, both of which are positive constants. The first and third output signals -αVo1 and -αVo2 are differential output signals of the operational amplifier, and are output to the first and second output terminals OUT1 and OUT2.
At the common connection node of the second -output terminals of the third and fourth inverting amplifier circuits A3 and A4, the second output signal -βVo1 and the fourth output signal -βVo1 are added, resulting in an anti-phase signal component. Are canceled and only the in-phase signal component is output, thereby generating a pseudo-in-phase output signal Voc. When the outputs of the third and fourth inverting amplifier circuits A3 and A4 are current signals, the third output signal -βVo1 and the fourth output signal -βVo1 are simply connected to each second -output terminal. Addition is possible. The non-inverting amplifier circuits A5 and A6 receive the pseudo in-phase output signal Voc and feed back to the outputs of the first and second inverting amplifier circuits A1 and A2, that is, the inputs of the third and fourth inverting amplifier circuits A3 and A4. To do.

  In the operational amplifier of FIG. 1, the pseudo in-phase output signal Voc is fed back to the + input terminals of the inverting amplifier circuits A3 and A4. Here, when the voltage of the pseudo in-phase output signal Voc increases, the non-inverting amplifier circuits A5 and A6 try to increase the output voltages Vo1 and Vo2. On the other hand, as a result of the inverting amplifier circuits A3 and A4 trying to lower the output voltage, negative feedback is applied to the inverting amplifier circuits A3 and A4. Therefore, the in-phase signal components included in the output signals −αVo1 and −αVo2 that are differential output signals output from the output terminals OUT1 and OUT2 are effectively suppressed.

  In addition, the operational amplifier of this embodiment has one internal node in each of two signal paths for differential input signals, that is, a positive phase signal path for transmitting a + signal and a negative phase signal path for transmitting a-signal. . For this reason, compared with the configuration having a plurality of internal nodes, the deterioration of the frequency characteristics due to the parasitic capacitance in the internal nodes can be minimized, so that the operation speed can be increased.

  Next, the operation of the operational amplifier of this embodiment will be described in more detail. The differential gain of the operational amplifier of this embodiment, that is, the gain with respect to the differential input signal is the product of the gains of the inverting amplifier circuits A1 (A2) and A3 (A4). Here, it is assumed that the inverting amplifier circuits A1 and A2, A3 and A4, and the non-inverting amplifier circuits A5 and A6 have the same characteristics.

  The operational amplifier of FIG. 1 can be represented by an equivalent circuit shown in FIG. 4 for in-phase signals. Here, gm1 is the transconductance of the inverting amplifier circuit A1, βgm3 is the transconductance from the positive input terminal of the inverting amplifier circuit A3 to the output of the pseudo in-phase output signal Voc, gm5 is the transconductance of the non-inverting amplifier circuit A5, and ro1 is inverted. The output resistance of the amplifier circuit A1, ro5 represents the output resistance of the non-inverting amplifier circuit A5, and ro3 and ro4 represent the output resistances at the second-output terminals of the inverting amplifier circuits A3 and A4. A transfer function from the input signal Vin to the output signal Voc is obtained by the following equation.

ここで、ｒｏ１／／ｒｏ５はｒｏ１とｒｏ５の並列合成抵抗、ｒｏ３／／ｒｏ４はｒｏ１とｒｏ５の並列合成抵抗をそれぞれ表す。ｇｍ５（ｒｏ１／／ｒｏ５）≫１、ｇｍ１＝ｇｍ５とすると、式（１）から同相信号に対する演算増幅器の利得、すなわち同相利得は１となり、入力同相電圧はそのまま出力に現れる。通常、演算増幅器では差動信号に対する利得、すなわち差動利得が１より非常に大きくなるように設計されるから、本実施形態によると非常に大きなＣＭＲＲ（同相信号除去比）を得ることができる。

Here, ro1 // ro5 represents the parallel combined resistance of ro1 and ro5, and ro3 // ro4 represents the parallel combined resistance of ro1 and ro5, respectively. If gm5 (ro1 // ro5) >> 1 and gm1 = gm5, the gain of the operational amplifier with respect to the common-mode signal, that is, the common-mode gain is 1, from Equation (1), and the input common-mode voltage appears at the output as it is. In general, an operational amplifier is designed so that a gain with respect to a differential signal, that is, a differential gain is much larger than unity. Therefore, according to the present embodiment, a very large CMRR (common mode rejection ratio) can be obtained. .

Further, since the inverting amplifier circuits A3 and A4 have no internal node, the operational amplifier shown in FIG. 1 has one internal node in each of the two signal paths of the differential input signal, thereby maintaining good frequency characteristics. it can.
(Modification of the first embodiment)
FIG. 5 shows an example in which the operational amplifier shown in FIG. 1 is modified. In the operational amplifier of FIG. 5, fifth to eighth inverting amplifier circuits A7 to A10 are added to the operational amplifier of FIG. That is, the inverting amplifier circuits A7 and A8 are connected between the output terminals of the first and second inverting amplifier circuits A1 and A2 and the input terminal terminals of the third and fourth inverting amplifier circuits A3 and A4, respectively. The inverting amplifier circuits A9 and A10 are connected in antiparallel between the output terminals of the second inverting amplifier circuits A1 and A2.

  According to the operational amplifier of FIG. 5, the output voltages of the inverting amplifier circuits A1 and A2 have a relationship of Vo1 = −Vo2 with respect to the differential signal components of the differential input signals from the input terminals IN1 and IN2. Therefore, the signal component output from the inverting amplifier circuit A9 is canceled by the signal component output from the inverting amplifier circuit A8. Similarly, the signal component output from the inverting amplifier circuit A10 is canceled by the signal component output from the inverting amplifier circuit A7. That is, as shown in FIGS. 6A and 6B, the inverting amplifier circuits A7 to A10 make no contribution to the differential input signal.

  On the other hand, for the in-phase signal components of the differential input signals from the input terminals IN1 and IN2, the output voltages of the inverting amplifier circuits A1 and A2 have a relationship of Vo1 = Vo2. In this case, the signal component output from the inverting amplifier circuit A9 is added to the signal component output from the inverting amplifier circuit A8. Similarly, the signal component output from the inverting amplifier circuit A10 is added to the signal component output from the inverting amplifier circuit A7.

  As a result, the inverting amplifier circuits A7 to A10 are as shown in FIGS. 7A and 7B for the in-phase signal components. That is, the resistance component at the outputs of the inverting amplifier circuits A1 and A2 takes a value proportional to the reciprocal of the transconductance of the inverting amplifier circuit A7 to the inverting amplifier circuit A10, and therefore becomes very small. Therefore, the common mode gain at the outputs of the inverting amplifiers A1 and A2 can be reduced without increasing the internal nodes in the two signal paths of the differential input signal, and the common mode gain of the entire operational amplifier can be reduced.

(Second Embodiment)
FIG. 8 shows a balanced operational amplifier according to a second embodiment of the present invention. In the operational amplifier of FIG. 8, a third input terminal IN3 and third and fourth non-inverting amplifier circuits A11 and A12 are added to the operational amplifier shown in FIG. The third input terminal IN3 receives the in-phase input signal Vic corresponding to the in-phase component of the first and second input signals input to the first and second input terminals IN1 and IN2. The in-phase input signal Vic can be generated using a multi-input multi-output amplifier. The positive input terminals of the non-inverting amplifier circuits A11 and A12 are connected to the third input terminal IN3. The + output terminals of the non-inverting amplifier circuits A11 and A12 are connected to the − output terminals of the first and second inverting amplifier circuits A1 and A2, respectively.

  In the operational amplifier of FIG. 8, the first and second inverting amplifier circuits A1 and A2 are, as in the first embodiment, the first and second input terminals IN1 and IN2 that are differential input signals of the operational amplifier. The first and second input signals from are inverted and amplified and output. On the other hand, the newly added third and fourth non-inverting amplifier circuits A11 and A12 amplify and output the in-phase input signal Vic from the third input terminal IN3.

  The third inverting amplifier circuit A3 has, at the + input terminal, an output signal of the first inverting amplifier circuit A1 and a signal proportional to the pseudo in-phase input signal Vic, which is an output signal of the third non-inverting amplifier circuit A11. When the addition signal Vo1 is input, the first output signal -αVo1 is output from the first -output terminal, and the second output signal -βVo1 is output from the second -output terminal.

  Similarly, the fourth inverting amplifier circuit A4 is proportional to the pseudo in-phase input signal Vic that is the output signal of the second inverting amplifier circuit A2 and the output signal of the fourth non-inverting amplifier circuit A12 at the + input terminal. When the addition signal Vo2 with the signal is input, the third output signal -αVo2 is output from the first -output terminal, and the fourth output signal -βVo2 is output from the second -output terminal.

Here, α is the first gain and β is the second gain, both of which are positive constants. The first and third output signals -αVo1 and -αVo2 are differential output signals of the operational amplifier, and are output to the first and second output terminals OUT1 and OUT2.
Also in this embodiment, the differential gain is the product of the gains of the inverting amplifier circuits A1 (A2) and A3 (A4), as in the first embodiment. On the other hand, the output signals of the inverting amplifiers A1 and A2 and the output signals of the non-inverting amplifiers A6 and A7 are added to cancel the common-mode signal. Become. Therefore, the common-mode gain can be reduced without increasing the number of internal nodes.

(Modification of the second embodiment)
FIG. 9 shows an operational amplifier in which the inverting amplifiers A7 to A10 for reducing the gain of the inverting amplifiers A1 and A2 with respect to the in-phase signal are added to the operational amplifier of FIG. . With such a configuration, the common-mode gain can be further reduced without increasing the number of internal nodes as in the operational amplifier of FIG.

(Third embodiment)
FIG. 10 shows an operational amplifier with a balanced configuration according to the third embodiment of the present invention. In the operational amplifier of FIG. 10, a fifth non-inverting amplifier circuit A13 is added to the operational amplifier shown in FIG. The non-inverting amplifier circuit A13 has two input terminals and two output terminals, the two input terminals are connected to the first and second input terminals IN1 and IN2, respectively, and the two output terminals are the first and second output terminals. Are connected to the output terminals of the inverting amplifier circuits A1 and A2, that is, the input terminals of the third and fourth inverting amplifier circuits A3 and A4. The operational amplifier shown in FIG. 10 does not receive an in-phase input signal from the outside unlike the operational amplifier shown in FIG. 8, and the non-inverting amplifier circuit A13 receives the in-phase input signal from the first and second input signals IN1 and IN2. An example of generation is shown.

  In the operational amplifier of FIG. 10, the first and second inverting amplifier circuits A1 and A2 are the first and second input terminals IN1 and IN2 which are differential input signals of the operational amplifier, as in the first embodiment. The first and second input signals from are inverted and amplified and output. On the other hand, the newly added fifth non-inverting amplifier circuit A13 outputs a signal proportional to the sum of the first and second input signals from the input terminals IN1 and IN2 (hereinafter simply referred to as a sum signal). . The sum signal is added to the output signals of the first and second inverting amplification circuits A1 and A2, and the resulting addition signals Vo1 and Vo2 are input to the third and fourth inverting amplification circuits A3 and A4, respectively.

  The third inverting amplifier circuit A3 receives the sum signal Vo1 of the output signal of the first inverting amplifier circuit A1 and the output signal of the fifth non-inverting amplifier circuit A13 at the + input terminal. The first output signal -αVo1 is output from the -output terminal of the second output signal, and the second output signal -βVo1 is output from the second -output terminal.

  Similarly, the fourth inverting amplifier circuit A4 receives the addition signal Vo2 of the output signal of the second inverting amplifier circuit A2 and the output signal of the fifth non-inverting amplifier circuit A13 at the + input terminal. The third output signal -αVo2 is output from the first -output terminal, and the fourth output signal -βVo2 is output from the second -output terminal.

Here, α is the first gain and β is the second gain, both of which are positive constants. The first and third output signals -αVo1 and -αVo2 are differential output signals of the operational amplifier, and are output to the first and second output terminals OUT1 and OUT2.
The non-inverting amplifier circuit A13 includes a multi-input / multi-output amplifier circuit, for example, inverting amplifier circuits Ab1 to Ab5 as shown in FIG. That is, the output terminals of the inverting amplifier circuits Ab1 and Ab2 are connected to each other and connected to the input terminal of the inverting amplifier circuit Ab3. The input / output terminals of the inverting amplifier circuit Ab3 are connected to each other and to the input terminals of the amplifiers Ab4 and Ab5. With this configuration, the in-phase signals from the inverting amplifier circuits Ab1 and Ab2 are added together and input to the inverting amplifier circuits Ab3 and Ab5 via the inverting amplifier circuit Ab3. From the inverting amplifier circuits Ab3 and Ab5, a signal proportional to the sum of the input signals IN1 and IN2 is output.

(Modification of the third embodiment)
FIG. 12 shows an example in which the in-phase gain is further reduced by adding the inverting amplifier circuits A7 to A10 described in FIG. 5 to the operational amplifier of FIG.
FIG. 13 shows a first circuit diagram in which the operational amplifier shown in FIG. 12 is realized by a MOS transistor. The NMOS transistor MN1 corresponds to the inverting amplifier circuit A1, and the transistor MN2 corresponds to the inverting amplifier circuit A2. The transistors MN13_1 and MN13_2 and the PMOS transistors MP13_1, MP13_2, MP5_2, and MP6 constitute a non-inverting amplifier circuit A13. Here, the transistors MP5_2, MP13_1, and MP13_2 are shared with the non-inverting amplifier circuit A5, and the transistors MP6, MP13_1, and MP13_2 are shared with the non-inverting amplifier circuit A6. The NMOS transistors MN7 to MN10 and PMOS MP7 to MP10 correspond to the inverting amplifier circuits A7 to A10, respectively.

  The NMOS transistor MN5 and the PMOS transistors MP5_1, MP5_2, MP13_1, and MP13_2 constitute a non-inverting amplifier circuit A5, and the NMOS transistor MN5 and the PMOS transistors MP5_1, MP6, MP13_1, and MP13_2 constitute a non-inverting amplifier circuit A6. The NMOS transistors MN3_1 and MN3_2 and the PMOS transistors MP3_1 and MP3_2 constitute an inverting amplifier circuit A3, and the NMOS transistors MN4_1 and MN4_2 and the PMOS transistors MP4_1 and MP4_2 constitute an inverting amplifier circuit A4.

As is clear from the transistor circuit shown in FIG. 13, the operational amplifier of this embodiment can be realized with a configuration that avoids vertical stacking of transistors, and is therefore suitable for lowering the power supply voltage.
As described above, the number of internal nodes is one in each of the two signal paths of the differential input signal, that is, the path from the input terminal IN1 to the output terminal OUT1 and the path from the input terminal IN2 to the output terminal OUT2. This can improve the frequency characteristics for differential signals.

  FIG. 14 shows another circuit example in which the operational amplifier shown in FIG. 12 is realized by a MOS transistor. In this example, the inverting amplifier circuits A1, A2, A7, A8, A9, A10 and the non-inverting amplifier circuits A5, A6, A13 have a cascode configuration. Amplifying circuits A1 and A2 have a cascode configuration to increase the differential gain, and amplifying circuits A5, A6, A7, A8, A9, and A10 have a cascode configuration to enhance the common-mode signal suppression effect. .

  Further, in the circuit of FIG. 14, a gain enhancing amplifier composed of transistors MN14_1, MN14_1C, MP14_1, MN14_2, MN14_2C, and MP14_2 is added to form a cascode transistor MP5_2C and an inverting amplifier circuit A2 constituting the inverting amplifier circuit A1. By increasing the gain of the cascode transistor MP6C, the gains of the inverting amplifier circuits A1 and A2 are increased. Further, the output common mode voltage of the gain enhancement amplifier is stabilized by connecting the gate terminals of the current source transistors MN14_1 and MN14_2 constituting the gain enhancement amplifier to the pseudo common mode output signal Voc. As described above, in the operational amplifier having the two-stage configuration, the output amplitude of the first stage is 1 / (gain of the second stage) as compared with the output amplitude of the second stage. Therefore, the cascode configuration is used for the first amplification stage. However, the performance of the operational amplifier can be easily improved without any problem.

  15 and 16 show a sample and hold circuit using an operational amplifier according to an embodiment of the present invention. In this sample and hold circuit, in the sampling state, that is, in writing, as shown in FIG. 15, the switches SW1 to SW6 are turned on and the switches SW7 to SW10 are turned off to correspond to the input signals from the input terminals IN1 and IN2. The accumulated charges are stored in the capacitors C1 and C2.

  On the other hand, in the hold state, that is, when reading is performed, the switches SW1 to SW6 are turned off and the switches SW7 to SW10 are turned on as shown in FIG. A signal is input to the OPA.

  In this sample and hold circuit, the switch is constituted by a MOS transistor. A MOS transistor has a channel formation when it is turned on / off. When this channel is formed, the charge components enter in phase. For this reason, the voltage rises in the channel portion, and a saturation state occurs unless this voltage rise is suppressed. According to the present embodiment, since the common-mode component is canceled out in the operational amplifier OPA, the common-mode gain is reduced, and the power supply voltage of the sample and hold circuit can be reduced.

  FIG. 17 shows a filter using an operational amplifier according to an embodiment of the present invention. The filter is composed of an integrator, and the integrator is composed of an amplifier Amp1, resistors R1 to R4, and capacitors C1 and C2, as shown in FIG. An operational amplifier according to the embodiment of the present invention is used as the amplifier Amp1. The filter shown in FIG. 17 includes operational amplifiers Int1 to Int5. Here, the operational amplifier Int1 in the first stage uses an operational amplifier that internally generates an in-phase input signal as shown in FIG. 1 or FIG. On the other hand, since the operational amplifiers Int2 to Int5 in the subsequent stage can use the in-phase component included in the output signal of the operational amplifier in the previous stage, the operational amplifier shown in FIG. 8 or FIG. 9 is used.

  In the above embodiment, an example in which field effect transistors (especially MOS transistors) are used as all transistors has been described. However, bipolar transistors can also be used. When using a bipolar transistor, the gate terminal, drain terminal, and source terminal of the field effect transistor may be replaced with the base terminal, collector terminal, and emitter terminal of the bipolar transistor, respectively.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a circuit diagram of an operational amplifier according to the first embodiment of the present invention. 1 is a circuit diagram of an inverting amplifier circuit with one input and two outputs shown in FIG. Circuit diagram showing an example of inverting amplifier circuit 1 is an equivalent circuit diagram for the in-phase signal component of the operational amplifier shown in FIG. Circuit diagram of operational amplifier according to a modification of the first embodiment The figure explaining the operation | movement with respect to the in-phase signal component of the operational amplifier of FIG. The figure explaining the operation | movement with respect to the differential signal component of the operational amplifier of FIG. Circuit diagram of operational amplifier according to the second embodiment Circuit diagram of operational amplifier according to a modification of the second embodiment Circuit diagram of operational amplifier according to the third embodiment Circuit diagram of the non-inverting amplifier circuit with two inputs and two outputs shown in FIG. Circuit diagram of operational amplifier according to a modification of the third embodiment Specific circuit diagram of the operational amplifier of FIG. Specific circuit diagram in which a cascode configuration is applied to the operational amplifier of FIG. The circuit diagram which shows the sampling state of the sample hold circuit using the operational amplifier according to the embodiment of the present invention Circuit diagram showing the hold state of the sample and hold circuit Circuit diagram showing filter using integrator Specific circuit diagram of the integrator

Explanation of symbols

  IN1, IN2, IN3: input terminal, OUT1, OUT2: output terminal, Int: integrator, A1 to A4, A7 to A10: inverting amplifier circuit, A5, A6, A11, A12, A13: non-inverting amplifier circuit, N1: MNOS transistor, P1: PMOS transistor, SW ~: switch, Vdd: first power supply potential point, Vss: second power supply potential point, C1, C2: capacitance, R1-R4: resistance.

Claims (8)

First and second input terminals for respectively inputting first and second input signals having a differential relationship;
A first inverting amplifier circuit for amplifying the first input signal;
A second inverting amplifier circuit for amplifying the second input signal;
A third inverting amplifier circuit for outputting a first output signal obtained by multiplying the output signal of the first inverting amplifier circuit by a first gain and a second output signal obtained by multiplying the second gain;
A fourth inverting amplifier circuit for outputting a third output signal obtained by multiplying the output signal of the second inverting amplifier circuit by a first gain and a fourth output signal multiplied by the second gain;
And a first non-inverting amplifier circuit that amplifies a sum signal of the second output signal and the fourth output signal and feeds back to the inputs of the third and fourth inverting amplifier circuits. Operational amplifier. A fifth inverting amplifier circuit that amplifies the output signal of the first inverting amplifier circuit and supplies the amplified signal to the input of the third inverting amplifier circuit;
A sixth inverting amplifier circuit that amplifies the output signal of the second inverting amplifier circuit and supplies the amplified signal to the input of the fourth inverting amplifier circuit;
A seventh inverting amplifier circuit that amplifies the output signal of the first inverting amplifier circuit and supplies the amplified signal to the input of the fourth inverting amplifier circuit;
The operational amplifier according to claim 1, further comprising an eighth inverting amplifier circuit that amplifies an output signal of the second inverting amplifier circuit and supplies the amplified signal to an input of the third inverting amplifier circuit. A third input terminal for inputting an in-phase input signal corresponding to an in-phase component of the first and second input signals;
A third non-inverting amplifier circuit that amplifies the in-phase input signal and supplies it to the input of the third inverting amplifier circuit;
The operational amplifier according to claim 1, further comprising a fourth non-inverting amplifier circuit that amplifies the common-mode signal and supplies the amplified signal to an input of the fourth inverting amplifier circuit.   A fifth non-inverting amplifier circuit which receives the first and second input signals and supplies a signal proportional to the sum of the first and second input signals to the inputs of the third and fourth inverting amplifier circuits The operational amplifier according to claim 1, further comprising:   The operational amplifier according to any one of claims 1 to 4, wherein the first and second inverting amplifier circuits have a cascode configuration.   The operational amplifier according to claim 1, wherein the first and second inverting amplifier circuits have a regulated cascode configuration.   A sample and hold circuit using the operational amplifier according to claim 1.   A filter circuit using the operational amplifier according to claim 1.

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