JP2005109768A - Digital modulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital modulator which can perform a stable burst transmission with a simple configuration. <P>SOLUTION: The digital modulator includes a transmitting slot having a lamp processing section of two symbols in a head and a tail interposing a normal transmitter to suppress the generation of a spuriousness. A modulation signal is multiplied by a gate signal of (a), and a burst signal having smooth rise/fall is outputted. a gate signal is a lamp waveform with the lamp processor of the two symbols as a transient response period in a normal mode NOR. At this time, at the starting point of a start symbol (SS) of a transient response end time point, a deterioration might generate in a modulation accuracy. Thus, as (b), the transient response period of the lamp waveform shortened further from the two symbols of the lamp process section to a short mode SHT is further provided. The transient response period of the short mode is about 3/2 symbol as the optimum value by considering a correlation between the spuriousness and the modulation accuracy. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital modulator, and more particularly to a digital modulator that burst-transmits a modulation signal.

  In recent years, mobile communication systems, which are rapidly developing, have proposed various multiplex connections in which a plurality of users share a wireless transmission path and perform communication at the same time in order to improve frequency utilization efficiency of radio waves. Has been put to practical use.

  For example, in the PHS (Personal Handyphone System), time division multiple access (TDMA) that separates radio channels by time is generally used as a method for separating transmission channels.

  FIG. 15 is a diagram illustrating transmission timing of a 4-channel multiplexed TDMA / TDD (Time Division Multiple Access / Time Division Duplex) scheme. As shown in FIG. 15, the time (one frame) in which one frequency is used is divided into eight time slots. The length of one slot is 240 bits at 625 μsec, and the length of one frame is 8 slots at 5 msec. When viewed from the radio base station (CS), the first half 4 slots TX1 to TX4 are for transmission to the mobile terminal device (PS), and the latter half 4 slots RX1 to RX4 are for reception from the PS. With one transmission slot TX and one reception slot RX as one set, three sets of slots are allocated to the communication channel for three users, and the remaining one set of slots is allocated to the control channel.

  In this configuration, information for 5 msec is transmitted from the CS as a burst signal at 625 μsec to each PS at the timing shown in FIG. Each PS compresses its own transmission information to 625 μsec after 2.5 msec from the time when the signal from the CS is received, and transmits it in bursts.

  Here, if transmission information is transmitted in bursts as it is, there is a problem that the so-called spurious, which is out-of-band leakage power, increases due to the steep rise of the transmission signal, and the frequency band of the transmission signal widens. For this reason, a method is known in which a fixed ramp period is provided before and after transmission of transmission information, and the transmission signal rises and falls according to a smooth envelope in this ramp period (for example, Patent Documents). 1 and 2). This processing is generally called ramp processing.

  FIG. 16 is a diagram for explaining an example of the allocation of the ramp period in one transmission slot and the generated ramp waveform.

  Referring to FIG. 16A, one transmission slot of a PHS TDMA / TDD frame has a length of 625 μsec and transmits 240-bit data at a transmission rate of 384 kbit / sec. A 4-bit burst rising ramp bit (R) is provided at the head of the slot.

  Furthermore, 16 guard bits (G) are provided in the last 16 bits of the slot. The guard bit is provided in order to prevent the burst signal from the PS from colliding in the CS due to the synchronization control of each CS communicating with the same CS and the difference in signal arrival time from each CS due to the difference in distance from the CS. It is a non-transmission section. As shown in FIG. 16A, the first 4 bits of the guard bit (G) are allocated to the ramp bits (R) of the burst falling of 4 bits. In the following, a signal section that is arranged corresponding to burst rising and falling and in which ramp processing is executed is also referred to as a ramp processing section.

  In one slot, a modulation signal representing the actual transmission content is input in a section of 220 bits (corresponding to the hatched portion in the figure) excluding these ramp bits (R) and guard bits (G). . Hereinafter, this section is also referred to as a normal transmission section. For example, in the normal transmission section of the call slot, a start symbol (SS) indicating the start of burst information from the PS, a preamble (PR) for establishing bit synchronization, and word synchronization of the burst signal are established. Unique word (UW), data (I), and error check bit (CRC) for confirming transmission quality.

  Referring to FIG. 16B, the gate signal represents the gain of the transmission signal and is given by a function that transitions between “0” and “1”. The gate signal smoothly increases or decreases in the ramp processing interval, and the signal level is maintained at “1” in the normal transmission interval.

A baseband signal representing dummy data is input to the 4-bit ramp bits (R) corresponding to the rising and falling edges of the burst, and a ramp waveform as shown in FIG. 16C based on the baseband signal. Is output. This ramp waveform is obtained by multiplying the gate signal shown in FIG. 16B by the modulation signal synthesized based on the baseband signal.
Japanese Patent Publication No. 9-2675468 JP-A-9-153919

  As described above, by performing the ramp processing, the burst signal rises or falls according to a smooth envelope, so that spurious generation can be suppressed.

  Here, the transient response characteristics accompanying the rise and fall of the burst signal will be described.

  First, with regard to the transient response accompanying the rising edge of the burst signal, the transition point at the boundary between the leading ramp bit (R) and the start symbol (SS) in the normal transmission period is transient in both the call slot and the control slot. The response end time is set as the initial phase identification point in the normal transmission section after the start symbol (SS).

  Next, with regard to the transient response accompanying the falling edge of the burst signal, the boundary point between the error check bit (CRC) of the last symbol in the normal transmission section and the ramp bit (R) in the guard bit (G) is made transient. The response start time.

  Here, since the end point of the transient response accompanying the rise of the burst signal is also the initial phase identification point, it is necessary that the transient response of the burst signal is surely completed at this point. This is because if the rising edge of the burst signal is incomplete, the modulation accuracy may be degraded in the identification of the initial phase.

  FIG. 17 is a vector diagram for explaining the modulation accuracy.

  As is well known, the modulation accuracy represents the quality of the modulation signal, and is represented by the magnitude of an error vector which is the difference between the actual modulation vector and the ideal modulation vector in the phase plane of FIG. This vector error is divided into an amplitude error component and a phase error component, and is caused by the amplitude / phase error of the quadrature modulator and the nonlinearity of the power amplifier. In PHS, it is standard that the vector error is 12.5% or less (RCR STD-28).

  In the conventional digital modulator, the ramp processing is effective in suppressing the occurrence of spurious signals, but on the other hand, it causes a deterioration in the modulation accuracy of the normal transmission section. It was difficult.

  Therefore, an object of the present invention is to provide a digital modulator capable of stable burst transmission with a simple configuration.

  The digital modulator according to the present invention includes a high-order processor means for generating a digital baseband signal, a means for serial-parallel conversion of the baseband signal for each successive plurality of bits, and a quadrature in-phase and quadrature for each successive plurality of bits. A mapping means for uniquely providing symbol mapping data comprising a phase, and a digital filter for generating a modulation signal by performing band division limitation on in-phase and quadrature-phase symbol mapping data and multiplying with a carrier signal in a time-division multiplexed manner Means for detecting the timing of a burst rising interval of the modulation signal, a normal transmission interval for transmitting the modulation signal, and a burst falling interval of the modulation signal, and storing a ramp waveform in the burst rising interval and burst falling interval , Burst rising interval and burst falling interval And means for multiplying the definitive ramp waveform and the modulating signal, and means for converting the output of the multiplying means into an analog modulation signal. A ramp waveform storing means for providing a first transient response period having a symbol length within a range of the burst rising period and the burst falling period with respect to the burst rising period and the burst falling period; A second ramp waveform that provides a second transient response period that is within the range of the burst rising period and the burst falling period and that has a different symbol length from the first transient response period is stored. The upper processor means further includes means for generating a selection signal for selecting one of the first and second transient response periods. The ramp waveform storage means selectively outputs the first and second ramp waveforms according to the detection signal and the selection signal from the timing detection means.

  Preferably, the ramp waveform storage means further includes means for storing a constant value corresponding to the gain of the modulation signal with respect to the normal transmission interval, and selectively selects the constant value according to the detection signal indicating the normal transmission interval. The multiplication means multiplies the constant value in the normal transmission interval by the modulation signal.

  Preferably, the first transient response period is equal to a known ramp signal section provided at the beginning portion and the end portion of the modulation signal, and the second transient response period is shorter than the known ramp signal section. .

  Preferably, the timing detection means includes counting means for counting the symbol length of the modulation signal, and detects timings of the burst rising period, burst falling period, and normal transmission period based on the count value of the counting means.

  According to the present invention, it is possible to avoid the deterioration of modulation accuracy that may occur due to the ramp processing for suppressing the occurrence of spurious, and to realize stable burst transmission.

  Furthermore, since the digital modulator according to the present invention has a configuration in which slight changes are added to the conventional digital modulator, it can be easily realized without increasing the circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment]
FIG. 1 is a diagram conceptually showing the operating principle of the present invention. In the following embodiment, π / 4 shift QPSK (Quadrature Phase Shift Keying) defined by the PHS standard is used as a modulation method. In π / 4 shift QPSK, one symbol corresponds to 2 bits.

  Referring to FIG. 1, a transmission slot normally includes a 4-bit (2 symbols) ramp processing section provided at a head portion and a tail portion (not shown), and actual transmission information after a start symbol (SS). It consists of a transmission interval. When the transmission slot is input to the digital modulator as a serial baseband signal (modulated wave signal), a band-limited modulated signal is generated.

  Further, this modulated signal is multiplied by a gate signal indicating the gain of the transmission signal and output as a transmission burst signal. As shown in FIG. 1A, the gate signal is a function that normally increases or decreases smoothly in the 2-symbol ramp processing interval and indicates “1” in the normal transmission interval. By this gate signal, the modulation signal is processed into a waveform that smoothly increases or decreases at the rise and fall of the burst signal. Hereinafter, a normal mode in which the transient response period of the rising and falling edges of the burst signal is two symbols of the ramp processing section is also referred to as a normal mode, and is expressed using a symbol NOR.

  Here, as described above, in the normal mode, the signal level is not fixed at the boundary point between the ramp bit (R) and the start symbol (SS), which is the end point of the transient response, and the modulation accuracy deteriorates. There is a problem of end. In order to solve this, it is necessary that the gate signal is stable at “1” at the start point of the normal transmission interval.

  Therefore, in the present embodiment, a configuration is adopted in which the transient response period of the rising and falling edges of the burst signal is made shorter than two symbols in the normal ramp processing section, and the gate signal is increased or decreased in this shortened section. . Hereinafter, a mode in which the transient response period is shortened is also referred to as a short mode, and is described using a symbol SHT.

  When the length of the transient response period in the short mode is shortened, the modulation accuracy at the start point of the normal transmission interval is improved, while the rise and fall become steep and the spurious in the ramp processing interval increases. Problems arise. That is, it can be seen that the modulation accuracy and the occurrence of spurious are in a trade-off relationship. Therefore, it is necessary to consider the optimum length of the transient response period in consideration of this trade-off. As shown in FIG. 1B, the transient response period is empirically obtained in the vicinity of 3/2 symbols, so in this embodiment, the transient response in the short mode is obtained. The period is set to 3/2 symbols, which is 3/4 of the period of the normal mode. Hereinafter, the configuration of the digital modulator for realizing the operation principle of FIG. 1 will be described in detail.

  FIG. 2 is a block diagram showing the configuration of the digital modulator according to the embodiment of the present invention. In the following, a configuration of a digital modulator corresponding to the π / 4 shift QPSK modulation method is proposed.

  Referring to FIG. 2, the digital modulator includes a CPU (central processing unit) 10, a timing signal generation circuit 20, a serial / parallel conversion circuit (S / P) 30, a mapping circuit 40, and a digital filter 50. A ramp waveform storage unit 100, a digital / analog converter (D / A) 80, and a low-pass filter (LPF) 90.

  The CPU 10 is a host processor for controlling the modulation processing of the entire digital modulator, and generates a serial baseband signal (modulated wave signal) AN during burst transmission.

  The CPU 10 further determines whether the transient response period of the burst signal is 2 symbols in the normal mode or 3/2 symbols in the short mode, and a 1-bit mode selection signal NOR / for specifying the mode. Output SHT. The mode selection signal NOR / SHT indicates “0” (corresponding to “L” level) when the normal mode is selected, and “1” (corresponding to “H” level) when the short mode is selected. It is.

  The timing signal generation circuit 20 is driven by an input clock signal CLK higher than the symbol speed, and time information T1 [0: 3] (to be supplied to the clock signals T2, T3, T6 and the digital filter 50 and the ramp waveform storage unit 100). = T1-0 to T1-3).

  As shown in FIG. 2, the timing generation circuit 20 includes a ramp period detection circuit 21 for detecting whether the transmission burst signal is in a rising ramp processing period, a normal transmission period, or a falling ramp processing period. . The ramp section detection circuit 21 detects which section is by counting the clock signal of the symbol period, and generates a 2-bit detection signal UP / DOWN [0: 1] as a detection result. The detection signal UP / DOWN is input to the ramp waveform storage unit 100.

  FIG. 3 is a circuit diagram showing a configuration of timing signal generating circuit 20 shown in FIG.

  Referring to FIG. 3, timing signal generation circuit 20 includes a counter circuit 21 that counts input clock signal CLK, and decoders 23 and 24.

  The timing signal generation circuit 20 further includes a counter circuit 25 that counts the clock signal CLK-SYMBOL having a symbol period, decoders 26 to 29, and OR circuits G21 and G22 as the ramp period detection circuit 21.

  Although not shown, the counter circuit 21 includes five stages of cascaded flip-flops, and constitutes a 32-ary up counter. When a clock signal CLK having a frequency higher than the symbol rate is input to the first-stage flip-flop, the clock signal T6 is output as an output pulse obtained by dividing the frequency of the input clock signal CLK2 by half. . As will be described later, the clock signal T6 is used for time division multiplexing of the digital filter 50 between the I-phase data and the Q-phase data.

  When the clock signal T6 is input to the second-stage flip-flop, an output pulse T1-0 further divided by 1/2 is output. Similarly, output pulses T1-1, T1-2, and T1-3 divided by 1/2 for each stage are also output from the third, fourth, and fifth stage flip-flops. These output pulses T1-0 to T1-3 become 4-bit time information T1 [0: 3] given to the digital filter 50 and the ramp waveform storage unit 100 shown in FIG.

The output pulse T1-2 divided by 1/16 (= 1/2 ⁴ ) of the input clock signal CLK among the output pulses T1-0 to T1-3 is inverted by the NOT circuit G20, and the clock signal CLK− Output as SYMBOL. The clock signal CLK-SYMBOL is a signal having the same speed as the symbol speed. The clock signal CLK-SYMBOL is transmitted to the ramp section detection circuit 21.

  Further, the output pulses T1-0 and T1-1 are decoded by the decoder 23 to generate the clock signal T2. The clock signal T2 has a speed equal to the data rate of the π / 4 shift QPSK modulation method.

  The output pulses T1-0, T1-1, T1-2 are decoded by the decoder 24 to generate a clock signal T3. The clock signal T3 is a signal equal to the symbol period.

  The clock signal CLK-SYMBOL having the symbol period is input to the counter circuit 25 of the ramp period detection circuit 21. The counter circuit 25 counts up the clock signal CLK-SYMBOL one symbol at a time. The count value is output as 6-bit signals C0 to C5. The 6-bit count value is input to the decoders 26 to 29, respectively.

  Decoders 26 to 29 output an activated (“H” level) signal in response to the decoded count value matching a predetermined value set in advance. Specifically, the decoder 26 sets “0” as a set value, and outputs an “H” level signal in response to the count value becoming “0”. The set value “0” corresponds to the 0th symbol of the 1 transmission slot shown in FIG. 16, and indicates that burst transmission has started.

  The decoder 27 sets the set value to “1” and outputs an “H” level signal in response to the count value becoming “1”. That is, the decoder 27 outputs an “H” level signal with a delay of 1 symbol with respect to the decoder 26. Output signals of the decoders 26 and 27 are input to the OR circuit G21. The OR circuit G21 calculates a logical sum of these two signals and outputs a detection signal UP / DOWN0. The detection signal UP / DOWN0 becomes “1” in response to the start of burst transmission, indicating that the transmission burst signal is in the rising ramp processing section.

  The decoder 28 sets the set value to “113” and outputs an “H” level signal in response to the count value becoming “113”. The set value “113” indicates the 113th symbol of one slot shown in FIG. 16, and corresponds to the head portion of the ramp bit (R) included in the guard bit (G).

  The decoder 29 sets the set value to “114” and outputs an “H” level signal in response to the count value becoming “114”. That is, the decoder 29 outputs an “H” level signal with a delay of one symbol with respect to the decoder 28. The output signals of the decoders 28 and 29 are input to the OR circuit G22. The OR circuit G22 calculates a logical sum of these two signals and outputs a detection signal UP / DOWN1. The detection signal UP / DOWN1 becomes “1” in accordance with the end of the normal transmission interval, indicating that the transmission burst signal is in the falling ramp processing interval.

  In this way, the ramp period detection circuit 21 detects the state of the transmission burst signal and generates a 2-bit detection signal UP / DOWN [0: 1]. Specifically, the detection signal UP / DOWN [0: 1] (= (UP / DOWN1, UP / DOWN0)) is (0, 1) during the rising ramp processing interval and (0) during the normal transmission interval. , 0), and (1,0) during the falling ramp processing section. In the following, when the detection signals UP / DOWN [0: 1] are generically referred to, they are referred to by reference symbols UP / DOWN.

  FIG. 4 is an operation waveform diagram for explaining various signals generated by the timing signal generation circuit 20 of FIG.

  Referring to FIG. 4, in the signal interval of 120 symbols per slot, the signal interval of the first two symbols and the last two symbols are a rising ramp processing interval and a falling ramp processing interval, respectively. The normal transmission section is a 110 symbol (220 bits) signal section sandwiched between these ramp processing sections.

  In the π / 4 shift QPSK modulation method, a 2-bit baseband signal AN is transmitted per symbol. The time information T1 [0: 3] represents the elapsed time during the two symbol periods. The clock signal T2 is a signal having the same speed as the data rate. The clock signal T3 is a signal having a period equal to the symbol period. The clock signal T6 is a signal that transits between “1” and “0” at a rate twice as fast as the least significant bits T1-0 of the time information T1 [0: 3].

  As described above, the detection signal UP / DOWN [0: 1] indicates (0, 1) in the rising ramp processing interval, indicates (0, 0) in the normal transmission interval, and (1 in the falling ramp processing interval. , 0).

  Referring to FIG. 2 again, when the serial baseband signal AN is given from the CPU 10, the serial / parallel conversion circuit 30 is parallel 2-bit data (Yk, Xk) in synchronization with the clock signals T2, T3. Convert to

  FIG. 5 is a circuit diagram showing a configuration of serial / parallel conversion circuit 30 shown in FIG.

  Referring to FIG. 5, serial / parallel conversion circuit 30 includes two flip-flops 31 and 32 connected in cascade, and two flip-flops connected corresponding to the outputs of flip-flops 31 and 32, respectively. 33, 34.

  The serial baseband signal AN input via the input terminal is sampled at the timing of the data rate clock signal T2 supplied from the timing signal generation circuit 20 and held in the flip-flops 31 and 32 for 2 bits. As shown in FIG. 5, 2-bit parallel data (Yk-1, Xk-1) is held and output from the flip-flops 31, 32 in response to the clock signal T2.

  Further, 2-bit parallel data (Yk-1, Xk-1) is sampled at the timing of the clock signal T3 of the symbol period provided from the timing signal generation circuit 20, and is held in each of the flip-flops 33, 34. .

  The flip-flops 33 and 34 output 2-bit parallel data (Yk, Xk) in response to the clock signal T3.

  Referring to FIG. 2 again, parallel 2-bit data (Yk, Xk) is transmitted to mapping circuit 40. The mapping circuit 40 maps 2-bit parallel data according to the clock signal T3 having a symbol period.

  FIG. 6 is a circuit diagram showing a configuration of mapping circuit 40 shown in FIG.

  Referring to FIG. 6, mapping circuit 40 is a part that performs mapping by differentially encoding 2-bit parallel data (Yk, Xk) input from serial / parallel converter circuit 30 of FIG. A parallel register 41, an EXOR circuit G40, an adder 42, EXNOR circuits G41, G42, G44, G45, and a NOT circuit G43 are included.

  The EXOR circuit G40 performs a coincidence comparison of the 2-bit parallel data (Yk, Xk), and outputs “0” (corresponding to “L”) when the two are equal as a coincidence comparison result. 1 ″ (= corresponding to “H”) is output. The coincidence comparison result signal is input to the input A2 of the adder 42.

  Further, (Xk) of the 2-bit parallel data is input to the input A3 of the adder 42. As shown in FIG. 6, the inputs A2 and A3 of the adder 42 and the inputs A1 and A4 to which the power supply voltage and the ground voltage are respectively applied constitute 4-bit data [A4; A1] indicating a phase change.

  The adder 42 adds the phase change indicated by the 2-bit parallel data (Wk, Vk) to the symbol point one symbol before, and derives the symbol point in the current symbol. The symbol points are displayed as 3-bit signals (SM2, SM1, SM0) output from the outputs S1 to S3 of the adder 42.

  The 4-bit parallel register 41 holds a 3-bit signal (SM2, SM1, SM0) indicating a symbol point one symbol before in response to a clock signal T3 having a symbol period. Further, these 3-bit signals are input to the inputs B1 to B3 of the adder 42 at the timing of the current symbol. The inputs B1 to B3 of the adder 42 and the input B4 to which the ground voltage is applied constitute 4-bit data [B4; B1] indicating a symbol point one symbol before.

  The adder 42 outputs the addition result of [A4; A1] and [B4; B1] of the input data to outputs S1 to S4. As shown in FIG. 6, the output S4 indicating the most significant bit of the addition result is not used, and is encoded into 3-bit binary numbers (SM2, SM1, SM0) by the outputs S1 to S3. The 3-bit binary code (SM2, SM1, SM0) is input to the subsequent logic circuits G41 to G45 and held in the 4-bit parallel register 41.

  The EXNOR circuits G41, G42, G44, G45 and the NOT circuit G43 decode the 3-bit binary code (SM2, SM1, SM0) and generate 4-bit symbol mapping data (I1, I0, Q1, Q0). Occur.

  Hereinafter, the operation principle of the mapping circuit 40 in the π / 4 shift QPSK modulation method will be described in detail.

  In the π / 4 shift QPSK modulation system, differential encoding is usually performed in which data is discriminated from the relative phase between consecutive symbols. If the symbol point layout in the π / 4 shift QPSK modulation system is phase-shifted by π / 8, the I-phase and Q-phase data each have a ternary level as shown in FIG. Π / 4 shift QPSK modulation using such differential encoding is generally referred to as π / 4 shift DQPSK modulation.

  FIG. 7 is a diagram showing the arrangement of symbol points by the π / 4 shift DQPSK modulation method.

  Referring to FIG. 7, in π / 4 shift DQPSK modulation, symbol points necessary to represent a phase are displayed in the form of a 3-bit binary code. In the mapping operation shown below, these symbol points are expressed by decimal numbers from “0” to “7” in order to simplify the calculation. That is, the symbol points (000), (001), (010),... (111) are displayed as “0, 1, 2,.

  Further, as the symbol points are represented by decimal numbers, the phase change indicated by the 2-bit parallel data (Yk, Xk) is also converted into decimal notation (ADD-DATA).

  FIG. 8 is a truth table for explaining the mapping operation in the π / 4 shift QPSK modulation method.

  Referring to FIG. 8, 2-bit parallel data (Yk, Xk) is “1” when (0, 0), and “3”, (1, 1) when (1, 0). It is represented by decimal data (hereinafter also referred to as ADD-DATA), such as “7” when “5”, (0, 1). This ADD-DATA is added to “0” to “7” indicating the symbol point one symbol before, and the result is subjected to MOD8 arithmetic processing, whereby “0” to “7” indicating the symbol point of the current symbol. A numerical value can be obtained. The MOD8 calculation process is an operation for obtaining a remainder obtained by dividing a certain numerical value by eight. As described above, in an actual circuit, numerical values “0” to “7” indicating symbol points are represented by 3-bit binary codes (SM2, SM1, SM0). Therefore, the ADD-DATA indicated by “1”, “3”, “5”, and “7” is also binary encoded by the EXOR circuit G40 shown in FIG.

  FIG. 9 is a truth table for explaining a symbol point calculation method in the π / 4 shift QPSK modulation method.

  Referring to FIG. 9, numerical values “0” to “7” indicating the symbol points of the current symbol are represented as 3-bit binary codes (SM2, SM1, SM0). These 3-bit binary codes are further decoded to generate 4-bit symbol mapping data (I1, I0, Q1, Q0). For example, the phase point “0” is represented by a 3-bit binary code (SM2, SM1, SM0) = (0, 0, 0), and this binary code is further converted to 4-bit symbol mapping data (I1). , I0, Q1, Q0) = (1, 1, 1, 0).

  The output symbol mapping data is transmitted to the digital filter 50 of FIG. The digital filter 50 limits the band of the baseband signal given by the symbol mapping data (I1, I0, Q1, Q0) and multiplies it with the carrier signal, and outputs digital data.

  FIG. 10 is a circuit diagram showing a configuration of digital filter 50 shown in FIG. The digital filter 50 of FIG. 10 basically uses a symbol tap ROM (Read Only Memory) division method.

  In the symbol tap ROM division method, the digital filter 50 is composed of a plurality of ROMs, and the multiplication result of the baseband signal and the carrier wave signal band-limited by the Nyquist filter is stored in the corresponding ROM for each symbol. In this method, the outputs of the respective ROMs are added. In the present embodiment, data corresponding to 4 symbol intervals, that is, a total of 9 symbol intervals, are accumulated before and after the central symbol interval, and the baseband signal passing through the Nyquist filter is multiplied by the carrier signal. It is assumed that the obtained data is output.

  Referring to FIG. 10, a digital filter 50 includes a symbol mapping data storage circuit 51, nine ROMs 51A to 51I arranged for each symbol section, and an adder 52 that outputs the sum of the outputs of the ROMs 51A to 51I. Is provided.

  When the symbol mapping data (I1, I0, Q1, Q0) generated in the mapping circuit 40 shown in FIG. 6 is input to the symbol mapping data storage circuit 51, the symbol mapping data storage circuit 51 performs nine symbol intervals at the timing of the clock signal T3 of the symbol period. Accumulate minute data.

  FIG. 11 is a circuit diagram showing a detailed configuration of the symbol mapping data storage circuit 51.

  Referring to FIG. 11, symbol mapping data storage circuit 51 includes four 8-bit shift registers 54A to 54D, four flip-flops 55A to 55D, and ten multiplexers 56 to 65. Hereinafter, when the 8-bit shift registers 54A to 54D and the flip-flops 55A to 55D are collectively referred to, reference numerals 54 and 55 are used, respectively.

  Although not shown, the 8-bit shift register 54 includes eight stages of delay elements connected in cascade. The I-phase symbol mapping data (I1, I0) and the Q-phase symbol mapping data (Q1, Q0) are sequentially input to the 8-bit shift register 54 for each sampling period (corresponding to the symbol period clock signal CLK2). . Each delay element (not shown) sequentially holds input symbol mapping data while being delayed for each sampling period. Of the outputs Q0 to Q7 of each stage of the 8-bit shift register 54, the output Q7 is further output as an output Q delayed in the sampling period in the cascaded flip-flop 55. That is, the 8-bit shift register 54 and the flip-flop 55 constitute a nine-stage delay element. The outputs Q0 to Q7, Q of each stage form nine tap outputs of the digital filter 50, as will be described later.

  The outputs Q0 to Q7 and Q of the 8-bit shift register 54 and the flip-flop 55 are divided and given to five multiplexers 56 to 60 or 61 to 65. Specifically, out of the outputs Q0 to Q7 of the 8-bit shift register 54A that holds the I-phase symbol mapping data I1, the outputs Q0 and Q1 are input to the inputs A0 and B0 of the multiplexer 56, respectively. The outputs Q2 and Q3 are input to the inputs A0 and B0 of the multiplexer 57. The outputs Q4 and Q5 are input to the inputs A0 and B0 of the multiplexer 58. The outputs Q6 and Q7 are given to the inputs A0 and B0 of the multiplexer 59. The output Q of the flip-flop 55A is delayed by the sampling period and input to the input A0 of the multiplexer 60.

  Similarly, of the outputs Q0 to Q7 of the 8-bit shift register 54B that holds the Q-phase symbol mapping data Q1, the outputs Q0 and Q1 are input to the inputs A1 and B1 of the multiplexer 56, respectively. The outputs Q2 and Q3 are input to the inputs A1 and B1 of the multiplexer 57. The outputs Q4 and Q5 are input to the inputs A1 and B1 of the multiplexer 58. The outputs Q6 and Q7 are given to the inputs A1 and B1 of the multiplexer 59. The output Q of the flip-flop 55B is delayed by the sampling period and input to the input A1 of the multiplexer 60.

  As shown in FIG. 11, the multiplexers 56 to 65 receive outputs Q0 to Q7 at inputs (A0, A1, B0, B1) and receive a clock signal T6 as a control input SE for selecting an output. Note that the clock signal T6 is generated by the timing signal generation circuit 20 described above and passes between “1” and “0” at twice the speed of the least significant bit T1-0 of the time information T1 [0: 3]. It is a transition signal.

  In response to the clock signal T6, the multiplexers 56 to 65 selectively output 2 bits of the 4-bit inputs (A0, A1, B0, B1) as outputs A and B. Specifically, when the clock signal T6 is “0”, the multiplexers 56 to 65 select the input (A0, B0) and output it to the outputs A, B. On the other hand, when the clock signal T6 is “1”, the multiplexers 56 to 65 select the inputs (A1, B1) and output them to the outputs A, B.

  When the above operation is examined with respect to the multiplexers 56 to 60 that receive the outputs Q0 to Q7 from the 8-bit shift registers 54A and 54B, when the clock signal T6 is "0", the inputs (A0, Outputs Q0 to Q7 based on the I-phase symbol mapping data I1 input to B0) are selected and output. Regarding the multiplexer 60, since the input B0 is set to the ground potential, the output Q7 given to the input A0 is output to the output A.

  Therefore, when the clock signal T6 is “0”, the data for nine symbol sections of the I-phase mapping data I1 are selected from the multiplexers 56 to 60, and as shown in FIG. 11, the data (M41, M31, M21, M11, PM01, P11, P21, P31, P41).

  On the other hand, when the clock signal T6 is “1”, outputs Q0 to Q7 based on the Q-phase symbol mapping data Q1 input to the inputs (A1, B1) of the multiplexers 56 to 60 are selected and output. As for the multiplexer 60, since the input B1 is set to the ground potential, the output Q7 given to the input A1 is output to the output A.

  Therefore, when the clock signal T6 is “1”, the data for nine symbol sections of the Q-phase symbol mapping data Q1 are selected from the multiplexers 56 to 60, and the data (M41, M31) are selected as shown in FIG. , M21, M11, PM01, P11, P21, P31, P41).

  Similarly for the I-phase symbol mapping data I0 and the Q-phase symbol mapping data Q0, the data Q0 to Q7 accumulated for each sampling period CLK2 by the 8-bit shift registers 54C and 54D and the flip-flops 55C and 55D. Are input to the inputs (A0, A1, B0, B1) of the multiplexers 61-65.

  The multiplexers 61 to 65 alternately select data for 9 symbol sections of the I-phase symbol mapping data I1 and data for 9 symbol sections of the Q-phase symbol mapping data Q1, according to the clock signal T6, Output as data (M40, M30, M20, M10, PM00, P10, P20, P30, P40).

  As described above, the I-phase symbol mapping data (I0, I1) and the Q-phase symbol mapping data (Q0, Q1) are alternately output in response to the clock signal T6. By adopting such a configuration, one digital filter can be used in a time-division multiplexed manner, so that it is not necessary to provide a digital filter for each of the I phase and the Q phase, and the circuit configuration is simplified. Can do.

  In general, in digital wireless communication, a digital filter is used to narrow the band of digital data from the viewpoint of effective use of radio waves, and there is no intersymbol interference as a digital filter that realizes this narrow band. A known Nyquist filter having transmission characteristics (Nyquist characteristics) is used.

  The basic processing of the Nyquist filter is as follows. That is, a tap coefficient for each sampling point of a desired impulse response waveform with respect to an impulse input is held, and input digital data is sequentially held in a shift register having a predetermined number of taps, and each tap output is multiplied by the corresponding tap coefficient. To obtain the filter output.

  FIG. 12 is an impulse response waveform of a digital filter that realizes the Nyquist characteristic.

  Referring to FIG. 12, the impulse response waveform has a waveform that rapidly attenuates around the main lobe. The impulse response waveform is discretely quantized at sampling points corresponding to the number of tap outputs of the digital filter at predetermined sampling (symbol) intervals. The widening quantized at each sampling point corresponds to the aforementioned tap coefficient.

  In the symbol tap ROM division method employed in the present embodiment, for each sampling point, a band-limited baseband signal obtained by multiplying a tap output and a corresponding tap coefficient is multiplied by a carrier signal. Filter output data is obtained, and the filter output data is stored in advance in a plurality of ROMs arranged for each tap output. The filter output can be obtained by reading the multiplication result for each ROM using the input digital data as an address and adding them. Note that the data length of the multiplication result stored in each ROM differs depending on the ROM depending on the dynamic range of each symbol section of the impulse response waveform of the Nyquist filter with a roll-off factor α = 0.5.

  Referring to FIG. 10 again, the data for nine symbol sections of the I-phase and Q-phase symbol mapping data stored in symbol mapping data storage circuit 51 is divided and input into nine ROMs 51A to 51I. The total of nine ROMs 51A to 51I corresponds to the total number of tap outputs in the digital filter 50 described above.

  When the clock signal T6 is “0”, the data for nine symbol sections of the I-phase symbol mapping data (I0, I1) is supplied to the corresponding ROMs 51A to 51I for each symbol section. On the other hand, when the clock signal T6 is “1”, the data for nine symbol sections of the Q-phase symbol mapping data (Q0, Q1) is supplied to the corresponding ROMs 51A to 51I for each symbol section.

  The ROMs 51A to 51I use the 4-bit time information T1 [0: 3] given from the timing signal generation circuit 20 of FIG. 3 and the 2-bit symbol mapping data of the corresponding symbol section as address inputs A0 to A5. In each of the ROMs 51A to 51I, filter output data having a predetermined data length is read as symbol data D in response to address inputs A0 to A5.

  Specifically, in consideration of the dynamic range of each symbol interval, the ROM 51A corresponding to the symbol interval of the accumulation number -4 and the ROM 51I corresponding to the symbol interval of the accumulation number 4 each have symbol data having a data length of 3 bits. D0 to D2 are output. Similarly, symbol data D0 to D3 having a data length of 4 bits are output from the ROM 51B corresponding to the symbol interval of accumulation number -3 and the ROM 51H corresponding to the symbol interval of accumulation number 3, respectively. Further, symbol data D0 to D5 having a data length of 6 bits are output from the ROM 51C corresponding to the symbol interval of the accumulation number −2 and the ROM 51G corresponding to the symbol interval of the accumulation number 2 respectively. Further, the ROM 51D corresponding to the symbol interval of the accumulation number -1 and the ROM 51F corresponding to the symbol interval of the accumulation number 1 respectively output symbol data D0 to D8 having a data length of 9 bits. Finally, symbol data D0 to D9 having a data length of 10 bits are output from the ROM 51E corresponding to the symbol interval of 0 stored.

  These filter output data are added by the adder 52 and converted into 10-bit digital signals DA0 to DA9. The digital signals DA0 to DA9 are input to the multiplier 70 as shown in FIG. In addition to the digital signals DA0 to DA9, the multiplier 70 receives ramp waveform data stored in the ramp waveform storage unit 100.

  FIG. 13 is a block diagram showing the configuration of the ramp waveform storage unit 100 shown in FIG.

  Referring to FIG. 13, ramp waveform storage unit 100 includes a ROM 110 for storing ramp waveform data, an AND circuit G100, and a selector circuit 120.

  The ROM 110 receives the time information T1 [0: 3] generated by the timing generation circuit 20, the detection signal UP / DOWN1 generated by the ramp section detection circuit 21, and the mode selection signal NOR / SHT output by the CPU 10 as an address input A. The ramp waveform data is stored as [0: 5].

  FIG. 14 is a schematic diagram for explaining the ramp waveform data stored in the ROM 110.

  Referring to FIG. 14, the ramp waveform data storage area in the ramp processing section includes an area for storing ramp waveform data when the lamp length of the ramp processing section is in the normal mode (2 symbols), and a short mode (3/2). Symbol) and the area for storing the ramp waveform data. In the normal mode and short mode storage areas, rising ramp waveform data and falling ramp waveform data are stored, respectively.

  Here, the ramp waveform data stored in the ramp waveform data storage area in the ramp processing section will be described. As shown in FIG. 1, the ramp waveform data is a gate signal indicating the gain of the transmission signal, and increases or decreases smoothly in the ramp processing section. For example, a function such as Expression (1) is used as the rising ramp waveform data.

  Further, as the falling ramp waveform data, a function as shown in Expression (2) is used.

  In Equations (1) and (2), N is a sampling point with an oversampling period that is eight times the symbol period, and the total number is 16 in the 2-symbol ramp processing section. Further, n is a natural number equal to or less than N given by the time information T1 [0: 3], and takes any value from “0” to “15”.

  In this way, the ramp waveform data has a waveform that smoothly increases or decreases between “0” and “1” using a signal period of two symbols in the normal mode. Here, in the short mode in which the ramp processing section is 3/2 symbols, N is 12 (= 16 × 3/4) and n is a natural number of 0 to 12 in the functions shown in the equations (1) and (2). And As a result, the ramp waveform data has a waveform that transitions between “0” and “1” using a signal interval of 3/2 symbols in the short mode. For N = 13, 14, and 15 given by the time information T1 [0: 3], the ramp waveform data may be fixed to “1”.

  Next, data corresponding to the normal transmission section stored in the ramp waveform storage unit 100 will be described. The stored data is the level of the gate signal in the normal transmission interval, and is fixed to “1”. This data “1” is always output to the subsequent selector circuit 120 regardless of the address input A [0: 5].

  Referring to FIG. 13 again, ramp waveform data D corresponding to time information T1 [0: 3], detection signal UP / DOWN1, and mode selection signal NOR / SHT is read from ROM 110 from ROM 110. , Input to the first input terminal of the selector circuit 120. In parallel with this, data “1” is always input to the second input terminal of the selector circuit 120.

  More specifically, for example, when the detection signal UP / DOWN1 is “0” (corresponding to the detection target symbol being in the rising ramp processing interval or the normal transmission interval), the mode selection signal NOR / SHT is “0” (normal). Corresponding to the mode), the rising ramp waveform data D in the normal mode is read from the storage area of the ramp processing section according to the time information T1 [0: 3]. The rising ramp waveform data D is input to the selector circuit 120. On the other hand, when the mode selection signal NOR / SHT is “1” (corresponding to the short mode), the rising ramp waveform data of the short mode is read from the storage area of the ramp processing section according to the time information T1 [0: 3]. .

  When the data “1” and the rising ramp waveform data D are input, the selector circuit 120 selects and outputs either one according to the control signal. The control signal is a signal output as a logical product operation result of the detection signals UP / DOWN [0: 1] in the AND circuit G100. That is, the control signal becomes “0” according to (0, 1) and (1, 0) in the rising ramp processing interval and the falling ramp processing interval, and according to (0, 0) in the normal transmission interval. “1”.

  Therefore, when the control signal is “0”, the selector circuit 120 selects and outputs the corresponding rising ramp waveform data D. On the other hand, when the control signal is “1”, selector circuit 120 selects and outputs data “1” representing the normal transmission interval. The output data of the selector circuit 120 is given to the multiplier 70 shown in FIG.

  Similarly, when the detection signal UP / DOWN0 is “1” (corresponding to the detection target symbol being in the falling ramp processing section), the mode selection signal NOR / SHT is “0” (corresponding to the normal mode). Thus, the falling ramp waveform data D in the normal mode is read from the storage area of the ramp processing section according to the time information T1 [0: 3]. On the other hand, when the mode selection signal NOR / SHT is “1” (corresponding to the short mode), the rising ramp waveform data of the short mode is read from the storage area of the ramp processing section according to the time information T1 [0: 3]. . The read falling ramp waveform data D is input to the selector circuit 120.

  The selector circuit 120 selects and outputs the corresponding falling ramp waveform data D when the control signal is “0”. On the other hand, when the control signal is “1”, data “1” representing the normal transmission interval is selected and output.

  In this way, ramp waveform data corresponding to the ramp processing interval and data “1” corresponding to the normal transmission interval are sequentially read from the ramp waveform storage unit 100 for each sampling point.

  Referring to FIG. 2 again, the band-limited digital signal DA [9: 0] output from the digital filter 50 and the ramp waveform data output from the ramp waveform storage unit 100 are multiplied by the multiplier 70. The The multiplier 70 outputs a transmission burst signal. In the transmission burst signal, in the normal mode, a ramp processing period of 2 symbols arranged at the beginning and end of one slot is set as a transient response period. On the other hand, in the short mode, 3/2 symbols in the ramp processing interval are set as transient response periods.

  When the output signal of the multiplier 70 is converted into an analog signal by the digital / analog converter 80, the sampling noise is removed by the LPF 90 and output as a modulated signal S (t).

  In this embodiment, the configuration of the digital modulator has been described with the modulation method being a π / 4 shift QPSK modulation method. However, the present invention can also be applied to a modulation method having a large number of multiple values such as 16QAM (Quadrature Amplitude Modulation). Is clear.

  The transient response period of the burst signal is selected between two normal symbols and a shorter symbol length in accordance with the selection signal from the CPU. However, a configuration in which the burst signal is fixed to a short symbol length may be used. . Even in this configuration, the same effect as in the present embodiment can be obtained.

  Further, in the present embodiment, as a digital filter mounted on the digital modulator, a ROM type filter that calculates a filter output in advance and stores it in a ROM and obtains an output waveform by using input data as an address is employed. A software filter realized by software processing using a digital signal processor (DSP) and a transversal filter configured by hardware using a shift register, a multiplier, and an adder may be employed.

  As described above, according to the embodiment of the present invention, in the ramp processing applied to the falling and falling of the burst transmission, the transient response period of the burst signal is added to two symbols that are normal ramp processing sections. Since it can be set to a shorter symbol, the trade-off between transmission spurious generation and modulation accuracy can be improved.

  Furthermore, since the conventional digital modulator can be configured with only a slight change, it can be easily realized without increasing the circuit scale and complication.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows notionally the principle of operation of this invention. It is a block diagram which shows the structure of the digital modulator according to embodiment of this invention. FIG. 3 is a circuit diagram showing a configuration of a timing signal generation circuit 20 shown in FIG. 2. FIG. 4 is an operation waveform diagram for explaining various signals generated by the timing signal generation circuit 20 of FIG. 3. FIG. 3 is a circuit diagram showing a configuration of a serial / parallel conversion circuit 30 shown in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a mapping circuit 40 shown in FIG. 2. It is a figure which shows arrangement | positioning of the symbol point by (pi) / 4 shift DQPSK modulation system. It is a truth table for demonstrating the mapping operation | movement in a (pi) / 4 shift QPSK modulation system. It is a truth table for demonstrating the calculation method of the symbol point in a pi / 4 shift QPSK modulation system. FIG. 3 is a circuit diagram showing a configuration of a digital filter 50 shown in FIG. 2. 3 is a circuit diagram showing a detailed configuration of a symbol mapping data storage circuit 51. FIG. It is an impulse response waveform of a digital filter realizing Nyquist characteristics. FIG. 3 is a block diagram illustrating a configuration of a ramp waveform storage unit 100 illustrated in FIG. 2. It is the schematic for demonstrating the ramp waveform data memorize | stored in ROM110. It is a figure which shows the transmission timing of 4 channel multiplexing TDMA / TDD system. It is a figure for demonstrating an example of the allocation of the ramp period in 1 transmission slot, and the ramp waveform produced | generated. It is a vector diagram for demonstrating modulation accuracy.

Explanation of symbols

  10 CPU, 20 timing signal generation circuit, 21 ramp section detection circuit, 22 and 25 counter circuit, 26 to 29 decoder, 30 serial / parallel conversion circuit, 31 to 34, 55A to 55D flip-flop, 40 mapping circuit, 41 4 bits Parallel register, 42 adder, 50 digital filter, 51 symbol mapping data storage circuit, 51A-51I, 54A-54D 8-bit shift register, 56-65 multiplexer, 70 multiplier, 80 digital / analog converter, 90 LPF, 100 Ramp waveform storage unit, 110 ROM, 120 selector circuit, G20, G43 NOT circuit, G21, G22 OR circuit, G40 EXOR circuit, G41, G42, G44, G45 EXNOR circuit, G100 AND Road.

Claims (4)

Upper processor means for generating a digital baseband signal;
Means for serial-parallel conversion of the baseband signal for each successive plurality of bits;
Mapping means for uniquely giving symbol mapping data composed of orthogonal in-phase and orthogonal phase for each of a plurality of consecutive bits;
Digital filter means for band-limiting the in-phase and quadrature-phase symbol mapping data, performing multiplication with a carrier signal in a time division multiplex manner, and generating a modulation signal;
Means for detecting timings of burst rising intervals of the modulated signal, normal transmission intervals for transmitting the modulated signal, and burst falling intervals of the modulated signal;
Means for storing a ramp waveform in the burst rising period and the burst falling period;
Means for multiplying the modulation signal by the ramp waveform in the burst rising interval and the burst falling interval;
Means for converting the output of the multiplication means into an analog modulation signal,
The ramp waveform storage means provides a first ramp for providing a first transient response period having a symbol length within the range of the burst rising period and the burst falling period with respect to the burst rising period and the burst falling period. Storing a waveform and a second ramp waveform that provides a second transient response period within a range of the burst rising period and burst falling period and having a symbol length different from the first transient response period. ,
The upper processor means further includes means for generating a selection signal for selecting one of the first and second transient response periods;
The ramp waveform storage means selectively outputs the first and second ramp waveforms according to a detection signal from the timing detection means and the selection signal. The ramp waveform storage means further includes means for outputting a constant value corresponding to the gain of the modulation signal for the normal transmission section,
In response to the detection signal indicating the normal transmission interval, selectively output the constant value,
The digital modulator according to claim 1, wherein the multiplication unit multiplies the constant value and the modulation signal in the normal transmission section.   The first transient response period is equal to a known ramp signal interval provided at the beginning and end of the modulation signal, and the second transient response period is shorter than the known ramp signal interval. The digital modulator according to claim 2.   The timing detection unit includes a counting unit that counts a symbol length of the modulation signal, and detects timings of the burst rising period, the burst falling period, and the normal transmission period based on a count value of the counting unit. The digital modulator according to claim 3.

Images