JP2005108487A - Manufacturing method of field electron emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a field electron emitting device for field emission display having high electron emitting efficiency, without the waste of a carbon nano-tube constructing an electron emission part due to oxidation, at high etching speed, and without the adhesion of any by-product of etching to a space of the electron emission part, with high productivity. <P>SOLUTION: The manufacturing method of the field electron emitting device comprises a process of forming the electron emission part containing a carbon nano-tube on the surface of a cathode electrode formed on a substrate; a process of forming an insulation layer on the exposed face of the cathode electrode, the electron emission part, and the substrate by drying and solidifying a silicon ladder polymer; a process of forming a gate electrode formed by exposing a part of the upper face of the insulation layer on the insulation layer; a process of removing the surface of the insulation layer from the exposed part of the insulation layer; and a process of forming an opening with a part of the upper face of the electron emission part as a whole part by wet-etching a part of the insulation layer formed by removing the surface from the exposed part of the insulation layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a field electron emission device, and more particularly to a method for manufacturing a field electron emission device for a field emission display (hereinafter referred to as FED).

  A field electron emission device for an FED includes an electron emission including a glass substrate, a cathode electrode formed on the upper surface of the glass substrate, and a carbon nanotube (hereinafter referred to as CNT) formed on a part of the upper surface of the cathode electrode. , An insulating layer having a flat upper surface formed on the upper surface of the cathode electrode around the electron emitting portion and the peripheral portion of the electron emitting portion, and a gate electrode formed on the upper surface of the insulating layer.

  The insulating layer that supports the gate electrode is resistant to heat treatment exposed in the FED manufacturing process, has low thermal shrinkage during formation of the insulating layer, is less degassed because it is used in vacuum, Characteristics such as excellent adhesion are required. Silicone ladder polymers have been disclosed as insulating materials with high heat resistance, low shrinkage, low degassing properties, and high adhesion that satisfy these requirements (see, for example, Patent Document 1).

  The insulating layer is provided with a space for moving electrons emitted from the electron emission portion. That is, in order to manufacture a field electron emission device for FED, processing for providing the space in the insulating layer is necessary, and a dry etching method such as reactive ion etching is disclosed as the processing method. (For example, refer nonpatent literature 1).

JP-A-8-245792 (second page)

Proceedings of the 50th Joint Conference on Applied Physics (Page 1026), March 2003

  Reactive ion etching is used in the process of providing a space in the insulating layer of the silicone ladder polymer in the manufacture of a field electron emission device for FED. Since the dry etching gas used for reactive ion etching is a mixed gas of fluorine-based gas and oxygen, the CNTs constituting the electron emission portion are oxidized and consumed by oxygen during etching. That is, there has been a problem that a field electron emission device for FED having excellent electron emission efficiency due to damaged CNTs cannot be obtained.

  In addition, when processing an insulating layer made of a silicone ladder polymer by dry etching, the etching rate is slow and it takes a long time to process, and by-products adhere to the inner wall of the space during dry etching, and these deposits are removed. There is a problem that productivity is low.

  The present invention has been made in order to solve the above-described problems, and the object thereof is to eliminate the oxidization consumption of the CNTs constituting the electron emission portion, and to provide a high etching rate and a space portion on the electron emission portion. It is another object of the present invention to provide a manufacturing method capable of manufacturing a field electron emission device for FED having high electron emission efficiency without adhesion of etching by-products with high productivity.

  The method of manufacturing a field electron emission device according to the present invention includes a step of forming a cathode electrode on a substrate, a step of forming an electron emission portion containing CNT on the cathode electrode, an exposed surface of the cathode electrode, A process of forming an insulating layer by drying and solidifying the silicone ladder polymer after applying a liquid or paste-like silicone ladder polymer on the exposed surface of the electron emission portion and the exposed surface of the substrate; and A step of forming a gate electrode on the insulating layer; a step of forming a resist film on the gate electrode; a step of exposing / developing the resist film; and the gate electrode using the developed resist film pattern as a mask. Etching to expose a part of the upper surface of the insulating layer, removing the surface layer portion of the insulating layer from the exposed portion of the insulating layer, A step of performing wet etching on the insulating layer from which the surface layer portion has been removed from the exposed portion of the insulating layer to form an opening having a part of the upper surface of the electron emission portion as a whole of the bottom surface thereof. is there.

  According to the method of manufacturing a field electron emission device of the present invention, the surface layer of the exposed portion of the insulating layer where the gate electrode is exposed from the etched portion is removed, and then the insulating layer from which the surface layer has been removed is wet-etched. An opening having a part of the upper surface of the part as the entire bottom surface is formed, there is no oxidation consumption of the CNT constituting the electron emission part, and the etching rate of the insulating layer is high, and the space above the electron emission part A field electron emission device for FED with high electron emission efficiency without adhesion of etching by-products to the part can be manufactured with high productivity.

Embodiment FIG. 1 is a cross-sectional view illustrating the structure of a field electron emission device for FED.

  As shown in FIG. 1, a field electrode emission device for FED 10 has a cathode electrode 2 formed on one surface of a substrate 1. An electron emission portion 3 containing CNT is provided on a part of the surface of the cathode electrode 2 facing the surface bonded to the substrate 1. An insulating layer 4 of a ladder silicone polymer is provided on the surface of the cathode electrode 2 around the electron emitting portion 3 and on the side surface and the peripheral portion of the electron emitting portion 3, and the electron emitting portion 3 is provided on the insulating layer 4. A space 8 (hereinafter referred to as an electron emission opening) 8 in which electrons emitted from the substrate move is provided. A gate electrode 5 is provided on the surface of the insulating layer 4 that faces the surface that is bonded to the cathode electrode 2.

  In the manufacture of the field electron emission device 10 for FED shown in FIG. 1, the formation of the electron emission opening 8 by the conventional dry etching method has the above-mentioned problems. As a method for forming the opening 8 for the substrate, a wet etching method was used in which a silicone ladder polymer having a molecular weight adjusted was used for the insulating layer 4 and the insulating layer 4 was etched with a solvent.

  However, a gate electrode 5 is provided on the surface of the insulating layer 4, and an opening is provided in the gate electrode 5 by a conventional photolithography method. Using this gate electrode 5 as a mask, for example, anisole and xylene (2: 1 by weight). However, the insulating layer 4 could not be etched at all. As a result of diligently elucidating the cause, the inventors have formed the gate electrode 5 by vacuum deposition or sputtering of metal, so that the surface of the insulating layer 4 in contact with the gate electrode 5 and its surface as shown in FIG. It has been clarified that the altered portion 20 of the insulating layer 4 is formed in the nearby insulating layer. Then, by providing the step of removing the altered portion 20, it was found that the insulating layer 4 can be wet-etched and the electron emission opening 8 can be formed, and the present invention has been completed.

Embodiment 1 FIG.
FIG. 3 is a diagram for explaining a manufacturing process of the field electron emission device for FED in the first embodiment.

  First, the cathode electrode 2 of a transparent conductive film is formed on the upper surface of the glass substrate 1 by using a sputtering method (FIG. 3A).

  Next, a paste containing CNT powder is applied on the upper surface of the cathode electrode 2 by screen printing, and the resin in the paste is thermally decomposed to form the electron emission portion 3. At that time, the electron emission portion is not provided over the entire upper surface of the cathode electrode 2 but only on the region corresponding to the region immediately below the electron emission opening 8 and on the peripheral region within the upper surface of the cathode electrode 2. 3 is formed (FIG. 3B).

  Next, a liquid silicone ladder polymer is applied on the exposed surface of the cathode electrode 2, the exposed surface of the electron emission portion 3, and the exposed surface (not shown) of the substrate 1, and then the silicone ladder polymer is dried. By doing so, the insulating layer 4 having a thickness of, for example, about 10 μm is formed in which the electron emitting portion 3 is buried (FIG. 3C).

  Next, an Al film having a film thickness of, for example, about 0.3 μm is formed on the upper surface 4 of the insulating layer by using a vacuum deposition method to form a metal film to be the gate electrode 5 (FIG. 3D). .

  Next, a resist film is formed on the entire surface of the gate electrode 5. For example, a resist film is applied by spin coating using a positive resist solution, and after drying, a resist film pattern 6 having a pattern corresponding to the first electron emission opening 8a is formed by photolithography (see FIG. FIG. 3 (e)).

  Next, the gate electrode 5 is etched using the developed resist film pattern 6 as a mask to form a first electron emission opening 8a in the gate electrode 5 to expose a part of the upper surface of the insulating layer (FIG. 3). (F)).

  Next, after removing the resist film pattern 6 with a resist stripping solution, the exposed upper surface of the insulating layer is subjected to any one of a treatment with buffered hydrofluoric acid, a reactive ion etching treatment, and an ion beam etching treatment. By processing, for example, about 1 μm of the upper surface layer portion of the insulating layer 4 is removed, and the insulating layer altered portion 20 formed on the surface layer of the upper surface of the insulating layer when the gate electrode is formed is removed (FIG. 3G). . If the insulating layer altered portion 20 can be removed and the electron emitting portion 3 is not exposed, the thickness for removing the surface layer portion of the insulating layer 4 is not limited to 1 μm.

  Next, the insulating layer 4 exposed from the first electron emission opening 8a from which the altered portion 20 of the surface layer has been removed is about 100 to 180 in, for example, a mixed solution of anisole and xylene (2: 1 by weight). Immersion for 2 seconds, wet etching is performed, and a second electron emission opening 8b is formed in which a part of the upper surface of the electron emission portion 3 is the entire bottom surface. That is, an electron emission opening 8 composed of the first electron emission opening 8a and the second electron emission opening 8b is formed (FIG. 3H).

  Examples of the silicone ladder polymer used in this embodiment include polyphenylsilsesoxane (hereinafter referred to as PPSQ) having a phenyl group, and polyphenylvinylsilsesoxane (hereinafter referred to as PPSQ) having a vinyl group in a part of the side chain. , PVSQ), and polymethylsilsesoxane (hereinafter referred to as PMSQ) in which all of the side chains are methyl groups.

  As the PPSQ, those having a weight average molecular weight in the range of 10,000 to 200,000 are used. When the weight average molecular weight is less than 10,000, a film having a thickness required for the insulating layer 4, for example, about 10 μm cannot be formed. Further, when the weight average molecular weight is larger than 200,000, the residue of the insulating layer remains in wet etching for a desired time, and it takes a long time to form the opening 8 for electron emission.

  As the PVSQ, those having a weight average molecular weight in the range of 10,000 to 300,000 are used. When the weight average molecular weight is less than 10,000, a film having a thickness required for the insulating layer 4, for example, about 10 μm cannot be formed. Further, when the weight average molecular weight is larger than 300,000, the residue of the insulating layer remains in wet etching for a desired time, and it takes a long time to form the opening 8 for electron emission.

  As the PMSQ, those having a weight average molecular weight in the range of 20,000 to 400,000 are used, and when the weight average molecular weight is less than 20,000, a film having a thickness required for the insulating layer 4, for example, about 10 μm cannot be formed. In addition, when the weight average molecular weight is larger than 400,000, a residue of the insulating layer remains by wet etching for a desired time, and it takes a long time to form the opening 8 for electron emission.

  In the present embodiment, the surface layer of the insulating layer 4 exposed from the first electron emission opening 8a of the gate electrode 5 is treated with buffered hydrofluoric acid, reactive ion etching, or ion beam etching. The insulating layer altered portion 20 formed in the surface layer on the upper surface of the insulating layer was removed by performing any of the treatments, and was exposed from the first electron emission opening 8a of the gate electrode 5 The wet etching of the insulating layer 4 becomes possible. The second electron emission opening 8b is formed by wet etching the insulating layer 4 and the CNT of the electron emission part 3 is not oxidized and consumed. Further, since no etching by-product adheres to the electron emission opening 8, a step of removing it is unnecessary. Further, since the etching rate is high, the electron emission opening 8 can be formed in a short time.

  Next, the present invention will be described in more detail with reference to examples.

Example 1.
As shown in FIG. 3A, first, a film of a cathode electrode 2 made of, for example, an ITO film which is a transparent conductive film is formed on the upper surface of the glass substrate 1 by a sputtering method. The film thickness is, for example, 0.3 μm.

  Next, as shown in FIG. 3B, the electron emission portion 3 is formed on the upper surface of the cathode electrode 2. At that time, the electron emission portion is not provided over the entire upper surface of the cathode electrode 2 but only on the region corresponding to the region immediately below the electron emission opening 8 and on the peripheral region within the upper surface of the cathode electrode 2. 3 is formed.

Specifically, the electron emission portion 3 is formed by screen printing using a paste containing CNT powder. At this time, the average particle diameter of the CNT powder is 1.5 μm, and the composition ratio of the paste is CNT: ethyl cellulose: butyl carbitol: butyl carbitol acetate = 4: 13: 42: 41 in weight ratio. As a screen printing mask, a 250 mesh screen is used.
After printing the electron emission part 3, the part 3 is dried at 150 ° C., and then the part 3 is baked for 10 minutes at 450 ° C. in the atmosphere to burn and decompose the resin and solvent in the part 3.

  Next, as shown in FIG. 3C, a liquid silicone ladder polymer is applied on the exposed surface of the cathode electrode 2, the exposed surface of the electron emission portion 3, and the exposed surface (not shown) of the substrate 1. Then, the insulating layer 4 having a film thickness of about 10 μm is formed by drying the silicone ladder polymer.

Specifically, as a silicone ladder polymer, a PPSQ having a weight average molecular weight of 200,000 (which is liquid in this state) is uniformly applied on the exposed surface using a table coater, and a flat surface without unevenness is applied. A coating layer of PPSQ is formed.
Next, the substrate 1 on which the insulating layer 4 as a liquid PPSQ layer having a flat upper surface is formed is preliminarily dried at a temperature of 150 ° C. using a hot plate, and further, at a temperature of 250 ° C. using an oven. The PPSQ solid insulating layer 4 is obtained by performing a drying process for 1 hour. In the drying process at 250 ° C., PPSQ does not undergo a dehydration condensation reaction of silanol groups at the molecular terminals, and the PPSQ solid insulating layer 4 has solubility in a solvent.
In addition, as a result of the drying process, the film thickness of the insulating layer becomes about 10 μm. Moreover, since the insulating layer 4 is solidified from a liquid having a flat upper surface while the flatness of the upper surface is maintained, the upper surface of the insulating layer after drying also has a flat surface with no unevenness. It has become.

  Next, as shown in FIG. 3D, a metal film to be the gate electrode 5 is formed on the upper surface of the insulating layer. For example, an Al film is deposited using a vacuum deposition method. The film thickness is 0.3 μm.

Next, as shown in FIG. 3E, a resist film is entirely formed on the gate electrode 5. For example, a positive resist solution is applied by spin coating to form a resist film. Thereafter, the resist film is dried.
After drying the resist film, the resist film is exposed using an exposure mask (not shown) having a circular transmission portion corresponding to the cross-sectional shape of the first electron emission opening 8a. Further, development is performed with an alkaline developer, and the exposed resist film is removed. Thus, a resist film pattern 6 having a pattern corresponding to the first electron emission opening 8a is formed.

  Next, as shown in FIG. 3F, the gate electrode 5 is etched using the developed resist film pattern 6 as a mask to expose a part of the upper surface of the insulating layer. That is, the Al film located immediately below the circular opening in the resist film pattern 6 is etched, and the first electron penetrating the portion is formed in the portion of the gate electrode 5 located immediately above the upper surface of the electron emission portion 3. A discharge opening 8a is formed. Etching of the Al film is performed using, for example, a phosphoric acid-based etching solution having a liquid temperature of 40 ° C.

  Next, as shown in FIG. 3G, after the resist film pattern 6 is removed with a resist stripper containing organic amine as a main component, the insulating layer exposed to the first electron emission opening 8a. About 1 μm of the upper surface portion of the insulating layer 4 was removed by buffered hydrofluoric acid treatment by immersing the upper surface in a 3% HF aqueous solution at 25 ° C. for 10 minutes, and formed on the upper surface of the insulating layer when forming the gate electrode. The insulating layer altered portion 20 is removed.

  Next, as shown in FIG. 3 (h), the insulating layer 4 exposed in the first electron emission opening 8a from which the altered portion 20 of the surface layer has been removed is mixed with a mixed solution (by weight ratio) of anisole and xylene. 2: 1) is immersed for 110 seconds, and wet etching is performed to form a second electron emission opening 8b in which a part of the upper surface of the electron emission portion 3 is the entire bottom surface.

  Regarding the field electron emission device for FED provided with the electron emission opening 8 composed of the first electron emission opening 8a and the second electron emission opening 8b thus obtained, the electron emission It was observed using a microscope whether the insulating layer 4 remained in the opening 8 for use, whether or not etching by-products were attached to the opening 8 for electron emission, or whether CNT in the electron emission 3 was consumed. . The observation results are shown in Table 1.

Examples 2-6.
A field electron emission device for FED was obtained in the same manner as in Example 1 except that a silicone ladder polymer having the type and weight average molecular weight shown in Examples 2 to 6 in Table 1 was used as the insulating layer 4. About the obtained field electron emission device for FED, it carried out similarly to Example 1, and observed the opening part 8 and the electron emission part 3 for electron emission. The observer results are shown in Table 1.

Example 7.
Removal of about 1 μm from the upper surface of the insulating layer exposed to the first electron emission opening 8a, that is, removal of the insulating layer altered portion 20 was performed by reactive etching using a mixed gas of CF ₄ and O _2. In the same manner as in Example 1, a field electron emission device for FED was obtained. The reactive etching conditions are CF ₄ gas flow rate of 100 sccm, O ₂ gas flow rate of 25 sccm, gas pressure of 100 mTorr, RF power of 300 W, and etching time of 3 minutes. For the obtained field electron emission device for FED, the electron emission opening 8 and the electron emission portion 3 were observed in the same manner as in Example 1, and the observation results are shown in Table 1.

Example 8.
The electric field for FED is the same as that of Example 1 except that the removal of about 1 μm of the upper surface of the insulating layer exposed to the first electron emission opening 8a, that is, the removal of the insulating layer altered portion 20 is performed by ion beam etching. An electron emission device was obtained. The ion beam etching conditions are a shilling angle of 45 °, a gas flow rate of 8 sccm, a pressure in the chamber of 0.03 Pa, an output of 600 V / 240 mA, a deceleration voltage of −200 V, and an etching time of 5 minutes. For the obtained field electron emission device for FED, the electron emission opening 8 and the electron emission portion 3 were observed in the same manner as in Example 1, and the observation results are also shown in Table 1.

Example 9.
FED field electron emission device in the same manner as in Example 1 except that a mixed solution of cyclohexanone and diethylbenzene (2: 1 by weight) was used to form the second electron emission opening 8b by wet etching. Got. For the obtained field electron emission device for FED, the electron emission opening 8 and the electron emission portion 3 were observed in the same manner as in Example 1, and the observation results are shown in Table 1.

Comparative Examples 1-6.
A field electron emission device for FED was obtained in the same manner as in Example 1 except that a silicone ladder polymer having the type and weight average molecular weight shown in Comparative Examples 1 to 6 in Table 1 was used as the insulating layer 4. For the obtained field electron emission device for FED, the electron emission opening 8 and the electron emission portion 3 were observed in the same manner as in Example 1, and the observation results are shown in Table 1.

Comparative Example 7
Field electron emission device for FED as in Example 1 except that the removal of about 1 μm of the upper surface of the insulating layer exposed to the first electron emission opening 8a, ie, the removal of the insulating layer altered portion 20, was not performed. Got. For the obtained field electron emission device for FED, the electron emission opening 8 and the electron emission portion 3 were observed in the same manner as in Example 1, and the observation results are shown in Table 1.

  As apparent from Table 1, the insulating layer 4 has a PPSQ having a weight average molecular weight in the range of 10,000 to 200,00, a PVSQ having a weight average molecular weight in the range of 10,000 to 300,00, or a weight average molecular weight. When using PMSQ in the range of 20,00 to 400,00, the insulating layer 4 can be easily formed by the manufacturing method of the present invention, and the CNT of the electron emission portion 3 is not oxidized and consumed. Etching by-products are not attached to the electron emission opening 8 and the electron emission opening 8 can be formed in a short time.

However, the silicone ladder polymer used for the insulating layer 4 is a PPSQ having a weight average molecular weight of less than 10,000, a PVSQ having a weight average molecular weight of less than 10,000, or a weight average molecular weight of 20,
In the case of a PMSQ of less than 00, for example, the 10 μm thick insulating layer 4 could not be formed, and a field electron emission device for FED could not be obtained.

  When the silicone ladder polymer used for the insulating layer 4 is PPSQ having a weight average molecular weight of more than 200,00, PVSQ having a weight average molecular weight of more than 300,00, or PMSQ having a weight average molecular weight of more than 400,000, In a short wet etching, the residue of the insulating layer remains, the second electron emission opening 8b cannot be formed, and the FED field electron emission device cannot be obtained.

  Further, even when a wet-etchable silicone ladder polymer is used for the insulating layer 4, removal of about 1 μm of the upper surface of the insulating layer exposed at the first electron emission opening 8 a, that is, removal of the insulating layer altered portion 20 is performed. Otherwise, wet etching could not be performed, the second electron emission opening 8b could not be formed, and a field electron emission device for FED could not be obtained.

  The present invention can be applied to the manufacture of a highly reliable field electron emission device for FED that forms an electron emission portion without damaging the CNT of the electron emission portion.

It is a figure explaining the structure of a field electron emission apparatus. It is a figure which shows the insulating layer alteration part formed by gate electrode formation with the manufacturing method of this invention. It is a figure explaining the manufacturing process of the field electron emission apparatus in Embodiment 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, 2 cathode electrode, 3 Electron emission part, 4 Insulating layer, 5 Gate electrode, 6 Resist film pattern, 8 Electron emission opening part, 10 Field electron emission apparatus, 20 Altered part of insulating layer

Claims (3)

Forming a cathode electrode on the substrate;
Forming an electron emission portion containing CNTs on the cathode electrode;
Insulation is carried out by applying a liquid or paste-like silicone ladder polymer on the exposed surface of the cathode electrode, the exposed surface of the electron emission portion, and the exposed surface of the substrate, and then drying and solidifying the silicone ladder polymer. Forming a layer;
Forming a gate electrode on the insulating layer;
Forming a resist film on the gate electrode;
Exposing / developing the resist film;
Etching the gate electrode using the developed resist film pattern as a mask to expose a portion of the upper surface of the insulating layer;
Removing the surface layer portion of the insulating layer from the exposed portion of the insulating layer;
And wet etching the insulating layer from which the surface layer portion has been removed from the exposed portion of the insulating layer, thereby forming an opening having a part of the upper surface of the electron emission portion as its entire bottom surface. A method for manufacturing a field electron emission device.   2. The method of manufacturing a field electron emission device according to claim 1, wherein the method of removing the surface layer portion of the insulating layer is one of buffered hydrofluoric acid treatment, reactive ion etching treatment, and ion beam etching treatment. . For the silicone ladder polymer, use one of PPSQ having a weight average molecular weight in the range of 10,000 to 200,000, PVSQ having a weight average molecular weight in the range of 10,000 to 300,000, and PMSQ having a weight average molecular weight in the range of 20,000 to 400,000. The method of manufacturing a field electron emission device according to claim 1.

Images