JP2005108429A - Semiconductor storage device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance retention characteristics of a semiconductor storage device having ferroelectric capacitors storing data by bias of polarization of a ferroelectric films. <P>SOLUTION: Memory cells are constituted of: the ferroelectric capacitors 30 storing data by bias of polarization of the ferroelectric films; and selection transistors 20 connected in parallel to the ferroelectric capacitors 30. A read-out transistor 10 reading out data by detecting bias of polarization of the ferroelectric film of the selected ferroelectric capacitor 30 is connected to one end of a serial circuit, wherein the plurality of ferroelectric capacitors 30 are continuously connected in a bit line direction and a memory cell block is constituted of the plurality of ferroelectric capacitors 30, the plurality of selection transistors 20 and the one read-out transistor 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device having a ferroelectric capacitor and a driving method thereof.

  As shown in FIG. 6, a semiconductor memory device having a ferroelectric capacitor includes a field effect transistor (hereinafter referred to as FET) 1 having a drain region 1a, a source region 1b and a gate electrode 1c, an upper electrode 2a, A ferroelectric capacitor 2 having an electrode 2b and a ferroelectric film 2c, the lower electrode 2b of the ferroelectric capacitor 2 is connected to the gate electrode 1c of the FET 1, and the ferroelectric capacitor 2 is connected to the gate potential of the FET 1. A nondestructive readout method used for control is known. In FIG. 6, reference numeral 3 denotes a substrate.

  When writing data in this semiconductor memory device, a write voltage is applied between the upper electrode 2a of the ferroelectric capacitor 2 serving as a control electrode and the substrate 3.

  For example, when data is written by applying a positive voltage (control voltage) with respect to the substrate 3 to the upper electrode 2 a, downward polarization occurs in the ferroelectric film 2 c of the ferroelectric capacitor 2. Thereafter, even if the upper electrode 2a is grounded, the positive charge remains in the gate electrode 1c of the FET 1, so that the potential of the gate electrode 1c becomes positive.

  If the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on state. Therefore, if a potential difference is applied between the drain region 1a and the source region 1b, the drain region 1a and the source region 1b Current flows between the two. Thus, for example, the logical state of the ferroelectric memory in which a current flows between the drain region 1a and the source region 1b is defined as “1”.

  On the other hand, when a voltage that is negative with respect to the substrate 3 is applied to the upper electrode 2 a of the ferroelectric capacitor 2, upward polarization occurs in the ferroelectric film 2 c of the ferroelectric capacitor 2. After that, even if the upper electrode 2a is grounded, since the negative charge remains in the gate electrode 1c of the FET 1, the potential of the gate electrode 1c becomes negative. In this case, since the potential of the gate electrode 1c is always smaller than the threshold voltage of the FET 1, the FET 1 is in an off state. Therefore, even if a potential difference is applied between the drain region 1a and the source region 1b, No current flows between the source region 1b. Thus, for example, the logical state of the ferroelectric memory in which no current flows between the drain region 1a and the source region 1b is defined as “0”.

  Even if the power supply to the ferroelectric capacitor 2 is cut off, that is, even if a voltage is not applied to the upper electrode 2a of the ferroelectric capacitor 2, the above-described respective logical states are preserved, so that the nonvolatile memory is stored. A device is realized. That is, when the power supply is turned off for a certain period and then supplied again to apply a voltage between the drain region 1a and the source region 1b, when the logic state of the ferroelectric memory is "1", the drain region 1a Since a current flows between the source region 1b, data "1" can be read. On the other hand, when the logic state of the ferroelectric memory is "0", a current flows between the drain region 1a and the source region 1b. Therefore, data “0” can be read out.

  In order to correctly retain data even during the power-off period (the characteristic of retaining data in this way is called retention), even during the power-off period, when the data is “1”, the gate electrode 1c of the FET 1 Is always maintained higher than the threshold voltage of the FET 1, and when the data is “0”, the potential of the gate electrode 1 c of the FET 1 must always be maintained at a negative voltage.

  Incidentally, during the power-off period, the upper electrode 2a and the substrate 3 of the ferroelectric capacitor 2 are at the ground potential, so that the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 7, the hysteresis loop 4 at the time of writing data to the ferroelectric capacitor 2 and the first of the gate capacitance load line 5 of the FET 1 when the bias voltage is 0V. Is the potential of the gate electrode 1c for the data "1", and the second intersection d of the hysteresis loop 4 and the gate capacitance load line 5 is the potential of the gate electrode 1c for the data "0". In FIG. 7, the vertical axis represents the charge Q appearing on the upper electrode 2 a (or the gate electrode 1 c), and the horizontal axis represents the voltage V.

However, in reality, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, so that the potential of the gate electrode 1c drops through this resistance component. This potential drop is exponential and has a time constant obtained by multiplying the parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 and the resistance component of the ferroelectric capacitor 2. This time constant is about 10 ⁴ seconds at most. Therefore, the potential of the gate electrode 1c is halved in a few hours.

  As shown in FIG. 7, since the potential of the gate electrode 1c is about 1V at the first intersection c, when this potential is halved, the potential of the gate electrode 1c becomes about 0.5V and the threshold value of the FET 1 is reached. Since the voltage is lower than the voltage (generally about 0.7 V), the FET 1 that should be in the on state is turned off in a short time.

  As described above, the ferroelectric memory using the ferroelectric capacitor 2 for controlling the gate potential of the FET 1 has an advantage that a rewrite operation is not necessary after the data is read. Has the following problems. That is, a potential is generated in the gate electrode 1c of the FET 1 after the data is written, and the ability to hold the gate potential determines the retention characteristic. However, the ferroelectric capacitor 2 has a resistance component due to the resistance component of the ferroelectric capacitor 2. Since the time constant until discharge is short, there is a problem that the data retention capability is short, that is, the retention characteristic is not good.

  Further, as the semiconductor integrated circuit device is highly integrated and miniaturized, it is required to reduce the area of the semiconductor memory device mounted on the semiconductor integrated circuit device. However, in the conventional semiconductor memory device, each memory cell has a strong strength. Since the dielectric capacitor 2 and the FET 1 for reading data stored in the ferroelectric capacitor 2 are provided, there is a problem that the area of each memory cell and thus the semiconductor memory device cannot be sufficiently reduced.

  In view of the foregoing, a first object of the present invention is to improve the retention characteristics of a semiconductor memory device having a ferroelectric capacitor for storing data by polarization deviation of the ferroelectric film. A second object is to reduce the area of the apparatus.

  A semiconductor memory device according to the present invention includes a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film, and one end side of a plurality of ferroelectric capacitors whose gates are connected in series. Connected continuously to a memory cell block having a read transistor for reading data by detecting a polarization deviation of a ferroelectric film of a selected ferroelectric capacitor among a plurality of ferroelectric capacitors A set line connected to the other end of the plurality of ferroelectric capacitors, a bit line connected at one end to the drain of the read transistor, a reset line connected at one end to the source of the read transistor, and a plurality of Corresponding to each of the ferroelectric capacitors and provided to be orthogonal to the bit line, a plurality of ferroelectric capacitors are connected to the data. And a plurality of word lines for selecting the ferroelectric capacitors for performing writing or reading.

  According to the semiconductor memory device of the present invention, the gate of the read transistor that detects the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor is connected to one end side of the plurality of ferroelectric capacitors. Therefore, there is no need to arrange a read transistor for each memory cell, so that the area of the memory cell and thus the semiconductor memory device can be reduced.

  In addition, since a plurality of word lines provided so as to be orthogonal to the bit lines select a ferroelectric capacitor for writing or reading data from a plurality of ferroelectric capacitors, 1 is provided for each of the plurality of ferroelectric capacitors. Even if two read transistors are connected, data can be reliably written to or read from the selected ferroelectric capacitor.

  Furthermore, since the amplification function of the read transistor can be used when reading data, the sensitivity for detecting the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor is improved.

  The semiconductor memory device according to the present invention preferably includes a plurality of selection transistors that are connected in parallel to each of the plurality of ferroelectric capacitors and each gate is connected to each of the plurality of word lines. .

  In this way, the ferroelectric capacitor for writing and reading data can be selected by controlling the voltage applied to the word line to turn on / off the selection transistor. In addition, since the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor can be removed by turning on the selection transistor, the potential is reduced due to the resistance component of the ferroelectric capacitor. Since it is suppressed, the retention characteristic is improved.

  In the semiconductor memory device according to the present invention, the first voltage obtained by dividing the read voltage applied to the set line based on the ratio between the capacitance value of the ferroelectric capacitor and the gate capacitance value of the read transistor is provided at the gate of the read transistor. The division voltage is induced, and the read voltage is VR> VT> VS (where VT is the threshold voltage of the read transistor, and VS is the read transistor when data is written to the selected ferroelectric capacitor. VR is a first divided voltage induced at the gate of the read transistor when data is not written in the selected ferroelectric capacitor. The size is preferably set so that the relationship is established.

  As described above, when the read voltage is set to a magnitude that satisfies the relationship of VR> VT> VS, even if the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor is removed, the ferroelectric is Data held in the body capacitor can be read without any trouble.

  In the semiconductor memory device according to the present invention, between the upper electrode and the lower electrode of the ferroelectric capacitor, the read voltage applied to the set line includes the capacitance value of the ferroelectric capacitor and the gate capacitance value of the read transistor. It is preferable that the second divided voltage divided based on the ratio is induced, and the read voltage is set to a magnitude such that the second divided voltage does not exceed the coercive voltage of the ferroelectric capacitor.

  As described above, when the read voltage is set to a value that does not exceed the coercive voltage of the ferroelectric capacitor, the second divided voltage applied between the upper electrode and the lower electrode of the ferroelectric capacitor is set to the set line. When the applied read voltage is removed, the polarization deviation of the ferroelectric film can be reliably returned to the deviation before data reading.

  The semiconductor memory device according to the present invention preferably includes a resistive load having one end connected to the other end of the bit line.

  In this way, when a read voltage is applied to the set line, it is possible to detect the voltage change that occurs across the resistive load due to the current flowing between the drain and source of the read transistor, that is, the current flowing through the bit line. It is possible to detect data written in the ferroelectric capacitor. Further, unlike a voltage change due to a capacitive load, a voltage change due to a resistive load can be detected at any time while a read voltage is being applied, so that the voltage change can be easily detected.

  When the semiconductor memory device according to the present invention includes a resistive load, the resistive load is preferably a MOS transistor.

  In this way, the resistive load can be actively driven.

  When the semiconductor memory device according to the present invention includes a resistive load, a power supply voltage is applied to the other end of the resistive load, and the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor is affected. Accordingly, it is preferable to provide comparison means for comparing a reference voltage with a voltage change that occurs across the resistive load due to a current flowing between the drain and source of the different read transistors.

  In this way, when a read voltage is applied to the set line, the voltage change generated at both ends of the resistive load due to the current flowing between the drain and source of the read transistor, that is, the current flowing through the bit line, and the reference voltage are By comparing, the data written in the selected ferroelectric capacitor can be detected easily and reliably.

  The semiconductor memory device according to the present invention has the same configuration as that of the memory cell block, and other memory cell blocks arranged in the word line direction of the memory cell block, and one end side constitutes another memory cell block. Another bit line connected to the drain of the read transistor, one resistive load having one end connected to the other end of the bit line and the other end connected to the power supply voltage, and one end connected to the other bit line. Other resistive load connected to the other end side and the other end side connected to the power supply voltage, and the set line is also connected to the other end side of a plurality of ferroelectric capacitors constituting another memory cell block The reset line is also connected to the sources of other read transistors constituting other memory cell blocks, and when the read voltage is applied to the set line, the read line is The first voltage change that occurs across one resistive load due to the current flowing between the drain and source of the transistor and the other resistive load across the other read load due to the current flowing between the drain and source of the other read transistor It is preferable to provide a comparison means for comparing the second voltage change occurring in

  In this way, the first voltage change that occurs at both ends of one resistive load due to the current flowing between the drain and source of the read transistor that constitutes the memory cell block that reads data, and another memory that does not read data A memory cell block for reading data is formed by comparing a second voltage change generated across the other resistive load due to a current flowing between the drain and source of another read transistor constituting the cell block. Data written in the selected ferroelectric capacitor can be reliably detected.

  A first semiconductor memory device driving method according to the present invention includes a plurality of ferroelectric capacitors each storing data by a polarization deviation of a ferroelectric film, and a plurality of ferroelectric capacitors in which a gate is connected in series. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of ferroelectric capacitors connected in series, a bit line connected at one end to the drain of the read transistor, and an end connected to the source of the read transistor A selected ferroelectric that corresponds to each of the reset line and each of the plurality of ferroelectric capacitors and is orthogonal to the bit line. A method for driving a semiconductor memory device including a plurality of word lines for selecting capacitors, and is used when selecting a selected ferroelectric capacitor or writing data to a selected ferroelectric capacitor. The voltage applied to the line, the reset line, and the word line is one of a power supply voltage and a ground voltage.

  According to the first method for driving a semiconductor memory device, when a ferroelectric capacitor is selected or when data is written to the selected ferroelectric capacitor, the voltage applied to the set line, the reset line, and the word line is the power supply Since the voltage is one of the voltage and the ground voltage, a negative voltage generation circuit for inverting the polarization deviation of the ferroelectric film of the ferroelectric capacitor becomes unnecessary. Further, the potential applied to the first well region of the read transistor when a reverse bias voltage is applied between the upper electrode and the lower electrode of the ferroelectric capacitor is different from that of the first well region of the read transistor. Since there is no need to make the potential applied to the second well region different, there is no need to separate the first well region from the second well region.

  Therefore, the area of the semiconductor memory device can be reduced.

  A second semiconductor memory device driving method according to the present invention includes a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film, and a plurality of ferroelectric capacitors in which a gate is continuously connected. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of ferroelectric capacitors connected in series, a bit line connected at one end to the drain of the read transistor, and an end connected to the source of the read transistor A selected ferroelectric that corresponds to each of the reset line and each of the plurality of ferroelectric capacitors and is orthogonal to the bit line. Targeting a method for driving a semiconductor memory device having a plurality of word lines for selecting capacitors, when none of a plurality of ferroelectric capacitors constituting a memory cell block is selected when reading data Then, the read transistor constituting the memory cell block is turned off.

  According to the second method for driving a semiconductor memory device, when data is read, if none of the plurality of ferroelectric capacitors that constitute the memory cell block is selected, the read that constitutes the memory cell block Since the transistor is kept off, no current flows between the bit line and the reset line. For this reason, when data is read from another ferroelectric capacitor constituting another memory cell block, a voltage is applied between the upper electrode and the lower electrode of the ferroelectric capacitor constituting the memory cell block. However, this does not hinder the reading of the data of the ferroelectric capacitors constituting the other memory cell blocks.

  Therefore, an operation margin when reading data is increased, and a stable operation can be realized.

  A third semiconductor memory device driving method according to the present invention includes a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film, and a plurality of ferroelectric capacitors in which a gate is continuously connected. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of ferroelectric capacitors connected in series, a bit line connected at one end to the drain of the read transistor, and an end connected to the source of the read transistor A selected ferroelectric that corresponds to each of the reset line and each of the plurality of ferroelectric capacitors and is orthogonal to the bit line. In a method for driving a semiconductor memory device including a plurality of word lines for selecting capacitors, the process of writing data to a selected ferroelectric capacitor applies a power supply voltage to a set line and grounds a reset line. A ferroelectric film of the selected ferroelectric capacitor is applied by applying a voltage and applying a potential difference obtained by subtracting the ground voltage from the power supply voltage between the upper electrode and the lower electrode of the selected ferroelectric capacitor. Is applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the set line, and then a step of directing the direction of polarization in the direction of the potential gradient of the potential difference And a step of removing a potential difference.

  According to the third method for driving a semiconductor memory device, when data is written to the selected ferroelectric capacitor, data is written by applying a potential difference between the upper electrode and the lower electrode of the selected ferroelectric capacitor. After that, since the potential difference applied between the upper and lower electrodes of the selected ferroelectric capacitor is removed, the potential drop due to the resistance component of the ferroelectric capacitor is suppressed, so that the retention characteristic Will improve.

  According to a fourth method of driving a semiconductor memory device of the present invention, a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film and a plurality of strong capacitors in which a gate is connected in series. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of ferroelectric capacitors connected in series, a bit line connected at one end to the drain of the read transistor, and an end connected to the source of the read transistor A selected ferroelectric that corresponds to each of the reset line and each of the plurality of ferroelectric capacitors and is orthogonal to the bit line. In a method for driving a semiconductor memory device including a plurality of word lines for selecting capacitors, the step of erasing data written in the selected ferroelectric capacitors applies a ground voltage to the set lines. And selecting a ferroelectric capacitor by applying a power supply voltage to the reset line and applying a potential difference obtained by subtracting the power supply voltage from the ground voltage between the upper electrode and the lower electrode of the selected ferroelectric capacitor. The step of directing the polarization direction of the ferroelectric film in the direction of the potential gradient of the potential difference, and then applying a ground voltage to the reset line between the upper electrode and the lower electrode of the selected ferroelectric capacitor Removing a potential difference applied to the.

  According to the fourth method for driving a semiconductor memory device, when erasing data written in the selected ferroelectric capacitor, data is transferred between the upper electrode and the lower electrode of the selected ferroelectric capacitor. In order to remove the potential difference applied between the upper and lower electrodes of the selected ferroelectric capacitor after erasing the data by applying a potential difference opposite to that written, the resistance component of the ferroelectric capacitor Since the potential drop due to the is suppressed, the retention characteristics are improved.

  A fifth semiconductor memory device driving method according to the present invention includes a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film, and a plurality of ferroelectric capacitors in which a gate is connected in series. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of ferroelectric capacitors connected in series, a bit line connected at one end to the drain of the read transistor, and an end connected to the source of the read transistor A selected ferroelectric that corresponds to each of the reset line and each of the plurality of ferroelectric capacitors and is orthogonal to the bit line. A method of reading data from a selected ferroelectric capacitor is intended for a method of driving a semiconductor memory device having a plurality of word lines for selecting capacitors, and a power supply voltage is applied to a bit line and a reset line is grounded Applying a potential or applying a ground voltage to the bit line and applying a power supply potential to the reset line and applying a read voltage to the set line; And a step of removing a potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the set line.

  According to the fifth method for driving a semiconductor memory device, when data is read from the selected ferroelectric capacitor, the read voltage is applied to the set line, the data is read, and then the selected ferroelectric capacitor is read. Since the potential difference applied between the electrode and the lower electrode is removed, a decrease in potential due to the resistance component of the ferroelectric capacitor is suppressed, so that the retention characteristics are improved.

  The fifth method for driving a semiconductor memory device according to the present invention preferably further includes a step of turning off the read transistor after the step of removing the potential difference.

  As described above, when the read transistor is turned off after the data is read, no current flows between the bit line and the reset line. Therefore, as in the second method for driving the semiconductor memory device, other memory cell blocks Since the operation of reading data of the ferroelectric capacitors constituting the circuit is not affected, the operation margin when reading data is increased, and a stable operation can be realized.

  A sixth method for driving a semiconductor memory device according to the present invention includes a plurality of ferroelectric capacitors each storing data by polarization deviation of a ferroelectric film, and a plurality of ferroelectric capacitors in which a gate is connected in series. A memory cell having a read transistor connected to one end of the dielectric capacitor and for reading data by detecting a polarization deviation of the ferroelectric film of the selected ferroelectric capacitor among the plurality of ferroelectric capacitors A block, a set line connected to the other end of a plurality of continuously connected ferroelectric capacitors, and a bit having one end connected to the drain of the read transistor and the other end connected to one end of the resistive load A line, a reset line having one end connected to the source of the read transistor, a bit line corresponding to each of the plurality of ferroelectric capacitors, A step of reading data from a selected ferroelectric capacitor, which is directed to a method for driving a semiconductor memory device provided with a plurality of word lines for selecting a selected ferroelectric capacitor, Apply power supply voltage to the other end of the resistive load and apply ground voltage to the reset line, or apply ground voltage to the other end of the resistive load and apply ground voltage to the reset line, and When a read voltage is applied, a step of comparing a reference voltage with a voltage change that occurs across the resistive load due to a current flowing between the drain and source of the read transistor, and then applying a ground voltage to the set line And a step of removing a potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor.

  According to the sixth method for driving a semiconductor memory device, when data is read from the selected ferroelectric capacitor, the voltage generated across the resistive load connected to the bit line when a read voltage is applied to the set line Since the change is compared with the reference voltage, the data written in the selected ferroelectric capacitor can be reliably read out. In addition, in order to remove the potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor after reading the data from the selected ferroelectric capacitor, the resistance component of the ferroelectric capacitor is used. Since the potential decrease due to the suppression is suppressed, the retention characteristics are improved.

  The sixth method for driving a semiconductor memory device preferably further includes a step of turning off the reading transistor after the step of removing the potential difference.

  As described above, when the read transistor is turned off after the data is read, no current flows between the bit line and the reset line. Therefore, as in the second method for driving the semiconductor memory device, other memory cell blocks Since the operation of reading data of the ferroelectric capacitors constituting the circuit is not affected, the operation margin when reading data is increased, and a stable operation can be realized.

  In the sixth method for driving a semiconductor memory device according to the present invention, the semiconductor memory device has a configuration similar to that of the memory cell block and one end of the other memory cell block arranged in the word line direction of the memory cell block. The other side is connected to the drain of another read transistor constituting another memory cell block and the other side is connected to one end side of another resistive load, and the set line is another memory cell block Is connected to the other end side of the plurality of ferroelectric capacitors constituting the memory cell, and the reset line is also connected to the sources of other read transistors constituting the other memory cell block. Apply a power supply voltage to the other end of the other resistive load and a ground voltage to the reset line, or apply a ground voltage to the other end of the other resistive load and When a ground voltage is applied to the reset line and a read voltage is applied to the set line, the voltage change occurs across the other resistive load due to the current flowing between the drain and source of the other read transistor. Is preferred.

  In this way, the first voltage change that occurs at both ends of one resistive load due to the current flowing between the drain and source of the read transistor that constitutes the memory cell block that reads data, and another memory that does not read data A memory cell block for reading data is formed by comparing a second voltage change generated across the other resistive load due to a current flowing between the drain and source of another read transistor constituting the cell block. Data written in the selected ferroelectric capacitor can be reliably detected.

  According to the semiconductor memory device of the present invention, since it is not necessary to arrange a read transistor for each memory cell, the area of the memory cell and thus the semiconductor memory device can be reduced, and the strength of the selected ferroelectric capacitor can be reduced. Sensitivity for detecting the polarization deviation of the dielectric film is improved.

  According to the first method for driving a semiconductor memory device of the present invention, the area of the semiconductor memory device can be reduced.

  According to the second method for driving a semiconductor memory device of the present invention, the operation margin for reading data is increased, and thus stable operation can be realized.

  According to the third, fourth, fifth, or sixth method for driving a semiconductor memory device according to the present invention, since the potential decrease due to the resistance component of the ferroelectric capacitor is suppressed, the retention characteristic is improved.

(First embodiment)
The semiconductor memory device and the driving method thereof according to the first embodiment of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b).

  FIG. 1A shows an equivalent circuit of the semiconductor memory device according to the first embodiment. The ferroelectric capacitor 30 stores data by the polarization deviation of the ferroelectric film, and the ferroelectric body. A memory cell is constituted by a selection field effect transistor (hereinafter simply referred to as a selection transistor) 20 connected in parallel to the capacitor 30.

  A ferroelectric film of the ferroelectric capacitor 30 selected from among the plurality of ferroelectric capacitors 30 is disposed on the lower end side of the series circuit in which the plurality of ferroelectric capacitors 30 are connected in series in the bit line direction. A read field effect transistor (hereinafter simply referred to as a read transistor) 10 for reading data by detecting polarization deviation is connected to a plurality of ferroelectric capacitors 30, a plurality of select transistors 20, and A memory cell block is configured by one read transistor 10, and a plurality of memory cell blocks having the same configuration are arranged in a direction (word line direction) perpendicular to the bit line direction. It is configured.

  FIG. 1B shows a configuration of the lowermost memory cell and the read transistor 10. The read transistor 10 includes a drain region 11, a source region 12, and a gate electrode 13, and the select transistor 20 includes a drain region 21, The ferroelectric capacitor 30 has an upper electrode 31, a lower electrode 32, and a ferroelectric film 33. The ferroelectric capacitor 30 has a source region 22 and a gate electrode 23. In FIG. 1B, reference numeral 14 denotes a substrate on which the read transistor 10 is formed.

  As shown in FIGS. 1A and 1B, the gate electrode 23 of the selection transistor 20 constituting the memory cell in the first row is connected in common to the first word line WL1, and the memory cell in the second row is connected to the memory cell in the second row. The gate electrode 23 of the selection transistor 20 constituting the memory cell is commonly connected to the second word line WL2, and the gate electrode 23 of the selection transistor 20 constituting the memory cell of the third row is commonly connected to the third word line WL3. The gate electrodes 23 of the select transistors 20 constituting the memory cells in the fourth row are commonly connected to the fourth word line WL4.

  In the memory cell block in the first column, a plurality of ferroelectric capacitors 30 in the first column are connected to the upper end portion of the series circuit connected in series in the bit line direction, that is, the ferroelectric capacitors 30 in the first row. A lower end portion of a series circuit in which an upper electrode 31 is connected to a first control line (first set line) BS1 and a plurality of ferroelectric capacitors 30 in the first column are connected in series in the bit line direction; That is, the lower electrode 32 of the ferroelectric capacitor 30 in the fourth row is connected to the gate electrode 13 of the read transistor 10, and the drain region 11 of the read transistor 10 is connected to the first bit line BL1.

  In the memory cell block in the second column, the upper end portion of the series circuit in which the plurality of ferroelectric capacitors 30 in the second column are connected in series in the bit line direction, that is, the ferroelectric capacitors 30 in the first row. A lower end portion of a series circuit in which the upper electrode 31 is connected to a second control line (second set line) BS2, and a plurality of ferroelectric capacitors 30 in the second column are connected in series in the bit line direction; That is, the lower electrode 32 of the ferroelectric capacitors 30 in the fourth row is connected to the gate electrode 13 of the read transistor 10, and the drain region 11 of the read transistor 10 is connected to the second bit line BL2.

  The source region 12 of the read transistor 10 in the first column and the source region 12 of the read transistor 20 in the second column are commonly connected to the reset line RST.

(Data write operation)
The write operation in the semiconductor memory device according to the first embodiment is as follows. Here, a case where data is written to the ferroelectric capacitor 30 constituting the memory cell in the fourth row of the first column will be described.

  First, the substrate potentials of all the read transistors 10 are set to the ground voltage VSS (0 V), and the potentials of the first and second control lines BS1 and BS2 and the first to fourth word lines WL1 to WL4 are all grounded. After setting to VSS, the potential of the first control line BS1 is raised to the power supply potential VDD (5V).

  Next, the potential of the first to third word lines WL1 to WL3 is raised to the power supply voltage, while the potential of the fourth word line WL4 is kept at the ground potential.

  Thus, the selection transistors 10 in the first to third rows whose gates are connected to the first to third word lines WL1 to WL3 are turned on, while the gates are connected to the fourth word line WL4. Since the selection transistors 10 in the fourth row that have been turned off remain in the OFF state, the ferroelectric capacitors 30 that constitute the memory cells in the fourth row in the first column are selected.

  Further, since a potential difference between the power supply voltage VDD and the ground voltage VSS is applied between the upper electrode 31 and the lower electrode 32 of the ferroelectric capacitor 30 constituting the memory cell in the fourth row of the first column, Downward polarization occurs in the ferroelectric film 33 of the ferroelectric capacitor 30 and data “1” is written. When the potential of the first control line BS1 is lowered from the ground voltage to a negative potential (−5V), the data written in the ferroelectric film 30 constituting the memory cell in the fourth row of the first column ” 1 ”is erased, and the logical state of the ferroelectric capacitor 30 becomes data“ 0 ”.

(Data read operation)
The read operation in the semiconductor memory device according to the first embodiment is as follows. Here, a case where data written in the ferroelectric capacitor 30 constituting the memory cell of the fourth row in the first column is read will be described.

  First, the substrate potentials of all the read transistors 10 are set to the ground voltage VSS (0 V), and the potentials of the first and second control lines BS1 and BS2 and the first to fourth word lines WL1 to WL4 are all grounded. After setting to VSS, the potential of the first control line BS1 is raised to the power supply potential VDD (5V).

  Next, the potential of the first to third word lines WL1 to WL3 is raised to the power supply voltage, while the potential of the fourth word line WL4 is kept at the ground potential.

  Thus, the selection transistors 10 in the first to third rows whose gates are connected to the first to third word lines WL1 to WL3 are turned on, while the gates are connected to the fourth word line WL4. Since the selection transistors 10 in the fourth row that have been turned off remain in the OFF state, the ferroelectric capacitors 30 that constitute the memory cells in the fourth row in the first column are selected.

  In this state, when the potential of the first bit line BL1 is set to the power supply voltage VDD and the potential of the reset line RST is set to the ground potential VSS, when the data “1” is held, the drain region of the read transistor 10 On the other hand, a current flows between the source region 12 and the source region 12, while no current flows between the drain region 11 and the source region 12 of the read transistor 10 when data “0” is held. In this manner, data written in the ferroelectric capacitor 30 constituting the memory cell in the fourth row of the first column can be read out.

  When data reading is completed, the potential of the fourth word line WL4 is raised to the power supply voltage, and the selection transistors 10 in the fourth row whose gates are connected to the fourth word line WL4 are turned on. By doing so, the upper electrode 31 and the lower electrode 32 of the ferroelectric capacitor 30 from which the data has been read are brought into conduction, so that the potential difference generated between the upper electrode 31 and the lower electrode 32 is removed.

  According to the first embodiment, the gate electrode 13 of the read transistor 10 that detects the polarization deviation of the ferroelectric film 33 of the selected ferroelectric capacitor 30 includes a plurality of gate electrodes 13 connected in series in the bit line direction. Since it is connected to one end side of the ferroelectric capacitor 30, it is not necessary to arrange a read transistor for each memory cell, so that the area of the memory cell and thus the semiconductor memory device can be reduced.

  In addition, a plurality of ferroelectric capacitors connected in series are selected in order to select the ferroelectric capacitor 30 on which data is written or read by the first to fourth word lines WL1 to WL4 provided so as to be orthogonal to the bit lines. Even if one read transistor 10 is connected to the body capacitor 30, data can be written to or read from the selected ferroelectric capacitor 30 with certainty.

  Further, since the amplification function of the read transistor 10 can be used when reading data, the sensitivity for detecting the polarization deviation of the ferroelectric film 33 of the selected ferroelectric capacitor 30 is improved.

  In addition, since the potential difference generated between the upper electrode 31 and the lower electrode 32 of the ferroelectric capacitor 30 is removed after the data is read out, a decrease in potential due to the resistance component of the ferroelectric capacitor 30 is suppressed. Therefore, the retention characteristics are improved.

(Second Embodiment)
A semiconductor memory device and a driving method thereof according to the second embodiment of the present invention will be described below with reference to FIGS.

  By the way, in the semiconductor memory device according to the first embodiment, after data “1” is written in the ferroelectric capacitor 30 of the selected memory cell, the data “1” is erased and the data “0” is retained. In order to achieve this, a negative voltage with respect to the substrate 14 of the read transistor 10 is applied to the first control line BS1, or a positive voltage with respect to the first control line BS1 is applied to the substrate of the read transistor 10. 14 need to be applied.

  Therefore, according to the former method, it is necessary to provide a negative voltage generating circuit, and according to the latter method, it is necessary to divide the well region finely so that the potential of the substrate of the memory cell can be specifically controlled. There's a problem.

  In the semiconductor memory device according to the first embodiment, when reading data, for example, when a positive voltage is applied to the gate electrode 13 of the read transistor 10, the ferroelectric capacitor 30 stores the data “1”. When held, the positive voltage works in a direction to emphasize the polarization of the ferroelectric film 33, but when the ferroelectric capacitor 30 holds data “0”, the positive voltage is applied to the ferroelectric film 33. Since it works in the direction of reversing the polarization, there is a problem that data is lost while the read operation is repeated.

  Further, data is detected depending on whether or not a current flows between the drain region 11 and the source region 12 of the read transistor 10 according to the polarization direction of the ferroelectric film 33 of the ferroelectric capacitor 30. At this time, the problem of how to compare the reference voltage with the voltage change due to the current between the drain region 11 and the source region 12 and the problem of how to generate this reference voltage are newly introduced. Occur.

  The second embodiment has been made in order to solve the above-described problems of the first embodiment.

  FIG. 2 shows an equivalent circuit of the semiconductor memory device according to the second embodiment. The memory cell block includes a plurality of ferroelectric capacitors CF1, CF2, CF3, and CF4 connected in series and each of the strong capacitors. A plurality of cell selection field effect transistors (hereinafter simply referred to as cell selection transistors) Q1, Q2, Q3, and Q4 that are connected in parallel to the dielectric capacitor and connected in series to each other, and the gates are connected in series. A plurality of ferroelectric capacitors connected to one end of a readout field effect transistor (hereinafter simply referred to as a readout transistor) Q7.

  The first ferroelectric capacitor CF1 and the first cell selection transistor Q1 constitute a first memory cell, and the second ferroelectric capacitor CF2 and the second cell selection transistor Q2 constitute a second memory cell. A third memory cell is formed by the third ferroelectric capacitor CF3 and the third cell selection transistor Q3, and a fourth memory cell is formed by the fourth ferroelectric capacitor CF4 and the fourth cell selection transistor Q4. Is configured.

  The lower ends of the plurality of cell selection transistors connected in series are connected to a reset line RST via a read selection field effect transistor (hereinafter simply referred to as a read selection transistor) Q6 and connected in series. The upper ends of the plurality of ferroelectric capacitors and the upper ends of the plurality of cell selection transistors connected in series are connected via a block selection field effect transistor (hereinafter simply referred to as a block selection transistor) Q5. It is connected to the set line SRD. The cell selection transistors Q1 to Q4, the block selection transistor Q5, the read selection transistor Q6, and the read transistor Q7 are all N-channel transistors.

  The first word line WL1 is connected to the gate of the first cell selection transistor Q1, the second word line WL2 is connected to the gate of the second cell selection transistor Q2, and the third cell selection transistor Q3 The third word line WL3 is connected to the gate, and the fourth word line WL4 is connected to the gate of the fourth cell selection transistor Q4.

  The gate of the read transistor Q7 is connected to the reset line RST via the read selection transistor Q6, the drain of the read transistor Q7 is connected to the lower end side of the bit line BL, and the source of the read transistor Q7 is connected to the reset line RST. Yes.

  The gate of the block selection transistor Q5 is connected to the block selection line BS, and the gate of the read selection transistor Q6 is connected to the read selection line / RS. Note that, although not shown in the figure, an operation amplifier circuit composed of a sense amplifier is connected to the tip of the lower end side of the bit line BL.

  A drain of a P-channel field effect transistor (hereinafter referred to as a load transistor) Q8 as a resistive load is connected to the upper end side of the bit line BL, and the source of the load transistor Q8 is connected to the first control line LS. The gate of the load transistor Q8 is connected to the second control line LG.

  In the second embodiment, the first to fourth word lines WL1 to WL4 are selected when a ferroelectric capacitor for writing or reading data is selected from the first to fourth ferroelectric capacitors CF1 to CF4. The voltage applied to the set line SRD or the reset line RST when data is written to the selected ferroelectric capacitor is always the power supply voltage VDD (for example, 5V) or the ground voltage VSS (for example, 0V). ).

  In the second embodiment, the potential of the read selection line / RE is set to the ground voltage VSS during the read operation, and is set to the power supply voltage VDD except during the read operation. Therefore, the read selection transistor Q6 is turned off only during the read operation, and a current flows from the selected ferroelectric capacitor to the gate of the read transistor Q7. The line SRD and the reset line RST are connected via a selected ferroelectric capacitor to prepare for a data write operation and an erase operation.

  Therefore, when any of the ferroelectric capacitors constituting the memory cell block is not selected during the data read operation, no voltage is applied to the gate of the read transistor Q7, and the read transistor Q7 Off state. Therefore, since no current flows between the bit line BL connected to the memory cell block and the reset line RST, when reading data of other ferroelectric capacitors constituting another memory cell block, Even if a voltage is applied between the upper electrode and the lower electrode of the ferroelectric capacitor constituting the memory cell block, it does not hinder reading data of the ferroelectric capacitor constituting another memory cell block. .

(Data write operation)
Hereinafter, an operation of writing data “1” to the ferroelectric capacitor CF4 in the fourth row will be described.

  First, the potential of the block selection line BS is set to the power supply voltage VDD, and the block selection transistor Q5 is turned on.

  Next, the first to third word lines WL1 to WL3 connected to the respective gates of the first to third cell selection transistors Q1 to Q3 constituting the first to third memory cells in which no data is written. The potential is set to the power supply voltage VDD to turn on the first to third cell selection transistors Q1 to Q3, while the fourth word line WL4 connected to the gate of the fourth cell selection transistor Q4 The potential is set to the ground voltage VSS, and the fourth cell selection transistors Q1 to Q3 are turned off.

  Thus, the upper electrode of the selected fourth ferroelectric capacitor CF4 is connected to the set line SRD and the lower electrode is connected to the reset line RST.

  Next, the potential of the reset line RST remains at the ground voltage VSS, and the potential of the set line SRD is raised to the power supply voltage VDD.

  In this way, a potential difference of + (VDD−VSS) is given between the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4, so that the ferroelectric film of the fourth ferroelectric capacitor CF4 Is directed downward, and data “1” is written to the fourth ferroelectric capacitor CF4.

  Thereafter, the potential of the set line SRD is set to the ground voltage VSS, and the potential difference of + (VDD−VSS) applied between the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4 is removed.

  Hereinafter, referring to FIG. 3, the ferroelectric substance is obtained when the potential difference applied between the upper electrode and the lower electrode of the ferroelectric capacitor is removed after the data “1” is written as described above. The behavior of the capacitor will be described.

  In FIG. 3, the vertical axis indicates the charge Q that is stored in and out of the ferroelectric film of the ferroelectric capacitor, and the horizontal axis is applied between the upper electrode and the lower electrode of the ferroelectric capacitor. Voltage. In FIG. 3, point a indicates the polarization charge when a voltage of + (VDD−VSS) is applied to the ferroelectric capacitor, and point b applies a voltage of − (VDD−VSS) to the ferroelectric capacitor. The point c indicates the polarization charge immediately after the voltage of + (VDD−VSS) is applied to the ferroelectric capacitor and then the voltage is removed, and the point d indicates the ferroelectric capacitor. 2 shows the polarization charge immediately after the voltage of-(VDD-VSS) is applied and then the voltage is removed, both of which are data “1” written.

  Before the start of the write operation, the potential difference between both electrodes of the ferroelectric capacitor is zero, so the polarization of the selected ferroelectric capacitor is between point c and point d. For example, when the polarization of the ferroelectric capacitor is at the point e, the polarization reaches the point c after moving from the point e to the point a by the write operation. For example, when the polarization of the ferroelectric capacitor is at the point f, the polarization moves from the point f to the point a by the write operation, and then reaches the point c. As described above, when data “1” is written in the ferroelectric capacitor, the polarization position moves to the point c regardless of the polarization position before writing.

(Data erase operation)
Hereinafter, an operation of erasing data “1” written in the ferroelectric capacitor CF4 in the fourth row, that is, an operation of rewriting data “1” to data “0” will be described.

  First, the potential of the block selection line BS is set to the power supply voltage VDD, and the block selection transistor Q5 is turned on.

  Next, the first to third word lines WL1 to WL3 connected to the respective gates of the first to third cell selection transistors Q1 to Q3 constituting the first to third memory cells in which no data is written. The potential is set to the power supply voltage VDD to turn on the first to third cell selection transistors Q1 to Q3, while the fourth word line WL4 connected to the gate of the fourth cell selection transistor Q4 The potential is set to the ground voltage VSS, and the fourth cell selection transistors Q1 to Q3 are turned off.

  Thus, the upper electrode of the fourth ferroelectric capacitor CF4 constituting the selected fourth memory cell is connected to the set line SRD and the lower electrode is connected to the reset line RST.

  Next, the potential of the reset line RST is raised to the power supply voltage VDD while the potential of the set line SRD line remains at the ground voltage VSS.

  In this way, a potential difference of − (VDD−VSS) is given between the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4, so that the ferroelectric film of the fourth ferroelectric capacitor CF4 The polarization becomes upward, and data “0” is written in the fourth ferroelectric capacitor CF4.

  Thereafter, the potential of the reset line RST is set to the ground voltage VSS, and the potential difference of − (VDD−VSS) applied between the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4 is removed.

  Hereinafter, referring to FIG. 3, the ferroelectric substance is obtained when the potential difference applied between the upper electrode and the lower electrode of the ferroelectric capacitor is removed after the data “0” is written as described above. The behavior of the capacitor will be described.

  Before the data “0” is written, that is, before the data “1” is erased, the potential difference between both electrodes of the ferroelectric capacitor is zero, so that the polarization of the selected ferroelectric capacitor is point c and point d. For example, when the polarization of the ferroelectric capacitor is at point g, the polarization reaches point d after moving from point g to point b by the erase operation. For example, when the polarization of the ferroelectric capacitor is at the point h, the polarization moves from the point h to the point b by the erase operation, and then reaches the point d. As described above, when the data “1” written in the ferroelectric capacitor is erased, the position of the polarization moves to the point d regardless of the position of the polarization before erasure.

(Data read operation)
Hereinafter, an operation of reading data written in the ferroelectric capacitor CF4 in the fourth row will be described.

  First, the potential of the block selection line BS is set to the power supply voltage VDD, and the block selection transistor Q5 is turned on.

  Next, the first to third word lines WL1 to WL3 connected to the gates of the first to third cell selection transistors Q1 to Q3 constituting the first to third memory cells from which data is not read. The potential is set to the power supply voltage VDD to turn on the first to third cell selection transistors Q1 to Q3, while the fourth word line WL4 connected to the gate of the fourth cell selection transistor Q4 The potential is set to the ground voltage VSS, and the fourth cell selection transistors Q1 to Q3 are turned off.

  Thus, the upper electrode of the fourth ferroelectric capacitor CF4 constituting the selected fourth memory cell is connected to the set line SRD and the lower electrode is connected to the reset line RST.

  Next, the potential of the read selection line / RS is set to the ground potential VSS, the read transistor Q6 is turned off, and then the potential of the first control line LS connected to the source of the load transistor Q8 is set to the power supply voltage VDD. In addition, the potential of the second control line LG connected to the gate of the load transistor Q8 is set to the ground voltage VSS, and the load transistor Q8 is turned on.

  Next, with the potential of the reset line RST being the ground voltage VSS, the potential of the set line SRD is set to the read voltage VRD, and the voltage change caused by the current flowing through the read transistor Q7 in the bit line BL and the reference voltage VREF The difference is detected by the sense amplifier and output.

  Next, after the potential of the set line SRD is lowered to the ground voltage VSS, the potential of the read selection line / RS is set to the power supply voltage VDD to turn on the read selection transistor Q6.

  Hereinafter, the magnitude of the read voltage VRD will be considered.

  When the potential of the set line SRD is set to the read voltage VRD, the read voltage VRD is determined based on the ratio between the capacitance value of the fourth ferroelectric capacitor CF4 and the gate capacitance value of the read transistor Q7. And the second divided voltage, the first divided voltage is induced at the gate of the read transistor Q7, and the second ferroelectric capacitor CF4 has a second electrode between the upper electrode and the lower electrode. A division voltage is induced.

  Here, the threshold voltage of the read transistor Q7 is VT, and the first divided voltage induced at the gate of the read transistor Q7 when the fourth ferroelectric capacitor CF4 holds the data “1”. When the first divided voltage induced at the gate of the read transistor Q7 when the fourth ferroelectric capacitor CF4 holds data “0” is VR, the read voltage VRD is VR. The size is set such that the relationship> VT> VS is established.

  Thus, when the data “1” or the data “0” held in the fourth ferroelectric capacitor CF4 is read by the read transistor Q7, the current flowing between the drain and the source of the read transistor Q7. This is preferable because the ratio of the values can be increased.

Hereinafter, with reference to FIG. 4, the above-described read operation will be described separately for the case where data “1” is held and the case where data “0” is held. In FIG. 4, the vertical axis indicates the charge Q that is stored in and out of the ferroelectric film of the ferroelectric capacitor CF4 and the horizontal axis indicates the capacitance of the ferroelectric capacitor CF4 and the gate capacitance of the read transistor Q7. The voltage applied to the series circuit. <Read operation when data “1” is held>
First, the potential of the substrate on which the read transistor Q7 is formed is set to the ground voltage VSS.

  When data “1” is held in the fourth ferroelectric capacitor CF4, the polarization charge of the fourth ferroelectric capacitor CF4 is at the position of the point p.

  Next, by selecting the memory cell (ferroelectric capacitor), the upper electrode of the fourth ferroelectric capacitor CF4 is connected to the set line SRD and the lower electrode is connected to the reset line RST. The potential of the line / RE is set to the ground potential VSS to turn off the read selection transistor Q6, and the potential of the first control line LS is set to the power supply voltage VDD.

  In this state, if the potential of the set line SRD is set to the read voltage VRD while the potential of the reset line RST is kept at the ground voltage VSS, the fourth ferroelectric is between the set line SRD and the substrate of the read transistor Q7. A voltage of (VRD−VSS) is applied to a series circuit in which the capacitance of the body capacitor CF4 and the gate capacitance of the read transistor Q7 are connected in series.

  Hereinafter, this operation will be described with reference to FIG.

  When a voltage (VRD−VSS) is applied to the series circuit of the capacitance of the fourth ferroelectric capacitor CF4 and the gate capacitance of the read transistor Q7, the voltage (VRD−VSS) is applied to the gate of the read transistor Q7. From the point p to the point s, generated between the first divided voltage VS from the point r to the point s and generated between the substrate and the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4. To the second divided voltage (VRD-VSS-VS).

  In FIG. 4, 8 is a gate capacitance load line of the read transistor Q7 during the read operation of data “1”, and the position of the point s, that is, the magnitude of the first divided voltage VS, is the value of the read transistor Q7 in the read operation. Depends on the gate capacitance. Further, the channel conductance of the read transistor Q7 when data “1” is read is determined by the first divided voltage VS.

  The fourth ferroelectric capacitor is set such that a relationship of VT> VS is established between the threshold voltage VT of the read transistor Q7 and the first divided voltage VS when the data “1” is held. If the capacitance ratio between the capacitance value of CF4 and the gate capacitance value of the read transistor Q7 is set, the current value that flows from the reset line RST to the reset line RST through the channel of the load transistor Q8, the bit line BL, and the read transistor Q7. Is relatively small, the voltage change of the bit line BL can be reduced. This voltage change is detected by a sense amplifier connected to the bit line BL, and the detected voltage change is compared with a preset reference voltage. If the detected voltage change does not exceed the reference voltage, data “1” is detected. Is determined to be held.

  Next, when the potential of the set line SRD is returned to the ground voltage VSS, the polarization charge of the fourth ferroelectric capacitor CF4 moves almost along the outermost periphery of the hysteresis loop and returns to the point p, and the read transistor Q7 The gate capacitance load line 7 intersects the vertical axis at point p.

  Thereafter, even if the potential of the read selection line / RE is set to the power supply voltage VDD and the read selection transistor Q6 is turned on, the voltage applied to the fourth ferroelectric capacitor CF4 is zero, so that the data “1” The magnitude of the polarization charge held in the fourth ferroelectric capacitor CF4 after "" is read is almost the same as the magnitude of polarization charge before the data "1" is read.

<Read operation when data “0” is held>
When data “0” is held in the fourth ferroelectric capacitor CF4, the polarization charge of the fourth ferroelectric capacitor CF4 is at the position of the point q.

  Next, by selecting the memory cell (ferroelectric capacitor), the upper electrode of the fourth ferroelectric capacitor CF4 is connected to the set line SRD and the lower electrode is connected to the reset line RST. The potential of the line / RE is set to the ground potential VSS to turn off the read selection transistor Q6, and the potential of the first control line LS is set to the power supply voltage VDD.

  In this state, if the potential of the set line SRD is set to the read voltage VRD while the potential of the reset line RST is kept at the ground voltage VSS, the fourth ferroelectric is between the set line SRD and the substrate of the read transistor Q7. A voltage of (VRD−VSS) is applied to a series circuit in which the capacitance of the body capacitor CF4 and the gate capacitance of the read transistor Q7 are connected in series.

  When the voltage (VRD-VSS) is applied to the series circuit of the capacitance of the fourth ferroelectric capacitor CF4 and the gate capacitance of the read transistor Q7, the voltage (VRD-VSS) is applied to the gate of the read transistor Q7 and the substrate. Between the first divided voltage VR from the point u to the point v and between the upper electrode and the lower electrode of the fourth ferroelectric capacitor CF4. Divided into a second divided voltage (VRD-VSS-VR).

  In FIG. 4, reference numeral 7 denotes a gate capacitance load line of the read transistor Q7 at the read operation point of data “0”. The position of the point v, that is, the magnitude of the first divided voltage VS is determined by the read transistor Q7 in the read operation. Depends on the gate capacitance. Further, the channel conductance of the read transistor Q7 when data “0” is read is determined by the first divided voltage VR.

  The fourth ferroelectric capacitor is set such that a relationship of VR> VT is established between the threshold voltage VT of the read transistor Q7 and the first divided voltage VR when data “0” is held. If the capacitance ratio between the capacitance value of CF4 and the gate capacitance value of the read transistor Q7 is set, the current value that flows from the reset line RST to the reset line RST through the channel of the load transistor Q8, the bit line BL, and the read transistor Q7. Becomes relatively large, so that the voltage change of the bit line BL can be increased. This voltage change is detected by a sense amplifier connected to the bit line BL, and the detected voltage change is compared with a preset reference voltage. When the detected voltage change exceeds the reference voltage, data “0” is stored. It is determined that it is held.

  Thereafter, when the potential of the read selection line / RE is set to the power supply voltage VDD, the read selection transistor Q6 is turned on, and the voltage applied to the fourth ferroelectric capacitor CF4 is set to zero, the ferroelectric capacitor CF4. The polarization charge of the following traces the region inside the hysteresis loop and reaches the position of the point w. The magnitude of the polarization charge held in the fourth ferroelectric capacitor CF4 after reading the data “0” is clearly smaller than the polarization charge before reading the data “0”.

  Therefore, the voltage of the set line SRD is forcibly returned to the ground voltage VSS before the read selection transistor Q6 is turned on and the voltage applied to the fourth ferroelectric capacitor CF4 is made zero. In this way, although the polarization charge of the fourth ferroelectric capacitor CF4 follows the region inside the hysteresis loop, the gate capacitance load line 8 of the read transistor Q7 has the fourth axis so as to intersect the vertical axis at the point q. Therefore, the polarization charge moves quickly from the point v to the point x.

  Here, since the slope of the gate capacitance load line of the read transistor Q7 is set to be sufficiently small, the polarization charge at the point x is slightly smaller than the polarization charge at the point q, but the polarization charge at the point x and the point q The magnitude is almost equal to the polarization charge. Therefore, after that, even if the potential of the read selection line / RE is set to the power supply voltage VDD, the read selection transistor is turned on, and the voltage applied to the fourth ferroelectric capacitor CF4 is zero, the data “ The magnitude of the polarization charge of the fourth ferroelectric capacitor CF4 held after reading “0” is almost the same as the magnitude of polarization before reading the data “0”.

  However, even if the decrease in polarization charge due to one read operation of data “0” is slight, if the read operation is repeated many times, the polarization charge at the point q may move toward the point p. In the read operation of data “0”, the voltage (VRD−VSS−VR) applied to the fourth ferroelectric capacitor CF4, that is, the voltage from the point q to the point v is the fourth strong voltage. Since it is set so as not to exceed the coercive voltage VC of the dielectric capacitor CF4, the polarization charge at the point q does not move above the origin O even if the data “0” is repeatedly read out. .

  The relationship of VR> VT> VS is established under the condition that the voltage (VRD−VSS−VR) applied to the fourth ferroelectric capacitor CF4 does not exceed the coercive voltage VC of the fourth ferroelectric capacitor CF4. It is possible to set the capacitance ratio between the capacitance value of the fourth ferroelectric capacitor CF4 and the gate capacitance value of the read transistor Q7.

  The above description is valid not only for the fourth ferroelectric capacitor CF4 but also for any ferroelectric capacitor.

  In the present embodiment, one memory cell block is configured by four memory cells, but the number of memory cells in the memory cell block can be arbitrarily set.

  Hereinafter, a circuit for generating a reference voltage used for determining whether data “1” is held or data “0” is held by comparing the voltage change of the bit line BL with the reference voltage. Will be described with reference to FIG.

  FIG. 5 shows the memory cell block shown in FIG. 2 and a reference voltage generation circuit composed of the reference block 0 and the reference block 1. The reference block 0 and the reference block 1 are the same as the memory cell block shown in FIG. Circuit configuration.

  The set line SRD is commonly connected to the block selection transistor Q5 of the memory cell block, the block selection transistor Q50 of the reference block 0, and the block selection transistor Q51 of the reference block 1, and the reset line RST is a read selection of the memory cell block. The transistor Q6, the read selection transistor Q60 of the reference block 0, and the read selection transistor Q61 of the reference block 1 are connected in common, and the read selection line / RE is connected to the read selection transistor Q6 of the memory cell block and the read selection transistor Q60 of the reference block 0. The gates of the read selection transistors Q61 of the reference block 1 are connected in common. Further, the tip of one end of the bit line BL of the memory cell block and the tip of each one end of the bit line BL0 of the reference block 0 and the bit line BL1 of the reference block 1 are connected to the sense amplifier SA.

  The reference block 0 stores data “0” in advance by the above-described data “0” writing method, and the reference block 1 stores data “1” in advance by the above-described data “1” writing method. Stored.

  During the read operation, data is read from the reference block 0 and the reference block 1 by the read method described above. When the bit line potential generated in the read operation of data “0” is VBL0 and the bit line potential generated in the read operation of data “1” is VBL1, the bit line BL0 of the reference block 0 and the bit line BL1 of the reference block 1 Generates a reference potential of (VBL0 + VBL1) × ½. The reference potential and the bit line potential generated in the memory cell block that performs the read operation are compared by the sense amplifier SA, and if the bit line potential does not exceed the reference potential, it is determined that the data “1” is held. If the bit line potential exceeds the reference potential, it is determined that the data “0” is held.

  In this case, the reference potential is set to an intermediate potential between the bit line potential VBL0 when the data “0” is held and the bit line potential VBL1 when the data “1” is held. The operating range is widened.

  The bit line potential VBL0 and the bit line potential VBL1 are generated from the ferroelectric capacitor of the reference block 0 and the ferroelectric capacitor of the reference block 1, which are located in the same row as the ferroelectric capacitor that reads data in the memory cell block. This is preferable because the influence of parasitic capacitance and the like can be made equal. Specifically, for example, when reading data held in the third ferroelectric capacitor CF3 in the memory cell block, the third ferroelectric capacitor CF30 in the reference block 0 and the third ferroelectric capacitor CF3 in the reference block 1 are read. The bit line potentials VBL0 and VBL1 are preferably generated from the data held in the ferroelectric capacitor CF31.

  The number of memory cell blocks in the reference blocks 0 and 1 is preferably the same as the number of memory cell blocks in the memory cell array. That is, in the circuit configuration shown in FIG. 5, only one memory cell block is connected to the bit line BL, bit line BL0, and bit line BL1, but for example, 10 memory cell blocks are connected to the bit line BL. In this case, it is preferable to connect 10 memory cell blocks to the bit line BL0 and the bit line BL1, respectively. In this way, stable operation is possible.

  According to the semiconductor memory device of the present invention, the area of the memory cell and thus the semiconductor memory device can be reduced, and the sensitivity for detecting the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor is improved. .

  According to the first method for driving a semiconductor memory device of the present invention, the area of the semiconductor memory device can be reduced.

  According to the second semiconductor memory device driving method of the present invention, a stable operation of the semiconductor memory device can be realized.

  According to the third, fourth, fifth, or sixth method for driving a semiconductor memory device according to the present invention, the retention characteristics of the semiconductor memory device are improved.

(A) is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment, and (b) is an equivalent circuit showing the configuration of the lowermost memory cell and read transistor of the semiconductor memory device according to the first embodiment. FIG. FIG. 5 is an equivalent circuit diagram of a semiconductor memory device according to a second embodiment. The behavior of the ferroelectric capacitor when the potential difference applied between the upper electrode and the lower electrode of the ferroelectric capacitor is removed after data is written in the semiconductor memory device according to the second embodiment will be described. FIG. It is a figure explaining the behavior of a ferroelectric capacitor when data is read from the semiconductor memory device according to the second embodiment. FIG. 6 is an equivalent circuit diagram for explaining a circuit for generating a reference potential in the semiconductor memory device according to the second embodiment. It is a circuit diagram of a conventional semiconductor memory device. It is a figure explaining the behavior of a ferroelectric capacitor when writing data in a conventional semiconductor memory device.

Explanation of symbols

6 Gate capacitive load line 7 Gate capacitive load line 8 Gate capacitive load line 10 Read transistor 11 Drain region 12 Source region 13 Gate electrode 14 Substrate 20 Select transistor 21 Drain region 22 Source region 23 Gate electrode 30 Ferroelectric capacitor 31 Upper electrode 32 Lower electrode 33 Ferroelectric capacitor WL1 First word line WL2 Second word line WL3 Third word line WL4 Fourth word line BS1 First control line (first set line)
BS2 Second control line (second set line)
RST reset line BL1 first bit line BL2 second bit line Q1 first cell selection transistor Q2 second cell selection transistor Q3 third cell selection transistor Q4 fourth cell selection transistor Q5 block selection transistor Q50 block selection Transistor Q51 Block selection transistor Q6 Read selection transistor Q60 Read selection transistor Q61 Read selection transistor Q7 Read transistor Q70 Read transistor Q71 Read transistor Q8 Load transistor Q80 Load transistor Q81 Load transistor CF1 First ferroelectric capacitor CF2 Second ferroelectric Capacitor CF3 Third ferroelectric capacitor CF4 Fourth ferroelectric capacitor WL1 First word line W 2nd word line WL3 3rd word line WL4 4th word line SRD set line RST reset line BS block selection line / BS read selection line BL bit line BL0 bit line BL1 bit line LS 1st control line LG 1st 2 control lines SA sense amplifier VDD power supply voltage VSS ground voltage VRD read voltage

Claims (17)

A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor;
A set line connected to the other end of the plurality of ferroelectric capacitors;
A bit line having one end connected to the drain of the read transistor and the other end connected to a control line;
One end side is connected to the source of the read transistor, a write voltage is applied at the time of writing, and a reset line to which a ground potential is applied at the time of reading;
A plurality of word lines provided to correspond to each of the plurality of ferroelectric capacitors and selecting a ferroelectric capacitor for writing or reading data from the plurality of ferroelectric capacitors. A semiconductor memory device. A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor;
A set line connected to the other end of the plurality of ferroelectric capacitors;
A bit line having one end connected to the drain of the read transistor and the other end connected to a control line;
One end side is connected to the source of the read transistor, a write voltage is applied at the time of writing, and a reset line to which a ground potential is applied at the time of reading;
A plurality of word lines provided corresponding to each of the plurality of ferroelectric capacitors and selecting a ferroelectric capacitor for writing or reading data from the plurality of ferroelectric capacitors;
A first divided voltage obtained by dividing the read voltage applied to the set line based on the ratio of the capacitance value of the ferroelectric capacitor and the gate capacitance value of the read transistor is induced at the gate of the read transistor. ,
The read voltage is VR>VT> VS (where VT is the threshold voltage of the read transistor, and VS is the gate of the read transistor when data is written to the selected ferroelectric capacitor. VR is a first divided voltage induced at the gate of the read transistor when data is not written in the selected ferroelectric capacitor. A semiconductor memory device characterized in that it is set to such a size that the relationship holds. 2. The semiconductor device according to claim 1, further comprising a plurality of selection transistors connected in parallel to each of the plurality of ferroelectric capacitors and each gate connected to each of the plurality of word lines. 2. The semiconductor memory device according to 2. Between the upper electrode and the lower electrode of the ferroelectric capacitor, a read voltage applied to the set line is divided based on a ratio between a capacitance value of the ferroelectric capacitor and a gate capacitance value of the read transistor. A second divided voltage is induced,
3. The semiconductor memory device according to claim 1, wherein the read voltage is set such that the second divided voltage does not exceed a coercive voltage of the ferroelectric capacitor. 3. The semiconductor memory device according to claim 1, further comprising a resistive load having one end connected to the other end of the bit line. 6. The semiconductor memory device according to claim 5, wherein the resistive load is a MOS transistor. A power supply voltage is applied to the other end of the resistive load,
A voltage change generated at both ends of the resistive load and a reference voltage due to a current flowing between the drain and the source of the read transistor which varies depending on the polarization deviation of the ferroelectric film of the selected ferroelectric capacitor 6. The semiconductor memory device according to claim 5, further comprising comparison means for comparing the two. Another memory cell block having the same configuration as the memory cell block and arranged in the word line direction of the memory cell block;
One end side includes another bit line connected to the drain of another read transistor constituting the other memory cell block,
The set line is also connected to the other end side of the plurality of ferroelectric capacitors constituting the other memory cell block,
The reset line is also connected to the source of the other read transistor constituting the other memory cell block,
When a read voltage is applied to the set line, a first voltage change generated at both ends of the one resistive load due to a current flowing between the drain and source of the read transistor, and a drain of the other read transistor 3. The semiconductor memory device according to claim 1, further comprising a comparison unit that compares a second voltage change generated across the other resistive load due to a current flowing between the first and second sources. . A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor, and a set line connected to the other end of the plurality of ferroelectric capacitors A bit line having one end connected to the drain of the read transistor and the other end connected to the control line, a reset line having one end connected to the source of the read transistor, and each of the plurality of ferroelectric capacitors And a plurality of word lines for selecting the selected ferroelectric capacitor. A method of driving a device,
When writing data to the selected ferroelectric capacitor, the voltage applied to the set line and the reset line is a writing process in which any one of a power supply voltage and a ground voltage is applied. A method for driving a semiconductor memory device, comprising: After the writing step, the method further includes a step of removing the potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the set line. The method of driving a semiconductor memory device according to claim 9. A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor, and a set line connected to the other end of the plurality of ferroelectric capacitors One end side is connected to the drain of the read transistor, the other end side is connected to the control line, and one end side is connected to the source of the read transistor. A reset line to which a potential is applied and a plurality of the ferroelectric capacitors are provided so as to correspond to each other. A method of driving a semiconductor memory device and a plurality of word lines for selecting the ferroelectric capacitor selected,
Erasing data written in the selected ferroelectric capacitor,
A ground voltage is applied to the set line and a power supply voltage is applied to the reset line, and the power supply voltage is subtracted from the ground voltage between the upper electrode and the lower electrode of the selected ferroelectric capacitor. Directing a direction of polarization of the ferroelectric film of the selected ferroelectric capacitor in a direction of a potential gradient of the potential difference by applying a potential difference; and
And thereafter removing the potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the reset line. For driving a semiconductor memory device. A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor, and a set line connected to the other end of the plurality of ferroelectric capacitors A bit line having one end connected to the drain of the read transistor and the other end connected to the control line, a reset line connected to the source of the read transistor at one end and a write voltage at the time of writing, A plurality of ferroelectric capacitors are provided corresponding to each of the plurality of ferroelectric capacitors, and the selected ferroelectric capacitor is selected. A method of driving a semiconductor memory device and a plurality of word lines,
Reading data from the selected ferroelectric capacitor comprises:
A power supply voltage is applied to the bit line and a ground potential is applied to the reset line, or a ground voltage is applied to the bit line and a power supply potential is applied to the reset line, and a read voltage is applied to the set line. Detecting a change in voltage generated in the bit line,
Thereafter, a step of removing a potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the set line,
2. The method of driving a semiconductor memory device according to claim 1, wherein the read voltage has such a magnitude that when the read voltage is removed, the polarization of the ferroelectric film is not reversed and the read data is not destroyed. The method of driving a semiconductor memory device according to claim 12, further comprising a step of turning off the read transistor after the step of removing the potential difference. A plurality of ferroelectric capacitors for storing data by deviation of polarization of the ferroelectric film, and a gate are connected to one end side of the plurality of ferroelectric capacitors, and selected from the plurality of ferroelectric capacitors. A memory cell block having a read transistor for reading data by detecting a polarization deviation of the ferroelectric film of the ferroelectric capacitor, and a set line connected to the other end of the plurality of ferroelectric capacitors A bit line having one end connected to the drain of the read transistor and the other end connected to the control line, a reset line connected to the source of the read transistor at one end and a write voltage at the time of writing, A plurality of ferroelectric capacitors are provided corresponding to each of the plurality of ferroelectric capacitors, and the selected ferroelectric capacitor is selected. A method of driving a semiconductor memory device and a plurality of word lines,
In the step of reading data from the selected ferroelectric capacitor, a power supply voltage is applied to the other end of the resistive load and a ground voltage is applied to the reset line, or a ground is connected to the other end of the resistive load. When a voltage is applied and a ground voltage is applied to the reset line and a read voltage is applied to the set line, a current flowing between the drain and source of the read transistor is generated at both ends of the resistive load. Comparing the voltage change with a reference voltage;
And removing a potential difference applied between the upper electrode and the lower electrode of the selected ferroelectric capacitor by applying a ground voltage to the set line,
2. The method of driving a semiconductor memory device according to claim 1, wherein the read voltage has such a magnitude that when the read voltage is removed, the polarization of the ferroelectric film is not reversed and the read data is not destroyed. 15. The method of driving a semiconductor memory device according to claim 14, further comprising a step of turning off the read transistor after the step of removing the potential difference. The semiconductor memory device has a configuration similar to that of the memory cell block, and other memory cell blocks arranged in the word line direction of the memory cell block, and other one of which one end side configures the other memory cell block A plurality of ferroelectrics that are connected to the drain of the read transistor and have the other end connected to one end of another resistive load, and the set line constitutes the other memory cell block In addition to being connected to the other end side of the capacitor, the reset line is also connected to the source of the other read transistor constituting the other memory cell block,
The reference voltage may be a power supply voltage applied to the other end of the other resistive load and a ground voltage applied to the reset line, or a ground voltage applied to the other end of the other resistive load. Further, when a ground voltage is applied to the reset line and a read voltage is applied to the set line, a current flowing between the drain and source of the other read transistor is generated at both ends of the other resistive load. The method of driving a semiconductor memory device according to claim 14, wherein the voltage change is a change in voltage. In the step of reading data, when none of the plurality of ferroelectric capacitors constituting the memory cell block is selected when reading data, the read transistor constituting the memory cell block is turned off. 15. The method of driving a semiconductor memory device according to claim 12, wherein:

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