JP2005107233A - Display device and driving method for display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of performing high quality display and a driving method for a display panel. <P>SOLUTION: An organic electro luminescence display 1 is equipped with an organic electro luminescence display panel 2, pixels P<SB>i, j</SB>are arranged like a matrix in the organic electro luminescence display panel 2 and the pixels P<SB>i, j</SB>are provided with organic EL elements E<SB>i, j</SB>and pixel circuits D<SB>i, j</SB>. The organic electro luminescence display panel 2 is driven by a data driver 3, a selection scanning driver 5 and a voltage supply driver 6. When the pixel circuits D<SB>i, j</SB>are selected by the selection scanning driver 5, they hold in a transistor 23 voltage at a level according to size of tone specification current which flows to a signal line Y<SB>j</SB>. The pixel circuits D<SB>i, j</SB>supply drive current with size according to a voltage level of the transistor 23 to the organic El elements E<SB>i, j</SB>in a luminescence period. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention includes a display panel driving method for driving a display panel including a light emitting element whose luminance is uniquely determined when the magnitude of a flowing current is determined for each pixel, and the display panel, a data driver, and a scan driver. The present invention also relates to a display device that drives the display panel with the data driver and the scan driver.

  In general, there are two types of liquid crystal displays: an active matrix driving type and a simple matrix driving type. In an active matrix liquid crystal display, high brightness, high contrast, and high definition screen display is performed as compared with a simple matrix liquid crystal display. In an active matrix liquid crystal display, a liquid crystal element that also functions as a capacitor and a transistor that functions as a switching element are provided for each pixel. In the active matrix driving method, when a scan line is selected by a scan driver that is a shift register and a voltage indicating a level is applied to a signal line by a data driver, the voltage is applied to the liquid crystal element through a transistor. Is done. The liquid crystal element functions as a capacitor even if the transistor is turned off after the selection of the scanning line until the next selection of the scanning line. The voltage level is maintained until the scanning line is selected. As described above, when the scanning line is selected, the light transmittance of the liquid crystal element is newly refreshed, and the backlight light is transmitted through the liquid crystal element with the refreshed light transmittance. Gradation expression is performed.

  On the other hand, an organic electroluminescence display using an organic EL (Electro Luminescence) element, which is a self-luminous element, does not require a backlight unlike a liquid crystal display, and is optimal for thinning. Since there is no restriction on the viewing angle, it is expected to be put to practical use as a next-generation display device.

From the viewpoint of high brightness, high contrast, and high definition, an organic electroluminescence display of an active matrix driving system has been developed as well as a liquid crystal display. For example, in the conventional active matrix driving type organic electroluminescence display described in Patent Document 1, an organic EL element, a current control transistor connected to the organic EL element, and switching of the current control transistor are performed. A switching transistor is provided for each pixel. In this organic electroluminescence display, when a voltage having a level representing luminance is applied to the signal line by the X-direction peripheral drive circuit when the scanning line is selected by the Y-direction peripheral drive circuit, the switching transistor is turned on. By applying the voltage of the signal line to the gate of the current control transistor, luminance data is written to the gate of the current control transistor. As a result, the current control transistor is turned on, and a drive current having a magnitude corresponding to the level of the gate voltage flows from the power source to the organic EL element through the current control transistor, and the organic EL element corresponds to the magnitude of the current. Emits light with high brightness. From the end of the selection of the scanning line to the next selection of the scanning line, even if the switching transistor is turned off, the level of the gate voltage of the current control transistor is maintained, and the organic EL element Light is emitted with luminance according to the magnitude of the drive current according to the voltage.
JP-A-8-330600 (FIG. 4)

  By the way, in general, a transistor has a channel resistance that changes due to a change in ambient temperature, or a channel resistance that changes due to long-term use. Different. Therefore, in the conventional active matrix driving type organic electroluminescence display, the magnitude of the current flowing in the organic EL element is changed by changing the level of the gate voltage of the current control transistor, in other words, for current control. Even when the luminance of the organic EL element is changed by changing the level of the voltage applied to the gate of the transistor, the magnitude of the current flowing through the organic EL element is uniquely determined by the level of the gate voltage of the current control transistor. It is difficult to specify. That is, even when the same level of gate voltage is applied to the current control transistor between pixels, the light emission luminance of the organic EL element differs between pixels, resulting in variations within the display surface.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display device and a display panel driving method capable of performing high-quality display.

In order to solve the above problems, the display device of the present invention provides:
A plurality of light emitting elements disposed at each intersection of a plurality of scanning lines and a plurality of signal lines substantially perpendicular to the plurality of scanning lines, and emitting light at a luminance according to the magnitude of a flowing current;
A selective scanning driver for sequentially selecting the plurality of scanning lines;
A data driver that causes a designated current of a magnitude according to a video signal to flow through the plurality of signal lines when the plurality of scanning lines are selected by the selection scanning driver;
When the selection scan driver sequentially selects the plurality of scan lines, the designated current reference voltage is applied to the plurality of signal supply lines, and the selection scan driver finishes sequentially selecting the plurality of scan lines. A voltage supply driver that later applies a reference voltage for drive current to the plurality of signal supply lines;
The signal supply circuit is provided around each of the plurality of light emitting elements, and the voltage supply driver applies a reference voltage for a specified current to the signal supply line when the scanning line is selected by the selection scanning driver. The designated current flowing from the line to the signal line is converted into a voltage level, and the voltage supply driver drives the signal supply line after the selected scan driver finishes selecting the plurality of scan lines sequentially. And a plurality of pixel circuits for applying a current reference voltage to cause the drive current having a magnitude according to the level of the converted voltage to flow through the light emitting element.

  After the voltage supply driver applies the drive current reference voltage to the plurality of signal supply lines, the selection scan driver sequentially selects the plurality of scan lines again and the voltage supply driver again sets the designated current reference voltage. It is preferable to apply to the plurality of signal supply lines.

Each of the plurality of pixel circuits is
While the voltage supply driver is applying the reference voltage for the designated current to the plurality of signal supply lines, the designated current that flows through the signal line is supplied to itself when the scanning line is selected by the selected scanning driver. By converting the magnitude of the specified current into a voltage level,
While the voltage supply driver is applying the reference voltage for the designated current to the plurality of signal supply lines, the designated current flowing through the signal line is cut off when the scanning line is not selected by the selected scanning driver. Holding the level of the converted voltage;
After the selection scan driver finishes sequentially selecting the plurality of scan lines, the voltage supply driver applies a reference voltage for drive current to the signal supply line to drive according to the held voltage level. It is preferable to pass a current through the light emitting element.

  It is preferable that the light emitting element is an organic electroluminescence element, and an anode of the organic electroluminescence element is connected to the pixel circuit.

Each of the plurality of pixel circuits is
A first transistor having a gate connected to the scan line and one of a drain and a source connected to the signal line;
A second transistor having a gate connected to the scan line and one of a drain and a source connected to the signal supply line;
The gate is connected to the other of the drain and source of the second transistor, one of the drain and source is connected to one of the drain and source of the second transistor, and the other of the drain and source is And a third transistor connected to the other of the drain and the source of the first transistor and connected to the anode of the organic electroluminescence element.

When the selected scan driver selects the scan line and turns on the first transistor while the voltage supply driver is applying the designated current drive voltage to the plurality of signal supply lines, the first transistor is turned on. One transistor causes a specified current to flow from the voltage supply driver to the signal line through the drain-source of the third transistor, so that the third transistor can reduce the magnitude of the specified current to the level of the gate-source voltage. Converted,
When the selection scan driver does not select the scan line and the first transistor is turned off while the voltage supply driver is applying the designated current drive voltage to the plurality of signal supply lines, The second transistor maintains the level of the gate-source voltage converted by the third transistor;
When the voltage supply driver is applying a reference voltage for driving current to the plurality of signal supply lines after the selection scan driver finishes sequentially selecting the plurality of scan lines, the third transistor holds the holding voltage. It is preferable that a driving current having a magnitude according to the level of the measured voltage is supplied from the signal supply line to the organic electroluminescence element.

  A reference voltage for specified current applied to the plurality of signal supply lines by the voltage supply driver is set to be equal to or lower than a voltage of a cathode of the organic electroluminescence element, and is applied to the plurality of signal supply lines by the voltage supply driver. It is preferable that the drive current reference voltage is set so as to exceed the voltage of the cathode of the organic electroluminescence element.

And another display device of the present invention is:
A scanning line group having a scanning line of the first row and a scanning line of the second row;
A first optical element that is connected to the scanning line of the first row and emits light according to the current value of the flowing driving current, and a second optical element that is connected to the scanning line of the second row and emits light according to the current value of the flowing driving current. An optical element group comprising: an optical element;
A first pixel circuit that is connected to the first optical element and flows a drive current equal to the current value of the specified current that flows, and a second pixel circuit that is connected to the second optical element and flows a drive current equal to the current value of the specified current that flows. A pixel circuit group having a pixel circuit;
A reference voltage for a specified current is applied in each selection period of the scanning line group, and after the selection period of the second scanning line after the selection period of the first scanning line, the first row A power source for applying a driving current reference voltage for flowing the driving current to the pixel circuit group in the second row and the second row;
Is provided.

  The power supply outputs the drive current reference voltage to all the pixel circuits in synchronization, thereby minimizing the number of times the drive current reference voltage is applied in one frame period composed of the selection period and the light emission period. Therefore, power consumption due to switching between the designated current reference voltage and the drive current reference voltage can be minimized.

  The designated current reference voltage is preferably lower than the drive current reference voltage.

The display panel driving method of the present invention includes:
A plurality of light emitting elements disposed at each intersection of a plurality of scanning lines and a plurality of signal lines substantially perpendicular to the plurality of scanning lines and emitting light at a luminance according to the magnitude of a flowing current; and the plurality of light emitting elements A pixel circuit provided around each of the display panels, and a display panel comprising:
Sequentially selecting the plurality of scan lines;
When each of the plurality of scanning lines is selected, a designated current having a magnitude according to a video signal is passed through the plurality of signal lines,
When the selection scan driver sequentially selects the plurality of scan lines, the designated current reference voltage is applied to the plurality of signal supply lines, and the selection scan driver finishes sequentially selecting the plurality of scan lines. Later, a reference voltage for driving current is applied to the plurality of signal supply lines,
By applying a reference voltage for a specified current to the signal supply line when the scanning line is selected, the magnitude of the specified current flowing from the signal supply line to the signal line is converted to a voltage level by the pixel circuit. Then, after the selection of the plurality of scanning lines is completed, a driving current reference voltage is applied to the signal supply line to thereby generate a driving current having a magnitude according to the level of the converted voltage. The light is sent to the light emitting element by a circuit.

  In the present invention, when a plurality of scanning lines are sequentially selected, a designated current voltage is applied to the plurality of signal supply lines. When a certain scanning line is selected, the designated current voltage is applied to the signal supply line, so that the designated current flowing through the signal line flows to the pixel circuit, and the magnitude of the designated current is the voltage by the pixel circuit. Is converted to the level. By sequentially selecting a plurality of scanning lines, each pixel circuit converts the magnitude of the designated current into a voltage level in a row-sequential manner, and when the selection of the plurality of scanning lines is completed. In all pixel circuits, the magnitude of the designated current is converted into a voltage level. When the plurality of scanning lines are sequentially selected, the driving current reference voltage is applied to the plurality of signal supply lines, so that each pixel circuit is driven with a magnitude according to the level of the converted voltage. A current is passed through the light emitting element. As a result, when the selection of a plurality of scanning lines is completed, all the light emitting elements emit light, but the magnitude of the drive current is in accordance with the voltage level converted by the pixel circuit, and the voltage level is the specified current. Therefore, the light emitting element emits light with luminance depending on the magnitude of the designated current.

  According to the present invention, when the plurality of scanning lines are sequentially selected, all the light emitting elements emit light, but the light emitting elements emit light with a luminance depending on the magnitude of the designated current. In other words, since the light emitting element emits light with a desired luminance according to the magnitude of the designated current, if the designated current level is the same among the pixels, there is no luminance variation among the plurality of light emitting elements, High-quality screen display can be performed.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

FIG. 1 is a view showing an organic electroluminescence display 1 in an embodiment to which an organic electroluminescence display of the present invention is applied. As shown in FIG. 1, the organic electroluminescence display 1 has, as a basic configuration, selection scanning lines X _{1 to} X _m , signal supply lines Z _{1 to} Z _m , signal lines Y _{1 to} Y _n, and pixels P _1,1. to P m, the organic electroluminescent display panel 2 equipped with a _n, a selection scanning driver 5 sequentially selects the selection scan lines X ₁ to X _m, the selection scanning lines X ₁ to X _m is selected, each Sometimes, the data driver 3 that sends the gradation designation current I _DATA to the signal lines Y _{1 to} Y _n and the selective scanning driver 5 sequentially selects the selective scanning lines X _{1 to} X _m (non-light emission period to be described later) the gradation designating current reference voltage V _LOW is applied to the T _NL) to the selection scan line X ₁ to X _m, after completion of that the selection scanning driver 5 sequentially selects the selection scan lines X ₁ to X _m (later emission period T _L) in the selection scanning lines X ₁ to X _m on the driving current for groups And voltage supply driver 6 applies the voltage V _HIGH, the switching circuit 7 to switch the output to the signal line Y ₁ to Y _n from the gradation designating current I _DATA or vice versa to the reset voltage V _R, the data driver 3, selection scanning And a controller 11 for controlling the driver 5, the voltage supply driver 6 and the switching circuit 7.

  The organic electroluminescence display panel 2 has a structure in which a display portion 4 on which an image is substantially displayed is provided on a transparent substrate 8. A selective scanning driver 5, a data driver 3, and a voltage supply driver 6 are disposed around the display unit 4. The selective scanning driver 5 and the data driver 3 may be provided on the transparent substrate 8, or may be provided on a circuit board disposed around the transparent substrate 8.

In the display unit 4, (m × n) pixels P _{1,1 to} P _{m, n} are provided in a matrix on the transparent substrate 8, and m pixels P are arranged in the vertical direction, that is, in the column direction. _{i, j} are arranged, and n pixels P _{i, j} are arranged in the horizontal direction, that is, in the row direction. Here, m and n are natural numbers of 2 or more, i is an arbitrary natural number of 1 to m, and j is an arbitrary natural number of 1 to n. Accordingly, the pixel that is i-th (that is, i-th row) vertically and j-th (that is, j-th column) is the pixel P _{i, j} .

In the display unit 4, m selection scanning lines X _{1 to} X _m extending in the row direction are arranged on the transparent substrate 8 in the column direction. M signal supply lines Z _{1 to} Z _m extending in the row direction are arranged on the transparent substrate 8 and arranged in the column direction so as to correspond to the selected scanning lines X _{1 to} X _m . Each signal supply line Z _k (1 ≦ k ≦ m−1) is arranged between the selected scanning line X _k and the selected scanning line X _{k + 1,} and the selected scanning line X _m is connected to the signal supply line Z _m−1 . It is disposed between the signal supply line Z _m. Further, the signal lines Y ₁ to Y _n of the n extending in the column direction are provided on the transparent substrate 8 are arranged in the row direction. These selection scanning lines X _{1 to} X _m , signal supply lines Z _{1 to} Z _m, and signal lines Y _{1 to} Y _n are insulated from each other by an intervening insulating film or the like. N pixels P _{i, 1 to} P _{i, n} arranged in the row direction are connected to the selected scanning line X _i and the signal supply line Z _i , and arranged in the column direction to the signal line Y _j. The m pixels P _{1, j to} P _{m, j} are connected, and the pixel P _{i, j} is arranged at the intersection of the selected scanning line X _i and the signal line Y _j . The selection scanning lines X _{1 to} X _m are connected to the respective output terminals of the selection scanning driver 5, and the signal supply lines Z _{1 to} Z _m are electrically connected to each other and connected to the output terminal of the voltage supply driver 6. That is, the same signal is output to all of the signal supply lines Z _{1 to} Z _m .

Incidentally, instead, the selection scanning lines X ₁ to X _m substantially perpendicular to the selected scanning lines X ₁ to X _m are parallel and the signal supply lines Z ₁ to Z _m and the signal lines Y ₁ to Y _n The plurality of signal supply lines may be substantially perpendicular to the signal lines Y _{1 to} Y _n . In this case, the number of signal supply lines is n, the signal lines Y _{1 to} Y _n and a plurality of signal lines are alternately arranged, and the selected scanning line X _i includes n pixels arranged in the row direction. P _{i, 1 to} P _{i, n} are connected, and m pixels P _{1, j to} P _{m, j} arranged in the column direction are connected to the signal line Y _j to supply signals in arbitrary j columns. The lines are connected to _m pixels P _{1, j to} P _{m, j} arranged in the column direction, and the plurality of signal supply lines are electrically connected to each other and connected to the voltage supply driver 6.

Next, the pixels P _{1,1 to} P _{m, n} will be described with reference to FIGS. FIG. 2 is a plan view showing the pixel P _{i, j} , and FIG. 3 shows four adjacent pixels P _{i, j} , P _{i + 1, j} , P _{i, j + 1} , P _{i + 1, j +. 1 is} an equivalent circuit diagram of 1. FIG. In FIG. 2, the electrodes in the pixels P _{i, j} are mainly shown for easier understanding.

The pixel P _{i, j} is provided in the vicinity of an organic electroluminescence (Electro Luminescence) element E _{i, j} as a self-luminous element that emits light with luminance according to the magnitude of the current _, and the organic EL element E _{i, j.} And a pixel circuit D _{i, j} for driving the organic electroluminescence element E _{i, j} . Hereinafter, the organic electroluminescence element is abbreviated as an organic EL element.

The organic EL element E _{i, j} transports holes and electrons injected by an electric field with the pixel electrode 51 functioning as an anode, recombines the transported holes and electrons, and excitation generated by the recombination. The organic EL layer 52 that functions as a light emitting layer in a broad sense that emits light by supplementing a child and the common electrode that functions as a cathode are stacked on the transparent substrate 8 in this order.

The pixel electrode 51 is patterned so as to be divided for each pixel P _{i, j in} each surrounding area surrounded by the signal lines Y _{1 to} Y _n and the selection scanning lines X _{1 to} X _m .

The pixel electrode 51 has conductivity and is transmissive to visible light. In addition, the pixel electrode 51 has a relatively high work function, and is preferably one that injects holes into the organic EL layer 52 efficiently. Examples of the pixel electrode 51 include tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO). ).

An organic EL layer 52 is formed on each pixel electrode 51. The organic EL layer 52 is also patterned for each of the pixels P _{1,1 to} P _m , _n . Although the organic EL layer 52 contains a light emitting material (phosphor) that is an organic compound, the light emitting material may be a high molecular material or a low molecular material. The organic EL layer 52 has a two-layer structure in which a hole transport layer and a narrowly-defined light emitting layer are sequentially stacked from the pixel electrode 51. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light-emitting layer in a narrow sense is made of a polyfluorene-based light-emitting material. In addition to the two-layer structure, the organic EL layer 52 may have a three-layer structure that becomes a hole transport layer, a narrow light-emitting layer, and an electron transport layer in order from the pixel electrode 51, or from a narrow light-emitting layer. It may be a single layer structure, a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

The organic electroluminescence display panel 2 can perform full-color display or multi-color display. In this case, the organic EL layer 52 of each pixel P _{i, 1 to} P _{i, n} is, for example, any one of red, green, and blue It is a broad light-emitting layer having a function of emitting light. That is, the organic EL layer 52 of each of the pixels P _{i, 1 to} P _{i, n} selectively emits light in red, green, and blue, so that these colors can be displayed in a combined color tone.

  The organic EL layer 52 is preferably an electronically neutral organic compound, whereby holes and electrons are injected and transported in a balanced manner in the organic EL layer 52. In addition, an electron transporting substance may be appropriately mixed in the narrowly defined light emitting layer, a hole transporting substance may be appropriately mixed in the narrowly defined light emitting layer, and the electron transporting substance and the positive transporting substance may be mixed. A hole transporting substance may be appropriately mixed in the light-emitting layer in a narrow sense. Alternatively, the charge transport layer which is an electron transport layer or a hole transport layer may function as a recombination region for recombining electrons and holes, and light may be emitted by mixing phosphors in the charge transport layer.

The common electrode formed on the organic EL layer 52 is a single electrode formed in common for all the pixels P _{1,1 to} P _{m, n} . Instead of the common electrode common to all the pixels P _{1,1 to} P _{m, n} , the pixels P _{1, h-1 to} P _{m, h-1} (h is an arbitrary natural number) in the column direction. And 2 ≦ h ≦ n) the stripe-shaped common electrodes connecting the groups, the stripe-shaped common electrodes connecting the pixels P _{1, h to} P _{m, h} groups in the column direction, and so on. A plurality of stripe-shaped electrodes connected to each other may be used. In addition, a stripe-shaped common electrode that connects groups of pixels P _{g-1,1 to} P _{g-1, n} (g is an arbitrary natural number and 2 ≦ g ≦ m) in the row direction, May be a stripe-shaped common electrode that connects the pixels P _{1,1 to} P _{g, n,} and a plurality of stripe-shaped electrodes that are connected for each row.

In any case, the common electrode is electrically insulated from the selection scanning lines X _{1 to} X _m , the signal lines Y _{1 to} Y _n , and the signal supply lines Z _{1 to} Z _m . The common electrode is formed of a material having a low work function, for example, a single element or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal. In addition, the common electrode may have a laminated structure in which layers of the above various materials are laminated, or may have a laminated structure in which a metal layer is deposited in addition to the above layers of various materials. Includes a laminated structure of a low-work-function high-purity barium layer provided on the interface side in contact with the organic EL layer 52 and an aluminum layer provided so as to cover the barium layer, a lower layer including a lithium layer, an upper layer And a laminated structure in which an aluminum layer is provided. In addition, when the pixel electrode 51 is a transparent electrode and light emitted from the organic EL layer 52 is emitted from the transparent substrate 8 side through the pixel electrode 51, the common electrode has a light shielding property against the light emitted from the organic EL layer 52. It is more preferable that the light emitted from the organic EL layer 52 has high reflectivity.

In the organic EL element E _{i, j} having a stacked structure as described above, when a forward bias voltage (the pixel electrode 51 has a higher potential than the common electrode) is applied between the pixel electrode 51 and the common electrode, holes are formed. Are injected from the pixel electrode 51 into the organic EL layer 52, and electrons are injected from the common electrode into the organic EL layer 52. Then, holes and electrons are transported in the organic EL layer 52, and excitons are generated by recombination of the holes and electrons in the organic EL layer 52. The excitons excite the organic EL layer 52, The organic EL layer 52 emits light.

The organic EL element E _i, the emission luminance of the _j depends on the magnitude of the current flowing the organic EL element E _i, in _j, also the light emission luminance as the flowing current increases to increase. In other words, the organic EL element E _i, to be taken into account the deterioration of _j, the organic EL element E _i, the magnitude of the drive current flowing to _j is determined, the organic EL element E _i, the luminance of _j is determined uniquely.

Each pixel circuit D _{i, j} includes three thin film transistors (hereinafter simply referred to as transistors) 21, 22, and 23, and a capacitor 24.

  The transistors 21, 22, and 23 are N-channel MOS type field effect transistors each including a gate, a drain, a source, a semiconductor layer, an impurity semiconductor layer, a gate insulating film, and the like. In particular, amorphous silicon is used as a semiconductor layer (channel region). However, it may be a p-Si transistor using polysilicon as a semiconductor layer. Any of the transistors 21, 22, and 23 is an N-channel field effect transistor. The structure of the transistors 21, 22, and 23 may be an inverted stagger type or a coplanar type.

  The transistors 21, 22, and 23 may be formed at the same time in the same process. In this case, the composition of the gate, drain, source, semiconductor layer, impurity semiconductor layer, gate insulating film, and the like is the same as that of the transistors 21, 22, and 23. The transistor 21, 22, 23 has the same shape, size, dimension, channel width, channel length, and the like depending on the functions of the transistors 21, 22, 23. Hereinafter, the transistor 21 is referred to as a first transistor 21, the transistor 22 is referred to as a second transistor 22, and the transistor 23 is referred to as a third transistor 23.

  The capacitor 24 includes an electrode connected to the gate 23g of the third transistor 23, an electrode connected to the source 23s of the transistor 23, and an insulating film (dielectric film) interposed between these two electrodes. The third transistor 23 has a function of accumulating charges between the gate 23g and the source 23s.

In each second transistor 22 of the _i-th pixel circuit D _{i, 1 to} D _{i, n} , the gate 22g is connected to the _i-th selection scanning line X _i , and the drain 22d is the i-th signal supply line. Connected to Z _i . In each third transistor 23 of the _i-th pixel circuit D _{i, 1 to} D _{i, n} , the drain 23d is connected to the _i-th signal supply line Z _i . In each of the first transistors 21 of the _i-th pixel circuits D _{i, 1 to} D _{i, n} , the gate 21g is connected to the _i-th selected scanning line X _i . In each first transistor 21 of the pixel circuit D _{1, j to} D _{m, j in} the j-th column, the source 21s is connected to the signal line Y _j in the j-th column.

In each pixel P _{i, j to} P _{m, n} , the source 22 s of the second transistor 22 is connected to the gate 23 g of the third transistor 23 through the contact hole 25 and to one electrode of the capacitor 24. ing. The source 23 s of the third transistor 23 is connected to the other electrode of the capacitor 24 and to the drain 21 d of the first transistor 21. The source 23s of the third transistor 23, the other electrode of the capacitor 24, and the drain 21d of the first transistor 21 are all connected to the pixel electrode 51 of the organic EL element E _{i, j} .

The voltage of the common electrode of the organic EL elements E _{1,1 to} Em _{, n} is kept constant at the reference voltage V _SS , and in this embodiment, the common voltage of the organic EL elements E _{1,1 to} Em _{, n} is common. The reference voltage V _SS is set to 0 [V] by grounding the electrode.

  Next, the controller 11, the selective scanning driver 5, the voltage supply driver 6, the switching circuit 7, and the data driver 3 will be described.

As shown in FIG. 1, the controller 11 includes a data driver clock signal CK1, a start signal ST1, and a latch signal based on a dot clock signal CK _DT , a horizontal synchronization signal H _SYNC , and a vertical synchronization signal V _SYNC input from the outside. outputs a control signal group D _CNT containing L data driver 3, selection scanning driver clock signal CK2, and outputs a control signal G _CNT including the start signal ST2 to the selection scanning driver 5, the clock signal CK3 for voltage supply driver Output to the voltage supply driver 6.

More specifically, the data driver clock signal CK1 is a signal for sequentially shifting the selected column in synchronization with the dot clock signal CK _DT , and an 8-bit red digital gradation video signal S _R , green from an external circuit. The digital gradation video signal S _G and the blue digital gradation video signal S _B are captured at the timing of the clock signal CK1. The start signal ST1 is a signal for returning the selected column to the first column in synchronization with the horizontal synchronization signal H _SYNC . The latch signal L is synchronized with the horizontal synchronization signal _HSYNC, and the digital converter video signal for red is captured by the DA converter in the data driver 3 for one row of data, that is, for the pixels P _{i, 1 to} P _{i, n.} S _R, green digital gradation video signal S _G, and blue digital tone image signal S _B analog gradation designating current signal line Y ₁ to Y I _DATA is in parallel based on the analog gradation designating signal analog conversion on the _This signal is made to flow through _n . The selection scanning driver clock signal CK2 is a signal for sequentially shifting the selected row in synchronization with the horizontal synchronization signal _HSYNC . The start signal ST2 is a signal for returning the selected row to the first row in synchronization with the vertical synchronization signal _VSYNC . The voltage supply driver clock signal CK3 is a clock signal having a longer cycle than the selective scanning driver clock signal CK2.

The selective scanning driver 5 is a so-called shift register, and has a configuration in which m flip-flop circuits and the like are connected in series. In other words, the selective scanning driver 5 is arranged in the order from the selective scanning line X ₁ to the selective scanning line X _m based on the selective scanning driver clock signal CK 2 input from the controller 11 (next to the selective scanning line X _m is the selective scanning line X ₁₎ to the on-level (high level) by the sequential output, it is to sequentially select the selection scan lines X ₁ to X _m.

In detail, as shown in FIG. 4, the selective scanning driver 5 uses a high level on voltage V _ON (which is sufficiently higher than the reference voltage V _SS ) or a low level off voltage V _OFF (reference voltage) as a selection signal. The selected scanning lines X _{1 to} X _m are sequentially selected by individually applying a voltage of any level of V _SS or less) to the selected scanning lines X _{1 to} X _m . Here, in FIG. 4, the horizontal axis represents time.

That is, the selection scanning driver 5 is set to apply the _ON voltage V _ON to the selection scanning line X _i as an ON level selection signal, and thereby the i-th selection scanning line X _i is selected. The selection scanning driver 5 applies the _ON voltage V _ON to the i-th selection scanning line X _i , and the period during which the i- _th selection scanning line X _i is selected is referred to as the i-th selection period T _SE . Called.

Each of the pixel circuits D _{i, 1 to} D _{i, n} connected to the _{i- th} selection scanning line X _i is applied by the selection scanning driver 5 applying the _ON voltage V _ON to the i-th selection scanning line X _i. Then, the transistors 21 and 22 are turned on. When the first transistor 21 is turned on, currents flowing through the signal lines Y _{1 to} Y _n can flow to the pixel circuits D _{i, j to} D _{i, n ,} respectively. On the other hand, in the non-selection period T _NSE other than the selection period T _SE in which the _i-th selection scan line X _i is selected, the selection scan driver 5 applies the off voltage V _OFF to the selection scan line X _i . Thereby, in each of the pixel circuits D _{i, 1 to} D _{i, n} connected to the _i-th selected scanning line X _i , the transistors 21 and 22 are turned off. The first transistor 21 that turned off, the current flowing through the signal line Y ₁ to Y _n are as not to flow into the pixel circuits D _{i, 1} to D i, _n, respectively. _{Here, T SE + T NSE = T} SC period represented by, that the next selection period from the start time of the first row of the selection scanning lines X ₁ of the first row of the selection scanning lines X ₁ of the selection period T _SE T The period up to the _SE start time is one scanning period, and the selection periods T _SE of the selected scanning lines X _{1 to} X _m do not overlap each other.

Further, from the i-th row of the end time of the selection period T _SE of the selection scan line X _i to the start time of the selection scan line X _{i + 1} of the selection period T _SE of the next line (i.e., the selection scanning driver 5 i-th row of the selection scanning line X _i from the end of the application of the oN voltage V _oN (i + 1) in the row of the selection scanning lines X _{i + 1} until a turn-on voltage is applied to V _oN), the time interval There are, this period is applied the off-voltage V _oFF (hereinafter, the reset period T _R and referred.) in the selection scanning driver 5 all selected scan lines X ₁ to X _m. Also, the period until the start time of the selection period T _SE of the m-th row selection scan line X _m of the selection period T _SE of the end time from the first row of the selection scanning lines X ₁ (m-th row of the reset period T _R) It is set to be longer than the reset period T _R of the other rows. The period until the start time of the m-th row selection scan line X _m of the selection period T selection period of the selection scanning lines X ₁ of the first row from the end time of the _SE T _SE, called emission period T _L, a line the period from the eyes of the start time of the selection period T _SE of the selection scan line X ₁ to the end time of the selection period T _SE of the m-th row selection scan line X _m, referred to as non-emission period T _NL. The sum of the light emission period T _L and the non-light emission period T _NL corresponds to one scanning period T _SC .

The voltage supply driver 6 is an independent power source for applying a stable rated voltage to all the signal supply lines Z _{1 to} Z _m , and a signal having a phase according to the clock signal CK 3 is applied to the signal supply lines Z _{1 to} Z _m . Output. That is, a period in which the selection scanning driver 5 is selected from the selection scan line X ₁ of the first row of the selection scan line X _m in the m-th row in this order, i.e. the non-emission period T _NL, the voltage supply driver 6 and the low level The gradation designation current reference voltage V _LOW is set to be applied to all the signal supply lines Z _{1 to} Z _m . On the other hand, the period until the selection scanning driver 5 selects the selection scan line X ₁ of the first row select the selection scan line X _m in the m-th row, i.e. in the emission period T _L, the gradation designating current reference The drive current reference voltage V _HIGH that is higher than the voltage V _LOW is set to be applied to all the signal supply lines Z _{1 to} Z _m .

Here, the signal output from the voltage supply driver 6 to the signal supply lines Z _{1 to} Z _m after the signal output to the selection scan line X _m of the m-th row by the selection scan driver 5 falls to the OFF voltage V _{OFF. Rises} from the reference voltage V _LOW for gradation designation current to the reference voltage V _HIGH for drive current. This time is the end of the non-light emission period T _NL and the start of the light emission period _TL . When the signal output from the voltage supply driver 6 to the signal supply lines Z _{1 to} Z _m falls from the high-level drive current reference voltage V _HIGH to the low-level grayscale specified current reference voltage V _LOW , the selective scanning driver 5 As a result, the signal output to the selected scanning line X ₁ in the first row rises to the _ON voltage V _ON . This time is the end of the light emission period T _L and one scanning period T _SC and the beginning of the next one scanning period T _SC and the next non-light emitting period T _NL .

In addition, after the voltage supply driver 6 applies the drive current reference voltage V _HIGH to the signal supply lines Z _{1 to} Z _m , the selection scanning driver 5 selects the first scanning line X ₁ to the mth scanning line. the X _m will choose, the voltage supply driver 6 applies again gradation designating current reference voltage V _LOW to signal supply lines Z ₁ to Z _m in the non-emitting period T _NL at that time. As described above, the voltage supply driver 6 applies the gradation specifying current reference voltage V _LOW to the signal supply lines Z _{1 to} Z _m and the drive current reference voltage V _HIGH to the signal supply lines Z _{1 to} Z _m . While the voltage supply driver 6 is applying the gradation designated current reference voltage V _LOW to the signal supply lines Z _{1 to} Z _m , the selection scan driver 5 selects the selection scan lines X ₁ to X. The scanning lines _Xm are selected sequentially.

Since the reference voltage V _LOW for gradation designation current applied by the voltage supply driver 6 is set to be lower than the reference voltage V _SS , the third transistor 23 of each pixel P _{i, j} is turned on during the non-light emission period T _NL. even in the state, the organic EL element E _i, the anode of the _j - from so that zero voltage or a reverse bias voltage is applied between the cathode, the organic EL element E _i, since no current flows to _j, The organic EL element E _{i, j} does not emit light. On the other hand, the drive current reference voltage V _HIGH applied by the voltage supply driver 6 is higher than the reference voltage V _SS , and the source-drain voltage V _{DS of} the third transistor 23 is in the saturation region as shown in FIG. Is set to Therefore, if the third transistor 23 is in the ON state during the light emission period T _L , a forward bias voltage is applied to the organic EL element E _{i, j} , and thus the organic EL from the signal supply line Z _i. A current flows to the element E _{i, j} , and the organic EL element E _{i, j} emits light.

The drive current reference voltage V _HIGH will be described. FIG. 5 is a graph showing current-voltage characteristics of an N-channel field effect transistor. In FIG. 5, the horizontal axis represents the drain-source voltage level, and the vertical axis represents the drain-source current level. Unsaturation region in the figure (region where source-drain voltage V _DS <drain saturation threshold voltage V _TH : drain saturation threshold voltage V _TH is a function of gate-source voltage V _GS , gate-source If the gate-source voltage V _GS is determined, the gate-source voltage V _GS is uniquely determined.) If the gate-source voltage V _GS is constant, the source-drain voltage V _DS increases as the source-drain voltage V _DS increases. The drain current _IDS increases. Further, in the saturation region (source-drain voltage V _DS ≧ drain saturation threshold voltage V _TH ) in the figure, if the gate-source voltage V _GS is constant, even if the source-drain voltage V _DS increases. The source-drain current _IDS is almost constant.

In FIG. 5, the gate-source voltages V _{GS0 to} V _GSMAX have a relationship of V _GS0 = 0 [V] <V _GS1 <V _GS2 <V _GS3 <V _GS4 <V _GSMAX . That is, as apparent from FIG. 5, when the drain-source voltage V _DS is constant, the drain-source voltage is increased in either the unsaturated region or the saturated region as the gate-source voltage V _GS increases. The current _IDS increases. Furthermore, as the gate-source voltage V _GS increases, the drain saturation threshold voltage V _TH increases.

From the above, in the unsaturated region, when the source-drain voltage V _DS slightly changes, the source-drain current I _DS changes, but in the saturated region, the drain-source voltage is increased by the gate-source voltage V _GS . The current I _DS is uniquely determined.

Here, the drain-source current I _DS when the maximum gate-source voltage V _GSMAX is applied to the third transistor 23 is _equal to the pixel electrode 51 of the organic EL element E _{i, j} that emits light with the maximum luminance. The current flowing between the common electrode is set.
Further, even if the gate-source voltage V _{GS of} the third transistor 23 is the maximum voltage V _GSMAX , the following conditional expression is satisfied so that the third transistor 23 maintains the saturation region.
V _HIGH −V _E −V _SS ≧ V _THMAX
Here, V _E is the voltage between the anode and the cathode required for emitting light at the maximum luminance from the organic EL element E _{i, j} during the light emission lifetime. V _THMAX is a saturation threshold voltage level between the source and the drain of the transistor 23 at the time of V _GSMAX . The drive current reference voltage V _HIGH is set so as to satisfy the above conditional expression. Therefore, the organic EL element E _i, which is connected to the third transistor 23 in _series, the partial pressure of the _j source of the third transistor 23 - even if the drain voltage V _DS is low, the source - drain voltage V _DS is always since the range of the saturated state, the source flows through the third transistor 23 - drain current I _DS will be uniquely determined by the gate-source voltage V _GS.

As shown in FIG. 1, the switching circuit 7 is constituted by a unit switching circuits S ₁ to S _n, the unit switch circuit S ₁ to S _n are respectively connected to the signal lines Y ₁ to Y _n, further data Current terminals CT _{1 to} CT _{n of the} driver 3 are connected to the unit switching circuits S _{1 to} S _n , respectively. Unit The switching circuit S ₁ to S _n, the switching signal φ and the reset voltage V _R output from the controller 11 is input.

The switching circuit S _j (the switching circuit S _j is connected to the signal line Y _j in the j-th column) causes the gradation designation current I _DATA from the data driver 3 to flow through the signal line Y _j and the controller 11. The reset voltage V _R is switched to one of application of the reset voltage V _R to the signal line Y _j . That is, when switching signal φ to be output from the controller 11 to the unit switch circuit S _j is at the high level, the unit switch circuit S _j is the signal the reset voltage V _R from the controller 11 while interrupting the current of the current terminal CT _j Output to line Y _j . On the other hand, when the switching signal φ to be output from the controller 11 to the unit switch circuit S _j is at the low level, the unit switch circuit S _j is the reset voltage from the controller 11 with electric current of the current terminal CT _j to the signal line Y _j to cut off the V _R. It should be noted that the relationship between the high / low of the switching signal φ and the output of the switching circuit S _j may be reversed.

An example of the switching circuit S _j will be described. The switching circuit S _j includes a P-channel field effect transistor 31 and an N-channel field effect transistor 32. The gate of the transistor 31 and the gate of the transistor 32 are connected to the controller 11, and the switching signal φ is input from the controller 11 to the gate of the transistor 31 and the gate of the transistor 32. The source of the transistor 31 is connected to the signal line Y _j , and the drain of the transistor 31 is connected to the current terminal CT _j . The drain of the transistor 32 is connected to the signal line _Yj . The source of the transistor 32 is connected to the controller 11, and the reset voltage V _R is input to the source of the transistor 32. In this configuration, when the switching signal φ output from the controller 11 is at a high level, the transistor 32 is turned on and the transistor 31 is turned off. On the other hand, when the switching signal φ output from the controller 11 is at a low level, the transistor 31 is turned on and the transistor 32 is turned off. Note that the switching of the unit switching circuit S _j may be switched by setting the transistor 31 to be a P-channel type and the transistor 32 to be an N-channel type, with the high and low of the switching signal φ being in opposite phases.

Here, the cycle of the switching signal φ output from the controller 11 to the switching circuit 7 will be described. As shown in FIG. 4, when the selective scanning driver 5 applies the on-voltage V _ON to any _{one of the} selective scanning lines X _{1 to} X _m (that is, the selection period T _SE of each row). In addition, the switching signal φ output from the controller 11 is at a low level. Meanwhile, when the selection scanning driver 5 applies a turn-off voltage V _OFF to all the selection scan line X ₁ to X _m (i.e., reset period T _R of each row), the switching signal output from the controller 11 φ is at a high level.

The current value of the gradation designating current I _DATA is emitting organic EL element E _i, an extremely small value to be equal to the current value of the current flowing in accordance with the luminance of the _j organic EL element E _i, the _j. Here, for the wiring capacitance of the signal lines Y ₁ to Y _n, the signal lines Y ₁ would be to Y _n delay gradation designating current I _DATA flows to occur, the only time during the selection period T _SE, the There has been a problem that the charge corresponding to the gradation designation current I _DATA cannot be charged up between the gate and source of the three transistors 23. Therefore, the signal lines Y _{1 to} Y _n are forcibly reset in the reset period T _R between the selection period T _{SE of} a certain selected scanning line X _{i and} the selection period T _SE of the next selected scanning line X _{i + 1.} since a voltage is applied to V _R, even especially when the current value of the gradation designating current I _DATA is small luminance gradation, the gate of the third transistor 23 in the selection period T _SE - gradation designating current between the source Charge according to I _DATA can be charged up.

Note that the switching circuit 7 may not be provided. In this case, the current terminals CT _{1 to} CT _n of the data driver 3 are connected to the signal lines Y _{1 to} Y _n , respectively.

As shown in FIG. 1, the current terminal CT ₁ to CT _n of the data driver 3 through the unit switch circuit S ₁ to S _n, respectively, the signal lines Y ₁ to Y _n, respectively are connected. The data driver 3 receives a control signal group _DCNT including a data driver clock signal CK1, a start signal ST1, and a latch signal L from the controller 11, and receives an 8-bit red digital gradation video signal S _R , green from an external circuit. The digital gradation video signal S _G for blue and the digital gradation video signal S _B for blue are captured. The digital signal taken into the data driver 3 is converted into an analog signal by a DA converter in the data driver 3. The data driver 3 via the gradation designating current I _DATA signal lines Y ₁ to Y each unit switching circuit from _n paths S ₁ to S _n based on the latch signal L and the analog converted signal, the data driver 3 controlled to flow towards the respective current terminals CT ₁ to CT _n. Specifically, the data driver 3 includes the third transistor 23 and the first transistor of the pixel circuits D _{i, 1 to} D _{i, n} from the signal supply line Z _i of the selected row in the selection period T _SE of each row. 21, each of the signal lines Y ₁ to Y _n, is intended to generate a gradation designating current I _DATA flows through each of the unit switching circuits S ₁ to S _n in each of the current terminals CT ₁ to CT _n. The gradation designation current I _DATA is an organic EL having a luminance according to a gradation video signal such as a digital gradation video signal S _R for red, a digital gradation video signal S _G for green, and a digital gradation video signal S _B for blue. to the light-emitting element E _{1, 1} to E m, _n-in the light-emitting period T _L, a same size as the current flowing through the light-emitting period T _L organic EL element E _{1, 1} to E m, the _n Te is a current flowing from the signal line Y ₁ to Y _n to the respective current terminals CT ₁ to CT _n.

Next, functions of the pixel circuits D _1,1 to D _{m, n} will be described with reference to FIGS. Here, in FIGS. 6 to 8, the flow of current is indicated by arrows.
FIG. 6 is a circuit diagram showing the current and voltage states in the selection period _TSE of the i-th row. As shown in FIG. 6, in the selection period _TSE of the i-th row, the on-voltage V _ON is applied to the selected scanning line X _i by the selective scanning driver 5 and the designated current reference is applied to the signal supply line Z _i. The working voltage V _LOW is applied. Further, the i-th row selection period T _SE, so that each unit switching circuit S ₁ to S _n shed each current terminal CT ₁ to CT _n of current to each of the signal lines Y ₁ to Y _n Therefore, the data driver 3 controls the gradation designation current I _DATA to flow through the signal lines Y _{1 to} Y _n .

In the selection period T _SE of the i-th row, the second transistors 22 of the pixel circuits D _{i, 1 to} D _{i, n} in the _i- th row are in the on state. When the second transistor 22 of each pixel circuit D _{i, 1 to} D _{i, n} is turned on, a voltage is also applied to the gate 23g of the third transistor 23 of each pixel circuit D _{i, 1 to} D _{i, n} . Then, the third transistors 23 of the pixel circuits D _{i, 1 to} D _{i, n} are turned on. Furthermore, since the first transistors 21 of the pixel circuits D _{i, 1 to} D _{i, n} are also in the on state, the first transistor 21 is the signal in any of the pixel circuits D _{i, 1 to} D _{i, n.} The gradation designation current I _DATA is supplied from the supply line Z _i to the signal line Y _j through the drain 23d and the source 23s of the third transistor 23. In addition, the third transistor 23 of each pixel circuit D _{i, 1 to} D _{i, n} is in an on state, but a low-level gradation designation current reference voltage V _LOW is applied to the signal supply line Z _i. Therefore, no current flows from the signal supply line Z _i to the organic EL elements E _{i, 1 to} E _{i, n} . Therefore, the current value of the gradation designation current I _DATA flowing through the signal line Y _j is equal to the current value of the current I _DS between the source 23s and the drain 23d of the third transistor 23. The third transistor 23, the voltage between the gate 23g- source 23s is comprised of the drain 23d to a level in accordance with the magnitude of the gradation designating current I _DATA flows to the source 23s. For this reason, the capacitor 24 is charged with a charge according to the voltage level between the gate 23 g and the source 23 s of the third transistor 23.

FIG. 7 is a circuit diagram showing current and voltage states from the end of the selection period _TSE of the i-th row to the start of the light emission period _TL . As shown in FIG. 7, during the period from the end of the selection period T _SE of the i-th row to the start of the light emission period T _L , the off-voltage V _OFF is applied to the selection scanning line X _i by the selection scanning driver 5. In addition, a designated current reference voltage V _LOW is applied to the signal supply line Z _i . Further, when the selection scanning driver 5 selects another row between the end of the selection period _TSE of the i-th row and the start of the light emission period T _L , the same as the selection period _TSE of the i-th row. In addition, the data driver 3 controls the gradation designation current I _DATA to flow through the signal lines Y _{1 to} Y _n .

Since the first transistor 21 of each pixel circuit D _{i, 1 to} D _{i, n} is in the OFF state from the end of the selection period T _SE of the i-th row to the start of the light emission period T _L. In each of the pixel circuits D _{i, 1 to} D _{i, n} , the first transistor 21 cuts off the gradation designation current I _DATA flowing through the signal line Y _j , and the third transistor 23 is connected to the signal supply line Z _i . So that no current flows through the signal line _Yj . Further, when the second transistor 22 of each pixel circuit D _{i, 1 to} D _{i, n} is turned off, the electric charge charged in the capacitor 24 is confined and converted between the gate 23g and the source 23s of the third transistor 23. Hold the voltage level. Here, although the third transistors 23 of the pixel circuits D _{i, 1 to} D _{i, n} are in the on state, the low-level gradation-designated current reference voltage V _LOW is applied to the signal supply line Z _i. Therefore, no current flows from the signal supply line Z _i to the organic EL elements E _{i, 1 to} E _{i, n} .

FIG. 8 is a circuit diagram showing the current and voltage states during the light emission period _TL . As shown in FIG. 8, in the light emission period _TL , the off voltage V _OFF is applied to the selected scanning line X _i by the selective scanning driver 5 and the driving current reference voltage V _HIGH is applied to the signal supply line Z _i. Is applied.

Since the first transistors 21 of the pixel circuits D _{i, 1 to} D _{i, n} are in the off state, the first transistor 21 is connected to the signal supply line in any of the pixel circuits D _{i, 1 to} D _{i, n.} The current is prevented from flowing from Z _i to the signal line Y _j through the third transistor 23. Further, since the second transistor 22 of each pixel circuit D _{i, 1 to} D _{i, n} is in the off state, the second transistor 22 sets the level of the converted voltage between the gate 23g and the source 23s of the third transistor 23. Hold. Further, a high-level driving current reference voltage V _HIGH is applied to the signal supply line Z _{i so} that the source-drain voltage V _{DS of} the third transistor 23 is in a saturation region, and each pixel circuit D _{i, Since} the third transistors 23 of _{1 to} D _{i, n} are in the on state, a drive current flows from the signal supply line Z _i to the organic EL element E _{i, j} in the third transistor 23. At this time, the level of the voltage converted between the gate 23g and the source 23s of the third transistor 23 of the pixel circuits D _{i, 1 to} D _{i, n} is gradation in the signal lines Y _{1 to} Y _n during the selection period T _SE. Since it is equal to the voltage level when the designated current I _DATA is flowing, the current value of the drive current flowing through the organic EL elements E _{i, 1 to} E _{i, n} is _equal to the current value of the gradation designated current I _DATA . Therefore _, the light emission luminance of the organic EL elements E _{i, 1 to} E _{i, n} is uniquely determined by the current value of the gradation designation current I _DATA flowing through the pixel circuits D _{i, 1 to} D _{i, n} during the non-light emission period T _NL. Determined.

  Next, a method for driving the organic electroluminescence display panel 2 with the data driver 3, the selective scanning driver 5, and the voltage supply driver 6 and the display operation of the organic electroluminescence display 1 will be described.

As shown in FIG. 4, the non-emission period T _NL, selection scanning driver 5 based on the clock signal CK2 inputted from the controller 11, the first row of the selection from the scanning line X ₁ of the m-th row selection scan line The on voltage V _ON is applied and selected in the order of X _m . Thus, it is scanned from the selection scan line X ₁ in the order of selection scan line X _m. In the light emission period T _L after the non-light emission period T _NL , the selective scanning driver 5 applies the off voltage V _OFF to all the selection scan lines X _{1 to} X _m , and in the next non-light emission period T _NL , the selective scanning is performed again. driver 5 continue to apply the oN voltage V _oN from the selection scan line X ₁ of the first row in the order of the m-th row selection scan line X _m.

In the non-light emission period T _NL in which the selection scanning driver 5 sequentially selects the selection scanning lines X _{1 to} X _m , the voltage supply driver 6 applies the gradation designation current reference voltage V _LOW to all the signal supply lines Z _{1 to} Z _m. Apply. On the other hand, in the light emission period T _L from when the selection scan driver 5 finishes selecting the selection scan line X _m of the _m-th row until the selection scan line X ₁ of the first row is selected in the next scan period T _SC , The voltage supply driver 6 applies the drive current reference voltage V _HIGH to all the signal supply lines Z _{1 to} Z _m . The voltage supply driver 6 operates in this way by the clock signal CK3 input from the controller 11 to the voltage supply driver 6.

Further, in the non-emitting period T _NL which the selection scanning driver 5 sequentially selects the selection scan lines X ₁ to X _m, the controller 11 outputs a switching signal φ to the unit switching circuits S ₁ to S _n. Thereby, in the selection period T _{SE of} each row, the unit switching circuits S _{1 to} S _n allow current flow between the current terminals CT _{1 to} CT _n and the signal lines Y _{1 to} Y _n. blocking the application of the reset voltage V _R to each of the signal lines Y ₁ to Y _n, each line of the reset period T in _R, the unit switching circuits S ₁ to S _n are respectively current terminal CT ₁ to CT _n and the respective signal The current flow between the lines Y _{1 to} Y _n is interrupted, and the application of the reset voltage V _R to each of the signal lines Y _{1 to} Y _n is allowed. As a result, the wiring capacities of the signal lines Y _{1 to} Y _n can be quickly charged up, so that the gate of the third transistor 23 can be used even when a particularly small gradation designation current I _{DATA is} passed through the signal lines Y _{1 to} Y _n. The charge according to the gradation designation current _IDATA can be quickly charged up in the capacitor 24 between the sources.

Further, in the non-light emission period T _NL in which the selective scanning driver 5 sequentially selects the selective scanning lines X _{1 to} X _m , the data driver 3 uses 8-bit red from an external circuit based on the clock signal CK 1 input from the controller 11. digital gradation video signal S _R, a green digital tone image signal S _G, latch captures blue digital gradation video signal S _B. In the selection period T _SE of each row of the non-light emission period T _NL , the data driver 3 causes the gradation designation current I _DATA having a magnitude based on the gradation of the latched signal to flow through the signal lines Y _{1 to} Y _n. To.

Here, in the non-emission period T _NL , when the selective scanning driver 5 applies the _ON voltage V _ON to the i-th selection scanning line X _i (that is, the i-th selection period T _SE ), the other An off voltage V _OFF is applied to the selected scanning lines X _{1 to} X _m (excluding X _i ). Therefore, in the selection period _TSE of the i-th row, the first transistor 21 and the second transistor 22 of the pixel circuits D _{i, 1 to} D _{i, n} of the _i-th row are in the on state, and the pixel circuits of the other rows The first transistor 21 and the second transistor 22 of D _{1,1 to} D _{m, n} (excluding the pixel circuits D _{i, 1 to} D _{i, n} ) are off.

In such a selection period T _SE of the i-th row, the gradation designated current reference voltage V _LOW is applied to all the signal supply lines Z _{1 to} Z _n , and each pixel circuit D _{i, 1} to Since the second transistor 22 of D _{i, n} is in the on state, a voltage is also applied to the gate 23g of the third transistor 23 of each pixel circuit D _{i, 1 to} D _{i, n} in the _i- th row, and the third transistor 23 is turned on. Further, such the i-th row selection period T _SE, the unit switching circuits S ₁ to S _n of the transistor 31 is a unit switching circuits S ₁ by the ON state to S _n each current terminal CT ₁ ~ Since current flow between CT _n and the respective signal lines Y _{1 to} Y _n is allowed, the current terminals CT _{1 to} CT _n are electrically connected to the _i-th signal supply line Z _i . At this time, the data driver 3 causes the gradation designation current I _DATA to flow toward the current terminals CT _{1 to} CT _n by the latch signal L, and the gradation designation current reference voltage V _{LOW of} the signal supply line Z _i is the current terminal. It is set higher than the voltages of CT _{1 to} CT _n . Accordingly, in each pixel circuit D _{i, 1 to} D _{i, n} in the _i- th row, the gradation designation current I _{DATA is} between the source 21s and the drain 21d of the first transistor 21 and between the source 23s and the drain 23d of the third transistor 23. Is applied between the gate 23g-source 23s and the source 23s-drain 23d of the third transistor 23.

That is, as shown in FIG. 6, during the selection period T _SE of the i-th row, the gradation designation current I _{DATA that} is made to flow to each column by the data driver 3 is the signal supply line Z _i → each pixel circuit. D _i, 1 ~D _i, between the drain 23d- source 23s of the third transistor 23 of the _n → respective pixel circuits D _i, 1 ~D _i, between the drain 21d- source 21s of the first transistor 21 of the _n →, respectively will flow toward the signal line Y ₁ to Y _n → respective current terminals CT ₁ to CT _n transistor 31 → the data driver 3 of each switching signal S ₁ to S _n.

During the selection period T _SE of the i-th row, the gradation designation current I _DATA is changed from the signal supply line Z _{i to} the drain 23d-source 23s of the third transistor 23 of each pixel circuit D _{i, 1 to} D _{i, n} → each of the pixel circuits D _i, 1 ~D _i, between the drain 21d- source 21s of the first transistor 21 of the _n → respective signal lines Y ₁ to Y _n → respective switching signal S ₁ to S _n of the transistor 31 → data By flowing toward the respective current terminals CT _{1 to} CT _n of the driver 3, the signal supply line Z _i to the third transistor 23 to the first transistor 21 to the respective signal lines Y during the selection period T _SE of the i-th row. _{1 to} Y _n to the respective unit switching circuits S _{1 to} S _n to voltages in the data driver 3 are in a steady state.

That is, the gradation designation current I _DATA flows through the third transistors 23 of the pixel circuits D _{i, 1 to} D _{i, n} in the _i- th row, so that the signal supply line Z _i to the third transistor 23 to the first transistors 21 to 21. Each of the signal lines Y ₁ to Y _{n, the} respective unit switching circuits S _{1 to} S _n, and the voltage in the data driver 3 is in a steady state, so that the gradation designation current I _DATA flowing through the third transistor 23 is increased. A voltage according to the level is applied between the gate 23g and the source 23s of the third transistor 23, and a charge having a magnitude according to the level of the voltage between the gate 23g and the source 23s of the third transistor 23 is charged in the capacitor 24. .

As described above, the magnitude of the current flowing between the drain 23d and the source 23s of the third transistor 23 of the pixel circuits D _{i, 1 to} D _{i, n} in the _i- th row and the level of the voltage between the source 23s and the gate 23g are also determined. Since it is overwritten from the previous one scanning period T _SC , the magnitude of the charge charged in the capacitors 24 of the pixel circuits D _{i, 1 to} D _{i, n} in the i-th row during the selection period T _SE in the i-th row There is overwritten from one scanning period T _SC of the last time.

Here, the potential at an arbitrary point between the third transistor 23 to the first transistor 21 to the signal line Y _j changes due to the internal resistance of the transistors 21, 22, and 23 that change with time. However, in this embodiment, since the data driver 3 forcibly passes the gradation designation current I _DATA flowing from the third transistor 23 → the first transistor 21 → the signal line Y _j , Even if the internal resistance changes with time, the magnitude of the gradation designation current I _DATA becomes as desired.

In the selection period T _SE of the i-th row _, the common electrode of the _i-th organic EL elements E _{i, 1 to} E _{i, n} is the reference voltage V _SS , and the signal supply line Z _i is the reference voltage V _SS . Since the reference voltage V _LOW for gradation designation current is the same or lower than the reference voltage V _SS , a reverse bias voltage is applied to the organic EL elements E _{i, 1 to} E _{i, n} in the _i- th row. No current flows through the organic EL elements E _{i, 1 to} E _{i, n} in the i-th row, and the organic EL elements E _{i, 1 to} E _{i, n} do not emit light. In the non-light emitting period T _NL not only in the selection period T _SE of the i-th row _, the common electrode of all the organic EL elements E _{1,1 to} Em _{, n} is the reference voltage V _SS , and all the signal supply lines Z ₁ because to Z _n is a low gradation designating current reference voltage V _lOW than the same or reference voltage V _SS and the reference voltage V _SS, all organic EL elements E _{1, 1} to E m, the _n reverse bias voltage Is applied, no current flows through all the organic EL elements E _{1,1 to} E _{m, n} , and none of the organic EL elements E _{1,1 to} E _{m, n} emits light.

Subsequently, as shown in FIG. 7, the i-th row selection period T _SE of the end time (i-th row of the start time of the non-selection period T _NSE), is output from the selection scan driver 5 to the selection scan line X _i From the high-level on-voltage V _ON to the low-level off-voltage V _OFF , and the gate 21g of the first transistor 21 and the second transistor 22 of the pixel circuits D _{i, 1 to} D _{i, n} in the _i- th row An off voltage V _OFF is applied by the selective scanning driver 5 to the gate 22g.

For this reason, in the non-selection period T _NSE of the i-th row, the first transistors 21 of the pixel circuits D _{i, 1 to} D _{i, n} in the _i- th row are turned off, and current is supplied by the first transistor 21 in the off state. The signal supply line Z _i does not flow to the respective signal lines Y ₁ to Y _n . Further, in the non-selection period T _NSE of the i-th row, when the second transistors 22 of the pixel circuits D _{i, 1 to} D _{i, n} of the i-th row are turned off, the selection period T _SE of the immediately previous i-th row is selected. , The charge charged in the capacitor 24 is confined by the second transistor 22. Accordingly, in any of the pixel circuits D _{i, 1 to} D _{i, n in} the _i- th row, the third transistor 23 continues to be kept on during the non-selection period T _NSE . That is, in any of the _i-th pixel circuits D _{i, 1 to} D _{i, n} , the magnitude of the voltage V _GS between the gate 23g and the source 23s of the third transistor 23 in the non-selection period T _NSE is just before that. to be equal to the magnitude of the voltage V _GS between the gate 23g- source 23s of the third transistor 23 in the selection period T _SE, the second transistor 22 holds the voltage V _GS between the gate 23g- source 23s of the third transistor 23 To do.

The voltage supply driver 6 applies the gradation designation current reference voltage V _LOW to all the signal supply lines Z _{1 to} Z until the i-th selection period T _SE ends and the light emission period T _L starts. _Applied to _n . Therefore, the reverse bias voltage is applied to all the organic EL elements E _{1,1 to} E _{m, n} until the selection period T _SE of the i-th row ends and the light emission period T _L starts. No current flows through all the organic EL elements E _{1,1 to} Em _{, n} , and none of the organic EL elements E _{1,1 to} Em _{, n} emits light.

Here, since the i-th row selection period T _SE is finished (i + 1) until the row selection period T _SE starts (i.e., (i + 1) in row reset period T _R), respectively unit transistor 31 of the switching circuit S ₁ to S _n are turned off, each of the unit switching circuits S ₁ to S _n of the transistor 32 is turned on. Therefore, (i + 1) th row in the reset period T _R, but does not flow gradation designating current I _DATA to any signal line Y ₁ to Y _n, the reset voltage V _R is all the signal lines Y ₁ to Y _n To be applied. Moreover, has a (i + 1) th row of the reset period T in _R, all the pixel circuits do not even selection period T _SE of which lines D _{1, 1} to D m, the first transistor 21 is turned off in the _n . Accordingly, the reset voltage V _R is applied to the signal lines Y ₁ to Y _n, the charge in the parasitic capacitance of the signal lines Y ₁ to Y _n is charged.

Then, when the selection period _TSE of the (i + 1) th row starts, the selection scanning driver 5 selects the selection scanning line X _{i + 1} of the (i + 1) th row, as in the case of the i-th row. by further transistor 31 of the unit switching circuits S ₁ to S _n is turned on, the signal supply lines in each column Z _{i + 1} → third transistor 23 → first transistor 21 → respective signal lines Y ₁ ~ Y _n → gradation designating current I _dATA towards the transistor 31 → the data driver 3 of each unit switching circuits S ₁ to S _n flows. Thereafter, the non-selection period T _NSE of the (i + 1) th row is reached, and the first transistors of the pixel circuits D _{i + 1,1 to} D _{i + 1, n} of the (i + 1) th row are the same as in the i-th row. 21 is turned off, and no current flows from the signal supply line Z _{i + 1} to each of the signal lines Y ₁ to Y _n by the first transistor 21 in the off state.

As described above, in the reset period T _R, the reset voltage V _R is forcibly applied to the signal lines Y ₁ to Y _n, a small current flows through the charge amount of the parasitic capacitance of the signal lines Y ₁ to Y _n Sometimes the charge amount when it becomes steady is approached. Therefore, to be the (i + 1) (i + 1) immediately steady state current also flowing through the signal line Y ₁ to Y _n in the row selection period T _SE is a small after the row reset period T _R it can.

As described above, the non-emission period T _NL selection scanning driver 5 continue the selection scan line X ₁ to X _n to the selected row sequentially in the data in the selection period T _SE of each selection scan line X ₁ to X _n The driver 3 causes the gradation designation current I _DATA to flow through the signal lines Y _{1 to} Y _n , whereby the magnitude of the gradation designation current I _DATA is the gate of the third transistor 23 of the pixel circuits D _{1,1 to} D _{m, n} . Conversion to the magnitude of the voltage between 23g and the source 23s is performed in a row sequential manner.

As shown in FIG. 8, in the light emission period T _L after the non-light emission period T _NL , the selection scan driver 5 applies the off voltage V _OFF to all the selection scan lines X _{1 to} X _m . In the pixel circuits D _{1,1 to} D _{m, n} , the first transistor 21 and the second transistor 22 are in the off state. When the second transistor 22 is in the OFF state, the second transistor 22 holds the voltage V _GS between the gate 23g and the source 23s of the third transistor 23 as described above. Further, in the light emission period TL after the non-light emission period TNL, the voltage supply driver 6 applies the drive current reference voltage V _HIGH to all the signal supply lines Z _{1 to} Z _m . Here, in the light emission period T _L , the common electrode of all the organic EL elements E _{1,1 to} E _{m, n} is the reference voltage V _SS , and all the signal supply lines Z _{1 to} Z _m are the reference voltage V _SS. Since the higher drive current reference voltage V _HIGH and the third transistors 23 of all the pixel circuits D _{1,1 to} D _{m, n} are in the on state, all the organic EL elements E _{1,1 to} E _{m, A} forward bias voltage is applied to _n . Accordingly, the pixel circuits D _{1, 1} to D _m, in any of the _n well, each of the organic EL element E _{1, 1} to E _m through third transistor 23 from the respective signal supply lines Z ₁ to Z _m, drive to _n A current flows, and each of the organic EL elements E _{1,1 to} E _{m, n} emits light.

That is, in each pixel circuit D _{i, j} during the light emission period T _L , the first transistor 21 functions to electrically cut off between the signal line Y _j and the third transistor 23, and the second transistor 22, by confining the electric charge of the capacitor 24 functions to hold the level of the voltage between the gate 23g- source 23s of the third transistor 23, which is converted in the selection period T _SE, the third transistor 23, It functions so that a drive current having a magnitude corresponding to the level of the voltage between the held gate 23g and the source 23s flows to the organic EL element E _{i, j} .

Here, the magnitude of the drive current flowing through each of the organic EL elements E _{1,1 to} E _{m, n} during the light emission period T _L is the third transistor 23 of each pixel circuit D _{1,1 to} D _{m, n} . Therefore, it is the same as the magnitude of the gradation designation current I _DATA flowing in the third transistor 23 of each pixel circuit D _{1,1 to} D _{m, n} in the selection period T _SE . As described above, in the selection period T _SE , the magnitude of the gradation designation current I _DATA flowing through the third transistor 23 of each pixel circuit D _{1,1 to} D _{m, n} is as desired. The magnitude of the drive current flowing through the EL elements E _{1,1 to} E _{m, n} is also as desired, and each organic EL element E _{1,1 to} E _{m, n} emits light with a desired gradation luminance.

As described above, in the present embodiment, the level of the drive current flowing in each of the organic EL elements E _{1,1 to} Em _{, n} in the light emission period _TL is set in the selection period T _SE in the non-light emission period T _NL. This is indicated by the magnitude of the adjustment specified current _IDATA . Thus, for example, the pixel circuits D _{1, 1} to D m, even if there are variations in the characteristics of the third transistor 23 between the _n pixel circuits D _{1, 1} to D m, the gradation designating current between the _n If the magnitude of I _DATA is the same, there is no variation in luminance between the organic EL elements E _{1,1 to} Em _{, n} . In other words, in the present embodiment, it is possible to suppress the in-plane variation in which the luminance varies between pixels even when the luminance gradation signal of the same level is output to the pixels. Therefore, the organic electroluminescence display 1 of the present embodiment can perform high-quality image display.

In addition, although two selection scanning lines X _i and signal supply lines Z _i are provided for each row, the signal supply lines Z _i are not signals for scanning, but reference voltages V _LOW for gradation designation currents. And a periodic signal composed of the reference voltage V _HIGH for driving current is output by the voltage supply driver 6. The selective scanning driver 5 is the only driver that is a shift register included in the organic electroluminescence display 1. The shift register is generally composed of m flip-flop circuits and the like, but the voltage supply driver 6 that outputs a periodic signal has a small mounting area and a simple configuration compared to the shift register. The number of is also small. Therefore, even if compared with the conventional organic electroluminescent display provided with two shift registers as a driver, the manufacturing cost of the organic electroluminescent display 1 of this embodiment is low, and a yield is high.

The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention.
For example, in each of the above embodiments, an organic EL element is used as a light emitting element, but another light emitting element having a rectifying property may be used. In other words, a light emitting element in which no current flows when a reverse bias voltage is applied and a current flows when a forward bias voltage is applied, emits light with a luminance according to the magnitude of the flowing current. It may be a light emitting element. Examples of the rectifying light emitting element include an LED (Light Emitting Diode) element.

It is a block diagram of the organic electroluminescent display 1 in embodiment to which this invention is applied. 2 is a plan view of a pixel P _{i, j} of the organic electroluminescence display 1. FIG. 4 is an equivalent circuit diagram of four adjacent pixels P _{i, j} , P _{i + 1, j} , P _{i, j + 1} , P _{i + 1, j + 1} of the organic electroluminescence display 1. FIG. 4 is a timing chart showing signal levels in the organic electroluminescence display 1. 6 is a graph showing current-voltage characteristics of an N-channel field effect transistor. FIG. 6 is a diagram showing current and voltage states in the selection period _TSE of the i-th row, along with an equivalent circuit diagram of two adjacent pixels P _{i, j} and P _{i, j + 1 in} the i-th row. Along with the equivalent circuit diagram of two adjacent pixels P _{i, j} and P _{i, j + 1 in} the i-th row, the current and voltage states from the end of the selection period T _{SE in} the i-th row to the light emission period T _L are shown. FIG. It is the figure which showed the state of the electric current of the light emission period _TL , and the voltage state with the equivalent circuit schematic of two pixels _{Pi, j} and _{Pi, j + 1 which} adjoin i line.

Explanation of symbols

1. Organic electroluminescence display (display device)
2… Organic electroluminescence display panel (display panel)
3. Data driver 5. Select scan driver (scan driver)
6 ... Voltage supply driver 21 ... 1st transistor 22 ... 2nd transistor 23 ... 3rd transistor _E1,1- Em _{, n} ... Organic EL element (light emitting element)
Y _{1 to} Y _n ... signal lines X _{1 to} X _n ... selected scanning lines (scanning lines)
Z _{1 to} Z _n ... signal supply lines P _{1,1 to} P _{m, n} ... pixel D _{1,1 to} D _{m, n} ... pixel circuit

Claims (11)

A plurality of light emitting elements disposed at each intersection of a plurality of scanning lines and a plurality of signal lines substantially perpendicular to the plurality of scanning lines, and emitting light at a luminance according to the magnitude of a flowing current;
A selective scanning driver for sequentially selecting the plurality of scanning lines;
A data driver that causes a designated current of a magnitude according to a video signal to flow through the plurality of signal lines when the plurality of scanning lines are selected by the selection scanning driver;
When the selection scan driver sequentially selects the plurality of scan lines, the designated current reference voltage is applied to the plurality of signal supply lines, and the selection scan driver finishes sequentially selecting the plurality of scan lines. A voltage supply driver that later applies a reference voltage for drive current to the plurality of signal supply lines;
The signal supply circuit is provided around each of the plurality of light emitting elements, and the voltage supply driver applies a reference voltage for a specified current to the signal supply line when the scanning line is selected by the selection scanning driver. The designated current flowing from the line to the signal line is converted into a voltage level, and the voltage supply driver drives the signal supply line after the selected scan driver finishes selecting the plurality of scan lines sequentially. A display device comprising: a plurality of pixel circuits that apply a current reference voltage to cause a driving current having a magnitude according to the level of the converted voltage to flow through the light emitting element.   After the voltage supply driver applies the drive current reference voltage to the plurality of signal supply lines, the selection scan driver sequentially selects the plurality of scan lines again and the voltage supply driver again sets the designated current reference voltage. The display device according to claim 1, wherein the display device is applied to the plurality of signal supply lines. Each of the plurality of pixel circuits is
While the voltage supply driver is applying the reference voltage for the designated current to the plurality of signal supply lines, the designated current that flows through the signal line is supplied to itself when the scanning line is selected by the selected scanning driver. By converting the magnitude of the specified current into a voltage level,
While the voltage supply driver is applying the reference voltage for the designated current to the plurality of signal supply lines, the designated current flowing through the signal line is cut off when the scanning line is not selected by the selected scanning driver. Holding the level of the converted voltage;
After the selection scan driver finishes sequentially selecting the plurality of scan lines, the voltage supply driver applies a reference voltage for drive current to the signal supply line to drive according to the held voltage level. The display device according to claim 1, wherein a current is passed through the light emitting element.   The display device according to claim 1, wherein the light emitting element is an organic electroluminescence element, and an anode of the organic electroluminescence element is connected to the pixel circuit. Each of the plurality of pixel circuits is
A first transistor having a gate connected to the scan line and one of a drain and a source connected to the signal line;
A second transistor having a gate connected to the scan line and one of a drain and a source connected to the signal supply line;
The gate is connected to the other of the drain and source of the second transistor, one of the drain and source is connected to one of the drain and source of the second transistor, and the other of the drain and source is The display device according to claim 4, further comprising: a third transistor connected to the other of the drain and the source of the first transistor and connected to the anode of the organic electroluminescence element. When the selected scan driver selects the scan line and turns on the first transistor while the voltage supply driver is applying the designated current drive voltage to the plurality of signal supply lines, the first transistor is turned on. One transistor causes a specified current to flow from the voltage supply driver to the signal line through the drain-source of the third transistor, so that the third transistor can reduce the magnitude of the specified current to the level of the gate-source voltage. Converted,
When the selection scan driver does not select the scan line and the first transistor is turned off while the voltage supply driver is applying the designated current drive voltage to the plurality of signal supply lines, The second transistor maintains the level of the gate-source voltage converted by the third transistor;
When the voltage supply driver is applying a reference voltage for driving current to the plurality of signal supply lines after the selection scan driver finishes sequentially selecting the plurality of scan lines, the third transistor holds the holding voltage. The display device according to claim 5, wherein a driving current having a magnitude according to the level of the applied voltage is supplied from the signal supply line to the organic electroluminescence element.   A reference voltage for specified current applied to the plurality of signal supply lines by the voltage supply driver is set to be equal to or lower than a voltage of a cathode of the organic electroluminescence element, and is applied to the plurality of signal supply lines by the voltage supply driver. The display device according to any one of claims 4 to 6, wherein a drive current reference voltage to be set is set to exceed a voltage of a cathode of the organic electroluminescence element. A scanning line group having a scanning line of the first row and a scanning line of the second row;
A first optical element that is connected to the scanning line of the first row and emits light according to the current value of the flowing driving current, and a second optical element that is connected to the scanning line of the second row and emits light according to the current value of the flowing driving current. An optical element group comprising: an optical element;
A first pixel circuit that is connected to the first optical element and flows a drive current equal to the current value of the specified current that flows, and a second pixel circuit that is connected to the second optical element and flows a drive current equal to the current value of the specified current that flows. A pixel circuit group having a pixel circuit;
A reference voltage for a specified current is applied in each selection period of the scanning line group, and after the selection period of the second scanning line after the selection period of the first scanning line, the first row A power source for applying a driving current reference voltage for flowing the driving current to the pixel circuit group in the second row and the second row;
A display device comprising:   The display device according to claim 8, wherein the power supply outputs the drive current reference voltage to all the pixel circuits in synchronization.   The display device according to claim 8, wherein the designated current reference voltage is lower than the drive current reference voltage. A plurality of light emitting elements disposed at each intersection of a plurality of scanning lines and a plurality of signal lines substantially perpendicular to the plurality of scanning lines and emitting light at a luminance according to the magnitude of a flowing current; and the plurality of light emitting elements A pixel circuit provided around each of the display panels, and a display panel comprising:
Sequentially selecting the plurality of scan lines;
When each of the plurality of scanning lines is selected, a designated current having a magnitude according to a video signal is passed through the plurality of signal lines,
When the selection scan driver sequentially selects the plurality of scan lines, the designated current reference voltage is applied to the plurality of signal supply lines, and the selection scan driver finishes sequentially selecting the plurality of scan lines. Later, a reference voltage for driving current is applied to the plurality of signal supply lines,
By applying a reference voltage for a specified current to the signal supply line when the scanning line is selected, the magnitude of the specified current flowing from the signal supply line to the signal line is converted to a voltage level by the pixel circuit. Then, after the selection of the plurality of scanning lines is completed, a driving current reference voltage is applied to the signal supply line, so that a driving current according to the converted voltage level is generated by the pixel circuit. A method for driving a display panel that is caused to flow through a light emitting element.

Images