JP2005102384A - Switched reluctance motor drive controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To diagnose a faulty section and the state of a switched reluctance motor and an inverter. <P>SOLUTION: This controller diagnoses the faulty section and the state of fault of the inverter 2 and the SRM, based on a winding current detected by winding current sensors 4a-4c and DC power voltage detected by a DC voltage detector 5c, by performing the switching, according to a plurality of switching patterns, for the switching elements of each phase of the inverter 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a drive control device for a switched reluctance motor (hereinafter referred to as SRM), and more particularly to a motor and device failure diagnosis method.

  Peak values Ip1 to Ip3 of the coil current of the SRM are detected by the peak hold circuit, and if any of the coil current peak values is an abnormal value compared to the other coil current peak values, it is determined that the motor drive control device has failed. An SRM drive control apparatus as described above is known (see, for example, Patent Document 1).

Prior art documents related to the invention of this application include the following.
JP 2002-010681 A

  However, since the conventional SRM drive control device simply detects and compares the coil current peak value of the SRM, which part of the SRM drive control device has failed, and what kind of There is a problem that it is not possible to specify whether the state is a failure.

  Switching is performed according to a plurality of switching patterns for the switching elements of each phase of the inverter, and based on the winding current detected by the current detector and the DC power supply voltage detected by the voltage detector, the inverter and the SRM Diagnose the location of failure and the state of failure.

  According to the present invention, it is possible to easily and accurately diagnose which part of the inverter and the SRM is in failure and what kind of failure state it is.

<< First Embodiment >>
In the first embodiment, switching patterns of four types of inverters A, B, C, and D are executed in the order of A, B, C, and D, and the failure is determined from the value of the winding current or DC voltage as the switching pattern execution result. Identify the location and state of

  FIG. 1 shows the configuration of the first embodiment. The SRM drive control device of the first embodiment applies a rectangular wave voltage to the U-phase winding 1a, V-phase winding 1b and W-phase winding 1c of the switched reluctance motor (SRM) of the three-phase winding. The SRM drive inverter 2 to be applied and the SRM control unit 5 that controls the SRM drive inverter 2 are configured.

  A switched reluctance motor (SRM) is a motor that does not use a permanent magnet, and has a salient pole structure rotor and stator, and the magnetic reluctance (reluctance) between these rotors and stator is minimal. Rotational power is generated by switching the excitation phases of the windings 1a to 1c so that. This SRM has a robust structure, can be used even in a high temperature environment, and is suitable for high-speed driving, and is expected to be applied to electric vehicles and high-speed motors. In FIG. 1, only the windings 1a to 1c of the SRM are illustrated, and the mechanical and structural parts of the SRM are not directly related to the present invention and are not illustrated.

  The SRM driving inverter 2 converts the DC voltage of the DC power source 3 into a rectangular wave voltage by using six switching elements 2a to 2f and six diodes 2g to 2l, and converts them into three-phase windings 1a, 1b and 1c of the SRM. Apply. A connection line between the inverter 2 and the DC power source 3 is called a DC link, and a DC link capacitor (not shown) is connected between the positive side (P side) and the negative side (N side) of the DC power source 3. . In addition, an angular position sensor (not shown) is provided for detecting the relative position between the SRM stator and the relative rotating rotor.

  In the first embodiment, six switching elements 2a to 2f are divided into a U-phase upper stage (P side) switching element 2a, a V phase upper stage (P side) switching element 2b, and a W phase upper stage (P side) switching element. 2c, U-phase lower stage (N side) switching element 2d, V-phase lower stage (N side) switching element 2e, and W-phase lower stage (N side) switching element 2f. Further, the six diodes 2g to 2l are composed of a U-phase upper stage (P side) diode 2g, a V phase upper stage (P side) diode 2h, a W phase upper stage (P side) diode 2i, and a U phase lower stage (N side) diode 2j. , V phase lower stage (N side) diode 2k and W phase lower stage (N side) diode 2l.

  Further, the upper side (P side) switching elements 2a, 2b, and 2c of the U, V, and W phases are collectively referred to as "upper stage switching elements" or "P side switching elements", and the lower side of the U, V, and W phases ( N-side) switching elements 2d, 2e, and 2f are collectively referred to as “lower switching elements” or “N-side switching elements”. Furthermore, the upper stage (P side) diodes 2g, 2h, and 2i of the U, V, and W phases are collectively referred to as "upper stage diode" or "P side diode", and the lower stage side (N side) of the U, V, and W phases. The diodes 2j, 2k, and 2l are collectively referred to as “lower diodes” or “N-side diodes”.

  The SRM driving inverter 2 also includes a U-phase winding current sensor 4a that detects a current flowing in the U-phase winding 1a of the SRM, a V-phase winding current sensor 4b that detects a current flowing in the V-phase winding 1b, And a W-phase winding current sensor 4c for detecting a current flowing through the W-phase winding 1c.

  The SRM control unit 5 includes an inverter drive signal generation unit 5a that supplies drive signals to the inverter switching elements 2a to 2f, a current sample unit 5b that calculates a winding current value from output values of the winding current sensors 4a to 4c, and a direct current Based on at least one of the output value of the direct current voltage detector 5c for detecting the direct current voltage of the power source 3 and the output value of the current sampler 5b or the direct current voltage detector 5c, the failure part and the failure of the inverter 2 and the SRM And a failure detection unit 5d for specifying the state.

  Next, the four types of switching patterns A to D according to the first embodiment will be described. FIG. 2 shows drive signals for the upper and lower switching elements for one phase in the four types of switching patterns A, B, C, and D. FIG.

  In the switching pattern A, the upper stage (P side) switching element of the phase to be diagnosed for failure is turned on for a predetermined time, and the lower stage (N side) switching element of the same phase remains off. In switching pattern B, the lower (N side) switching element of the phase to be diagnosed is turned on for a predetermined time tbn, and the upper (P side) switching element of the same phase is kept off.

  In the switching pattern C, the upper stage (P side) switching element and the lower stage (N side) switching element of the failure diagnosis target phase are simultaneously turned on for a predetermined time tcp, and then the upper stage (P side) switching element is turned off and the lower stage (P side) N side) The switching element is continuously turned on for a predetermined time tcn. In the switching pattern D, the upper stage (P side) switching element and the lower stage (N side) switching element of the failure diagnosis target phase are simultaneously turned on for a predetermined time tdp, and then the lower stage (N side) switching element is turned off. P side) The switching element is continuously turned on for a predetermined time tdn.

  Next, the U-phase winding current, U-phase winding voltage, and DC voltage when switching patterns are applied to the switching elements 2a and 2d above and below the U-phase in the order of A, B, C, and D are shown for each failure mode. This will be described with reference to FIGS. 3 to 15, in order from the top, the driving signal of the U-phase upper switching element 2a, the driving signal of the U-phase lower switching element 2d, the operating state of the U-phase upper switching element 2a, and the U-phase lower switching element 2d in each failure mode. , The winding current of the U-phase winding 1a of the SRM, and the waveform of the DC voltage of the inverter 2 are shown.

  First, FIG. 3 shows the waveform of each part of the U phase of the inverter 2 in a normal state. In the switching patterns A and B, the voltage and current of the SRM U-phase winding 1a are both zero.

In switching pattern C, current iu expressed by the following equation flows through U-phase winding 1a only during time tcp when both upper and lower switching elements 2a and 2d are on.
iu = (1 / L) · ∫Edt (1)
In the equation (1), L is the inductance of the U-phase winding 1a of the SRM, E is the voltage of the DC power supply 3, and t is the elapsed time since the upper switching element 2a and the lower switching element 2d are simultaneously turned on.

  When the time tcp elapses and only the upper switching element 2a is turned off, the winding current circulates through the lower diode 2j. When the time tcn elapses and the lower switching element 2d is also turned off, the upper diode 2g and the lower The winding current is regenerated to the DC power source 3 via the diode 2j, and the current is attenuated.

  In the switching pattern D, the current iu expressed by the above equation (1) flows through the U-phase winding 1a of the SRM at the time tdp when both the upper and lower switching elements 2a and 2d are on. Thereafter, when only the lower switching element 2d is turned off, the winding current is circulated through the upper diode 2g, and when the time tdn has elapsed and the upper switching element 2a is also turned off, the upper diode 2g and the lower diode 2j are passed. Thus, the winding current is regenerated to the DC power source 3, and the current is attenuated. The DC voltage value shows the same value as the voltage value E of the DC power supply 3 in all switching patterns.

  FIG. 4 shows each part waveform in the “failure mode 1” in which the U-phase upper switching element 2a is short-circuited. In switching patterns A and D, a winding current waveform similar to that in the normal state shown in FIG. 3 appears.

  In the switching pattern B, the winding current does not flow in the normal state, but at the time tbp when the lower switching element 2d is turned on when the failure mode 1 occurs, the SRM U-phase winding 1a is expressed by the above equation (1). The represented current iu flows. Thereafter, when the lower switching element 2d is turned off, the winding current is circulated through the upper diode 2g, and the current is attenuated.

  In the switching pattern C, the winding current increases only during the time tcp at the normal time, whereas the winding current increases during the time (tcp + tcn) when the lower switching element 2d is turned on when the failure mode 1 occurs. . Thereafter, when the lower switching element 2d is turned off, the winding current is circulated through the upper diode 2g, and the current is attenuated. Note that the DC voltage value is the same as that in the normal state shown in FIG. 3 in all switching patterns.

  FIG. 5 shows each part waveform in the “failure mode 2” in which the U-phase lower switching element 2d is short-circuited. In switching patterns B and C, a winding current waveform similar to that in the normal state shown in FIG. 3 appears.

  In the switching pattern A, the winding current does not flow in the normal state, but at the time tap when the upper switching element 2a is turned on when the failure mode 2 occurs, the SRM U-phase winding 1a is expressed by the above equation (1). The represented current iu flows. Thereafter, when the upper switching element 2a is turned off, the winding current is circulated through the lower diode 2j, and the current is attenuated.

  In the switching pattern D, the winding current increases only during the time tdp in the normal state, whereas the winding current increases during the time (tdp + tdn) in which the upper switching element 2a is on when the failure mode 2 occurs. . Thereafter, when the upper switching element 2a is turned off, the winding current is circulated through the lower diode 2j, and the current is attenuated. Note that the DC voltage value shows the same value as normal in all switching patterns.

  FIG. 6 shows respective waveforms in the “failure mode 3” in which the U-phase upper switching element 2a is in an open state. FIG. 7 shows the waveforms of each part in the “failure mode 4” in which the U-phase lower switching element 2d is in an open state. In the failure modes 3 and 4, the waveform obtained is the same, and no winding current flows in all switching patterns. Further, the DC voltage value shows the same value as normal in all switching patterns.

  FIG. 8 shows waveforms of respective parts in the “failure mode 5” in which the U-phase upper diode 2g is short-circuited. In failure mode 5, no winding current flows in all switching patterns. Further, the DC voltage value is the same as that in the normal state in the switching pattern A, and becomes substantially zero in the switching pattern B during the time tbn when the lower switching element 2d is on. Similarly, in the switching patterns C and D, the DC voltage value becomes substantially zero during the time (tcp + tcn) during which the lower switching element 2d is on and tdp.

  FIG. 9 shows waveforms of respective parts in the “failure mode 6” in which the U-phase lower diode 2j is short-circuited. In failure mode 6, no winding current flows in all switching patterns. The DC voltage value is the same as that in the normal state in the switching pattern B. In the switching pattern A, the DC voltage value is substantially zero during the time tap when the upper switching element 2a is on. Similarly, in the switching patterns C and D, the DC voltage value becomes substantially zero during the times tcp and (tdp + tdn) when the upper switching element 2a is on.

  FIG. 10 shows waveforms of respective parts in the “failure mode 7” in which the U-phase upper diode 2g is in an open state. In the switching patterns A, B, and C, a winding current waveform similar to that in the normal state appears. On the other hand, in the switching pattern D, a waveform of the winding current similar to that at the normal time appears during the time tdp. However, after the time tdp, the winding current attenuates at the normal time, whereas the winding current when the failure mode 7 occurs. The current immediately goes to zero. Note that the DC voltage value shows the same value as normal in all switching patterns.

  FIG. 11 shows waveforms of respective parts in the “failure mode 8” in which the U-phase lower diode 2j is in an open state. In the switching patterns A, B, and D, a winding current waveform similar to that in the normal state appears. On the other hand, in the switching pattern C, a winding current waveform similar to that at the normal time appears during the time tcp. However, after the time tcp, the winding current attenuates at the normal time, whereas the winding current when the failure mode 8 occurs. Immediately becomes 0. Note that the DC voltage value shows the same value as normal in all switching patterns.

  FIG. 12 shows each part waveform in the “failure mode 9” in which the SRM U-phase winding is short-circuited. In the switching patterns A and B, a winding current waveform similar to that in the normal state appears. In the switching patterns C and D, a large winding current flows during the times tcp and tdp when the switching elements 2a and 2d are both on. Further, the DC voltage value has a winding current waveform similar to that in the normal state in the switching patterns A and B, but in the switching patterns C and D, the times tcp and tdp in which the switching elements 2a and 2d are turned on in both the upper and lower stages. Becomes almost zero.

  FIG. 13 shows the waveform of each part in the “failure mode 10” in which the motor winding is in an open state. In failure mode 10, no winding current flows in all switching patterns. Further, the DC voltage value shows the same value as that in the normal state in all switching patterns.

  FIG. 14 shows the waveforms of each part in the “failure mode 11” in which the positive terminal of the motor winding is grounded. In the switching pattern B, a winding current waveform similar to that in the normal state is obtained. In the switching patterns A, C, and D, a large winding current flows at times tap, tcp, and (tdp + tdn) when the upper switching element is on. In addition, in the switching pattern B, the same DC current value as the normal winding current waveform is obtained. In the switching patterns A, C, and D, the DC voltage value is substantially zero at the times tap, tcp, and (tdp + tdn) when the upper switching element is on.

  FIG. 15 shows each part waveform in the “failure mode 12” in which the negative terminal of the motor winding is grounded. In the switching patterns B and C, a winding current waveform similar to that in the normal state is obtained. In the switching pattern A, the winding current does not flow in a normal state, but when the failure mode occurs, the winding switching current 2a is expressed by the expression (1) at the time tap when the upper switching element 2a is on. A current iu flows. Thereafter, when the upper switching element 2a is turned off, the winding current is circulated through the lower diode 2j, and the current is attenuated.

  In the switching pattern D, the winding current increases only during the time tdp in the normal state, whereas the winding current during the time (tdp + tdn) in which the upper switching element 2a is on when the failure mode 12 occurs. Will increase. Thereafter, when the upper switching element 2a is turned off, the winding current is circulated through the diode 2j, and the current is attenuated. Further, the DC voltage value is the same value as that in the normal state in all switching patterns.

Next, the timing for sampling the values of the winding current and the DC voltage for determining failure will be described.
As shown in FIGS. 3 to 15, in the switching pattern A, the values of the winding current and the DC voltage are sampled when the time tap / 2 has elapsed after the upper switching element is turned on, and the values are respectively i1 and Vdc1. And In switching pattern B, when the time tbn / 2 has elapsed since the lower switching element was turned on, the values of the winding current and the DC voltage are sampled, and the values are set to i2 and Vdc2, respectively.

  In switching pattern C, the winding current and the DC voltage are sampled when time tcp / 2 has elapsed since the upper switching element was turned on, and the values are i3 and Vdc3, respectively. Further, when the upper switching element is turned off, the value of the winding current is sampled and the value is set to ip3. Further, when the time tcn / 2 has elapsed since the upper switching element was turned off, the values of the winding current and the DC voltage are sampled, and the values are set to i4 and Vdc4, respectively.

  In switching pattern D, the values of the winding current and the DC voltage are sampled when time tdp / 2 has elapsed since the lower switching element is turned on, and the values are set to i5 and Vdc5, respectively. Further, when the lower switching element is turned off, the value of the winding current is sampled, and the value is set to ip5. Further, when the time tdn / 2 elapses after the lower switching element is turned off, the values of the winding current and the DC voltage are sampled, and the values are set to i6 and Vdc6, respectively.

  Next, a method for identifying a failure part and a failure state will be described with reference to FIG. FIG. 16 is a table in which winding currents and DC voltages sampled at the time of executing each switching pattern are summarized for each failure mode. From this table, it is determined that failure mode 1 has occurred if i1 = 0 and i2> 0. If i1> 0 and i2 = 0, it is determined that failure mode 2 or 12 has occurred.

  If i1 = 0, Vdc> 0, i2 = 0, Vdc> 2, and i3 = 0, it is determined that failure mode 3 or 4 or 10 has occurred. If Vdc2 = 0, it is determined that failure mode 5 has occurred. If i1 = 0 and Vdc1 = 0, failure mode 6 has occurred. If i1 = 0 and i4 <ip3, it is determined that failure mode 7 has occurred. If i3 = 0, i4 = 0, and Vdc3> 0, it is determined that failure mode 8 has occurred.

  If i5> 0, Vdc5 = 0, and Vdc6> 0, it is determined that failure mode 9 has occurred. If i1> 0 and Vdc1 = 0, it is determined that the failure mode 11 has occurred. Note that the winding current sensor output value does not always accurately show 0 even if no current is flowing due to an error in the winding current sensor, so the threshold value for failure determination is set to a predetermined value other than 0. May be. For the same reason, a predetermined threshold value other than 0 may be provided for the DC voltage sensor output value.

  Thus, by executing the four types of switching patterns A to D, it is possible to grasp the location and state of the failure.

  Note that the timing for sampling the values of the winding current and the DC voltage is not limited to the timing of the above-described embodiment. Furthermore, in the case of a system that does not have a DC voltage sensor, failure diagnosis can be performed only with the value of the winding current. In this case, the failure modes 3, 4, 5, 6, and 10 cannot be distinguished, but for the other failure modes, the location and state of the failure can be specified up to the same level as when a DC voltage is used. .

<< Second Embodiment >>
In this embodiment, in the process of sequentially executing a plurality of switching patterns, the next switching pattern is selected according to at least one value of the winding current and the DC voltage at the time of the previous switching pattern execution, and the number of times of diagnosis is small. This identifies the location and state of the failure. In the following, the case where the switching pattern executed for the first time is C will be described. The configuration of the second embodiment is the same as the configuration shown in FIG. 1 described above, and illustration and description thereof are omitted.

  FIG. 17 is a flowchart showing a failure diagnosis procedure according to the second embodiment. First, the switching pattern C is executed, and the winding currents i3, ip3, i4, and the DC voltages Vdc3, Vdc4 are sampled at the same timing as in the first embodiment. If i3> 0 and i4> ip3, it is determined that failure mode 1 has occurred. If i3> 0 and i4 <ip3, it is determined that one of failure modes 2, 7, and 12 has occurred.

  If i3> 0 and i4 = 0, it is determined that one of failure modes 8, 9, or 11 has occurred. If i3 = 0, Vdc3 = 0, and Vdc4 = 0, it is determined that failure mode 5 has occurred. If i3 = 0, Vdc3 = 0, and Vdc4> 0, it is determined that the failure mode 6 has occurred. If i3 = 0, Vdc3> 0, and Vdc4> 0, it is determined that one of failure modes 3, 4, and 10 has occurred.

  Next, as a result of executing the switching pattern C, when it is determined that one of the failure modes 2, 7, and 12 has occurred, the switching pattern D is executed to further narrow down the failure mode. If i6 = 0, it is determined that failure mode 7 has occurred. If i6> ip5, it is determined that one of failure modes 2 and 12 has occurred.

  Further, when it is determined as a result of executing the switching pattern C that one of the failure modes 8, 9, or 11 has occurred, the switching pattern D is executed to further narrow down the failure mode. If i6 <ip5, it is determined that failure mode 8 has occurred. If i6 = 0, it is determined that failure mode 9 has occurred. If i6 = ip5, it is determined that the failure mode 11 has occurred.

  As described above, the failure determination is performed at the time when the switching pattern C is executed once, and the diagnosis is terminated if the failure can be identified at that time. Depending on the failure mode, the switching pattern D is further executed to narrow down the failure mode. Therefore, since the number of times of execution of the switching pattern is only two, it is possible to specify a failure in a short time.

  The switching pattern executed for the first time is not necessarily C. Any one of the switching patterns A, B, and D may be executed for the first time in the same manner. Also, the procedure for the second and subsequent failure diagnosis is not always the same as the flowchart shown in this embodiment. In this embodiment, the case where the switching patterns C and D are executed has been described. However, a procedure using the switching patterns A or B can be configured.

<< Third Embodiment >>
In the third embodiment, failure diagnosis of a plurality of phases is simultaneously performed using four types of switching patterns A, B, C, and D, and the failure state and failure occurrence are based on the winding current and the DC voltage. Judge the phase. Here, an example is shown in which the diagnosis of the U phase and the V phase is first performed simultaneously, and then the diagnosis of the W phase is performed. The configuration of the third embodiment is the same as the configuration shown in FIG. 1 described above, and illustration and description thereof are omitted.

  The switching pattern given to the switching element at the time of failure diagnosis will be described with reference to FIG. In FIG. 18, first, four types of switching patterns are executed in the order of A, B, C, and D in the order of A, B, C, and D at the same time. The upper stage switching element drive signal and the lower stage switching element drive signal for three phases when executed are shown.

  In the switching pattern A, the upper switching element of any phase is turned on for a predetermined time, and the lower switching element of the same phase remains off. In the switching pattern B, the lower switching element of any phase is turned on for a predetermined time tbn, and the upper switching element of the same phase remains off.

  In the switching pattern C, the upper switching element and the lower switching element of any phase are simultaneously turned on for a predetermined time tcp, and then the upper switching element is turned off, and the lower switching element is continuously turned on for the predetermined time tcn. In switching pattern D, the upper switching element and the lower switching element of any phase are simultaneously turned on for a predetermined time tdp, and then the lower switching element is turned off, and the upper switching element is continuously turned on for a predetermined time tdn.

  The U-phase winding current and the DC voltage when the switching patterns A, B, C, and D are sequentially given to the U-phase upper and lower switching elements 2a and 2d are shown in FIG. 3 of the first embodiment described above. It is the same as that shown in. For the other V and W phases, the same winding current and DC voltage as in the U phase are generated.

  FIG. 19 shows a process of executing a switching pattern for failure diagnosis and determining a failure state and a failure site based on the winding current and the DC voltage. A failure determination method according to the third embodiment will be described with reference to FIG.

  First, in step 1, the phase to be diagnosed this time is confirmed. If the failure occurrence phase is known at this time, the switching pattern is not executed in the failure occurrence phase, and the inverter switching element is turned off. As a result, it is possible to continue diagnosis of other phases while preventing energization of the location determined to be a failure. In this embodiment, first, the U phase and the V phase are set as diagnosis target phases.

  Next, in step 2, a predetermined switching pattern is simultaneously executed for the U phase and the V phase. If the number of executions of Step 1 for each phase is the first time, the switching pattern A is executed, if the second time, the switching pattern B is executed, if the third time, the switching pattern C is executed, and if the fourth time, the switching pattern D is executed.

  Next, in steps 3 to 4, a failure state and a failure occurrence phase candidate are determined based on each phase winding current and DC voltage when the switching pattern is executed. The determination method of the failure state and the failure occurrence phase is the same as in the first embodiment described above, and the description and illustration are omitted. If it is determined that no failure has occurred, the process proceeds to step 10; if the switching pattern D has not been executed, the process returns to step 2; if the switching pattern D has been executed, it is determined that there is no failure in the diagnosis target phase; Proceed to step 8.

  On the other hand, if it is determined that a failure has occurred, the process proceeds to step 5. In step 5, the failure state and failure occurrence phase candidates determined in step 3 are confirmed, and it is determined whether a failure in which no current flows in the winding has occurred in two or more phases. The failure in which current does not flow through the winding is five types of failures: upper switching element open, lower switching element open, upper diode short circuit, lower diode short circuit, and winding open. Hereinafter, these five types of failures are collectively referred to as a group A failure.

  In a phase in which a group A fault has occurred, no current flows through the winding no matter what switching pattern is executed. Therefore, in order to further classify the state of the group A fault, a determination is made using the value of the DC voltage. To do. Therefore, if a group A failure has occurred in multiple phases, the process proceeds to step 9 to further classify the state of group A failure in each phase, and the subroutine shown in FIG. Execute the switching pattern. The subroutine of FIG. 2 will be described later.

  If it is determined in step 5 that a failure in which no current flows in the winding has not occurred in two or more phases, the process proceeds to step 6. In step 6, it is determined whether the failure state and failure occurrence phase candidates determined in step 3 have been determined, and all failure states and failure phases that have occurred for the diagnosis target phase have been identified. If there is a failure for which the failure state and the failure occurrence phase have not yet been identified, the process returns to step 2.

  If all the failure states and failure occurrence phases that have occurred for the diagnosis target phase can be identified, the process proceeds to step 7 to store the failure state and failure occurrence phase. In the subsequent step 8, it is determined whether or not there is a phase that has not been diagnosed. If a phase that has not been diagnosed remains, the process returns to step 1 to set a phase that has not been diagnosed (in this embodiment, the W phase) as the current phase to be diagnosed. Run in the same way as If there is no phase that has not been diagnosed, the process ends.

  Thus, by performing the failure diagnosis of a plurality of phases at the same time, the state of the failure can be determined in a shorter time than the failure diagnosis for each phase.

  Note that the order of the switching patterns to be executed is not limited to the order of the third embodiment. Further, all phases of the U, V, and W phases may be diagnosed simultaneously. In this case, since substantially the same current flows in each phase, diagnosis can be performed without generating motor torque even when a relatively large current is passed.

  With reference to FIG. 20, the state separation at the time of group A failure will be described by taking as an example the case where a group A failure has occurred in the U phase and the V phase. Here, group A faults occurring in a plurality of phases are classified into three types for each phase: upper switching element open, lower switching element open, and group B fault. The group B failure refers to two types of failures: a lower switching element short circuit and a winding negative terminal ground fault.

  First, in step 21, one of the phases in which the group A failure has occurred is set as the current diagnostic phase. Here, an example in which the U phase is set as the diagnosis target phase is shown. Next, at step 22, the switching pattern A is executed only for the diagnostic phase. During this time, the switching element drive signals for phases other than the diagnostic phase are turned off. In steps 23 to 24, it is determined whether or not the group A fault of the diagnostic phase can be further classified based on the value of the DC voltage at the time of executing step 22. If it cannot be determined, the switching pattern B is executed in the same procedure in steps 27 to 29 to determine whether or not the group A failure can be classified.

  If the group A failure cannot be classified in step 29, the switching pattern C is executed in the same procedure in steps 30 to 32 to determine whether the group A failure can be classified. If the group A fault cannot be classified even in step 32, the switching pattern D is executed in the same procedure in steps 33 to 34 to classify the group A fault.

  In this way, the switching patterns are executed in the order of A, B, C, and D until the group A failure can be classified. When the group A failure is classified, step 26 is executed, and it is determined whether or not there is an undiagnosed phase among the phases in which the group A failure has occurred. If there is an undiagnosed phase, the process returns to step 21 to set the undiagnosed phase (phase V in this embodiment) as the current diagnosis target phase, and execute the processing after step 22 in the same way as the first time. To do. If no undiagnosed phase remains, the process is terminated.

  As described above, by executing the switching pattern for each phase alone, the failure state for each phase can be subdivided even if a group A failure occurs in a plurality of phases.

<< Fourth Embodiment >>
In the fourth embodiment, in the current sampling unit 5b of the SRM control unit 5, when the number of phases that can simultaneously sample the outputs of the winding current sensors 4a to 4c is smaller than the number of phases to be diagnosed, the switching pattern for each phase The failure diagnosis is executed by shifting the execution timing. Here, the number of phases that can be sampled simultaneously is two. The configuration of the fourth embodiment is the same as that shown in FIG. 1, and illustration and description thereof are omitted.

  FIG. 21 shows a switching pattern shifted for each phase. First, the switching pattern A is executed for the U phase and the V phase, and the outputs of the two-phase winding current sensors 4a and 4b are sampled. In the meantime, the W-phase switching element drive signal remains off. Next, the switching pattern A is executed for the W phase, and the switching pattern B is executed for the U phase, while the V-phase switching element drive signal remains off. Subsequently, the switching pattern B is executed for the V phase and the W phase, and the outputs of the two-phase winding current sensors 4b and 4c are sampled. Meanwhile, the U-phase switching element drive signal remains off. Thereafter, the same processing is executed for the switching patterns C and D.

  FIG. 22 is a flowchart showing the operation of the fourth embodiment. Note that steps that perform the same processing as the processing shown in FIG. 19 are denoted by the same step numbers, and differences will be mainly described. In step 41, a switching pattern execution phase is set. When the number of executions of step 41 is the first or fourth time, the switching pattern is executed for the U phase and the V phase, and when the second time or the fifth time, the switching pattern is executed for the W phase and the U phase. In the third or sixth time, a switching pattern is executed for the V phase and the W phase.

  Next, in step 42, a predetermined switching pattern is simultaneously executed for the switching pattern execution phase. If the number of executions of the switching pattern of each phase is the first time, the switching pattern A is executed, the switching pattern B is executed if it is the second time, the switching pattern C is executed if it is the third time, and the switching pattern D is executed if it is the fourth time. In step 43, the winding current and DC voltage of the switching pattern execution phase are read.

  In this way, by actually performing sampling for the number of phases that can be sampled at the same time, even in a system with a small number of phases that can be sampled simultaneously, it is possible to diagnose a failure of a plurality of phases.

<< Fifth Embodiment >>
In the fourth embodiment, in the current sample unit 5b of the SRM control unit 5, the number of phases that can simultaneously sample the outputs of the winding current sensors 4a to 4c is smaller than the number of phases to be diagnosed. Fault diagnosis is executed by shifting the sampling timing of the outputs of the current sensors 4a to 4c. Many general-purpose CPUs for motor control have two simultaneous samples. Here, an example is shown in which the number of phases that can be sampled simultaneously is two. The configuration of the fifth embodiment is the same as that shown in FIG. 1, and illustration and description thereof are omitted.

  FIG. 23 shows the diagnostic switching pattern and sample timing of each phase. First, the switching pattern A is executed simultaneously for the three phases, and the U-phase winding current value iu1 and the V-phase winding current value iv1 are sampled. Thereafter, when a predetermined time tad has elapsed, the W-phase winding current iw1 and the DC voltage value Vdc1 are sampled, and the switching pattern A is terminated. The switching patterns B, C, and D are also sampled two by two at the same time using the same method.

  Further, the process of specifying the fault state and the fault occurrence phase when using the winding current sampling method shown in the fifth embodiment is the same as the process of the third embodiment shown in FIG. .

  In this failure diagnosis method, the failure is determined based on the 1 · 0 information indicating whether or not current is flowing. Therefore, the sample timing can be shifted within the same switching signal as in the fifth embodiment. is there.

  The predetermined time tad may be determined in consideration of the AD conversion time of the system. In the fifth embodiment, the predetermined time tad is set to the same value for all switching patterns. However, the present invention is not limited to this, and the predetermined time may be different for each switching pattern.

  As described above, according to one embodiment, each phase is composed of P-side and N-side switching elements and P-side and N-side diodes, and converts a DC power supply voltage into a rectangular wave voltage to switch a three-phase switch. SRM drive inverter 2 applied to the reluctance motor (SRM), winding current sensors 4a to 4c for detecting the current flowing in the respective phase windings 1a to 1c of the SRM, and the DC power supply voltage of the inverter 2 are detected. In the SRM drive control device including the DC voltage detection unit 5c, the switching current of each phase of the inverter 2 is switched according to a plurality of switching patterns, and the winding currents detected by the winding current sensors 4a to 4c are detected. And the failure location and failure of the inverter 2 and the SRM based on the DC power supply voltage detected by the DC voltage detection unit 5c Since the SRM control unit 5 for diagnosing the state is provided, a special failure diagnosis device is not required, which part of the inverter 2 and the SRM is broken in a simple manner, and what kind of failure state Can be diagnosed easily and accurately.

  Further, according to the embodiment, the switching pattern A in which the P-side switching element of the failure diagnosis target phase is turned on for a predetermined time and the N-side switching element of the same phase is kept off, and the N of the failure diagnosis target phase The side switching element is turned on for a predetermined time tbn, and the switching pattern B in which the P side switching element of the same phase remains off and the P side switching element and the N side switching element of the failure diagnosis target phase are simultaneously turned on for the predetermined time tcp. Thereafter, the P-side switching element is turned off, the switching pattern C in which the N-side switching element is continuously turned on for a predetermined time tcn, and the failure diagnosis target phase P-side switching element and the N-side switching element are simultaneously turned on for a predetermined time tdp. , The N-side switching element is turned off and the P-side switching element is continued for a predetermined time tdn. In order to diagnose the failure of the inverter 2 and the SRM by sequentially executing the switching pattern consisting of the switching pattern D to be connected, no special failure diagnosis device is required, and any part of the inverter 2 and the SRM is failed in a simple manner. It is possible to easily and accurately diagnose whether or not the failure is occurring.

  According to one embodiment, at least two of the four types of switching patterns A, B, C, and D are executed to diagnose the failure part and the failure state of the inverter 2 and the SRM. As a result, it is possible to specify the location and state of the failure in a short time with a small number of diagnostic steps.

  According to the embodiment, the next switching pattern is selected based on the winding current of the winding current sensors 4a to 4c or the DC power supply voltage of the DC voltage detection unit 5c at the time of the previous switching pattern execution. Therefore, it is possible to identify the part and the state of the failure in a short time with a small number of diagnostic steps.

  According to one embodiment, since at least two of the four types of switching patterns A, B, C, and D are simultaneously executed for a plurality of phases and diagnosed, one phase It is possible to identify the location and state of the failure in a short time compared to the failure diagnosis for each. Therefore, the time lag for shifting to the normal operation can be reduced at the normal time, and it is possible to realize a stand-up that does not make the user feel uncomfortable.

  According to one embodiment, when the number of phases that can simultaneously detect the SRM winding current is limited in the winding current sensors 4a to 4c, the fault diagnosis based on the switching pattern is performed simultaneously with the SRM winding current. Since the number of phases that can be detected is simultaneously executed, an expensive and complicated current sampling unit for simultaneously detecting the winding currents of all phases is not required, and the apparatus can be configured at low cost.

  According to one embodiment, since at least two of the four types of switching patterns A, B, C, and D are simultaneously executed for all phases for diagnosis, each phase is diagnosed. As a result, substantially the same value of current flows through the motor, and even if a relatively large current flows, a fault diagnosis can be performed without generating motor torque.

  According to one embodiment, when the number of phases that can simultaneously detect the winding current of the SRM is limited in the winding current sensors 4a to 4c, the current detection of each winding by the winding current sensors 4a to 4c is performed. Since the timing is shifted, there is no need for an expensive and complicated current sampling unit for simultaneously detecting the winding currents of all phases, and the apparatus can be configured at low cost.

  According to one embodiment, when a failure occurrence of any phase is diagnosed during the failure diagnosis by the switching pattern, the failure diagnosis for the phase is stopped and the failure diagnosis of the other phase is continued. Therefore, when it is determined that there is a failure, the current supply to the phase can be stopped, and the diagnosis of other phases can be continued while preventing the expansion of the failure part.

  According to one embodiment, when it is diagnosed that a failure in which no current flows in the winding of the SRM has occurred in two or more phases, a fault diagnosis is performed for each phase using a switching pattern, and Since the failure part and the failure state of the inverter 2 and the SRM are diagnosed based on the DC power supply voltage detected by the voltage detector 5c, a failure in which no winding current flows has occurred in a plurality of phases. However, it is possible to diagnose the failure state for each phase.

  The correspondence between the constituent elements of the claims and the constituent elements of one embodiment is as follows. That is, the winding current sensors 4a to 4c constitute a current detector, the DC voltage detector 5c constitutes a voltage detector, and the SRM controller 5 constitutes a failure diagnosis circuit. In addition, unless the characteristic function of this invention is impaired, each component is not limited to the said structure.

  In the above-described embodiment, the three-phase SRM has been described as an example, but the number of phases of the SRM is not limited to three.

It is a figure which shows the structure of 1st Embodiment. It is a time chart which shows four types of switching patterns A, B, C, and D. It is a time chart which shows each part waveform of the U phase of an inverter at the time of normal. It is a time chart which shows each part waveform at the time of "failure mode 1" where the U-phase upper stage switching element is short-circuited. It is a time chart which shows each part waveform at the time of "failure mode 2" where the U-phase lower stage switching element is short-circuited. It is a time chart which shows each part waveform at the time of "failure mode 3" when the U-phase upper stage switching element was in an open state. It is a time chart which shows each part waveform at the time of "failure mode 4" when the U-phase lower stage switching element was in an open state. It is a time chart which shows each part waveform at the time of "failure mode 5" where the U-phase upper stage diode is short-circuited. It is a time chart which shows each part waveform at the time of "failure mode 6" where the U-phase lower stage diode is short-circuited. It is a time chart which shows each part waveform at the time of "failure mode 7" where the U-phase upper stage diode was in an open state. 6 is a time chart showing waveforms of respective parts in “failure mode 8” in which a U-phase lower stage diode is in an open state. It is a time chart which shows each part waveform at the time of "failure mode 9" where the U phase winding of SRM was short-circuited. It is a time chart which shows each part waveform at the time of "failure mode 10" where a motor winding was in an open state. It is a time chart which shows each part waveform at the time of "failure mode 11" where the positive side terminal of the motor winding is grounded. It is a time chart which shows each part waveform at the time of "failure mode 12" in which the negative side terminal of the motor winding was grounded. It is the figure which summarized the winding current and DC voltage which were sampled at the time of each switching pattern execution for every failure mode. It is a flowchart which shows the procedure of the failure diagnosis of 2nd Embodiment. It is a figure which shows the switching pattern of 3rd Embodiment. It is a flowchart which shows the process which judges the failure state and failure location of 3rd Embodiment. It is a flowchart which shows the state isolation | separation process at the time of the group A failure of 3rd Embodiment. It is a figure which shows the switching pattern shifted for every phase of 4th Embodiment. It is a flowchart which shows operation | movement of 4th Embodiment. It is a figure which shows the switching pattern and sample timing of each phase of 5th Embodiment.

Explanation of symbols

1a to 1c SRM winding 2 SRM drive inverters 2a to 2f Switching elements 2g to 2l Diode 3 DC power sources 4a to 4c Winding current sensor 5 SRM control unit 5a Inverter drive signal generation unit 5b Current sampling unit 5c DC voltage detection unit 5d Failure detection unit

Claims (11)

Each phase is composed of P-side and N-side switching elements and P-side and N-side diodes, and converts a DC power supply voltage into a rectangular wave voltage to provide a multi-phase switched reluctance motor (hereinafter referred to as SRM). An inverter applied to the
A current detector for detecting a current flowing in each phase winding of the SRM;
A SRM drive control device comprising a voltage detector for detecting a DC power supply voltage of the inverter;
Switching according to a plurality of switching patterns for the switching elements of each phase of the inverter, based on the winding current detected by the current detector and the DC power supply voltage detected by the voltage detector, An SRM drive control device comprising a failure diagnosis circuit for diagnosing an inverter and a failure part and a failure state of the SRM. The SRM drive control device according to claim 1,
The plurality of switching patterns include a switching pattern A in which the P-side switching element of the failure diagnosis target phase is turned on for a predetermined time and the N-side switching element of the same phase is kept off,
A switching pattern B in which the N-side switching element of the failure diagnosis target phase is turned on for a predetermined time tbn and the P-side switching element of the same phase is kept off;
A switching pattern C in which the P-side switching element and the N-side switching element of the failure diagnosis target phase are simultaneously turned on for a predetermined time tcp, and then the P-side switching element is turned off and the N-side switching element is continuously turned on for a predetermined time tcn;
After the P-side switching element and the N-side switching element of the failure diagnosis target phase are simultaneously turned on for a predetermined time tdp, the N-side switching element is turned off, and the P-side switching element is continuously turned on for a predetermined time tdn. The SRM drive control apparatus characterized by the above-mentioned. The SRM drive control device according to claim 2,
The fault diagnosis circuit performs four types of the switching patterns A, B, C, and D in order to diagnose a fault site and a fault status of the inverter and the SRM, and performs SRM drive control. apparatus. The SRM drive control device according to claim 2,
The failure diagnosis circuit executes at least two switching patterns of the four types of switching patterns A, B, C, and D to diagnose a failure part and a failure state of the inverter and the SRM. The SRM drive control apparatus characterized by the above-mentioned. The SRM drive control device according to claim 4, wherein
The fault diagnosis circuit selects a next switching pattern based on a winding current of the current detector or a DC power supply voltage of the voltage detector at the time of the previous switching pattern execution. . The SRM drive control device according to claim 2,
The fault diagnosis circuit performs diagnosis by simultaneously executing at least two switching patterns of the four types of switching patterns A, B, C, and D for a plurality of phases. apparatus. The SRM drive control device according to claim 6,
The fault diagnosis circuit can simultaneously detect the SRM winding current by performing a fault diagnosis based on a switching pattern when the number of phases that can simultaneously detect the SRM winding current is limited in the current detector. An SRM drive control device that executes the number of phases simultaneously. The SRM drive control device according to claim 2,
The fault diagnosis circuit performs diagnosis by simultaneously executing at least two switching patterns of the four types of switching patterns A, B, C, and D for all phases. apparatus. In the SRM drive control device according to claim 6 or 8,
The fault diagnosis circuit shifts the current detection timing of each winding by the current detector when the number of phases capable of simultaneously detecting the winding current of the SRM is limited in the current detector. SRM drive control device. In the SRM drive control device according to any one of claims 6 to 9,
The failure diagnosis circuit is characterized in that when a failure occurrence of any phase is diagnosed during failure diagnosis by a switching pattern, the failure diagnosis for the phase is stopped and the failure diagnosis of another phase is continued. SRM drive control device. In the SRM drive control device according to any one of claims 6 to 9,
When it is diagnosed that a failure in which no current flows in the winding of the SRM has occurred in two or more phases, the failure diagnosis circuit performs a failure diagnosis using a switching pattern for each phase alone, and the voltage An SRM drive control device characterized by diagnosing a failure part and a failure state of the inverter and the SRM based on a DC power supply voltage detected by a detector.

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