JP2005101036A - Method for manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a reliable semiconductor element that prevents a decrease in the dimensional precision and disconnection of upper-layer wiring, by improving the flatness of an upper-layer insulating film formed on lower-layer wiring. <P>SOLUTION: After a polysiloxane-based and alkoxysilane-based organic silica liquid 24 filled into a container 23 is rotated and applied onto a buried insulating film 6 for 3,000-4,000 revolutions/minute from a plurality of supply ports 22 having the same hole diameter being provided at a supply plate 21, preparatory drying is made in a nitrogen atmosphere at 100°C or less, thus forming a thick flattened insulating film 7a made of organic silica. Then, by using a heat plate 26 heated to 300°C by an internal heater 25, the thick flattened insulating film 7a is pressurized and dried to form a flattened insulating film 7b with hardly any irregularities. Then, by a dry etching technique using CF<SB>4</SB>gas, the flattened insulating film 7b and one portion of the upper layer insulating film 6 are etched back for flattening. In this case, since flat properties before etchback are superior, flattening is made further uniformly. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element in which an interlayer insulating film is formed on a wiring.

  In recent years, semiconductor devices have become increasingly finer and more complicated in structure due to demands for higher speed and higher performance. Accordingly, various multilayer wiring techniques are employed for high integration of semiconductor elements. Such a semiconductor element is disclosed in, for example, JP-A-6-65746. FIG. 4A to FIG. 5F are cross-sectional views of relevant parts for explaining a conventional method of manufacturing the semiconductor element 41.

  First, as shown in FIG. 4A, an under-wire insulating film 43 made of silicon oxide is formed on a semiconductor substrate 42 on which active elements are formed by a CVD method. Next, aluminum is deposited on the insulating film 43 under the wiring by sputtering and patterned to form a lower layer wiring 44. Next, as shown in FIG. 4B, a base insulating film 45 made of silicon oxide by a plasma CVD method and an embedding made of silicon oxide by an atmospheric pressure CVD method are formed on the entire surface of the lower wiring insulating film 43 and the lower wiring 44. An insulating film 46 is formed to form a lower insulating film. At this time, a step is formed on the buried insulating film 46 due to the influence of the lower layer wiring 44. In order to alleviate this level difference, as shown in FIG. 4C, an organic silica solution is spin-coated on the buried insulating film 46 at 5000 rpm, and heat treatment is performed in a nitrogen atmosphere at 300 ° C. Then, a planarization insulating film 47 made of organic silica is formed.

Next, as shown in FIG. 5D, a part of the planarizing insulating film 47 and the embedded insulating film 46 is etched back and planarized by a dry etching technique using CF ₄ gas, and then as post-processing. Oxygen plasma treatment is performed for 10 seconds. Next, as shown in FIG. 5E, after an upper insulating film 48 made of silicon oxide is formed by plasma CVD, the underlying, buried, and upper insulating films are formed by a known photolithography technique and anisotropic etching technique. Contact holes 49 are formed in 45, 46 and 48. Finally, as shown in FIG. 5F, the upper layer wiring 50 made of aluminum is formed by sputtering so as to be connected to the lower layer wiring 44, and the semiconductor element 41 is obtained.
JP-A-6-65746 (page 4, paragraphs 0029 to 0032, FIG. 5)

  However, the conventional method for manufacturing the semiconductor element 41 has the following problems. As shown in FIG. 4C, after forming a lower insulating film comprising a base insulating film 45 and a buried insulating film 46 on the lower wiring 44 by plasma and atmospheric pressure CVD, it is made of organic silica by spin coating. A planarization insulating film 47 is formed. In this spin coating method, a predetermined amount of the organic silica liquid is dropped and then rotated at a high speed to spread the organic silica liquid by the centrifugal force. An insulating film 47 is formed in an uneven shape. Thereafter, a part of the planarizing insulating film 47 and the embedded insulating film 46 is etched back by a dry etching method, so that the convex portions are removed and the irregularities are somewhat relaxed, but the initial irregularities are large. It cannot be completely flattened. In particular, in the semiconductor element 41 that requires a large current, it is necessary to form the lower layer wiring 43 thick, so that the base step becomes larger and the flatness becomes worse.

  If there is a large step on the surface of the upper insulating film 48, the lens focus of the exposure system in the photolithography process is not adjusted, and the dimensional accuracy of the contact hole 49 and the upper wiring 50 is deteriorated. Furthermore, the film thickness of the upper layer wiring 50 at the stepped portion is reduced, causing a problem that the wiring is cut off and the product yield is lowered.

  In addition, if the planarization insulating film 47 is polished using a known CMP apparatus instead of being etched back by the dry etching method, it is possible to polish the substrate with less influence of the underlying material, so that improvement in flatness is expected. However, since there is a large step in the planarization insulating film 47 before polishing, there is a problem that the microscratch occurs without applying a uniform pressure, and the reliability of the semiconductor element 41 is significantly lowered.

  The present invention has been conceived to solve the above-described problems, and by improving the flatness of the upper insulating film formed on the lower layer wiring, it is possible to prevent the dimensional accuracy of the upper layer wiring from being lowered and the disconnection from occurring. An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention includes a step of forming a lower insulating film on a lower wiring and a step of forming a planarizing insulating film on the lower insulating film. Etching back a part of the lower insulating film and the planarizing insulating film; forming an upper insulating film on the lower insulating film and the planarizing film; and the lower insulating film and the upper insulating film. Forming a contact hole, and forming an upper wiring connected to the lower wiring through the contact hole, wherein the planarization insulating film is formed on the lower insulating film. When forming, the material of the planarization insulating film is spin-coated on the lower insulating film from a supply plate having a plurality of supply ports, and then heated and pressurized from above by a heat plate. According to this method, the material of the planarization insulating film is spin-coated on the lower insulating film and formed thick, and then heated and pressurized from above in an unsolidified state, so that it is not affected by the underlying step due to the lower wiring. A planarization insulating film without unevenness can be formed.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a lower insulating film on a lower wiring; forming a planarizing insulating film on the lower insulating film; and the lower insulating film and the flat A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole in an insulating insulating film; and a step of forming an upper layer wiring connected to the lower layer wiring through the contact hole, wherein the planarization is performed on the lower insulating film When forming the insulating film, the material of the planarization insulating film is spin-coated on the lower insulating film from a supply plate having a plurality of supply ports, and then heated and pressurized from above by a heat plate. . According to this method, since the planarizing insulating film also serves as the upper insulating film, the etch back process for the planarizing insulating film and the process for forming the upper insulating film are not required. Thereby, since a process is shortened significantly, manufacturing cost can be reduced.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, the organic silica liquid is applied to the entire surface from a plurality of supply ports of the supply plate, and then dried while being pressed from above with a heat plate. Therefore, it is possible to form a flattened insulating film without unevenness without being affected by a base step due to the lower layer wiring. As a result, the upper insulating film formed on the flattening insulating film is also flattened, and it is possible to prevent a decrease in dimensional accuracy of the upper wiring and disconnection. In addition, when a planarization insulating film is polished using a CMP apparatus instead of being etched back by a dry etching method, a high-quality semiconductor element free from micro scratches can be obtained.

  In addition, if polyimide is spin-coated instead of the organic silica liquid, the planarization insulating film and the upper insulating film can be used together, so the etch-back process for the planarizing insulating film and the process for forming the upper insulating film are unnecessary. Become. As a result, the process can be greatly shortened and the manufacturing cost can be reduced.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1A to FIG. 3I are cross-sectional views of relevant parts for explaining a method for manufacturing a semiconductor element 1 of the present invention.

  First, as shown in FIG. 1A, an under-wiring insulating film 3 made of silicon oxide is formed by plasma CVD on a semiconductor substrate 2 on which active elements are formed. Next, aluminum is deposited on the insulating film 3 under the wiring by sputtering and patterned to form the lower wiring 4. Next, as shown in FIG. 1B, a base insulating film 5 made of silicon oxide is formed by plasma CVD on the entire surface of the lower wiring insulating film 3 and the lower wiring 4, and then shown in FIG. 1C. Thus, the buried insulating film 6 made of silicon oxide is formed by the atmospheric pressure CVD method. The base insulating film 5 and the buried insulating film 6 become a lower insulating film.

Next, as shown in FIG. 2 (d), the polysiloxane-based or alkoxylane-based organic silica liquid 24 filled in the container 23 is supplied from a plurality of supply ports 22 having the same hole diameter provided in the supply plate 21. Then, after spin coating on the buried insulating film 6 at 3000 to 4000 rpm, preliminary drying is performed in a nitrogen atmosphere at 100 ° C. or lower to form a thick planarized insulating film 7a made of organic silica. Next, as shown in FIG. 2 (e), the thick planarization insulating film 7a is pressure-dried by using the heat plate 26 heated to 300 ° C. by the internal heater 25, so that the unevenness is almost flat. An insulating film 7b is formed. Next, as shown in FIG. 2F, the planarization insulating film 7b and part of the buried insulating film 6 are etched back and planarized by a dry etching technique using CF ₄ gas. At this time, since the flatness before etch-back is excellent, the surface can be more uniformly flattened. Next, oxygen plasma treatment is performed as a post-treatment for 10 seconds.

  Next, as shown in FIG. 3G, after forming an upper insulating film 8 made of silicon oxide by plasma CVD, as shown in FIG. 3H, a known photolithography technique and anisotropic etching are performed. Contact holes 9 are formed in the base, buried, and upper insulating films 5, 6, and 8 by a technique. Finally, as shown in FIG. 3I, the upper layer wiring 10 made of aluminum is formed by sputtering so as to be connected to the lower layer wiring 4, and the semiconductor element 1 is obtained.

  As described above, according to the present invention, since the organic silica liquid 24 is applied to the embedded insulating film 6 from the plurality of supply ports 22 provided in the supply plate 21 and having the same hole diameter, The coating amount can be easily increased. Further, since the coating is spread at a lower rotational speed, a thick planarization insulating film 7 a can be formed on the embedded insulating film 6. Further, since the thick planarization insulating film 7a is preliminarily dried at a low temperature and then dried with pressure on the heat plate 26 from above, the planarization without almost unevenness without being affected by the underlying step due to the lower layer wiring 4. The insulating film 7b can be formed.

  As a result, the surface of the upper insulating film 8 formed after the etch back of the flattening insulating film 7b is also flattened, and a reduction in dimensional accuracy and disconnection of the upper wiring 10 can be prevented. Further, even when polishing the planarization insulating film 7b using a CMP apparatus, since a uniform pressure is applied, the generation of micro scratches can be prevented, and a highly reliable semiconductor element 1 can be obtained. .

  In addition, the spin coating conditions and the pressurizing conditions of the organic silica liquid 24 can be appropriately changed depending on the level of the base step.

  In the above-described embodiment, the case where polysiloxane-based or alkoxylane-based organic silica is used as the material of the planarization insulating film 7b has been described. However, any material that can be applied and has a low dielectric constant may be used. Alternatively, it may be flattened by applying silanol-based inorganic silica or polyimide. Each is a material having a low dielectric constant that can be applied, and a flattened insulating film without unevenness can be formed without impairing element characteristics.

  In particular, if polyimide is used, it can also be used as the upper insulating film 8 for reducing the parasitic capacitance between the wirings, so that the etch back process of the planarizing insulating film 7b and the forming process of the upper insulating film 8 are not necessary, and the process is greatly increased. The manufacturing cost can be reduced.

  In the above-described embodiment, aluminum is used for the lower layer wiring 4 and the upper layer wiring 10, but polysilicon, titanium, titanium nitride, tungsten, tungsten nitride, gold, copper, and metal silicide may be used.

  After applying organosilica liquid to the entire surface from a plurality of supply ports of the supply plate and drying it while applying pressure from above with a heat plate, a flattened insulating film that is not affected by the underlying step due to the lower layer wiring and has no irregularities Can be formed. As a result, the upper insulating film formed on the flattening insulating film is also flattened, and it is possible to prevent a decrease in dimensional accuracy of the upper wiring and disconnection.

Sectional drawing of the principal part explaining the manufacturing method of the semiconductor element of this invention Sectional drawing of the principal part explaining the manufacturing method of the semiconductor element of this invention Sectional drawing of the principal part explaining the manufacturing method of the semiconductor element of this invention Cross-sectional view of relevant parts for explaining a conventional method of manufacturing a semiconductor device Cross-sectional view of relevant parts for explaining a conventional method of manufacturing a semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Insulating film under wiring 4 Lower layer wiring 5 Underlying insulating film 6 Embedded insulating film 7a Thick planarized insulating film 7b Flattened insulating film 8 Upper layer insulating film 9 Contact hole 10 Upper layer wiring 21 Supply plate 22 Supply port 23 Container 24 Organic silica liquid 25 Internal heater 26 Heat plate 41 Conventional semiconductor element 42 Semiconductor substrate 43 Insulating film under wiring 44 Lower layer wiring 45 Underlying insulating film 46 Embedded insulating film 47 Flattening insulating film 48 Upper insulating film 49 Contact hole 50 upper layer wiring

Claims (2)

  Forming a lower insulating film on the lower wiring; forming a planarizing insulating film on the lower insulating film; etching back a portion of the lower insulating film and the planarizing insulating film; A step of forming an upper layer insulating film on the lower layer insulating film and the planarizing film; a step of forming a contact hole in the lower layer insulating film and the upper layer insulating film; and an upper layer wiring connected to the lower layer wiring through the contact hole A method of manufacturing a semiconductor device comprising the step of: forming a material for the planarization insulating film from a supply plate having a plurality of supply ports when forming the planarization insulating film on the lower insulating film. A method of manufacturing a semiconductor device, comprising spin-coating on a lower insulating film and then heating and pressurizing from above with a heat plate.   Forming a lower insulating film on the lower wiring; forming a planarizing insulating film on the lower insulating film; forming a contact hole in the lower insulating film and the planarizing insulating film; and the contact A method of manufacturing a semiconductor device comprising a step of forming an upper layer wiring connected to the lower layer wiring through a hole, and having a plurality of supply ports when forming the planarization insulating film on the lower layer insulating film A method of manufacturing a semiconductor device, comprising: applying a material for the planarizing insulating film from a supply plate onto the lower insulating film by spin coating, and then heating and pressurizing from above with a heat plate.

Images