JP2005094061A - Image data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image data processor capable of dealing with application of jaggy correction processing optimum for individual resolution to binary image data with a plurality of resolutions. <P>SOLUTION: The image data processor is provided with: a temporary storage means 31; a plurality of image processing means 32; and a selector 33. Each image processing means is provided with: a window 40; a pattern recognition section 41; a memory block 42; and a video data output section 43. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electrophotographic image data processing apparatus using digital image data such as an optical printer such as a laser printer, a digital copying machine, and a plain paper fax machine.

For example, in Patent Document 1 and Patent Document 2, it is necessary to store the image data in advance in memory in order to correct the jaggy of the contour line and improve the image quality with respect to the image data developed in a bitmap shape. Reduce the data as much as possible, and determine the pixel that needs correction from the image data and determine the correction data for the pixel that needs to be corrected in a very short time by simple determination and calculation by a microprocessor. Is achieved by the method described below.
That is, in the image data processing method for achieving the above contents, the line segment shape of the boundary portion between the black pixel region and the white pixel region of the image data expanded in a bitmap shape is recognized, and each required pixel is detected. The feature of the line segment shape recognized is replaced with multi-bit code information, and at least a part of the code information is used to determine whether or not the pixel needs to be corrected. Then, correction according to the code information is performed.
On the other hand, an image data processing apparatus according to this image data processing method has a window for extracting data of each pixel in a predetermined area centered on a target pixel of image data expanded in a bitmap shape, and extracts through the window. A plurality of bits representing the feature of the line segment shape recognized for the target pixel by recognizing the line segment shape of the boundary between the black pixel region and the white pixel region of the image data, A pattern recognition unit that generates code information, a determination unit that determines whether or not a pixel needs correction using at least a part of the code information, and a pixel that is determined to be corrected by the unit A correction data memory for reading out and outputting correction data stored in advance using the code information generated by the pattern recognition means as an address; Was what was example.

Here, the pattern recognition means, as code information indicating the feature of the line segment shape recognized for each predetermined pixel, a code indicating whether the pixel to be pattern recognition is a black pixel or a white pixel, Generates code information including a code indicating the inclination direction of the line segment, a code indicating the degree of inclination, and a code indicating the position from the pixel at the end of the line segment continuous in the horizontal or vertical direction of the target pixel. It was a thing.
Then, according to the image data processing method and apparatus described above, the line segment shape of the boundary portion (contour line of characters, etc.) between the black pixel region and the white pixel region of the image data expanded in a bitmap shape is recognized. Then, replace each required pixel with code information of a plurality of bits, determine whether or not the pixel needs correction by using at least a part of the code information, and for the pixel that needs correction Since correction according to the code information is performed, it is not necessary to create and store in advance all feature patterns that need correction as templates, and correction data for pixels that need correction and need to be corrected It was possible to make a determination in a short time using the code information.
Further, in Patent Document 3, the line segment shape of the boundary portion between the black pixel region and the white pixel region of the image data is extracted from the image data by data extracted by a window means capable of changing the size of M × N pixels. It was possible to recognize and correct the image data.
Japanese Patent Laid-Open No. 5-207282 JP 2000-236446 A JP-A-10-215381

As described above, in the prior art, in order to improve the image quality by correcting the jaggies of the contour line for the image data developed in a bitmap shape, data that needs to be stored in advance in a memory is stored. It was possible to reduce as much as possible and to shorten the processing time. Further, the window size for pattern recognition for performing image correction can be changed.
In the present invention, in addition to the functions of the prior art, it is assumed that image data of a plurality of resolutions is handled, and the effect of image processing for each resolution in that case is achieved with minimal processing, and at a low cost. It is an object to be able to cope with a simple apparatus configuration.
Specifically, each claim has the following purposes.
It is an object of the present invention to make it possible to cope with optimum jaggy correction processing at each resolution for binary image data having a plurality of resolutions.
It is an object of the present invention to enable jaggy correction to pixels forming a diagonal line or an arc even for high-resolution image data with a cheaper device configuration.
According to a third aspect of the present invention, a storage unit capable of storing binary image data having an arbitrary resolution A expanded in a bitmap shape for N lines is used, and a resolution B (B is twice as large as A). It is an object of the present invention to improve the efficiency of the memory capacity required for the storage means by making it possible to process binary image data having a resolution less than or equal to the resolution of the image data.

  In order to achieve the above object, the invention according to claim 1 is characterized in that binary image data of an arbitrary resolution A expanded in a bitmap form can be stored for N lines, and stored in the storage means. First window of main scanning M pixels × sub-scanning N lines (M and N are both integers) for extracting data of each pixel in a predetermined area centering on a pixel targeted for image data developed in a bitmap shape Means, second scanning means of main scanning P pixels × sub-scanning Q lines (P and Q are both integers, Q ≠ N and Q <N), and black pixels of image data extracted through the first window means A first pattern for recognizing a line segment shape of a boundary portion with a white pixel of a region and generating a plurality of bits of pattern code information representing a feature of the recognized line segment shape for a pixel as a target of the image data Recognition means and before Recognizing the line segment shape of the boundary between the black pixel region and the white pixel of the image data extracted through the second window means, and the feature of the recognized line segment shape with respect to the target pixel of the image data Second pattern recognition means for generating a plurality of bits of pattern code information representing the image data, and at least a part of the pattern code information is used to correct the pixel that is the target of the image data as a pixel forming a diagonal line or an arc. A determination unit that determines whether or not the pixel is a necessary pixel, and a correction that is stored in advance with the pattern code information generated by the pattern recognition unit as an address for the pixel that is determined to be corrected by the determination unit An image data processing apparatus having a memory block means for reading and outputting data is the main feature.

According to the second aspect of the present invention, in the image data processing apparatus according to the first aspect, when processing binary image data having an arbitrary resolution A or less developed in the form of a bitmap, the first window means and the first pattern are used. A plurality of bits of pattern code information representing the features of the recognized line segment shape is generated for the pixels to be the target of the image data using the recognition means, and an arbitrary resolution B (B is A When processing binary image data having a resolution equal to or less than twice the resolution of the image data, the feature of the line segment shape recognized for the pixel that is the target of the image data using the second window means and the second pattern recognition means. The main feature is an image data processing apparatus that generates multi-bit pattern code information that represents.
According to a third aspect of the present invention, in the image data processing apparatus according to the second aspect, binary image data of an arbitrary resolution B (B is less than or equal to twice the resolution of A) expanded in the bitmap shape is processed. The main feature is an image data processing apparatus in which the number Q of sub-scanning lines of the second window means is N / 2 + 1 lines or less.

According to the first aspect of the present invention, according to the first aspect, it is possible to perform optimum jaggy correction processing correspondence at each resolution for binary image data having a plurality of resolutions.
According to the second aspect, it is possible to perform jaggy correction to pixels constituting a diagonal line or an arc even for high-resolution image data with a less expensive apparatus configuration.
According to the third aspect of the present invention, the resolution B (B is a value of A) developed in a bitmap format using storage means capable of storing binary image data of an arbitrary resolution A developed in a bitmap format for N lines. By making it possible to process binary image data having a resolution of 2 times or less), the memory capacity required for the storage means can be increased.

Hereinafter, an image data processing apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a digital copying machine to which a print control unit, which is an embodiment of an image data processing apparatus according to the present invention, is applied. FIG. 2 is a block diagram showing in detail the print control unit 18 of FIG. is there.
A digital copying machine 1 shown in FIG. 1 shows a one-beam system, and an image reading unit 2 that roughly reads a document (not shown), and various processes for image data read by the image reading unit 2. The signal processing unit 3 for performing the above and the image printing unit 4 for printing an image on a printing paper (not shown) by a known electrophotographic method based on the image data processed by the signal processing unit 3.
More specifically, in the image reading unit 2, the document placed on the contact glass 5 is illuminated by a light source 6 that is elongated in the main scanning direction, and the reflected light thereof is a first mirror 7, a second mirror 9, and a third mirror 10. Are sequentially reflected, then imaged by the imaging optical system 12, and photoelectrically converted by a CCD (Charge Coupled Device) sensor 13.
In this case, the light source 6 and the first mirror 7 constitute the first scanning unit 8, and the second mirror 9 and the third mirror 10 constitute the second scanning unit 11, and the first scanning unit 8 and the second scanning unit. 11 moves at a speed ratio of 2 to 1, whereby the document is scanned in the sub-main scanning direction.
In the signal processing unit 3, the analog image signal photoelectrically converted by the CCD sensor 13 is amplified by an amplifier 14 and then converted into a digital image signal by an A / D converter (ADC) 15. Next, the digital image signal is subjected to image processing such as lightness correction processing, scaling processing, and editing processing by the image processing unit 16, and then the raster image data subjected to image processing by the image processing unit 16 is smoothed by the print control unit 18. It is processed and converted into image data for one beam (one line).
The LD modulation unit 19 modulates the beam of one semiconductor laser of the LD unit 20 based on the image data for one line. A circuit that limits the image range or performs pattern synthesis may be provided between the print control unit 18 and the LD modulation unit 19.
In the image printing unit 4, one beam emitted from the LD unit 20 is converged by the cylinder lens 22, and then one beam deflected at a constant angular velocity by the polygon mirror 23 is corrected to a uniform velocity deflection by the fθ lens 24. The photosensitive drum 26 is irradiated to form a latent image for one line and is detected by the light detector 27. The photodetector 27 is disposed in front of the effective writing area in the main scanning direction, receives the beam, and feeds back the synchronization detection pulse signal XDETP to the print controller 18.
Although the case where a semiconductor laser that generates one laser beam is used is described here, the number of beams is not limited to one, and a semiconductor laser array having a plurality of beams may be used.

Here, the print control unit 18 also adjusts the input speed of the image data input from the image reading unit 2 and the output speed of outputting the image data to the image printing unit 4. That is, in the image reading unit 2, the original on the contact glass 5 is scanned in the sub scanning direction by the first and second scanning units 8 and 11 and read by the CCD sensor 13, so that the CCD sensor 13 continues in the sub scanning direction. The image data of the dot matrix of the plurality of main scanning lines is output to the signal control unit 3 line by line.
At this time, the CCD sensor 13 resets the address of the image data for one line by the line synchronization signal LSYNC, and then outputs one pixel at a time in the main scanning direction for each pixel clock. 18) is output line by line at a predetermined line period based on the scanning speed of the first and second scanning units 8, 11 and the reading period of the CCD sensor 13.
In the image printing unit 4, when the laser beam scanned by the polygon mirror 23 enters just before the photosensitive drum 26, the light detector 27 outputs the synchronization detection pulse signal XDETP, and the print control unit 18 detects this synchronization detection. Print timing is controlled based on the pulse signal XDETP.
The print control unit 18 performs a smoothing process. Here, the matrix for pattern recognition necessary for smoothing is two matrices of 9 lines including 4 lines before and after the target pixel and 5 lines including 2 lines before and after the target pixel.

As shown in FIG. 2, first, image data for nine lines or five lines in the form of a dot matrix from the image processing unit 16 is first temporarily stored for each pixel in synchronization with the first pixel clock. It is stored in the means 31.
The present invention can also be applied to the case where the image data from the previous stage is parallel data in which a plurality of data per clock is input via a plurality of signal lines. In this case, parallel-to-serial conversion is performed. The image data for 9 lines or 5 lines is stored in the first temporary storage means 31.
The image data for 9 lines or 5 lines stored in the first temporary storage means 31 is for 9 lines or 5 lines in synchronization with the second pixel clock while the image data for 1 line is input. Reads minutes at the same time. Here, the second pixel clock will be described as an example in which image data is read out in units of one pixel for each of nine lines or five lines from the first temporary storage unit 31.

FIG. 3 is a timing chart showing the reading operation of image data in units of one pixel by the second pixel clock from the first temporary storage means 31. The nine lines of image data read from the first temporary storage means 31 are simultaneously output to the image processing means 32-1 using a window 40-1 shown in FIG. The five lines of image data read from the first temporary storage unit 31 are simultaneously output to the image processing unit 32-2 using the window 40-2 shown in FIG.
The image processing means 32-1 generates a matrix from the data of 13 main-scanning pixels and 9 sub-scanning lines and reduces each value of the target pixel and peripheral pixels in order to reduce the jagged edges and arcs of the edge of the image. The feature of the pixel of interest is extracted based on the above, the value of the pixel of interest is determined, and the image processing means 32-2 generates a matrix from the data of the main scanning 5 pixels and the sub-scanning 5 lines, and Based on each value, the feature of the target pixel is extracted, and the value of the target pixel is determined.
Further, the image processing means 32 performs this smoothing process for each second pixel clock, thereby converting all the pixels into multi-value data having a plurality of bits per pixel. From the multi-value data for each pixel output from the two image processing means 32-1 and 32-2, the output image data from any one of the image processing means 32 is selectively output by the selector 33.

FIG. 4A is a block diagram showing a schematic configuration of the image processing unit 32-1 in FIG. 2, and FIG. 4B is a block diagram showing a schematic configuration of the image processing unit 32-2. FIG. 5A is a diagram showing the configuration of the window 40-1, which is the main part of the image processing means 32-1, and FIG. 5B is the configuration of the window 40-2 of the image processing means 32-2. FIG.
As shown in FIGS. 4A and 4B, the image processing means 32-1 and 32-2 respectively include a window 40, a pattern recognition unit 41, a memory block 42, a video data output unit 43, and these. And a timing control unit 44 that performs synchronous control.
A window 40-1 for the image processing means 32-1 is a shift register 40- for 13 pixels each in the main scanning direction for the image data for 9 lines output from the first temporary storage means 31 of FIG. 1a to 40-1i are serially connected to form a pattern detection window, and the window 40-2 for the image processing unit 32-2 is output from the first temporary storage unit 31 of FIG. With respect to image data for lines, shift registers 40-2c to 40-2g for 5 pixels are serially connected to each other in the main scanning direction to form a pattern detection window.
However, as described above, nine lines of image data read from the first temporary storage unit 31 are output to the image processing unit 32-1, and five lines are output to the image processing unit 32-2. The
As for the window 40-1 constituting the image processing means 32-1, the pixel position of the seventh pixel from the left end of the shift register 40-1e as shown in FIG. 5A (marked with (1) in FIG. 5A). The window 40-2 constituting the image processing means 32-2 is 3 from the left end of the shift register 40-2e as shown in FIG. 5B. The pixel position of the pixel (shown by (2) in FIG. 5B) is the storage position of the target pixel of interest.
Next, in the image processing means 32-1, the image data is sequentially shifted one pixel at a time within the shift registers 40-1a to 40-1i constituting the window 40-1, so that the pixel of interest is image processing means 32-1. The image data of the window 40-1 centering on the target pixel can be extracted continuously.
Further, in the image processing means 32-2, the pixel of interest is transferred to the image processing means 32-2 by sequentially shifting the image data pixel by pixel within the shift registers 40-2c to 40-2g constituting the window 40-2. On the other hand, the image data of the window 40-2 centering on the target pixel can be extracted continuously.

FIG. 6 shows a state in which the image data is sequentially shifted pixel by pixel within the shift registers 40-1a to 40-1i constituting the window 40-1 disposed for the image processing means 32-1. is there.
The diagram on the left side of FIG. 6 is shown in FIG. 5A at an arbitrary rising edge (at time T1 in the drawing) of the second pixel clock for the image data input from the image processing unit 16 in FIG. The image data in the shift registers 40-1a to 40-1i constituting the window 40-1 is shown.
Next, the diagram on the right side in FIG. 6 shows FIG. 5A at the rising edge of the second pixel clock (at T2 in the figure) that comes after an arbitrary rising edge of the second pixel clock. The image data in the shift registers 40-1a to 40-1i constituting the window 40-1 shown in FIG.
By sequentially shifting the image data in the shift registers 40-1a to 40-1i constituting the window 40-1 for each second pixel clock one pixel at a time, the image processing means 32-1 starts from the beginning of each line. The dot information is extracted with this pixel as the target pixel.

Although not shown here, the operation of shifting the image data sequentially one pixel at a time in the shift registers 40-2c to 40-2g constituting the window 40-2 arranged for the image processing means 32-2 is also described above. The operation is the same as that for the window 40-1.
The pattern recognition units 41-1 and 41-2 are the target pixel (target pixel) and surrounding information based on the dot information extracted for the target pixel of the windows 40-1 and 40-2. In particular, it is a block that recognizes the feature of the line segment shape at the boundary between the black pixel and the white pixel of the image data and outputs the recognition result as code information of a predetermined format.
The code information output from the pattern recognition unit 41-1 serves as a memory read address during image processing (smoothing) of the memory block 42-1, and the code information output from the pattern recognition unit 41-2 is stored in the memory. This is a read address for the memory at the time of image processing (smoothing) of the block 42-2.

FIG. 7 is a block diagram showing the internal configuration of the pattern recognition unit 41-1 and the relationship with the window 40-1. The sample window 40-1 is divided into a central 3 × 3 bit core area (Core) 40C, an upper area (Lower) 40D, a left area (Left) 40L, and a right area (Right) 40R. The However, the details thereof are the same as those described in Japanese Patent Application Nos. 3-314928 and 4-301395, which are the prior applications of the applicant of the present application, and are therefore omitted here.
Further, the pattern recognition unit 41-1 includes a core region recognition unit 411, a peripheral region recognition unit 412, multiplexers 413 and 414, a gradient (Gradient) calculation unit 415, a position (Position) calculation unit 416, a determination unit 417, and a gate 418. The peripheral region recognition unit 412 is further configured by an upper region recognition unit 412U, a right region recognition unit 412R, a lower region recognition unit 412D, and a left region recognition unit 412L. The actions of these parts are also the same as those described in Japanese Patent Application Nos. 3-314928 and 4-301395, which are the prior applications of the applicant of the present application, and are therefore omitted here.
In addition, regarding the internal configuration of the pattern recognition unit 41-2 and the relationship with the window 40-2, although not shown, the 3 × 3-bit core area (Core) 40C described above corresponds to a configuration of only a 5 × 5 core area. There are methods such as.

FIG. 8 is a diagram illustrating a configuration example of the memory block 42. A specific configuration example and operation of the memory block 42 will be described with reference to FIG. FIG. 8 is the same as the contents described in Japanese Patent Application Nos. 3-314928 and 4-301395, which are prior applications of the applicant of the present application, and the memory block 42 is composed of only the pattern memory 421, and the pattern recognition unit. The correction information (10 bits) stored in advance is read out using the code information (12 bits) output from 41 as an address, and image data for laser driving is output, which becomes a corrected dot pattern.
In the prior art, a horizontal line segment black pixel determined to be a pixel that does not require correction as a pixel constituting a diagonal line or an arc by the determination unit 417 shown in FIG. 7 has a width in the vertical direction of one pixel line or two or more pixels. The top black pixel or the bottom black pixel of the line (that is, the boundary between the black pixel region and the white pixel region in the image data developed in the form of a bitmap, but is not a pixel constituting the shaded line segment with jaggy. Some bits of the multi-bit code information representing the feature of the line segment shape for the black pixel) are replaced with unique values.
The smoothing correction data stored in advance in the memory block 42 of the image processing means 32 corresponds to the code information from the pattern recognition unit 41 in the memory block 42 before image processing (smoothing) is performed on the image data. Data must be set. The correction data setting I / F can be handled by writing data stored in a built-in memory arranged in the image forming apparatus system by the CPU.
According to the embodiment of the memory block 42 shown in FIG. 8, the correction data output is obtained by dividing the laser emission time into a plurality of main scanning 1 pixel widths for each pixel of the input image data (in this case, binary PWM). Signal output) or multi-value information. Even at this time, each correction data output is output for one pixel every second pixel clock.
The correction data output that is output by one pixel every second pixel clock is finally input to the image data conversion means and output as an output converted into the image data format for one pixel as described above. The data is output to the modulation unit 19, and the image data is written on the photosensitive drum 26 by ON / OFF of the LD of the LD modulation unit 19 and power control. The above is the embodiment of the invention described in claim 1.

Next, description will be given of the functional specifications of the apparatus according to the embodiment of the first aspect.
The larger the size of the window 40, the larger the number of pattern code information that is the result of extracting the features of the pixel of interest based on the values of the pixel of interest and the surrounding pixels, and the memory constituting the second temporary storage means 33 The number of data that should be stored in is also increased. In addition, as the number of the pattern code information increases, the number of target pixels that can be processed for individual pattern image data increases, and the effect of the smoothing process can be further expected. However, before the high-resolution image data is expected to have a smoothing effect, the image itself has less jaggies visible than the low-resolution image data, and the low-resolution image data is more visible. Since many jaggy are included, the effect of the smoothing process is expected.
According to the present invention, it is possible to perform smoothing processing on individual pixel patterns by using the large window 40-1 for low-resolution image data, and for high-resolution image data, By using a small window 40-2, it is possible to perform an accurate smoothing process for a jaggy occurrence location using image correction data stored in a smaller memory. Specifically, when processing image data of 600 dpi or less developed in a bitmap shape, the image processing unit 32-1 in FIG. 2 is used to process 1200 dpi image data developed in a bitmap shape. In this case, by using the image processing means 32-2 in FIG. 2, it is possible to accurately process the processing for improving the image quality of the input image data with the minimum correction data.
This is the embodiment of the second aspect.

Further, as shown in FIG. 9, the above-mentioned first temporary storage means 31 can be recognized by the image processing means 32-1 when the resolution is not more than an arbitrary resolution A developed in the form of a bitmap. As shown in FIG. 9, a line memory having a memory capacity (in FIG. 9, a resolution of 600 dpi or less of transfer sheet size A3 vertical) capable of storing all image data for one main scanning line of arbitrary resolution A is provided. Arbitrary resolution B composed of lines and expanded in the form of a bitmap in FIG. 10 (B is less than twice the resolution of A and more than A, 1200 dpi of transfer paper size A3 vertical) In this case, in order to enable the pattern recognition by the image processing unit 32-2, it is possible to store all the image data for one main scanning line of the resolution A used when the image processing unit 32-1 is used. A line memory having a re-capacity is added, and a line memory for 5 lines of resolution B is constituted by a line memory of 10 lines for resolution A, so that image processing means for resolution A with the minimum addition of memory The smoothing process by the image processing unit 32-2 with the resolution B can be simultaneously performed while the smoothing process by the 32-1 can be performed.
This is an embodiment as claimed in claim 3.

Additional explanation of FIG. 4 will be described below. The timing control unit 44 includes an FGATE signal that defines a writing period for one page of image data in the sub-scanning direction, an LGATE signal that defines a writing period for one main scanning line, and an LSYNC that indicates the writing start and end timing of each line. Signals: Image clock WCLK and RESET signal that take a reading and writing cycle for each dot are input, and a clock signal and the like necessary to synchronize the operation are generated for each block 40 to 42 in FIG.
The correction data in the memory block 42 can be selectively loaded from a storage means such as a ROM by the MPU or CPU in the image forming apparatus system, or can be downloaded from the host computer 1. It is possible to easily change the correction data for the pattern to be corrected.

1 is a configuration diagram showing a digital copying machine to which a print control unit that is an embodiment of an image data processing apparatus according to the present invention is applied. FIG. FIG. 2 is a block diagram illustrating in detail a print control unit 18 in FIG. 1. 4 is a timing chart showing an operation of reading image data in units of one pixel by a second pixel clock from the first temporary storage unit 31. (A) is a block diagram showing a schematic configuration of the image processing means 32-1 in FIG. 2, and (b) is a block diagram showing a schematic configuration of the image processing means 32-2. (A) is a figure which shows the structure of the window 40-1 which is the principal part of the image processing means 32-1, (b) is a figure which shows the structure of the window 40-2 of the image processing means 32-2. It is explanatory drawing which shows a mode that image data shifts one pixel at a time within the shift registers 40-1a-40-1i which comprise the window 40-1 arrange | positioned with respect to the image processing means 32-1. It is a block diagram which shows the internal structure of the pattern recognition part 41-1, and the relationship with the window 40-1. 3 is a diagram illustrating a configuration example of a memory block 42. FIG. It is explanatory drawing which shows the case below the arbitrary resolution A expand | deployed by the bitmap form. It is explanatory drawing which shows the case of the resolution below arbitrary resolution B expanded | deployed by the bitmap form, and more than A.

Explanation of symbols

32-1 Image processing unit 32-2 Image processing unit 40 Window 41 Pattern recognition unit 42 Memory block 43 Video data output unit 44 Timing control unit

Claims (3)

  Storage means capable of storing binary image data of an arbitrary resolution A expanded in a bitmap shape for N lines, and a pixel as a target of the image data expanded in a bitmap shape stored in the storage means First window means of main scanning M pixels × sub-scanning N lines (M and N are both integers) and main scanning P pixel × sub-scanning Q lines (P, Q Both recognize the line segment shape of the boundary portion between the second window means of integer, Q ≠ N and Q <N) and the white pixel of the black pixel area of the image data extracted through the first window means. Image data extracted through the second window means and first pattern recognition means for generating a plurality of bits of pattern code information representing the feature of the recognized line segment shape for the pixel as the object of the image data Recognizing the line segment shape of the boundary between the black pixel area and the white pixel in the black pixel region, and generating the multi-bit pattern code information representing the characteristics of the recognized line segment shape for the target pixel of the image data Discriminating means for discriminating whether or not the pixel that is the target of the image data is a pixel that needs to be corrected as a pixel constituting an oblique line or an arc by using at least a part of the pattern code information And a memory block means for reading out and outputting pre-stored correction data, with the pattern code information generated by the pattern recognition means as an address, for the pixels determined to be corrected by the determination means. An image data processing apparatus comprising:   2. The image data processing apparatus according to claim 1, wherein when processing binary image data having an arbitrary resolution A or less developed in a bitmap shape, the first window means and the first pattern recognition means are used. For a target pixel, a plurality of bits of pattern code information representing the feature of the recognized line segment shape is generated, and an arbitrary resolution B (B is equal to or less than twice the resolution of A) expanded in a bitmap shape. When processing binary image data, multi-bit pattern code information representing the feature of the recognized line segment shape for the pixel as the object of the image data using the second window means and the second pattern recognition means. Generating an image data processing apparatus.   3. The image data processing apparatus according to claim 2, wherein when processing binary image data of an arbitrary resolution B (B is equal to or less than twice the resolution of A) expanded in the bitmap shape, the second window means An image data processing apparatus, wherein the number Q of sub-scanning lines is N / 2 + 1 lines or less.

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