JP2005092793A - Electronic appliance circuit - Google Patents

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JP2005092793A
JP2005092793A JP2003328929A JP2003328929A JP2005092793A JP 2005092793 A JP2005092793 A JP 2005092793A JP 2003328929 A JP2003328929 A JP 2003328929A JP 2003328929 A JP2003328929 A JP 2003328929A JP 2005092793 A JP2005092793 A JP 2005092793A
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lsi
resistor
drive voltage
temperature
voltage
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Seiichi Uno
誠一 宇野
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NEC Engineering Ltd
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NEC Engineering Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an electronic appliance circuit where LSI design is easy even in a fast circuit and which is small and operates stably by reducing variation of signal propagation delay time inside of LSI with respect to temperature variation. <P>SOLUTION: The temperature of an LSI package case is detected by a thermister Rth1 of a temperature negative characteristic and thermister Rth2 of a temperature positive characteristic, and intermediate voltage Vk obtained by dividing LSI driving voltage is compared with reference voltage by an error amplifier 2. The intermediate voltage is varied by the variation of the resistance value of a thermister with the temperature of the package case of the LSI. The variation of the intermediate voltage is compared with the voltage of a reference signal source by an error amplifier to control LSI driving voltage. By controlling the LSI driving voltage to be high when the temperature of the package case is high and to be low when the temperature of the package case is low, variation of the signal propagation delay time inside of the LSI with respect to temperature (delay coefficient) is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、温度変動によるLSI内半導体回路の信号伝搬遅延時間の変動を抑制した電子機器回路に関する。   The present invention relates to an electronic device circuit in which fluctuations in signal propagation delay time of a semiconductor circuit in an LSI due to temperature fluctuations are suppressed.

LSI(大規模集積回路)の内部半導体回路の信号伝搬遅延時間は、半導体チップ温度(ジャンクション温度)およびLSI駆動電圧に依存している。特に、宇宙等熱対流のない環境下においては、ジャンクション温度とLSIパッケージケース温度は比例関係にある。すなわち、図8に示すように、LSIパッケージケース温度が上昇すれば信号伝搬遅延時間は増加し、LSIパッケージケース温度が低下すれば信号伝搬遅延時間は減少する。また、図9に示すように、LSI駆動電圧が上昇すれば信号伝搬遅延時間は減少し、LSI駆動電圧が低下すれば信号伝搬遅延時間は増加する。   The signal propagation delay time of an internal semiconductor circuit of an LSI (Large Scale Integrated circuit) depends on the semiconductor chip temperature (junction temperature) and the LSI drive voltage. In particular, in an environment without thermal convection such as in space, the junction temperature and the LSI package case temperature are in a proportional relationship. That is, as shown in FIG. 8, the signal propagation delay time increases as the LSI package case temperature increases, and the signal propagation delay time decreases as the LSI package case temperature decreases. As shown in FIG. 9, the signal propagation delay time decreases as the LSI drive voltage increases, and the signal propagation delay time increases as the LSI drive voltage decreases.

LSI設計においては、温度や電圧それぞれについて、ワースト条件下においても正常動作するように信号伝搬遅延時間に対して考慮される。しかし、宇宙等温度変動が大きく、また、熱対流がないために空冷ファン等が使用できず温度制御が困難な環境下での用途や、高速回路等タイミングの厳しい回路の設計は、信号伝搬遅延時間の変動を吸収する回路を必要とし、タイミング設計マ-ジンの検証が必要なため回路設計を複雑にしている。   In LSI design, the signal propagation delay time is taken into consideration so that each temperature and voltage can operate normally even under worst conditions. However, in applications where temperature control is difficult due to large temperature fluctuations in space, etc., and air cooling fans cannot be used because there is no thermal convection, and design of circuits with strict timing such as high-speed circuits, signal propagation delay The circuit design is complicated because it requires a circuit that absorbs time fluctuations and the timing design margin needs to be verified.

LSI駆動電源回路の出力電圧変動への対策を講じた従来の電子機器回路の例を図6に示す(文献公知発明でない)。この電子機器回路は、電源回路1のシリーズバストランジスタ4から出力されるLSI駆動電圧Voutを固定抵抗R1とR2とで分圧した中間電圧Vkを誤差増幅器2のマイナス入力端子に導いている。誤差増幅器2のプラス入力端子には基準信号源3からの基準電圧Vrefが供給され、誤差増幅器2の出力はシリーズバストランジスタ4のベース端子に供給されている。シリーズバストランジスタ4のコレクタ端子には入力電圧が供給され、エミッタ端子に現れる電圧がLSI駆動電圧Voutとされている。   FIG. 6 shows an example of a conventional electronic device circuit that takes measures against fluctuations in the output voltage of the LSI drive power supply circuit (not a known invention in the literature). In this electronic device circuit, an intermediate voltage Vk obtained by dividing the LSI drive voltage Vout output from the series bus transistor 4 of the power supply circuit 1 by the fixed resistors R1 and R2 is led to the negative input terminal of the error amplifier 2. The positive input terminal of the error amplifier 2 is supplied with the reference voltage Vref from the reference signal source 3, and the output of the error amplifier 2 is supplied to the base terminal of the series bus transistor 4. An input voltage is supplied to the collector terminal of the series bus transistor 4, and the voltage appearing at the emitter terminal is used as the LSI drive voltage Vout.

いま、入力電圧の変動によりLSI駆動電圧Voutが大きくなれば、中間電圧Vkと基準電圧Vrefとの差が小さくなるので、シリーズバストランジスタ4のコレクタ電流が減少してLSI駆動電圧Voutを降下させるように作用する。逆に、LSI駆動電圧Voutが小さくなれば、中間電圧Vkと基準電圧Vrefとの差が大きくなるので、シリーズバストランジスタ4のコレクタ電流が増加してLSI駆動電圧Voutを上昇させるように作用する。このようにして、入力電圧の変動によるLSI駆動電源回路の出力電圧は常に一定になるよう制御することにより、信号伝搬遅延時間の変動を抑制している。   Now, if the LSI drive voltage Vout increases due to fluctuations in the input voltage, the difference between the intermediate voltage Vk and the reference voltage Vref decreases, so the collector current of the series bus transistor 4 decreases and the LSI drive voltage Vout drops. Act on. On the contrary, if the LSI drive voltage Vout decreases, the difference between the intermediate voltage Vk and the reference voltage Vref increases, so that the collector current of the series bus transistor 4 increases and the LSI drive voltage Vout is increased. In this way, fluctuations in the signal propagation delay time are suppressed by controlling the output voltage of the LSI drive power supply circuit to be always constant due to fluctuations in the input voltage.

また、温度変動への対策を講じた従来の電子機器回路の例を図7に示す(例えば、特許文献1参照)。この電子機器回路は、温度が上がると動作速度が遅くなるという図8の性質と、電源電圧が上がると動作速度が速くなるという図9の性質とを利用することにより、遅延素子13の遅延値を一定値に保つというものである。   FIG. 7 shows an example of a conventional electronic device circuit that takes measures against temperature fluctuations (see, for example, Patent Document 1). The electronic device circuit uses the property shown in FIG. 8 that the operation speed becomes slower when the temperature rises and the property shown in FIG. 9 that the operation speed becomes faster when the power supply voltage rises. Is maintained at a constant value.

いま、遅延素子13の遅延値が所定値からの偏差を生じる場合、温度測定器14がその温度変化に対応した温度情報を電源電圧制御回路15に出力する。電源電圧制御回路15は温度情報に対応した偏差を相殺し、遅延値を一定に保つ。   If the delay value of the delay element 13 deviates from a predetermined value, the temperature measuring device 14 outputs temperature information corresponding to the temperature change to the power supply voltage control circuit 15. The power supply voltage control circuit 15 cancels the deviation corresponding to the temperature information and keeps the delay value constant.

特開平3−85814(第2頁、図1)Japanese Patent Laid-Open No. 3-85814 (2nd page, FIG. 1)

しかしながら、図6に表示の従来技術は温度変動に対処したものではなく、図7に表示の従来技術は電圧変動に対処したものでない。   However, the prior art shown in FIG. 6 does not deal with temperature fluctuations, and the prior art shown in FIG. 7 does not deal with voltage fluctuations.

したがって、両技術を併用したとしても、宇宙用の搭載電子機器等のように、温度変動が大きく、更に熱対流がないため温度制御が困難な環境下においては、内部の信号伝搬遅延時間の大きな変動に対する動作マージンの検証と確保が必要なため、LSI駆動電圧を広く制御できなければならないので、温度変動によるLSI内部の信号伝搬遅延時間の変動を考慮したLSI設計が複雑になるという第1の問題点がある。   Therefore, even if both technologies are used together, the internal signal propagation delay time is large in an environment where temperature control is difficult due to large temperature fluctuations and no thermal convection, such as onboard electronic equipment for space use. Since it is necessary to verify and ensure the operation margin against fluctuations, the LSI drive voltage must be widely controlled, so that the LSI design taking into account fluctuations in the signal propagation delay time inside the LSI due to temperature fluctuations becomes complicated. There is a problem.

また、内部信号の大きな伝搬遅延時間変動に対する動作マージン確保のために、対策回路や遅延素子を追加しなければならないのでは、回路の集積度が抑圧されるという第2の問題点がある。このことは、小型軽量が要請される宇宙用の搭載電子機器等においては深刻な問題となる。   Further, if a countermeasure circuit or a delay element has to be added in order to ensure an operation margin against a large propagation delay time fluctuation of the internal signal, there is a second problem that the degree of circuit integration is suppressed. This is a serious problem in space-mounted electronic devices that require small size and light weight.

そこで、本発明の目的は、簡単な構成で、体積,重量および消費電力を増加させずに宇宙用の搭載電子機器等動作温度範囲の大きい電子機器において、温度変動に対するLSI内部信号の伝搬遅延時間の変動を少なくし、高速回路においてもLSI設計を容易にし、かつ安定した動作を得ることができる電子機器回路を提供することにある。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a propagation delay time of an LSI internal signal with respect to temperature fluctuations in an electronic device having a large operating temperature range such as a space-mounted electronic device with a simple configuration without increasing volume, weight and power consumption. It is an object of the present invention to provide an electronic device circuit that can reduce LSI fluctuations, facilitate LSI design even in a high-speed circuit, and obtain stable operation.

請求項1記載の発明は、LSI駆動電圧の変動を抑制する電源回路を備えた電子機器回路において、当該LSIのパッケージケースに密着して固定され温度負特性を有する第1のサーミスタを含んで一端がLSI駆動電圧に接続された第1の抵抗と、一端が第1の抵抗、他端が大地に接続され固定抵抗から成る第2の抵抗とを設け、第1の抵抗と第2の抵抗によってLSI駆動電圧を分圧した中間電圧を電源回路へ負帰還することを特徴とする。   According to a first aspect of the present invention, an electronic device circuit including a power supply circuit that suppresses fluctuations in LSI drive voltage includes a first thermistor that is fixed in close contact with a package case of the LSI and has negative temperature characteristics. Is provided with a first resistor connected to the LSI drive voltage, a first resistor at one end, and a second resistor consisting of a fixed resistor connected at the other end to the ground. The first resistor and the second resistor An intermediate voltage obtained by dividing the LSI drive voltage is negatively fed back to the power supply circuit.

請求項2記載の発明は、LSI駆動電圧の変動を抑制する電源回路を備えた電子機器回路において、一端がLSI駆動電圧に接続された固定抵抗から成る第1の抵抗と、当該LSIのパッケージケースに密着して固定され温度正特性を有するサーミスタを含んで一端が第1の抵抗、他端が大地に接続された第2の抵抗とを設け、第1の抵抗と第2の抵抗とによってLSI駆動電圧を分圧した中間電圧を電源回路へ負帰還することを特徴とする。   According to a second aspect of the present invention, there is provided an electronic device circuit including a power supply circuit that suppresses fluctuations in LSI drive voltage, a first resistor including a fixed resistor having one end connected to the LSI drive voltage, and a package case of the LSI Including a thermistor fixed in close contact with the temperature positive characteristic, one end having a first resistor and the other end having a second resistor connected to the ground. The first resistor and the second resistor provide LSI. An intermediate voltage obtained by dividing the drive voltage is negatively fed back to the power supply circuit.

請求項3記載の発明は、LSI駆動電圧の変動を抑制する電源回路(図1の1)を備えた電子機器回路において、当該LSIのパッケージケースに密着して固定され温度負特性を有する第1のサーミスタ(図1のRth1)を含んで一端がLSI駆動電圧に接続された第1の抵抗と、当該LSIのパッケージケースに密着して固定され温度正特性の第2のサーミスタ(図1のRth2)を含んで一端が第1の抵抗、他端が大地に接続された第2の抵抗とを設け、第1の抵抗と第2の抵抗によってLSI駆動電圧を分圧した中間電圧を電源回路へ負帰還することを特徴とする。   According to a third aspect of the present invention, there is provided an electronic device circuit including a power supply circuit (1 in FIG. 1) that suppresses fluctuations in LSI drive voltage, and is fixed in close contact with the package case of the LSI and has a negative temperature characteristic. Including a first thermistor (Rth1 in FIG. 1), one end of which is connected to the LSI drive voltage, and a second thermistor (Rth2 in FIG. 1) that is fixed in close contact with the package case of the LSI. ) Including a first resistor at one end and a second resistor connected at the other end to the ground, and an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor is supplied to the power supply circuit. It is characterized by negative feedback.

請求項4記載の発明は、請求項1ないし3のいずれかにおいて、電源回路(図1の1)は、第1の抵抗と第2の抵抗によってLSI駆動電圧を分圧した中間電圧と基準電圧(図1のVref)との誤差を検出する誤差増幅器(図1の2)と、ベース端子に該誤差増幅器の出力が供給され、コレクタ端子が入力電源に接続されて、エミッタ端子からLSI駆動電圧を出力するシリーズバストランジスタ(図1の4)を備え、LSI駆動電圧が所定の2つの温度におけるLSI内部の信号伝搬遅延時間を補償して同一とするに、第1の抵抗の抵抗値に対する第2の抵抗の抵抗値の比を設定することを特徴とする。   According to a fourth aspect of the present invention, in any one of the first to third aspects, the power supply circuit (1 in FIG. 1) includes an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor, and a reference voltage. An error amplifier (2 in FIG. 1) for detecting an error from (Vref in FIG. 1), an output of the error amplifier is supplied to a base terminal, a collector terminal is connected to an input power source, and an LSI drive voltage is supplied from an emitter terminal. A series bus transistor (4 in FIG. 1) is provided, and the LSI drive voltage compensates for the signal propagation delay time in the LSI at two predetermined temperatures to be the same. The ratio of the resistance values of the two resistors is set.

本発明の第1の効果は、温度センサとしてサーミスタ等の温度抵抗変化素子によりLSIのパッケ−ジケ-ス温度変動を検出し、その信号でLSI駆動電圧を制御する構成としたため、温度補償と電圧補償とを一体化、したがってLSI内部の信号伝搬遅延時間の変動抑制用追加回路を削減し、回路の集積を高めて他ICを削除できるので、装置の性能向上とともに小型化および低価格化を図ることができるということである。これにより、宇宙用の搭載電子機器のみならず、同様な使用環境に晒される工業用の電子機器においても抜群の効用を発揮する。   The first effect of the present invention is that the temperature variation of the LSI package is detected by a temperature resistance change element such as a thermistor as a temperature sensor, and the LSI drive voltage is controlled by that signal. Compensation is integrated, so additional circuits for suppressing fluctuations in signal propagation delay time inside the LSI can be reduced, and other ICs can be eliminated by increasing circuit integration, thus improving device performance and reducing size and price Is that you can. As a result, not only on-board electronic equipment for space use, but also on industrial electronic equipment that is exposed to the same usage environment, it exhibits outstanding utility.

また、第2の効果は、第1の効果の波及効果として、LSI設計における温度変動によるタイミングマージンの検証を容易化するできるため、LSI設計を単純化し、設計期間の短縮を図ることができるということである。   In addition, the second effect is that, as a ripple effect of the first effect, it is possible to facilitate the verification of the timing margin due to temperature fluctuations in the LSI design, so that the LSI design can be simplified and the design period can be shortened. That is.

この発明では、LSIのパッケージケース温度を正ないしは負、または正負の特性を持った温度センサで検出し、温度センサからの中間電圧と基準電圧とを誤差増幅器で比較することでLSI駆動電圧を制御する。誤差増幅器に入力する中間電圧を温度ー抵抗変化素子であるサーミスタ等で分圧することで得る。   In the present invention, the LSI package case temperature is detected by a temperature sensor having positive, negative, or positive / negative characteristics, and the LSI drive voltage is controlled by comparing the intermediate voltage from the temperature sensor with a reference voltage using an error amplifier. To do. The intermediate voltage input to the error amplifier is obtained by dividing the voltage with a thermistor that is a temperature-resistance change element.

LSIのパッケージケース温度によりサーミスタの抵抗値が変化し中間電圧が変化する。この中間電圧の変化と基準電圧とを誤差増幅器により比較し、LSI駆動電圧を制御する。パッケージケース温度が高い時にはLSI駆動電圧を高くし、またパッケージケース温度が低い時にはLSI駆動電圧を低くなるよう制御することにより温度に対するLSI内部の信号伝搬遅延時間の変動(遅延係数)を小さくする。中間電圧を直列に接続された正負のサ-ミスタ間とGND間電圧とすれば、LSI駆動電圧の変動の感度が良くなり、制御範囲を大きくすることが可能である。   The resistance value of the thermistor changes depending on the LSI package case temperature, and the intermediate voltage changes. The change in the intermediate voltage and the reference voltage are compared by an error amplifier to control the LSI drive voltage. By controlling the LSI drive voltage to be high when the package case temperature is high and to lower the LSI drive voltage when the package case temperature is low, the fluctuation (delay coefficient) of the signal propagation delay time in the LSI with respect to the temperature is reduced. If the intermediate voltage is the voltage between the positive and negative thermistors connected in series and the voltage between GND, the sensitivity of fluctuation of the LSI drive voltage is improved and the control range can be increased.

次に、本発明の電子機器回路の実施例について図面を参照して詳細に説明する。   Next, embodiments of the electronic device circuit of the present invention will be described in detail with reference to the drawings.

図1を参照すると、この電子機器回路は、電源回路1のシリーズバストランジスタ4がLSI5に供給するLSI駆動電圧VoutをサーミスタRth1とサーミスタRth2で分割した中間電圧Vkを電源回路1に負帰還負帰還し、これによってLSI5の電源変動および温度変動に対するLSI5の信号伝搬遅延時間を制御するものである。   Referring to FIG. 1, in this electronic device circuit, an intermediate voltage Vk obtained by dividing the LSI drive voltage Vout supplied from the series bus transistor 4 of the power supply circuit 1 to the LSI 5 by the thermistor Rth1 and the thermistor Rth2 is negatively fed back to the power supply circuit 1. Thus, the signal propagation delay time of the LSI 5 with respect to the power supply fluctuation and temperature fluctuation of the LSI 5 is controlled.

すなわち、コレクタ端子が入力電圧に接続され、エミッタ端子からLSI駆動電圧Voutを出力するシリーズバストランジスタ4のベース端子に誤差増幅器2の出力が供給されている。誤差増幅器2のプラス入力端子には基準信号源3からの基準電圧Vrefが供給され、誤差増幅器2のマイナス入力端子に中間電圧を導いている。   That is, the collector terminal is connected to the input voltage, and the output of the error amplifier 2 is supplied to the base terminal of the series bus transistor 4 that outputs the LSI drive voltage Vout from the emitter terminal. The reference voltage Vref from the reference signal source 3 is supplied to the plus input terminal of the error amplifier 2, and an intermediate voltage is led to the minus input terminal of the error amplifier 2.

いま、誤差増幅器2のオープンループゲインをAとすると次式が成り立つ。
Vout=(A/β(1+A))Vref
ここで、β=Rth1/(Rth1+Rth2)であり、便宜、Rth1はサーミスタRth1の抵抗値、Rth2はサーミスタRth2の抵抗値を表わすものとする。
Assuming that the open loop gain of the error amplifier 2 is A, the following equation is established.
Vout = (A / β (1 + A)) Vref
Here, β = Rth1 / (Rth1 + Rth2). For convenience, Rth1 represents the resistance value of the thermistor Rth1, and Rth2 represents the resistance value of the thermistor Rth2.

誤差増幅器のオープンループゲインAが1に比べて十分大きい場合、上式は次のようになる。
Vout≒Vref/β=Vref(Rth1+Rth2)/Rth1=Vref(1+(Rth2/Rth1))
したがって、LSI駆動電圧Voutはサーミスタ抵抗値Rth1とサーミスタ抵抗値Rth2の抵抗値比により決定され、抵抗値を変化させることによりLSI駆動電圧を変化させることが可能である。温度センサとしてサーミスタを利用することは宇宙用部品として十分実績があり、また、アクティブ素子ではないので消費電力増加とはならない。
When the open loop gain A of the error amplifier is sufficiently larger than 1, the above equation is as follows.
Vout≈Vref / β = Vref (Rth1 + Rth2) / Rth1 = Vref (1+ (Rth2 / Rth1))
Therefore, the LSI drive voltage Vout is determined by the resistance value ratio of the thermistor resistance value Rth1 and the thermistor resistance value Rth2, and the LSI drive voltage can be changed by changing the resistance value. The use of a thermistor as a temperature sensor has a sufficient track record as a space component, and does not increase power consumption because it is not an active element.

サーミスタRth1は図2に示すような負の温度特性、すなわち温度が上昇すると抵抗値が減少するという特性を有し、サーミスタRth2は図3に示すような正の温度特性、すなわち温度が上昇すると抵抗値が増加するという特性を有する。   The thermistor Rth1 has a negative temperature characteristic as shown in FIG. 2, that is, a characteristic that the resistance value decreases as the temperature rises, and the thermistor Rth2 has a positive temperature characteristic as shown in FIG. 3, that is, a resistance as the temperature rises. It has the property that the value increases.

サーミスタRth1とサ−ミスタRth2は、図4に示すように、LSI5のLSIパッケージケース6の表面または裏面に密着させて熱伝導性固着剤7で固定する。これによって、サーミスタRth1とサ−ミスタRth2がLSIパッケージケース6の温度、したがってLSI5のジャンクション温度を最短時間で正確に測定できる。図4における線材8は、サーミスタRth1,サ−ミスタRth2の端子を電源回路1または大地へ接続するためのものである。   As shown in FIG. 4, the thermistor Rth1 and the thermistor Rth2 are brought into close contact with the front or back surface of the LSI package case 6 of the LSI 5 and fixed with the heat conductive adhesive 7. Thereby, the thermistor Rth1 and the thermistor Rth2 can accurately measure the temperature of the LSI package case 6, and hence the junction temperature of the LSI 5, in the shortest time. The wire 8 in FIG. 4 is for connecting the terminals of the thermistor Rth1 and the thermistor Rth2 to the power supply circuit 1 or the ground.

いま、入力電圧の変動によりLSI駆動電圧Voutが大きくなれば基準電圧Vrefとの差が小さくなるので、シリーズバストランジスタ4のコレクタ電流が減少してLSI駆動電圧Voutを降下させるように作用する。逆に、LSI駆動電圧Voutが小さくなれば基準電圧Vrefとの差が大きくなるので、シリーズバストランジスタ4のコレクタ電流が増加してLSI駆動電圧Voutを上昇させるように作用する。このように、先ず負帰還によって、入力電圧の変動による電源回路1の出力電圧は常に一定になるよう制御することにより、LSI5の信号伝搬遅延時間の変動を抑止している。   Now, if the LSI drive voltage Vout increases due to fluctuations in the input voltage, the difference from the reference voltage Vref decreases, so that the collector current of the series bus transistor 4 decreases and the LSI drive voltage Vout is lowered. Conversely, if the LSI drive voltage Vout decreases, the difference from the reference voltage Vref increases, so that the collector current of the series bus transistor 4 increases and the LSI drive voltage Vout is increased. As described above, first, the fluctuation of the signal propagation delay time of the LSI 5 is suppressed by controlling the output voltage of the power supply circuit 1 to be always constant by the fluctuation of the input voltage by the negative feedback.

本実施例では、更に、サーミスタの正負特性によって温度変動に対するLSI駆動電圧Voutの調整感度を飛躍的に向上させている。サーミスタの正特性では温度が上昇するごとにサーミスタ抵抗値が増加し、負特性では温度が上昇するごとに抵抗値が減少する。そこで、サーミスタRth1に負特性のサ-ミスタ、そしてサーミスタRth2に正特性のサ-ミスタを採用する。   In the present embodiment, the sensitivity of adjusting the LSI drive voltage Vout with respect to temperature fluctuations is greatly improved by the positive and negative characteristics of the thermistor. In the thermistor positive characteristic, the thermistor resistance value increases as the temperature rises, and in the negative characteristic, the resistance value decreases as the temperature rises. Therefore, a thermistor having a negative characteristic is adopted as the thermistor Rth1, and a thermistor having a positive characteristic is adopted as the thermistor Rth2.

LSIパッケージケース6の温度が上昇するとLSI5の信号伝搬遅延時間が増加する傾向になる。このとき、サーミスタRth1の抵抗値は減少し、かつサーミスタRth2の抵抗値は増加する。このため、上式から明らかなように、LSI駆動電圧Voutが増大し、LSI5の信号伝搬遅延時間を減少する傾向に導く。   When the temperature of the LSI package case 6 rises, the signal propagation delay time of the LSI 5 tends to increase. At this time, the resistance value of the thermistor Rth1 decreases and the resistance value of the thermistor Rth2 increases. For this reason, as is apparent from the above equation, the LSI drive voltage Vout increases and the signal propagation delay time of the LSI 5 tends to decrease.

逆に、LSIパッケージケース6の温度が下降するとLSI5の信号伝搬遅延時間が減少する傾向になる。このとき、サーミスタRth1の抵抗値は増加し、かつサーミスタRth2の抵抗値は減少する。このため、上式から明らかなように、LSI駆動電圧Voutが減少し、LSI5の信号伝搬遅延時間を増加する傾向に導く。   Conversely, when the temperature of the LSI package case 6 decreases, the signal propagation delay time of the LSI 5 tends to decrease. At this time, the resistance value of the thermistor Rth1 increases and the resistance value of the thermistor Rth2 decreases. For this reason, as is apparent from the above equation, the LSI drive voltage Vout decreases, leading to a tendency to increase the signal propagation delay time of the LSI 5.

この場合、サーミスタRth1に負特性のサ-ミスタ、サーミスタRth2に正特性のサ-ミスタを採用することにより、温度変動に対する(Rth2/Rth1)の値の変化が大きくなるため、上式から明らかなように、LSI駆動電圧Voutの変化が大きくなるので、電源電圧調整の感度を上げ、かつ広範囲の制御を行うことができることとなる。   In this case, by adopting a thermistor with negative characteristics for the thermistor Rth1 and a thermistor with positive characteristics for the thermistor Rth2, the change in the value of (Rth2 / Rth1) with respect to temperature fluctuations becomes large. As described above, since the change in the LSI drive voltage Vout becomes large, the sensitivity of the power supply voltage adjustment can be increased and a wide range of control can be performed.

かくして、サーミスタの温度特性とLSI駆動電圧Voutの変動によるLSI5内部の信号伝搬遅延時間変動とを適切に組み合わせにすることにより、温度変動によるLSI5内部の信号伝搬遅延時間の変動を補償することが可能である。   Thus, by appropriately combining the temperature characteristics of the thermistor and the signal propagation delay time fluctuation in the LSI 5 due to the fluctuation of the LSI drive voltage Vout, it is possible to compensate for the fluctuation in the signal propagation delay time in the LSI 5 due to the temperature fluctuation. It is.

例えば、温度変動によるLSI5内部の信号伝搬遅延時間変動の比を、25℃時の信号伝搬遅延時間を1として、-40℃時が0.8、+80℃時が1.2の比例関係にあるとする。また、LSI駆動電圧Voutの変動によるLSI5内部の信号伝搬遅延時間変動の比を、25℃,+5.0V時の信号伝搬遅延時間を1として、+4.75V時が1.5、+5.25V時が0.7の逆比例の関係があるとする。   For example, it is assumed that the ratio of the signal propagation delay time variation in the LSI 5 due to temperature variation is proportional to 0.8, when the signal propagation delay time at 25 ° C. is 1, and when + 40 ° C. is 1.2. In addition, the ratio of the signal propagation delay time fluctuation in the LSI 5 due to the fluctuation of the LSI drive voltage Vout is 1.5, the signal propagation delay time at 25 ° C. and +5.0 V is 1, 1.5 at +4.75 V, 0.7 at +5.25 V Suppose there is an inversely proportional relationship.

-40℃時の信号伝搬遅延時間を25℃時の信号伝搬遅延時間と同一にするためには、LSI駆動電圧Voutの変動によるLSI内部信号遅延時間変動の比を1.25、つまりLSI駆動電圧Voutが-40℃時に4.91Vになるように(Rth2/Rth1)を決定すればよい。何故なら、0.8×1.25=1だからである。   In order to make the signal propagation delay time at -40 ° C the same as the signal propagation delay time at 25 ° C, the ratio of the LSI internal signal delay time variation due to the variation in LSI drive voltage Vout is 1.25, that is, the LSI drive voltage Vout is (Rth2 / Rth1) should be determined to be 4.91V at -40 ℃. This is because 0.8 × 1.25 = 1.

また、+80℃時の信号伝搬遅延時間を25℃時の信号伝搬遅延時間と同一にするためには、LSI駆動電圧Voutの変動によるLSI5内部の信号伝搬遅延時間変動の比を0.83、つまりLSI駆動電圧Voutが+80℃時に5.17Vになるように(Rth2/Rth1)を決定すればよい。何故なら、1.25×0.83≒1だからである。   Further, in order to make the signal propagation delay time at + 80 ° C. the same as the signal propagation delay time at 25 ° C., the ratio of the signal propagation delay time variation in the LSI 5 due to the variation of the LSI drive voltage Vout is 0.83, that is, the LSI (Rth2 / Rth1) may be determined so that the driving voltage Vout is 5.17 V when the driving voltage Vout is + 80 ° C. This is because 1.25 × 0.83 ≒ 1.

図5は本発明の電子機器回路の他の実施例を示す。この例では、LSI駆動電圧Voutを分割するのに、図1におけるサーミスタRth1の代わりにサーミスタ9,固定抵抗10および固定抵抗11の合成抵抗を採用し、図1におけるサーミスタRth2の代わりに固定抵抗12としている。このような構成により、図1の構成に比べると電源電圧調整の感度は鈍るが、信号伝搬遅延時間の変動を補償するに当ってLSI駆動電圧Voutの変動を少なくでき微調整を行うことが可能になる。   FIG. 5 shows another embodiment of the electronic device circuit of the present invention. In this example, in order to divide the LSI drive voltage Vout, the combined resistance of the thermistor 9, the fixed resistor 10 and the fixed resistor 11 is adopted instead of the thermistor Rth1 in FIG. 1, and the fixed resistor 12 is substituted for the thermistor Rth2 in FIG. It is said. With such a configuration, the sensitivity of the power supply voltage adjustment is less than that of the configuration of FIG. 1, but the fluctuation of the LSI drive voltage Vout can be reduced and fine adjustment can be performed in compensating for the fluctuation of the signal propagation delay time. become.

なお、図5に限らず、図1におけるサーミスタRth1の代わりに固定抵抗12とし、図1におけるサーミスタRth2の代わりにサーミスタ9,固定抵抗10および固定抵抗11の合成抵抗を採用してもよい。更に、サーミスタと固定抵抗との合成抵抗を採用せず、図1におけるサーミスタRth1またはサーミスタRth2の一方のみを固定抵抗としてもよい。   Not limited to FIG. 5, the fixed resistor 12 may be used instead of the thermistor Rth1 in FIG. 1, and a combined resistor of the thermistor 9, fixed resistor 10 and fixed resistor 11 may be used instead of the thermistor Rth2 in FIG. Furthermore, the combined resistance of the thermistor and the fixed resistor may not be adopted, and only one of the thermistor Rth1 or thermistor Rth2 in FIG.

更に、以上の実施例では、温度抵抗変化素子としてサーミスタを採用しているが、本発明は、このことに限定されず、サーミスタの代わりに白金素子等を使用してもよい。   Furthermore, although the thermistor is employ | adopted as a temperature resistance change element in the above Example, this invention is not limited to this, You may use a platinum element etc. instead of a thermistor.

本発明の電子機器回路の一実施例を示すブロック図The block diagram which shows one Example of the electronic device circuit of this invention サーミスタの負特性を示す図Diagram showing the negative characteristics of the thermistor サーミスタの正特性を示す図Diagram showing the positive characteristics of the thermistor サーミスタのLSIパッケージケースへの取付方法を示す図Diagram showing the mounting method of the thermistor to the LSI package case 本発明の電子機器回路の他の実施例を示すブロック図The block diagram which shows the other Example of the electronic device circuit of this invention 従来技術の一例を示すブロック図Block diagram showing an example of the prior art 従来技術の他の例を示すブロック図Block diagram showing another example of the prior art LSIのパッケージケース温度とLSI内部の信号伝搬遅延時間との関係図Relationship between LSI package case temperature and internal signal propagation delay time LSI駆動電圧とLSI内部の信号伝搬遅延時間との関係図Relationship diagram between LSI drive voltage and internal signal propagation delay time

符号の説明Explanation of symbols

1 電源回路
2 誤差増幅器
3 基準信号源
4 シリーズバストランジスタ
5 LSI
6 LSIパッケージケース
7 熱伝導性固着剤
8 線材
9 サーミスタ
10〜12 固定抵抗
Rth1 サーミスタ
Rth2 サーミスタ
1 power supply circuit 2 error amplifier 3 reference signal source 4 series bus transistor 5 LSI
6 LSI package case 7 Thermal conductive adhesive 8 Wire material 9 Thermistor
10-12 Fixed resistance Rth1 thermistor Rth2 thermistor

Claims (4)

LSI駆動電圧の変動を抑制する電源回路を備えた電子機器回路において、
当該LSIのパッケージケースに密着して固定され温度負特性を有する第1のサーミスタを含んで一端が前記LSI駆動電圧に接続された第1の抵抗と、
一端が前記第1の抵抗、他端が大地に接続され固定抵抗から成る第2の抵抗とを設け、
前記第1の抵抗と前記第2の抵抗によって前記LSI駆動電圧を分圧した中間電圧を前記電源回路へ負帰還することを特徴とする電子機器回路。
In electronic equipment circuits with power supply circuits that suppress fluctuations in LSI drive voltage,
A first resistor having a first thermistor fixed in close contact with the package case of the LSI and having a negative temperature characteristic, one end of which is connected to the LSI drive voltage;
One end is provided with the first resistor, the other end is connected to the ground, and a second resistor comprising a fixed resistor is provided,
An electronic device circuit, wherein an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor is negatively fed back to the power supply circuit.
LSI駆動電圧の変動を抑制する電源回路を備えた電子機器回路において、
一端が前記LSI駆動電圧に接続された固定抵抗から成る第1の抵抗と、
当該LSIのパッケージケースに密着して固定され温度正特性を有するサーミスタを含んで一端が前記第1の抵抗、他端が大地に接続された第2の抵抗とを設け、
前記第1の抵抗と前記第2の抵抗とによって前記LSI駆動電圧を分圧した中間電圧を前記電源回路へ負帰還することを特徴とする電子機器回路。
In electronic equipment circuits with power supply circuits that suppress fluctuations in LSI drive voltage,
A first resistor comprising a fixed resistor having one end connected to the LSI drive voltage;
Including a thermistor fixed in close contact with the package case of the LSI and having a temperature positive characteristic, one end is provided with the first resistor, and the other end is provided with a second resistor connected to the ground.
An electronic device circuit, wherein an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor is negatively fed back to the power supply circuit.
LSI駆動電圧の変動を抑制する電源回路を備えた電子機器回路において、
当該LSIのパッケージケースに密着して固定され温度負特性を有する第1のサーミスタを含んで一端が前記LSI駆動電圧に接続された第1の抵抗と、
当該LSIのパッケージケースに密着して固定され温度正特性の第2のサーミスタを含んで一端が前記第1の抵抗、他端が大地に接続された第2の抵抗とを設け、
前記第1の抵抗と前記第2の抵抗によって前記LSI駆動電圧を分圧した中間電圧を前記電源回路へ負帰還することを特徴とする電子機器回路。
In an electronic equipment circuit equipped with a power supply circuit that suppresses fluctuations in LSI drive voltage,
A first resistor including a first thermistor fixed in close contact with the package case of the LSI and having a negative temperature characteristic, one end of which is connected to the LSI drive voltage;
Including a second thermistor fixed in close contact with the package case of the LSI and having a positive temperature characteristic, the first resistor being provided at one end and the second resistor having the other end connected to the ground;
An electronic device circuit, wherein an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor is negatively fed back to the power supply circuit.
前記電源回路は、前記第1の抵抗と前記第2の抵抗によって前記LSI駆動電圧を分圧した中間電圧と基準電圧との誤差を検出する誤差増幅器と、ベース端子に該誤差増幅器の出力が供給され、コレクタ端子が入力電源に接続されて、エミッタ端子から前記LSI駆動電圧を出力するシリーズバストランジスタを備え、
前記LSI駆動電圧が所定の2つの温度におけるLSI内部の信号伝搬遅延時間を補償して同一とするに、前記第1の抵抗の抵抗値に対する前記第2の抵抗の抵抗値の比を設定することを特徴とする請求項1ないし3のいずれかに記載の電子機器回路。
The power supply circuit includes an error amplifier that detects an error between an intermediate voltage obtained by dividing the LSI drive voltage by the first resistor and the second resistor and a reference voltage, and an output of the error amplifier is supplied to a base terminal The collector terminal is connected to the input power supply, and includes a series bus transistor that outputs the LSI drive voltage from the emitter terminal,
The ratio of the resistance value of the second resistor to the resistance value of the first resistor is set so that the LSI driving voltage is the same by compensating for the signal propagation delay time in the LSI at two predetermined temperatures. The electronic device circuit according to claim 1, wherein:
JP2003328929A 2003-09-19 2003-09-19 Electronic appliance circuit Pending JP2005092793A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011135395A (en) * 2009-12-25 2011-07-07 Mitsubishi Electric Corp Analog signal conversion apparatus
CN102591400A (en) * 2011-01-12 2012-07-18 深圳艾科创新微电子有限公司 Low-dropout regulator and method of improving power supply rejection of LDO (low-dropout regulator)
JP2017162905A (en) * 2016-03-08 2017-09-14 Necスペーステクノロジー株式会社 Temperature control device, method and control circuit used therefor
JP2018007476A (en) * 2016-07-06 2018-01-11 三菱電機株式会社 Power semiconductor module and power electronics device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011135395A (en) * 2009-12-25 2011-07-07 Mitsubishi Electric Corp Analog signal conversion apparatus
CN102591400A (en) * 2011-01-12 2012-07-18 深圳艾科创新微电子有限公司 Low-dropout regulator and method of improving power supply rejection of LDO (low-dropout regulator)
JP2017162905A (en) * 2016-03-08 2017-09-14 Necスペーステクノロジー株式会社 Temperature control device, method and control circuit used therefor
JP2018007476A (en) * 2016-07-06 2018-01-11 三菱電機株式会社 Power semiconductor module and power electronics device

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