JP2005086928A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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JP2005086928A
JP2005086928A JP2003317999A JP2003317999A JP2005086928A JP 2005086928 A JP2005086928 A JP 2005086928A JP 2003317999 A JP2003317999 A JP 2003317999A JP 2003317999 A JP2003317999 A JP 2003317999A JP 2005086928 A JP2005086928 A JP 2005086928A
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charge
power supply
circuit
high potential
load circuit
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Seizo Inagaki
誠三 稲垣
Shota Nakajima
章太 中島
Atsuo Inoue
敦雄 井上
Shunichi Iwanari
俊一 岩成
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems that, in a semiconductor integrated circuit, large consumption of electric charge in a load circuit increases the consumption of the charge stored in a power supply voltage smoothing capacitor and drops a voltage, which causes the malfunction of the load circuit, and that larger capacitance is required to prevent the voltage drop, which increases circuit scale. <P>SOLUTION: This circuit is provided with a basic capacitor (a first capacitor) 13 that accumulates electric charge by a first power source V1 and supplies the charge to the load circuit 14, and a charge-supplementing second capacitor 16 that accumulates the charge by a second power source V2 of higher potential than the first power source V1 and supplies the charge to the load circuit 14 via a change-over switch 17. The capacitance can be cut and total area can be made smaller, by supplementing the charge accumulated by the power source of the higher potential. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体集積回路、特に非接触半導体集積回路にかかわり、負荷回路に対する印加電圧を安定化するための技術に関する。   The present invention relates to a technique for stabilizing a voltage applied to a load circuit in connection with a semiconductor integrated circuit, particularly a non-contact semiconductor integrated circuit.

図４に従来の半導体集積回路の構成を示す。   FIG. 4 shows a configuration of a conventional semiconductor integrated circuit.

図４において、４１は高電位側電源端子（ＶＤＤ）、４２は低電位側電源端子（ＧＮＤ）、４３は高電位側電源端子４１と低電位側電源端子４２との間に挿入された容量素子、４４は容量素子４３の両端間に接続された負荷回路である。   In FIG. 4, reference numeral 41 denotes a high potential side power supply terminal (VDD), 42 denotes a low potential side power supply terminal (GND), and 43 denotes a capacitive element inserted between the high potential side power supply terminal 41 and the low potential side power supply terminal 42. , 44 is a load circuit connected between both ends of the capacitive element 43.

高電位側電源端子４１には電位Ｖ１の電源が印加され、静電容量Ｃ１の容量素子４３に電荷が蓄積される。この容量素子４３に蓄積された電荷が負荷回路４４に供給され、負荷回路４４を駆動する。容量素子４３は電源の電圧変動に対する平滑作用を有し、負荷回路４４に対する印加電圧を安定化させている。
特公平６−８１４９１号公報 A power supply having a potential V1 is applied to the high-potential-side power supply terminal 41, and charges are accumulated in the capacitive element 43 having the capacitance C1. The electric charge accumulated in the capacitive element 43 is supplied to the load circuit 44 to drive the load circuit 44. The capacitive element 43 has a smoothing action against voltage fluctuations of the power supply, and stabilizes the voltage applied to the load circuit 44.
Japanese Patent Publication No. 6-81491

しかしながら上記の構成では、負荷回路での電荷消費が大きいと、容量素子に蓄えられた電荷の消費も大きくなり、電圧が降下する。この電圧降下は、負荷回路の誤動作の原因になる。これを避けるためには、より大きい容量が必要になるが、回路規模が増大するという課題が生じる。   However, in the above configuration, if the charge consumption in the load circuit is large, the consumption of the charge stored in the capacitive element also increases and the voltage drops. This voltage drop causes a malfunction of the load circuit. To avoid this, a larger capacity is required, but there is a problem that the circuit scale increases.

本発明は上記従来の問題点を解決するもので、容量の大きさを削減でき、トータルの面積を小さくできる半導体集積回路を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the size of the capacitance and reducing the total area.

上記目的を達成するために、本発明は、通常の回路に簡単な回路を付加し、電荷補充をより効率化するものである。   In order to achieve the above object, the present invention adds a simple circuit to a normal circuit to make charge replenishment more efficient.

本発明による半導体集積回路は、第１の電源による電荷を蓄積し負荷回路に電荷を供給する第１の容量素子と、前記第１の電源より高電位の第２の電源による電荷を蓄積しスイッチを介して前記負荷回路に電荷を供給する電荷補充用の第２の容量素子とを備えた構成とされている。   A semiconductor integrated circuit according to the present invention includes a first capacitor element that accumulates electric charges from a first power source and supplies electric charges to a load circuit, and a switch that accumulates electric charges from a second power source having a higher potential than the first power source. And a charge replenishment second capacitive element for supplying a charge to the load circuit via the.

これは、通常の電源である第１の電源の他に、より高電位の電源である第２の電源と、この第２の電源による電荷を蓄積する電荷補充用の第２の容量素子を設け、第２の容量素子に蓄積した電荷をスイッチを介して負荷回路に供給することにより、負荷回路で消費された電荷を補充するものである。   In addition to the first power source that is a normal power source, a second power source that is a higher-potential power source and a second capacitance element for charge replenishment that accumulates charges from the second power source are provided. The charge accumulated in the second capacitor element is supplied to the load circuit via the switch to supplement the charge consumed in the load circuit.

この構成による作用は次のとおりである。負荷回路が電荷をより大きく消費することに起因する印加電圧の変動を抑制するに、電荷補充用の第２の容量素子の追加に加えて、第１の電源より高電位の第２の電源を追加し、第２の容量素子に印加する電圧をより高電位にすることで対応しているので、電荷補充用の第２の容量素子の容量の大きさのみで対応する場合に比べて、電圧降下の度合いをより小さくすることができ、負荷回路に対する印加電圧をより安定化することができる。加えて、電荷補充用に追加する第２の容量素子の容量はより小さなものですみ、回路規模・面積の増大を抑制することができる。   The effect | action by this structure is as follows. In order to suppress fluctuations in the applied voltage caused by the load circuit consuming a larger amount of charge, in addition to the addition of the second capacitive element for charge supplementation, a second power supply having a higher potential than the first power supply is used. In addition, since the voltage applied to the second capacitor element is set to a higher potential, the voltage is compared with the case where only the magnitude of the capacitance of the second capacitor element for charge supplementation is used. The degree of drop can be further reduced, and the applied voltage to the load circuit can be further stabilized. In addition, the capacity of the second capacitor element added for charge replenishment is smaller, and an increase in circuit scale and area can be suppressed.

上記においては、電源の入力端子として、第１の電源を入力するための端子と、第２の電源を入力するための端子との両方を備えていてよいが、回路構成の簡素化を進めるために次のように構成することが好ましい。   In the above, both the terminal for inputting the first power source and the terminal for inputting the second power source may be provided as the input terminals of the power source, but in order to facilitate the simplification of the circuit configuration. It is preferable to configure as follows.

上記において好ましい態様は、さらに、前記第２の電源から前記第１の電源を生成するレギュレータを備えていることである。第１の電源を得るのに、第２の電源を基にして、レギュレータを利用して第１の電源を生成する。したがって、レギュレータの追加が必要にはなるが、第１の電源を入力するための端子は必要としない。これにより、ピン数を削減することが可能となる。   In the above aspect, a preferable aspect is further provided with a regulator that generates the first power source from the second power source. In order to obtain the first power source, the first power source is generated using the regulator based on the second power source. Therefore, although a regulator needs to be added, a terminal for inputting the first power supply is not necessary. Thereby, the number of pins can be reduced.

また、上記において好ましい態様は、前記第１の電源から前記第２の電源を生成する昇圧回路を備えていることである。第２の電源を得るのに、第１の電源を基にして、昇圧回路を利用して第２の電源を生成する。したがって、昇圧回路の追加が必要にはなるが、第２の電源を入力するための端子は必要としない。これにより、ピン数を削減することが可能となる。   In the above, a preferable aspect is that a booster circuit that generates the second power supply from the first power supply is provided. In order to obtain the second power source, the second power source is generated using the booster circuit based on the first power source. Therefore, although it is necessary to add a booster circuit, a terminal for inputting the second power supply is not required. Thereby, the number of pins can be reduced.

上記において、さらに好ましい態様としては、前記昇圧回路につき、それが生成する前記第２の電源の電圧レベルが調整可能に構成されていることである。この第２の電源の電圧レベルを調整することで補充電荷量を調整することができ、印加電圧安定化をよりきめ細かく制御することができる。   In the above, a more preferable aspect is that the voltage level of the second power supply generated by the booster circuit is configured to be adjustable. By adjusting the voltage level of the second power source, the supplementary charge amount can be adjusted, and the applied voltage stabilization can be controlled more finely.

以上のように本発明によれば、負荷回路への印加電圧の変動を抑制するに、電荷補充用の第２の容量素子の追加に加えて、第１の電源より高電位の第２の電源を追加し、第２の容量素子に印加する電圧をより高電位にすることで対応するので、電圧降下の度合いをより小さくし、負荷回路への印加電圧をより安定化することができるとともに、第２の容量素子の容量はより小さなものですみ、回路規模・面積の増大を抑制することができる。   As described above, according to the present invention, in order to suppress fluctuations in the voltage applied to the load circuit, in addition to the addition of the second capacitance element for charge supplementation, the second power source having a higher potential than the first power source is provided. Is added, and the voltage applied to the second capacitive element is made higher, so that the degree of voltage drop can be made smaller and the applied voltage to the load circuit can be further stabilized. The capacity of the second capacitor element is smaller, and an increase in circuit scale and area can be suppressed.

また、内部でレギュレータまたは昇圧回路を内蔵することで、電源の入力端子の数を減らすことができ、回路構成の簡素化を図ることができる。   Further, by incorporating a regulator or a booster circuit inside, the number of input terminals of the power supply can be reduced, and the circuit configuration can be simplified.

以下、本発明の実施の形態を、図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施の形態１）
図１は、本発明の実施の形態１における半導体集積回路の構成を示す回路図である。 (Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

図１において、１１は標準の高電位側電源端子（ＶＤＤ）、１２は低電位側電源端子（ＧＮＤ）、１３は標準の高電位側電源端子１１と低電位側電源端子１２との間に挿入された基本の容量素子、１４は基本の容量素子１３の両端間に接続された負荷回路、１５は電荷補充用の高電位側電源端子、１６は電荷補充用の高電位側電源端子１５と低電位側電源端子１２との間に挿入された電荷補充用の容量素子、Ｐ１は基本の容量素子１３と負荷回路１４との高電位側の接続点、Ｑ１は電荷補充用の高電位側電源端子１５と電荷補充用の容量素子１６の接続点、１７は接続点Ｐ１と接続点Ｑ１との間に介挿された切り換えスイッチ、１８は切り換えスイッチ１７をオン／オフ制御するための制御信号である。   In FIG. 1, 11 is a standard high potential side power supply terminal (VDD), 12 is a low potential side power supply terminal (GND), and 13 is inserted between the standard high potential side power supply terminal 11 and the low potential side power supply terminal 12. 14 is a load circuit connected between both ends of the basic capacitor 13, 15 is a high potential side power supply terminal for charge replenishment, and 16 is a low potential power supply terminal 15 for charge replenishment. A charge replenishment capacitive element inserted between the potential power supply terminal 12, P1 is a high potential connection point between the basic capacitive element 13 and the load circuit 14, and Q1 is a high potential power supply terminal for charge replenishment. 15 is a connection point between the charge replenishment capacitive element 16, 17 is a changeover switch inserted between the connection point P1 and the connection point Q1, and 18 is a control signal for ON / OFF control of the changeover switch 17. .

電荷補充用の高電位側電源端子１５に印加される電位Ｖ２は、標準の高電位側電源端子１１に印加される電位Ｖ１よりも高く設定されている（Ｖ２＞Ｖ１）。Ｖ１が第１の電源に相当し、Ｖ２が第２の電源に相当する。基本の容量素子１３の静電容量をＣ１、電荷補充用の容量素子１６の静電容量をＣ２、負荷回路１４で消費される電荷量をＱとする。基本の容量素子１３が第１の容量素子に相当し、電荷補充用の容量素子１６が第２の容量素子に相当する。   The potential V2 applied to the high potential side power supply terminal 15 for charge replenishment is set higher than the potential V1 applied to the standard high potential side power supply terminal 11 (V2> V1). V1 corresponds to the first power supply, and V2 corresponds to the second power supply. Assume that the basic capacitance element 13 has a capacitance C1, the charge replenishment capacitance element 16 has a capacitance C2, and the load circuit 14 has a charge amount Q. The basic capacitive element 13 corresponds to a first capacitive element, and the charge replenishing capacitive element 16 corresponds to a second capacitive element.

制御信号１８がインアクティブで切り換えスイッチ１７がオフになっている状態では、負荷回路１４に対しては、電荷補充用の容量素子１６からの電荷は供給されず、標準の高電位Ｖ１で充電される基本の容量素子１３からの電荷のみが供給される。   In a state where the control signal 18 is inactive and the changeover switch 17 is turned off, the load circuit 14 is not supplied with the charge from the charge replenishment capacitive element 16 and is charged with the standard high potential V1. Only the electric charge from the basic capacitive element 13 is supplied.

一方、制御信号１８がアクティブで切り換えスイッチ１７がオンになっている状態では、負荷回路１４に対しては、標準の高電位Ｖ１で充電される基本の容量素子１３からの電荷と、電荷補充用の高電位Ｖ２で充電される電荷補充用の容量素子１６からの電荷とが供給される。   On the other hand, when the control signal 18 is active and the changeover switch 17 is turned on, the load circuit 14 is charged with the charge from the basic capacitive element 13 charged with the standard high potential V1 and the charge replenishment. The charge from the charge replenishing capacitive element 16 charged at the high potential V2 is supplied.

いま、切り換えスイッチ１７がオン状態になっているとする。負荷回路１４で電荷が消費されるために、電圧Ｖ１は電荷が消費される前と比べて小さくなる。その電圧降下をΔＶとすると、
ΔＶ ＝ （Ｑ−Ｃ２（Ｖ２−Ｖ１））／（Ｃ１＋Ｃ２） ………（１）
となる。 Now, assume that the changeover switch 17 is in an ON state. Since the load circuit 14 consumes charges, the voltage V1 becomes smaller than before the charges are consumed. If the voltage drop is ΔV,
ΔV = (Q−C2 (V2−V1)) / (C1 + C2) (1)
It becomes.

静電容量を増やすだけの従来の方法であれば、電圧降下ΔＶは、
ΔＶ ＝ Ｑ／（Ｃ１＋Ｃ２） ………………………………………（２）
となる。 If the conventional method only increases the capacitance, the voltage drop ΔV is
ΔV = Q / (C1 + C2) ……………………………………… (2)
It becomes.

式（１）、（２）より、式（１）の方が、Ｃ２（Ｖ２−Ｖ１）／（Ｃ１＋Ｃ２）の分だけ電圧降下は小さくなる。つまり、電圧降下がより小さいために、負荷回路１４に対する印加電圧がより安定化する。   From Equations (1) and (2), the voltage drop is smaller in Equation (1) by C2 (V2-V1) / (C1 + C2). That is, since the voltage drop is smaller, the applied voltage to the load circuit 14 is further stabilized.

以上のように、標準の高電位Ｖ１よりも高い電位の電荷補充用の高電位Ｖ２を印加する電荷補充用の高電位側電源端子１５と、それに接続される電荷補充用の容量素子１６とを追加することにより、回路が消費する電荷の影響を小さくすることが可能となる。   As described above, the charge replenishment high potential side power supply terminal 15 for applying the charge replenishment high potential V2 higher than the standard high potential V1 and the charge replenishment capacitive element 16 connected thereto are provided. By adding, it becomes possible to reduce the influence of the electric charge consumed by the circuit.

（実施の形態２）
図２は、本発明の実施の形態２における半導体集積回路の構成を示す回路図である。 (Embodiment 2)
FIG. 2 is a circuit diagram showing a configuration of the semiconductor integrated circuit according to the second embodiment of the present invention.

本実施の形態は、負荷回路に対して常時印加する標準の高電位を電荷補充用の高電位から電圧レギュレートによって生成するものである。図２において、２１は電荷補充用を兼ねる高電位側電源端子、２２は低電位側電源端子、２５は負荷回路、２３は電荷補充用を兼ねる高電位側電源端子２１と負荷回路２５の高電位側端子との間に挿入された電圧のレギュレータ、Ｐ２はレギュレータ２３と負荷回路２５との接続点、２４は接続点Ｐ２と低電位側電源端子２２との間に挿入された静電容量がＣ１の基本の容量素子、２６は電荷補充用を兼ねる高電位側電源端子２１と低電位側電源端子２２との間に挿入された静電容量がＣ２の電荷補充用の容量素子、Ｑ２は電荷補充用を兼ねる高電位側電源端子２１と電荷補充用の容量素子２６の接続点、２７は接続点Ｐ２と接続点Ｑ２との間に介挿された切り換えスイッチ、２８は切り換えスイッチ２７をオン／オフ制御するための制御信号である。負荷回路２５は接続点Ｐ２と低電位側電源端子２２との間に接続されている。   In this embodiment, a standard high potential that is always applied to the load circuit is generated from the high potential for charge replenishment by voltage regulation. In FIG. 2, reference numeral 21 denotes a high potential side power supply terminal also serving as charge replenishment, 22 denotes a low potential side power supply terminal, 25 denotes a load circuit, and 23 denotes a high potential of the high potential side power supply terminal 21 also serving as charge supplementation and the load circuit 25. A voltage regulator inserted between the side terminal, P2 is a connection point between the regulator 23 and the load circuit 25, and 24 is a capacitance inserted between the connection point P2 and the low potential side power supply terminal 22 as C1. The basic capacitive element 26 is a charge replenishment capacitive element having a capacitance C2 inserted between the high potential side power supply terminal 21 and the low potential side power supply terminal 22 which also serves as charge replenishment, and Q2 is charge replenishment. A connection point between the high-potential power supply terminal 21 and the charge replenishment capacitive element 26, which is also used for the purpose, 27 is a change-over switch interposed between the connection point P2 and the connection point Q2, and 28 is an on / off switch 27. Control signal for controlling It is. The load circuit 25 is connected between the connection point P <b> 2 and the low potential side power supply terminal 22.

レギュレータ２３は、電荷補充用を兼ねる高電位側電源端子２１に印加される電荷補充用の高電位Ｖ２を入力し、この高電位Ｖ２を電圧調整して標準の高電位Ｖ１を生成し、標準の高電位Ｖ１を負荷回路２５に印加する。   The regulator 23 inputs a high potential V2 for charge replenishment applied to the high potential side power supply terminal 21 which also serves for charge replenishment, and adjusts the high potential V2 to generate a standard high potential V1. A high potential V1 is applied to the load circuit 25.

制御信号２８がインアクティブで切り換えスイッチ２７がオフになっている状態では、負荷回路２５に対しては、電荷補充用の容量素子２６からの電荷は供給されず、標準の高電位Ｖ１で充電される基本の容量素子２４からの電荷のみが供給される。   In a state where the control signal 28 is inactive and the changeover switch 27 is turned off, the load circuit 25 is not supplied with the charge from the charge replenishment capacitive element 26 and is charged with the standard high potential V1. Only the electric charge from the basic capacitive element 24 is supplied.

一方、制御信号２８がアクティブで切り換えスイッチ２７がオンになっている状態では、負荷回路２５に対しては、標準の高電位Ｖ１で充電される基本の容量素子２４からの電荷と、電荷補充用の高電位Ｖ２で充電される電荷補充用の容量素子２６からの電荷とが供給される。   On the other hand, when the control signal 28 is active and the changeover switch 27 is turned on, the load circuit 25 is charged with the charge from the basic capacitive element 24 charged with the standard high potential V1 and the charge replenishment. The charge from the charge replenishment capacitive element 26 charged at the high potential V2 is supplied.

実施の形態１では、電位の異なる電源が２つ必要で、端子については、標準の高電位側電源端子１１と低電位側電源端子１２と電荷補充用の高電位側電源端子１５との３つの端子を必要としている。これに対して本実施の形態では、レギュレータ２３を用いることにより、電荷補充用の高電位Ｖ２から標準の高電位Ｖ１を生成するように構成してあるので、電源としては単一の電源でよく、端子については、電荷補充用を兼ねる高電位側電源端子２１と低電位側電源端子２２との２つの端子でよく、ピン数を削減することが可能である。電圧降下に関しては、実施の形態１と同様に小さくすることが可能で、電圧が安定する。   In the first embodiment, two power sources having different potentials are required, and there are three terminals including a standard high potential side power source terminal 11, a low potential side power source terminal 12, and a high potential side power source terminal 15 for charge replenishment. Need a terminal. On the other hand, in the present embodiment, the regulator 23 is used to generate the standard high potential V1 from the high potential V2 for charge replenishment. Therefore, a single power source may be used as the power source. The terminals may be two terminals, ie, the high-potential side power supply terminal 21 and the low-potential side power supply terminal 22 that also serve as charge replenishment, and the number of pins can be reduced. The voltage drop can be reduced as in the first embodiment, and the voltage is stabilized.

（実施の形態３）
図３は、本発明の実施の形態３における半導体集積回路の構成を示す回路図である。 (Embodiment 3)
FIG. 3 is a circuit diagram showing a configuration of the semiconductor integrated circuit according to the third embodiment of the present invention.

本実施の形態は、負荷回路に対して電荷補充用に印加する高電位を標準の高電位から昇圧によって生成するものである。図３において、３１は標準の高電位側電源端子、３２は低電位側電源端子、３３は標準の高電位側電源端子３１と低電位側電源端子３２との間に接続された静電容量がＣ１の基本の容量素子、３４は基本の容量素子１３の両端間に接続された負荷回路、３５は標準の高電位側電源端子３１に一端が接続された昇圧回路、３６は昇圧回路３５の他端と低電位側電源端子３２との間に接続された静電容量がＣ２の電荷補充用の容量素子、Ｐ３は基本の容量素子３３と負荷回路３４との高電位側の接続点、Ｑ３は昇圧回路３５と電荷補充用の高電位側電源端子３６の接続点、３７は接続点Ｐ３と接続点Ｑ３との間に介挿された切り換えスイッチ、３８は切り換えスイッチ３７をオン／オフ制御するための制御信号である。昇圧回路３５は、昇圧比が可変可能に構成されている。   In the present embodiment, a high potential to be applied for charge supplement to a load circuit is generated from a standard high potential by boosting. In FIG. 3, 31 is a standard high potential side power supply terminal, 32 is a low potential side power supply terminal, 33 is a capacitance connected between the standard high potential side power supply terminal 31 and the low potential side power supply terminal 32. C1 basic capacitive element, 34 a load circuit connected between both ends of the basic capacitive element 13, 35 a booster circuit having one end connected to the standard high potential side power supply terminal 31, and 36 a booster circuit 35 A charge replenishment capacitive element having a capacitance C2 connected between the terminal and the low potential side power supply terminal 32, P3 is a connection point on the high potential side between the basic capacitive element 33 and the load circuit 34, and Q3 is A connection point 37 between the booster circuit 35 and the high potential side power supply terminal 36 for charge replenishment, 37 is a change-over switch inserted between the connection point P3 and the connection point Q3, and 38 is for ON / OFF control of the change-over switch 37. Control signal. The booster circuit 35 is configured such that the boost ratio can be varied.

昇圧回路３５は、標準の高電位側電源端子３１に印加される標準の高電位Ｖ１を入力し、この高電位Ｖ１を昇圧して電荷補充用の高電位Ｖ２を生成する。   The booster circuit 35 receives a standard high potential V1 applied to the standard high potential power supply terminal 31, and boosts the high potential V1 to generate a high potential V2 for charge replenishment.

制御信号３８がインアクティブで切り換えスイッチ３７がオフになっている状態では、負荷回路３４に対しては、電荷補充用の容量素子３６からの電荷は供給されず、標準の高電位Ｖ１で充電される基本の容量素子３３からの電荷のみが供給される。   In a state where the control signal 38 is inactive and the changeover switch 37 is turned off, the load circuit 34 is not supplied with the charge from the charge replenishment capacitive element 36 and is charged with the standard high potential V1. Only the electric charge from the basic capacitive element 33 is supplied.

一方、制御信号３８がアクティブで切り換えスイッチ３７がオンになっている状態では、負荷回路３４に対しては、標準の高電位Ｖ１で充電される基本の容量素子３３からの電荷と、電荷補充用の高電位Ｖ２で充電される電荷補充用の容量素子３６からの電荷とが供給される。   On the other hand, when the control signal 38 is active and the changeover switch 37 is turned on, the load circuit 34 is charged with the charge from the basic capacitive element 33 charged with the standard high potential V1 and the charge replenishment. The charge from the charge replenishing capacitive element 36 charged at the high potential V2 is supplied.

実施の形態１では、電位の異なる電源が少なくとも２つ必要で、端子については、標準の高電位側電源端子１１と低電位側電源端子１２と電荷補充用の高電位側電源端子１５との３つの端子を必要としている。これに対して本実施の形態では、昇圧回路３５を用いることにより、標準の高電位Ｖ１から電荷補充用の高電位Ｖ２を生成するように構成してあるので、電源としては単一の電源でよく、端子については、標準の高電位側電源端子３１と低電位側電源端子３２との２つの端子でよく、ピン数を削減することが可能である。電圧降下に関しては、実施の形態１と同様に小さくすることが可能で、電圧が安定する。   In the first embodiment, at least two power sources having different potentials are required. As for the terminals, three of a standard high potential side power source terminal 11, a low potential side power source terminal 12, and a high potential side power source terminal 15 for charge supplementation are used. Need one terminal. In contrast, in the present embodiment, the booster circuit 35 is used to generate the charge replenishment high potential V2 from the standard high potential V1, so that the power source is a single power source. The terminals may be two terminals, ie, the standard high potential side power supply terminal 31 and the low potential side power supply terminal 32, and the number of pins can be reduced. The voltage drop can be reduced as in the first embodiment, and the voltage is stabilized.

また、昇圧回路３５で生成される電荷補充用の高電位Ｖ２を調整することにより、負荷回路３４へ供給する電荷量を調整することが可能である。   Further, the amount of charge supplied to the load circuit 34 can be adjusted by adjusting the high potential V2 for charge replenishment generated by the booster circuit 35.

本発明の実施の形態１における半導体集積回路の構成を示す回路図1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 本発明の実施の形態２における半導体集積回路の構成を示す回路図The circuit diagram which shows the structure of the semiconductor integrated circuit in Embodiment 2 of this invention 本発明の実施の形態３における半導体集積回路の構成を示す回路図The circuit diagram which shows the structure of the semiconductor integrated circuit in Embodiment 3 of this invention 従来例の半導体集積回路の構成を示す回路図Circuit diagram showing configuration of conventional semiconductor integrated circuit

符号の説明Explanation of symbols

１１，３１ 標準の高電位側電源端子
１２，２２，３２ 低電位側電源端子
１３，２４，３３ 基本の容量素子
１４，２５，３４ 負荷回路
１５ 電荷補充用の高電位側電源端子
１６，２６，３６ 電荷補充用の第２の容量素子
１７，２７，３７ 切り換えスイッチ
１８，２８，３８ 制御信号
２１ 電荷補充用を兼ねる高電位側電源端子
２３ レギュレータ
３５ 昇圧回路
11, 31 Standard high potential side power supply terminals 12, 22, 32 Low potential side power supply terminals 13, 24, 33 Basic capacitance elements 14, 25, 34 Load circuit 15 High potential side power supply terminals 16, 26, 36 Second capacitor element for charge replenishment 17, 27, 37 Changeover switch 18, 28, 38 Control signal 21 High potential side power supply terminal also serving for charge replenishment 23 Regulator 35 Booster circuit

Claims (4)

第１の電源による電荷を蓄積し負荷回路に電荷を供給する第１の容量素子と、前記第１の電源より高電位の第２の電源による電荷を蓄積しスイッチを介して前記負荷回路に電荷を供給する電荷補充用の第２の容量素子とを備えた半導体集積回路。 A first capacitive element for accumulating electric charge from a first power supply and supplying electric charge to a load circuit; an electric charge from a second power supply having a higher potential than the first power supply; and accumulating electric charge in the load circuit via a switch And a second capacitance element for charge replenishment for supplying the semiconductor integrated circuit. さらに、前記第２の電源から前記第１の電源を生成するレギュレータを備えた請求項１に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 1, further comprising a regulator that generates the first power supply from the second power supply. さらに、前記第１の電源から前記第２の電源を生成する昇圧回路を備えた請求項１に記載の半導体集積回路。 The semiconductor integrated circuit according to claim 1, further comprising a booster circuit that generates the second power supply from the first power supply. 前記昇圧回路は、それが生成する前記第２の電源の電圧レベルを調整可能に構成されている請求項３に記載の半導体集積回路。 4. The semiconductor integrated circuit according to claim 3, wherein the booster circuit is configured to be capable of adjusting a voltage level of the second power supply generated by the booster circuit.
JP2003317999A 2003-09-10 2003-09-10 Semiconductor integrated circuit Pending JP2005086928A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8111576B2 (en) 2008-11-25 2012-02-07 Samsung Electronics Co., Ltd. High-voltage sawtooth current driving circuit and memory device including same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8111576B2 (en) 2008-11-25 2012-02-07 Samsung Electronics Co., Ltd. High-voltage sawtooth current driving circuit and memory device including same

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