JP2005086489A - Amplifier circuit, and semiconductor integrated circuit employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit can be reduced in area in the case that the amplifier circuit is integrated into an IC by downsizing resistors and capacitors required for detecting offset. <P>SOLUTION: An offset control circuit 13 comprises: a peak hold circuit 14; transistors M13 and M14 comprising differential pairs; and a constant current circuit I12. The peak hold circuit 14 produces a first signal following up the peak value of an output signal outputted from a negative output terminal 17 and supplies the produced signals to the gate of the MOS transistor M13 and produces a second signal following up the peak value of an output signal outputted from a positive output terminal 16 and supplies the produced signals to the gate of the MOS transistor M14. The peak hold circuit 14 comprises: a buffer circuit 15A to be operated by receiving the output signal of the negative output terminal 17; a buffer circuit 15B to be operated by receiving the output signal of the positive output terminal 16; and a capacitor C11 to be connected to both ends of the output terminals of the buffer circuits 15A and 15B. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an amplifier circuit capable of handling differential signals, and a semiconductor integrated device using the amplifier circuit.

  In recent years, semiconductor integrated circuits (LSIs) have become capable of high-speed signal processing, and as a result, there are many cases in which differential signals are used as signals used for communication between semiconductor integrated circuits or signals transmitted over a network. It has become. In addition, the differential signal has a small amplitude in consideration of the influence of EMC (electromagnetic interference) and the like, and is affected by deterioration in the transmission path. Therefore, it is necessary to amplify on the receiving side.

For this reason, it has become common to use differential amplifier circuits in signal transmission systems. However, when differential amplifier circuits cause an offset, the gain is greatly reduced and good amplification characteristics are obtained. Absent.
A differential amplifier circuit generally has an offset component due to variations in device parameters and the like. An offset component is also generated depending on a signal to be communicated. This is because the content of communication data may be “0” or “1” continuously, and an offset is likely to occur after AC coupling (AC coupling) by communication between LSIs. Therefore, in communication, signal conversion is performed in order to improve signal quality so that “0” and “1” do not continue, but an offset still occurs.

Therefore, in the conventional differential amplifier circuit including the input buffer circuit 1, the preamplifier circuit 2, and the output buffer circuit 3 as shown in FIG. 7, an offset control circuit 4 is provided as shown.
This offset control circuit 4 usually takes out the difference of the offset component included in the output signal of the preamplifier circuit 2 using a low-pass filter composed of a resistor and a capacitor, and feeds it back to the input buffer circuit 1 to Inhibits ingredients.

Here, the cut-off frequency fc of the low-pass filter including the resistor R and the capacitor C is expressed by the following equation (1).
fc = 1 / (2π · R · C) (1)
By the way, since the offset component is close to the direct current component, it is necessary to lower the cut-off frequency of the low pass filter so as not to affect the communication signal which is the high frequency alternating current component (high frequency component). . For this purpose, according to the equation (1), it is necessary to increase the time constant determined by each value of the resistor and the capacitor.

However, when the differential amplifier circuit shown in FIG. 6 is integrated, in order to increase the values of the capacitors and resistors that constitute the low-pass filter, there is a problem that the area of the integrated circuit increases. is there.
As a differential amplifier circuit that solves such a problem, for example, the one shown in FIG. 8 (see Non-Patent Document 1) and the one shown in FIG. 9 (see Patent Document 1) are known.

The differential amplifier circuit shown in FIG. 8 includes a differential amplifier circuit 5 and a differential amplifier circuit 6 as shown in the figure, and includes an offset control circuit 7.
The differential amplifier circuit 5 includes a differential pair of MOS transistors M1 and M2, output resistors R1 and R2, and a current source I1. The offset control circuit 7 includes a low-pass filter 8 including resistors R3 and R4 and a capacitor C1, MOS transistors M3 and M4, and a constant current source I2.

In the offset control circuit 7 configured as described above, an offset component included in the output signal of the differential amplifier circuit 6 is extracted by the low-pass filter 8 and is extracted from the differential amplifier circuit 6 via the MOS transistors M3 and M4. Negative feedback is provided to the input side to suppress the offset.
On the other hand, the differential amplifier circuit shown in FIG. 9 is obtained by replacing the offset control circuit 7 shown in FIG. 8 with an offset control circuit 9 as shown.

The offset control circuit 9 includes a low-pass filter 10A, a low-pass filter 10B, MOS transistors M3 and M4, and a constant current source I2. The low-pass filter 10A includes a resistor R5, a capacitor C2, and P-type MOS transistors M5 and M6. The low-pass filter 10B includes a resistor R6, a capacitor C3, and P-type MOS transistors M7 and M8.
JP 2001-274640 A (see FIG. 1) T. Hu and PRGray, `` A Monolithic-480Mb / sec Parallel AGC / Decision / Clock-Recovery Circuit in 1.2u CMOS '' Digest of Technical Papers, 1993 International Solid-State Circuits Conference, February, 1993.

However, in the offset control circuit 7 of FIG. 8, the low-pass filter 8 is composed of resistors R3 and R4 and a capacitor C1, and the capacitor C1 is composed of one, so that an efficient filter is configured.
However, since the frequency of the signal cut by the low-pass filter 8 is still low, the resistors R3 and R4 become high resistance, and the capacitor C1 has a large capacity. For this reason, when the resistors R3 and R4 and the capacitor C1 are formed as an integrated circuit, they occupy a considerable area of the entire circuit and become large. In order to avoid the increase in size, a capacitor is externally attached.

On the other hand, in the offset control circuit 9 of FIG. 9, in the low-pass filters 10A and 10B, a large capacity can be realized by using the mirror effect, and in order to obtain the same time constant, the capacitors of the low-pass filters 10A and 10B The capacitance value and the resistance value of the resistor can be reduced.
However, in order to realize this, a MOS transistor is used, but the mutual conductance (gm) of the MOS transistor is smaller than that of a bipolar transistor or the like. For this reason, in order to increase the gain of a MOS transistor in order to increase the mirror capacitance, the size of the MOS transistor must be increased. As a result, there is a problem in that the circuit configuration increases and the area increases. .

By the way, in order to perform offset detection control, the appearance of a new circuit is desired without using a low-pass filter as described above, but in that case, it is desired to realize it with a simple configuration.
Accordingly, an object of the present invention is to provide an amplifier circuit capable of realizing a circuit for detecting and controlling an offset with a simple configuration, and a semiconductor integrated device using the same, in view of the above points.

  Furthermore, another object of the present invention is to use an amplifier circuit capable of reducing the capacitance of a circuit necessary for detecting an offset and realizing a reduction in the area as a whole when integrated circuits are used. The object is to provide a semiconductor integrated device.

In order to solve the above-mentioned problems and achieve the object of the present invention, each invention is configured as follows.
That is, according to a first aspect of the present invention, there is provided an amplifier circuit having a positive and negative input terminal and a positive and negative output terminal and capable of differentially amplifying an input signal. A peak hold circuit that generates a signal and generates a second signal that follows the peak value of the output signal of the positive output terminal; and a differential amplifier circuit that includes a first transistor and a second transistor formed of a differential pair; A first signal generated by the peak hold circuit is supplied to an input control terminal of the first transistor, and an output of the first transistor is supplied to a positive input terminal of the amplifier circuit. The second signal generated by the peak hold circuit is supplied to the input control terminal of the second transistor, and the output of the second transistor is supplied to the negative input of the amplifier circuit. A first buffer circuit that operates in response to an output signal from a negative output terminal of the amplifier circuit; and an output signal from a positive output terminal of the amplifier circuit. And a capacitor connected to both ends of the output terminal of the first buffer circuit and an output terminal of the second buffer circuit, and an output of the output terminal of the first buffer circuit Is taken out as the first signal, and the output of the output terminal of the second buffer circuit is taken out as the second signal.

  According to a second invention, in the amplifier circuit of the first invention, the first buffer circuit has a first MOS transistor and a first constant current circuit connected in series between a power source and a ground, and the input of the first MOS transistor The output signal of the negative output terminal of the amplifier circuit is input to the terminal, and the output is taken out from a common connection part of the first MOS transistor and the first constant current circuit. The second buffer circuit includes a second MOS transistor And a second constant current circuit connected in series between the power source and the ground, the output signal of the positive output terminal of the amplifier circuit is input to the input terminal of the first MOS transistor, and the second MOS transistor and the second MOS transistor The output is taken out from the common connection part of the two constant current circuits.

According to a third invention, in the amplifier circuit of the second invention, the first constant current circuit and the second constant current circuit include a circuit in which MOS transistors are cascade-connected, or a circuit in which MOS transistors are cascade-connected and an amplifier. Each circuit is configured by a combined circuit.
According to a fourth invention, in the amplifier circuit of the second invention, the first constant current circuit and the second constant current circuit are each replaced with a resistor.

  According to a fifth aspect of the present invention, there is provided an amplifier circuit having a positive and negative input terminal and a positive and negative output terminal and capable of differentially amplifying an input signal, the first signal following the bottom value of the output signal of the negative output terminal. And a bottom hold circuit that generates a second signal that follows the bottom value of the output signal of the positive output terminal, and a differential amplifier circuit that includes a first transistor and a second transistor that are a differential pair. Supplying the first signal generated by the bottom hold circuit to the input control terminal of the first transistor, and supplying the output of the first transistor to the positive input terminal of the amplifier circuit; The second signal generated by the bottom hold circuit is supplied to the input control terminal of the two transistors, and the output of the second transistor is supplied to the negative input terminal of the amplifier circuit The bottom hold circuit is configured to receive a first buffer circuit that operates in response to an output signal from the negative output terminal of the amplifier circuit, and an output signal from the positive output terminal of the amplifier circuit. A second buffer circuit that operates, and an output terminal of the first buffer circuit and a capacitor connected to both ends of the output terminal of the second buffer circuit, the output of the output terminal of the first buffer circuit being the first output The signal is extracted as one signal, and the output of the output terminal of the second buffer circuit is extracted as the second signal.

  According to a sixth invention, in the amplifier circuit of the fifth invention, the first buffer circuit includes a first MOS transistor and a first constant current circuit connected in series between a power supply and a ground, and an input of the first MOS transistor The output signal of the negative output terminal of the amplifier circuit is input to the terminal, and the output is taken out from a common connection part of the first MOS transistor and the first constant current circuit. The second buffer circuit includes a second MOS transistor And a second constant current circuit connected in series between the power source and the ground, the output signal of the positive output terminal of the amplifier circuit is input to the input terminal of the first MOS transistor, and the second MOS transistor and the second MOS transistor The output is taken out from the common connection part of the two constant current circuits.

According to a seventh invention, in the amplifier circuit of the sixth invention, the first constant current circuit and the second constant current circuit include a circuit in which MOS transistors are cascade-connected, or a circuit in which MOS transistors are cascade-connected and an amplifier. Each circuit is configured by a combined circuit.
According to an eighth aspect, in the amplifier circuit according to the sixth aspect, the first constant current circuit and the second constant current circuit are each replaced with a resistor.

A ninth invention includes a first amplifier circuit according to the first to eighth inventions, and a second amplifier circuit provided on a front stage side of the first amplifier circuit and capable of differentially amplifying an input signal. Consists of things.
According to the present invention having such a configuration, a peak hold circuit and a bottom hold circuit used for offset detection control can be realized with a simple configuration.
In addition, according to the present invention, it is possible to reduce the capacitance of the capacitor necessary for detecting the offset, and it is easy to make an integrated circuit. In addition, the area can be reduced as a whole when the integrated circuit is made. it can.

Embodiments of the present invention will be described below.
The configuration of the differential amplifier circuit to which the first embodiment of the present invention is applied will be described with reference to FIG.
As shown in FIG. 1, the differential amplifier circuit according to the first embodiment cascades a differential amplifier circuit 11 and a differential amplifier circuit 12, and an offset control circuit 13 A signal that follows the peak value of the output signal is generated, and this generated signal is negatively fed back to the input side of the differential amplifier circuit 12, thereby suppressing the offset generated in the differential amplifier circuits 11, 12, etc. Is.

The differential amplifier circuit 11 includes N-type MOS transistors M11 and M12 that constitute a differential pair, output resistors R11 and R12, and a constant current source I11, and is input to the gates of the MOS transistors M11 and M12. Differential amplification of positive and negative (positive and negative phase) input signals is performed.
More specifically, positive and negative input signals are input to the gates of the MOS transistors M11 and M12, respectively. The sources of the MOS transistors M11 and M12 are connected in common, and the common connection is connected to the ground via the constant current circuit I11. Further, the drains of the MOS transistors M11 and M12 are connected to the power supply via the resistors R11 and R12, respectively. The drain of the MOS transistor M11 is connected to the positive input terminal of the differential amplifier circuit 12, and the drain of the MOS transistor M12 is connected to the negative input terminal of the differential amplifier circuit 12.

The differential amplifier circuit 12 includes positive and negative input terminals that receive the output signals from the differential amplifier circuit 11 as positive and negative input signals as described above, and positive and negative output terminals 16 for taking out positive and negative output signals, 17 so that differential amplification of the positive and negative input signals can be performed.
As shown in FIG. 1, the offset control circuit 13 includes a peak hold circuit 14, N-type MOS transistors M13 and M14 forming a differential pair, and a constant current circuit I12.

  The peak hold circuit 14 generates a signal that follows the peak value of the negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12, supplies the generated signal to the gate of the MOS transistor M13, and A signal that follows the peak value of the positive output signal output from the positive output terminal 16 of the differential amplifier circuit 12 is generated, and the generated signal is supplied to the gate of the MOS transistor M14.

  Therefore, the peak hold circuit 14 receives the negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12 and operates, and the positive output of the differential amplifier circuit 12. The second buffer circuit 15B operates by receiving a positive output signal output from the terminal 16, and an output terminal of the first buffer circuit 15A and a capacitor C11 connected to both ends of the output terminal of the second buffer circuit 15B. . The output of the output terminal of the first buffer circuit 15A is supplied to the gate of the MOS transistor M13, and the output of the output terminal of the second buffer circuit 15B is supplied to the gate of the MOS transistor M14.

  More specifically, as shown in FIG. 1, the first buffer circuit 15A includes an N-type MOS transistor M15 and a constant current circuit 21, which are connected in series between the power supply and the ground. Further, a negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12 is supplied to the gate of the MOS transistor M15. Furthermore, the common connection part of the MOS transistor M15 and the constant current circuit 21 is connected to one end of the capacitor C11 and the gate of the MOS transistor M13.

  As shown in FIG. 1, the second buffer circuit 15B includes an N-type MOS transistor M16 and a constant current circuit 22, which are connected in series between the power supply and the ground. Further, a positive output signal output from the positive output terminal 16 of the differential amplifier circuit 12 is supplied to the gate of the MOS transistor M16. Further, the common connection part of the MOS transistor M16 and the constant current circuit 22 is connected to the other end of the capacitor C11 and the gate of the MOS transistor M14.

  As described above, the two outputs of the peak hold circuit 14 are supplied to the gates of the MOS transistors Q13 and Q14, respectively. The sources of the MOS transistors M13 and M14 are connected in common, and the common connection is connected to the ground via the constant current circuit I12. Further, the drain of the MOS transistor M13 is connected to the positive input terminal of the differential amplifier circuit 12, and the drain of the MOS transistor M14 is connected to the negative input terminal of the differential amplifier circuit 12.

Next, a specific configuration of the constant current circuits 21 and 22 shown in FIG. 1 will be described with reference to FIGS.
Since the constant current circuits 21 and 22 have the same configuration, a specific configuration of the constant current circuit 21 will be described here.
As shown in the figure, the constant current circuit 21 shown in FIG. 2 is configured by cascading MOS transistors M21 and M22, and uses a high resistance component in a region where constant current operation is performed. A high resistance is realized in terms of area. Here, a predetermined bias voltage is supplied to each gate of the MOS transistors M21 and M22.

  In the constant current circuit 21 shown in FIG. 3, the MOS transistor M21 and the MOS transistor M22 are cascade-connected as illustrated. The amplifier 23 is configured to compare the potential of the common connection between the MOS transistor M21 and the MOS transistor M22 with the reference voltage Vref and supply an output signal corresponding to the difference to the gate of the MOS transistor M21.

If the constant current circuit 21 includes the circuit shown in FIG. 3, a circuit having a higher resistance than that of the constant current circuit 21 shown in FIG. 5 can be realized, so that the capacitance value of the capacitor C11 can be made relatively smaller.
Next, the operation of the first embodiment configured as described above will be described with reference to FIG. 1, FIG. 4, and FIG.

Now, the output signal (output voltage) from the negative output terminal 17 of the differential amplifier circuit 12 of FIG. 1 is a high-frequency signal S1 (for example, the frequency is about 1000 MHz) as shown in FIG. Assume that the output signal from the positive output terminal 16 of the differential amplifier circuit 12 is a high-frequency signal S2 as shown in FIG.
The high frequency signal S1 is supplied to the gate of the MOS transistor M15 shown in FIG. At this time, when the high-frequency signal S1 increases in the positive direction and the potential difference between the gate and the source of the MOS transistor M15 is equal to or higher than the threshold voltage (threshold voltage) of the MOS transistor M15, the MOS transistor M15, the capacitor C11, A current flows through the constant current circuit 22.

As a result, the capacitor C11 is charged, and the source potential of the MOS transistor M15 rises. For this reason, when the potential between the gate and the source of the MOS transistor M15 becomes small and the potential becomes equal to or lower than the threshold voltage, no current flows through the MOS transistor M15, and the charging operation of the capacitor C11 is stopped.
When the MOS transistor M15 stops operating, the charge of the capacitor C11 is gradually discharged via the constant current circuit 21, and the source potential of the MOS transistor M15 is the voltage between the gate and the source of the MOS transistor M15. Decrease until threshold voltage is reached.

As described above, the peak hold circuit 14 follows the upper side (peak value) of the high-frequency signal S1 by repeating the charging by turning on the MOS transistor M15 and the discharging determined by the time constant of the capacitor C11 and the constant current circuit 21. A peak hold operation for generating the output voltage V1 is performed (see the waveform in FIG. 4A).
For this reason, since the output voltage V1 of the peak hold circuit 14 is similar to the offset component included in the output signal of the negative output terminal 17 of the differential amplifier circuit 12, it can be used to control (adjust) the offset component. It is done.

That is, when the output signal from the negative output terminal 17 of the direct differential amplifier circuit 12 is composed of an original signal component and an offset component (DC component) as shown in FIG. This is because it is similar to the peak hold waveform of the output voltage V1 of the peak hold circuit 14 as shown in FIG.
On the other hand, the high-frequency signal S2 shown in FIG. 4B is supplied to the gate of the MOS transistor M16 shown in FIG. At this time, when the high-frequency signal S2 increases in the positive direction and the potential difference between the gate and the source of the MOS transistor M16 is equal to or higher than the threshold voltage of the MOS transistor M16, the MOS transistor M16, the capacitor C11, and the constant current circuit A current flows through 21.

As a result, the capacitor C11 is charged, and the source potential of the MOS transistor M16 increases. For this reason, when the potential between the gate and the source of the MOS transistor M16 becomes small and the potential becomes equal to or lower than the threshold voltage, no current flows through the MOS transistor M16, and the charging operation of the capacitor C11 is stopped.
When the MOS transistor M16 stops operating, the charge of the capacitor C11 is gradually discharged through the constant current circuit 22, and the source potential of the MOS transistor M16 is the voltage between the gate and the source of the MOS transistor M16. Decrease until threshold voltage is reached.

As described above, the peak hold circuit 14 repeats the charging by turning on the MOS transistor M16 and the discharging determined by the time constants of the capacitor C11 and the constant current circuit 22, so that the output voltage V2 that follows the peak value of the high-frequency signal S2 is obtained. A peak hold operation is performed to generate (see the waveform in FIG. 4B).
For this reason, since the output voltage V2 of the peak hold circuit 14 is similar to the offset component included in the output signal of the positive output terminal 16 of the differential amplifier circuit 12, it can be considered that it can be used to control the offset component.

  Therefore, since the output voltage V1 of the peak hold circuit 14 is applied to the gate of the MOS transistor M13, the MOS transistor M13 changes the DC potential of the positive input terminal of the differential amplifier circuit 12. On the other hand, since the output voltage V2 of the peak hold circuit 14 is applied to the gate of the MOS transistor M14, the MOS transistor M14 changes the DC potential of the negative input terminal of the differential amplifier circuit 12. The direction of these changes is the direction in which the offset is reduced.

As a result, each offset component included in the positive and negative output signals output from the positive and negative output terminals 16 and 17 of the differential amplifier circuit 12 is reduced.
As described above, in the first embodiment, the peak hold circuit 14 is composed of the buffer circuits 15A and 15B and the capacitor C11, and the constant current circuits 21 and 22 of the buffer circuits 15A and 15B are MOS transistors with high resistance. To use.

For this reason, in the first embodiment, the capacitance value of the capacitor C11 can be reduced, and the integrated circuit of the capacitor is facilitated. In addition, when the integrated circuit is formed, the area thereof can be reduced as a whole.
Next, a second embodiment of the present invention will be described with reference to FIG.
In the differential amplifier circuit according to the fourth embodiment, as shown in FIG. 6, the differential amplifier circuit 11 and the differential amplifier circuit 12 are connected in cascade, and the offset control circuit 33 A signal that follows the bottom value of the output signal is generated, and this generated signal is negatively fed back to the input side of the differential amplifier circuit 12, thereby suppressing the offset generated in the differential amplifier circuits 11, 12, etc. Is.

The differential amplifier circuits 11 and 12 are configured in the same manner as the differential amplifier circuits 11 and 12 shown in FIG.
As shown in FIG. 6, the offset control circuit 33 includes a bottom hold circuit 34, N-type MOS transistors M13 and M14 constituting a differential pair, and a constant current circuit I12.

  The bottom hold circuit 34 generates a signal that follows the bottom value of the negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12, supplies the generated signal to the gate of the MOS transistor M13, and A signal that follows the bottom value of the positive output signal output from the positive output terminal 16 of the differential amplifier circuit 12 is generated, and the generated signal is supplied to the gate of the MOS transistor M14.

  For this purpose, the bottom hold circuit 34 receives the negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12 and operates, and the positive output of the differential amplifier circuit 12. The second buffer circuit 35B operates by receiving a positive output signal output from the terminal 16, and the capacitor C11 connected to both ends of the output terminal of the first buffer circuit 35A and the output terminal of the second buffer circuit 35B. . The output of the output terminal of the first buffer circuit 35A is supplied to the gate of the MOS transistor M13, and the output of the output terminal of the second buffer circuit 35B is supplied to the gate of the MOS transistor M14.

  More specifically, as shown in FIG. 6, the first buffer circuit 35A includes a constant current circuit 41 and a P-type MOS transistor M25, which are connected in series between the power supply and the ground. Further, the negative output signal output from the negative output terminal 17 of the differential amplifier circuit 12 is supplied to the gate of the MOS transistor M25. Further, the common connection portion of the MOS transistor M25 and the constant current circuit 41 is connected to one end side of the capacitor C11 and the gate of the MOS transistor M13.

  As shown in FIG. 6, the second buffer circuit 35B includes a constant current circuit 42 and a P-type MOS transistor M26, which are connected in series between the power supply and the ground. A positive output signal output from the positive output terminal 16 of the differential amplifier circuit 12 is supplied to the gate of the MOS transistor M26. Furthermore, the common connection part of the MOS transistor M26 and the constant current circuit 42 is connected to the other end side of the capacitor 11 and the gate of the MOS transistor M14.

  As described above, the two outputs of the bottom hold circuit 34 are supplied to the gates of the MOS transistors Q13 and Q14. The sources of the MOS transistors M13 and M14 are connected in common, and the common connection is connected to the ground via the constant current circuit I12. Further, the drain of the MOS transistor M13 is connected to the positive input terminal of the differential amplifier circuit 12, and the drain of the MOS transistor M14 is connected to the negative input terminal of the differential amplifier circuit 12.

The constant current circuits 41 and 42 are configured similarly to the constant current circuit 21 shown in FIG. 2 or the constant current circuit 21 shown in FIG.
Next, the operation of the second embodiment configured as described above will be described with reference to FIG.
The bottom hold circuit 34 generates voltages that follow the bottom values of the positive and negative output signals output from the positive and negative output terminals 16 and 17 of the differential amplifier circuit 12 based on the same principle as the above-described peak hold circuit 14. . Since each of these generated voltages is similar to each offset component of the positive and negative output signals of the positive and negative output terminals 16 and 17 of the differential amplifier circuit 12, it can be considered that it can be used to control each offset component.

  Since the output voltage V3 of the bottom hold circuit 34 is applied to the gate of the MOS transistor M13, the MOS transistor M13 changes the DC potential of the positive input terminal of the differential amplifier circuit 12. On the other hand, since the output voltage V4 of the bottom hold circuit 34 is applied to the gate of the MOS transistor M14, the MOS transistor M14 changes the DC potential of the negative input terminal of the differential amplifier circuit 12. The direction of these changes is the direction in which the offset is reduced.

As a result, each offset component included in the positive and negative output signals output from the positive and negative output terminals 16 and 17 of the differential amplifier circuit 12 is reduced.
As described above, in the second embodiment, the bottom hold circuit 34 is composed of the buffer circuits 35A and 35B and the capacitor C11, and the constant current circuits 41 and 42 of the buffer circuits 35A and 35B are MOS transistors capable of obtaining a high resistance. To use.

For this reason, in the second embodiment, the capacitance value of the capacitor C11 can be reduced, and the integrated circuit of the capacitor is facilitated. In addition, when the integrated circuit is formed, the area thereof can be reduced as a whole.
In the first embodiment, the constant current circuits 21 and 22 are used as the constituent elements of the buffer circuits 15A and 15B of the peak hold circuit 14, but the constant current circuits 21 and 22 are replaced with resistors. Anyway.

  In the second embodiment, the constant current circuits 41 and 42 are used as the constituent elements of the buffer circuits 35A and 35B of the bottom hold circuit 34. However, the constant current circuits 41 and 42 are replaced with resistors. Anyway.

It is a circuit diagram showing an example of composition of a 1st embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a specific configuration of the constant current circuit of FIG. 1. FIG. 3 is a circuit diagram showing another specific configuration of the constant current circuit of FIG. 1. It is a figure which shows the waveform example of the high frequency signal input into the peak hold circuit of FIG. 1, and its output voltage. It is explanatory drawing explaining the relationship between an offset component and a peak hold waveform. It is a circuit diagram which shows the structural example of 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of a conventional circuit. It is a circuit diagram which shows the other structure of the conventional circuit. It is a circuit diagram which shows other structure of the conventional circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11, 12 ... Differential amplifier circuit 13, 33 ... Offset control circuit, 14 ... Peak hold circuit, 15A, 15B ... Buffer circuit, 16 ... Positive output terminal, 17 ... Negative output terminal 21, 22, 41, 42... Constant current circuit, 34... Bottom hode circuit, 35A, 35B... Buffer circuit, M15, M16, M25, M26. ... capacitors.

Claims (9)

In an amplifier circuit having positive and negative input terminals and positive and negative output terminals and capable of differential amplification of input signals,
A peak hold circuit that generates a first signal that follows the peak value of the output signal at the negative output terminal and generates a second signal that follows the peak value of the output signal at the positive output terminal;
A differential amplifier circuit including a first transistor and a second transistor comprising a differential pair,
A first signal generated by the peak hold circuit is supplied to an input control terminal of the first transistor, and an output of the first transistor is supplied to a positive input terminal of the amplifier circuit; A second signal generated by the peak hold circuit is supplied to an input control terminal of the transistor, and an output of the second transistor is supplied to a negative input terminal of the amplifier circuit;
And the peak hold circuit is
A first buffer circuit that operates in response to an output signal of a negative output terminal of the amplifier circuit;
A second buffer circuit that operates in response to an output signal of a positive output terminal of the amplifier circuit;
A capacitor connected to both ends of the output terminal of the first buffer circuit and the output terminal of the second buffer circuit;
An amplifier circuit configured to extract the output of the output terminal of the first buffer circuit as the first signal and extract the output of the output terminal of the second buffer circuit as the second signal. The first buffer circuit includes a first MOS transistor and a first constant current circuit connected in series between a power supply and a ground, and an output signal of a negative output terminal of the amplifier circuit is input to an input terminal of the first MOS transistor. And taking out the output from the common connection of the first MOS transistor and the first constant current circuit,
The second buffer circuit connects a second MOS transistor and a second constant current circuit in series between a power supply and a ground, and inputs an output signal of a positive output terminal of the amplifier circuit to an input terminal of the first MOS transistor. 2. The amplifier circuit according to claim 1, wherein an output is taken out from a common connection portion of the second MOS transistor and the second constant current circuit.   The first constant current circuit and the second constant current circuit are each configured by a circuit in which MOS transistors are cascade-connected or a circuit in which MOS transistors are cascade-connected and an amplifier. 2. The amplifier circuit according to 2.   The amplifier circuit according to claim 2, wherein the first constant current circuit and the second constant current circuit are replaced with resistors, respectively. In an amplifier circuit having positive and negative input terminals and positive and negative output terminals and capable of differential amplification of input signals,
A bottom hold circuit that generates a first signal that follows the bottom value of the output signal of the negative output terminal and generates a second signal that follows the bottom value of the output signal of the positive output terminal;
A differential amplifier circuit including a first transistor and a second transistor comprising a differential pair,
A first signal generated by the bottom hold circuit is supplied to an input control terminal of the first transistor, and an output of the first transistor is supplied to a positive input terminal of the amplifier circuit; A second signal generated by the bottom hold circuit is supplied to an input control terminal of the transistor, and an output of the second transistor is supplied to a negative input terminal of the amplifier circuit;
And the bottom hold circuit is
A first buffer circuit that operates in response to an output signal of a negative output terminal of the amplifier circuit;
A second buffer circuit that operates in response to an output signal of a positive output terminal of the amplifier circuit;
A capacitor connected to both ends of the output terminal of the first buffer circuit and the output terminal of the second buffer circuit;
An amplifier circuit configured to extract the output of the output terminal of the first buffer circuit as the first signal and extract the output of the output terminal of the second buffer circuit as the second signal. The first buffer circuit includes a first MOS transistor and a first constant current circuit connected in series between a power supply and a ground, and an output signal of a negative output terminal of the amplifier circuit is input to an input terminal of the first MOS transistor. And taking out the output from the common connection of the first MOS transistor and the first constant current circuit,
The second buffer circuit connects a second MOS transistor and a second constant current circuit in series between a power supply and a ground, and inputs an output signal of a positive output terminal of the amplifier circuit to an input terminal of the first MOS transistor. 6. The amplifier circuit according to claim 5, wherein an output is taken out from a common connection portion of the second MOS transistor and the second constant current circuit.   The first constant current circuit and the second constant current circuit are each configured by a circuit in which MOS transistors are cascade-connected or a circuit in which MOS transistors are cascade-connected and an amplifier. 6. The amplifier circuit according to 6.   The amplifier circuit according to claim 6, wherein the first constant current circuit and the second constant current circuit are replaced with resistors, respectively. An amplifier circuit comprising the amplifier circuit according to any one of claims 1 to 8;
A semiconductor integrated device comprising: a second amplifier circuit provided on a front side of the first amplifier circuit and capable of differential amplification of an input signal.

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