JP2005086366A - Broadband high frequency power amplifier circuit and method of broadening band of high frequency power amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency circuit which adds a broadband matching circuit to the device equivalent output terminal Te of a device FET to attain the power matching and the efficiency over a broader band. <P>SOLUTION: A resonance matching circuit 10a is connected to the output terminal Te of an FET, and a resonance circuit 10b is connected between the matching circuit 10a and the Te. It causes resonance with a drain-source capacitance component Cds at an ω to cancel a Cds reactance component Xds. Without changing the value of the reactance components of an L1 parallel connected capacitance Cs and a series impedance functional inductance L1 in the circuit 10b at the ω, the resonance frequency with L1 and Cs is changed to adjust the third harmonic while the Te impedance Zk seen from a load resistance at the ω is set constant, thus controlling the matching at the ω and at the third harmonic independently. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wide band of power and efficiency of a high-frequency power amplifier circuit in which a constant K-type low-pass filter of a matching circuit added to a device equivalent output terminal of a high-power MOSFET device is improved.

  A matching circuit added to a device equivalent output terminal of a high output field effect transistor (LDMOSFET = Laterally Diffused Metal-oxide-semiconductor) (hereinafter referred to as a device FET) has conventionally been a constant K-type low pass filter (hereinafter referred to as a simple design). L-type LPF) is widely used. However, with the recent need for wider power and efficiency, the L-type LPF approach has its limits. This device FET is a MOSFET having a structure different from that of VDMOS and excellent in high-frequency characteristics, and has been developed using the MOSFET in this application described later.

  The L-type LPF that has been widely used in the past is, for example, the series impedance Z1 and the parallel impedance Z2 as described in QC Publishing Co., Ltd., page 202 of the first edition issued on October 20, 1992. And a numerical value K irrelevant to the frequency, the filter satisfies the relational expression Z1 · Z2 = K. In the matching circuit of the present application, the coil L is connected in series with the signal path, the capacitor C is connected in parallel, the low frequency signal passes through the coil L, and the high frequency signal is blocked by the coil L. In addition, an L-type LPF that is grounded by the capacitor C, bypassed, and attenuated is adopted as a part of the configuration.

  The L-type LPF is considered to have a limit in the approach using the L-type LPF because the L-type LPF cannot achieve both improvement in efficiency by harmonic processing and power matching for a desired angular frequency band. In the present application, the desired angular frequency band means a target frequency band to be amplified by the amplifier circuit, and other frequency components are treated as unnecessary frequencies (spurious emission including harmonic components). Is called.

  On the other hand, in recent years, a class F amplification operation has been developed which ideally processes both even-numbered, odd-numbered and even-numbered odd harmonic groups output from the device. A third harmonic parallel resonance circuit 10b according to the present invention, which will be described later, also performs a class F amplification operation for ideally processing both even-numbered, odd-numbered, and even-numbered odd-numbered harmonic groups output from the device FET. The principle is adopted.

  In the matching by the L-type LPF, the efficiency improvement by the harmonic processing and the power matching with respect to the desired angular frequency band are in a trade-off relationship. Mismatch loss must be tolerated. Therefore, it is unavoidable that flattened matching is a compromise so that one of power matching and high efficiency in the desired angular frequency band does not have low characteristics.

[Description Overview]
(1) First, with reference to FIG. 2 to FIG. 6, the prior art and characteristics obtained by analyzing the problems of the prior art will be described.
(2) Next, the functional gist of the present invention will be described with reference to FIG.
(3) Thereafter, the improved characteristics of the present invention will be described with reference to FIGS. 7 to 12 in correspondence with FIGS. 2 to 6 of the prior art.
[Definition of terms]
The terms used in the following description are defined. The symbols [Cds, Cp, L1, La, Lb, Pout, Rds, Rk, Td, Te, Tk, Zd, Zds, Zk] described below are shown in FIG. 2 and FIG. And also in FIG.

   In addition, the signs [10, 10a, 10b, Bn, Cds, Cp1, Cp2, Cs, L1, Lp, Pout, Rds, Rk, Tc, Td, Te, Tn, Tr, Zd, Zds, Zk, Zm, Zn] is described in FIGS. 7 and 8 (partly in FIG. 1 or FIGS. 2 and 3).

  Other symbols not described above are described in other figures.

  A matching circuit (hereinafter referred to as a Cds resonance matching circuit) 10a that is connected to a device equivalent output terminal Te (described later) and causes a resonance effect with the drain-source capacitance component Cds.

  A parallel resonance circuit (according to the present invention) formed by a series impedance functional inductance L1 functioning as a series impedance, an L1 parallel connection capacitance Cs connected in parallel to the series impedance function inductance L1, and a capacitance Cp2 functioning as a parallel impedance (hereinafter referred to as the present invention) A third harmonic parallel resonant circuit) 10b.

  A circuit formed of a Cds resonance matching circuit 10a and a third harmonic parallel resonance circuit 10b (respectively referred to as a Cds resonance / third harmonic resonance coupling circuit) 10 formed by coupling resonance circuits having different characteristics (according to the present invention). .

  A drain-source capacitance component (hereinafter referred to as a drain-source capacitance component) Cds at a desired angular frequency ω.

  A capacitance that functions as a parallel impedance of the L-type LPF (hereinafter referred to as a parallel impedance functional capacitance) Cp.

  A capacitance connected in series with the Cds resonance matching circuit forming inductance Lp, which shields the DC current applied to the device FET so as not to flow through the Cds resonance matching circuit forming inductance Lp (hereinafter, referred to as “DC blocking capacitance”). Cp1 (referred to as DC blocking capacitance).

  A capacitance Cp2 that functions as a parallel impedance of the third harmonic parallel resonance circuit 10b (hereinafter referred to as a capacitance within the third harmonic resonance circuit).

  Capacitance (hereinafter referred to as L1 parallel connection capacitance) Cs connected in parallel to a series impedance functional inductance L1 that functions as a series impedance.

  An inductance (hereinafter referred to as a series impedance functional inductance) L1 that functions as a series impedance of the L-type LPF or the third harmonic parallel resonance circuit 10b.

  Device-side inductance obtained by dividing the series impedance functional inductance L1 (hereinafter referred to as L1-divided device-side inductance) La.

  Load resistance side inductance (hereinafter referred to as L1 divided load resistance side inductance) Lb obtained by dividing the series impedance functional inductance L1.

  A Cds resonance circuit 10a is formed which is connected to the output terminal Te of the device FET (hereinafter referred to as device equivalent output terminal) Te in consideration of the influence of the drain-source capacitance component Cds and causes a resonance action with the drain-source capacitance component Cds. Inductance (hereinafter referred to as Cds resonance matching circuit forming inductance) Lp.

  The sharpness (hereinafter referred to as the Q of the L-type LPF) Q1 of the resonance curve of the L-type LPF circuit formed from the L1 divided load resistance side inductance Lb and the parallel impedance functional capacitance Cp.

  The sharpness of the resonance curve of the resonance matching / third harmonic parallel resonance circuit 10 formed from the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b (hereinafter, Q of the Cds resonance / third harmonic resonance coupling circuit). Q2).

  In FIG. 3, a pure resistance load in which the device direction load impedance Zds of the L-type LPF load connection terminal Tk becomes the load resistance value Rk at the desired angular frequency ω, or in FIG. 8, the third harmonic resonance circuit load connection terminal Tc A pure resistance load (hereinafter referred to as load resistance) Rk at which the device direction load impedance Zds becomes the load resistance value Rk at the desired angular frequency ω.

  A connection terminal (hereinafter referred to as a third harmonic resonance circuit load connection terminal) Tc between the third harmonic parallel resonance circuit 10b and the load resistor Rk.

  An output terminal (hereinafter referred to as a device FET pure output terminal) Td of a device FET that does not consider the influence of the drain-source capacitance component Cds.

  An output terminal (hereinafter referred to as a device equivalent output terminal) Te of a device FET considering the influence of the drain-source capacitance component Cds.

  A connection terminal (hereinafter referred to as an L-type LPF load connection terminal) Tk between the L-type LPF circuit and the load resistor Rk.

  A terminal (hereinafter referred to as a harmonic circuit 10b / network coupling terminal) Tn for coupling the third harmonic parallel resonant circuit 10b and the bias network BN.

  A connection terminal (hereinafter referred to as circuit 10a / circuit 10b connection terminal) Tr between the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b.

  A terminal Ts that divides the series impedance functional inductance L1 into a device side and a load resistance side (hereinafter referred to as an L-type LPF inductance dividing terminal) Ts.

  A reactance component of the drain-source capacitance component Cds (hereinafter referred to as a Cds reactance component) Xds.

  A reactance component (hereinafter referred to as a resonance matching reactance component or an inductive reactance component) Xds1 due to a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1.

  A reactance (hereinafter referred to as an Xds conjugate reactance) Xds1 conjugate with the Cds reactance component Xds in the resonance matching reactance component Xds1.

  Impedance viewed from the device equivalent output terminal Te in the device direction (hereinafter referred to as device direction Te impedance) Zd.

  Impedance (hereinafter referred to as device direction load impedance) Zds viewed from the L-type LPF load connection terminal Tk or the third harmonic resonance circuit load connection terminal Tc to the device FET.

  Impedance (hereinafter referred to as load resistance direction Te impedance) Zk viewed from the device equivalent output terminal Te in the direction of the load resistance Rk.

  A conjugate impedance (hereinafter referred to as a Zk conjugate impedance) Zk * of the load resistance direction Te impedance Zk.

  Impedance (hereinafter referred to as device direction Tr impedance) Zm viewed from the circuit 10a / circuit 10b connection terminal Tr in the direction of the device FET.

  Impedance (hereinafter referred to as Lp direction Tr impedance) Zn viewed from the circuit 10a / circuit 10b connection terminal Tr in the direction of the third harmonic parallel resonance circuit 10b.

  Impedance (hereinafter referred to as device direction Te impedance) Zs as viewed from the inductance division terminal Ts in the L-type LPF toward the device FET.

  A conversion ratio (hereinafter referred to as an impedance conversion ratio) Zds / Rds when the drain-source resistance Rds is impedance-converted to a device-direction load impedance Zds having a reactance component 0 at a desired angular frequency ω.

  Symbol (hereinafter referred to as reflection coefficient gamma) Γk for displaying the reflection coefficient of the load resistance direction Te impedance Zk.

  Phase angle of the reflection coefficient in the load resistance direction Te impedance Zk (hereinafter referred to as the phase angle of the reflection coefficient gamma) ΓkANG.

  The Zk reflection coefficient (reflection coefficient gamma) of the load resistance direction Te impedance when the characteristic impedance Z0 is normalized by the real part (real part) at the desired angular frequency ω of the load resistance direction Te impedance Zk (hereinafter referred to as the characteristic impedance reflection coefficient). ) Γk (@ Zo = Zk {Re}).

Magnitude of reflection coefficient of load resistance direction Te impedance Zk (hereinafter referred to as reflection coefficient gamma magnitude) ΓkMAG.
[Quality of conventional L-type LPF]
Hereinafter, the results of experiments and examinations in order to analyze the prior art in the creation process of the present invention and to extract the problems and the reasons will be described.

[Explanation of FIG. 2]
FIG. 2 is an L-type LPF equivalent circuit diagram of an equivalent circuit of the prior art in which an L-type LPF is added to the device equivalent output terminal Te of the device FET. When the power becomes high frequency, a drain-source capacitance component Cds is generated at both terminals (device FET pure output terminal Td) of the drain-source resistance Rds. A connection terminal between the Cds inclusion device and the L-type LPF or the Cds resonance matching circuit 10a according to the present invention when the drain-source capacitance component Cds is included in the device FET is defined as a device equivalent output terminal Te.

  In the step before performing the matching by the L-type LPF, the device FET is operated with a large signal, and the load pull measurement method is used to measure the impedance viewed from the device equivalent output terminal Te toward the load resistance Rk. Resistance direction Te impedance Zk is obtained.

  The load-pull measurement method described above is a general method for calculating the matching impedance added to the input / output of an amplifying device such as a transistor. In particular, it is essential for the high frequency of low-noise transistors and high-power transistors. It is an evaluation tool.

  In power matching, the conjugate impedance (Zk *) of the load resistance direction Te impedance Zk can be regarded as the device direction Te impedance Zd. Therefore, the output of the device FET at the device equivalent output terminal Te (hereinafter referred to as device output power Pout). Is represented by an extremely simplified equivalent circuit, and is replaced with a drain-source resistance Rds and a drain-source capacitance component Cds to perform power matching with respect to the device output power Pout.

  At the desired angular frequency ω, the impedance resistance value seen from the device FET pure output terminal Td in the direction of the load resistance Rk becomes the drain-source resistance Rds, and the device direction load impedance Zds is converted into an effective load having a reactance component 0. Is done.

  When impedance conversion is performed on this effective load with an L-type LPF, the drain-source capacitance component Cds is made part of the L-type LPF, and can be implemented with the series impedance functional inductance L1 and the parallel impedance functional capacitance Cp.

  However, it is difficult for the L-type LPF to achieve both power and efficiency matching to obtain a broad band. Next, we will qualitatively verify and clarify that this compatibility is difficult.

[Explanation of FIG. 3]
FIG. 3 is an equivalent circuit diagram of a conventional L1-divided L-type LPF obtained by dividing the series impedance functional inductance L1. In the same figure, in order to calculate the device direction load impedance Zds in which the reactance component of the L-type LPF equivalent circuit diagram of FIG. 2 is 0, the series impedance functional inductance L1 is divided into the L1 divided device side inductance La and the L1 divided load resistance side inductance. It is divided into Lb.

  The device direction Te impedance Zs of the reactance component 0 at the inductance division terminal Ts in the L-type LPF is calculated by [Equation 1] using the L-type LPF formed by the drain-source capacitance component Cds and the L1 division device-side inductance La.

  Next, the device direction load impedance Zds of the reactance component 0 is calculated by [Equation 2] using the device direction Te impedance Zs.

  Further, the Q of the L-type LPF of the L1 divided load resistance side inductance Lb and the parallel impedance functional capacitance Cp is calculated by [Equation 3]. Let Q1 be the Q of the L-type LPF calculated by [Equation 3].

  For example, when the Q of the L-type LPF is Q1 = 1 and the drain-source capacitance component Cds is 0 [pF], the maximum value 2Rds [Ω] of the device direction load impedance Zds of the reactance component 0 is obtained. It is done.

  However, in the device FET, the capacitance of the depletion layer formed by the drain N + layer and the P epi layer between this layer and the source greatly fluctuates in large signal operation, and the device FET transmits a large current to the load side. Since depletion is degenerated, the influence of the reactance component of the drain-source capacitance component Cds becomes more prominent as the frequency becomes particularly high.

  Therefore, in the L-type LPF, in order to obtain the device-direction load impedance Zds of the reactance component 0 at the desired angular frequency ω, the Q of the L-type LPF circuit increases as the frequency becomes higher, which is disadvantageous in terms of widening the power. .

  Next, the load resistance direction Te impedance Zk shown in FIG. 3 is calculated by [Expression 4]. The load resistance Rk is a pure resistance load in which the device-direction load impedance Zds of the L-type LPF load connection terminal Tk becomes the load resistance value Rk at the desired angular frequency ω.

[Explanation of FIG. 4]
FIG. 4 shows the L-type added to the Q (horizontal axis) of the L-type LPF, the device-direction load impedance Zds, the phase angle reflection coefficient ΓkANG of the reflection coefficient gamma, the drain-source resistance Rds, and the drain-source capacitance component Cds. Attenuation between the device equivalent output terminal Te of the second harmonic and third harmonic of the LPF and the L-type LPF load connection terminal Tk (hereinafter referred to as attenuation between Te and Tk) and the magnitude reflection coefficient of the reflection coefficient gamma It is a load impedance reflection coefficient characteristic diagram of L-type LPF alone showing a relationship with ΓkMAG (vertical axis).

  The figure shows the Q (horizontal axis) of the L-type LPF circuit (Network Circuit), the load impedance Zds [Ω] in the device direction (thin solid line with X mark), the phase angle reflection coefficient ΓkANG [deg] of the reflection coefficient gamma (thick) Solid line), Te-Tk attenuation [dB] (x thin solid line without mark) and the reflection coefficient Γk magnitude reflection coefficient ΓkMAG (dotted line) (vertical axis) showing the relationship between L-type LPF alone is there.

  In the figure, the reflection coefficient gamma (Load Gamma) is a sign for displaying the reflection coefficient of the load resistance direction Te impedance Zk, and is the phase angle of the reflection coefficient of the reflection coefficient ΓkANG load resistance direction Te impedance Zk. The coefficient ΓkMAG indicates the magnitude of the reflection coefficient of the load resistance direction Te impedance Zk.

  Here, the second harmonic of the L-type LPF added to the device output power Pout to the drain-source resistance Rds and the drain-source capacitance component Cds extracted from the data of the device FET (our product) according to the present invention. FIG. 4 shows the characteristic results of the calculated L-type LPF alone when the attenuation between the Te and Tk of the wave and the third harmonic is calculated in the direction in which the Q of the L-type LPF increases.

  In FIG. 4, the load resistance direction Te impedance Zk is converted into a reflection coefficient Γk (@ Zo = Zk {Re}) and displayed. This reflection coefficient Γk (@ Zo = Zk {Re}) is obtained by normalizing the characteristic impedance Z0 with the real part (real part) at the desired angular frequency ω of the load resistance direction Te impedance Zk. It is a reflection coefficient (characteristic impedance reflection coefficient).

  As shown in the load impedance reflection coefficient characteristic diagram of FIG. 4, the magnitude reflection coefficient ΓkMAG of the harmonic load impedance reflection coefficient Γk approaches 1 as the Q of the L-type LPF increases, and the phase of the load impedance reflection coefficient Γk The angle reflection coefficient ΓkANG approaches 0 [deg].

  Therefore, the load resistance direction Te impedance Zk of each harmonic has a high impedance characteristic close to open. As a result, in order to increase the efficiency of the L-type LPF by the third harmonic processing, the Q of the L-type LPF may be increased.

[Explanation of FIG. 5]
FIG. 5 is a power matching approach showing the relationship between the device output power Pout output from the device FET to the device equivalent output terminal Te of the L-type LPF, the drain efficiency ηd, and the gain (Gain) using the desired angular frequency ω as a parameter. FIG.

  In the figure, in order to select an optimally matched state, the desired angular frequency ω is changed from 460 [MHz] to 500 [MHz] every 10 [MHz], and output from the device FET to the device equivalent output terminal Te. The characteristic of the power matching approach showing the relationship between the device output power Pout [dBm] (horizontal axis), the drain efficiency ηd [%] and the gain [dB] (vertical axis) is shown.

[Explanation of FIG. 6]
FIG. 6 is a third harmonic processing approach characteristic diagram showing the relationship between the third harmonic processed device output power Pout output from the device FET to the device equivalent output terminal Te of the L-type LPF, the drain efficiency ηd, and the gain. is there.

  The figure shows a third harmonic process in which the desired angular frequency ω is changed from 460 [MHz] to 500 [MHz] every 10 [MHz] and output from the device FET to the device equivalent output terminal Te of the L-type LPF. Device output (hereinafter referred to as third harmonic processing device output) Pout [dBm] (horizontal axis), drain efficiency ηd [%] and gain [dB] (vertical axis) showing a third harmonic processing approach Shows the characteristics.

[Prior art 1]
As prior art 1, in Japanese Patent No. 2513146 (Japanese Patent Laid-Open No. 7-94974) (see Patent Document 1), when the impedance matching condition of the high output transistor output terminal is matched to the fundamental wave, It is described that it is effective for increasing the efficiency when open to the odd-order harmonics and when short-circuited to the even-order harmonics.

  As a means for making these matching conditions compatible, it is necessary to rationally perform harmonic processing that does not affect the fundamental wave matching. However, in the prior art 1, a transmission line such as a microstrip line is used, and depending on the wavelength. Utilizing the impedance characteristics, the second harmonic processing and the third harmonic processing are performed without affecting the fundamental wave matching.

[Prior Art 2]
The odd harmonic processing and even harmonic processing are, for example, circuits that process even higher harmonics such as the seventh harmonic and the eighth harmonic to improve efficiency. It is disclosed by Unexamined-Japanese-Patent No. 2001-11362 (refer patent document 2).

[Prior Art 3]
Further, a circuit for improving efficiency by focusing on the second harmonic processing is disclosed in Japanese Patent Laid-Open No. 2001-53510 (see Patent Document 3).

  As described above, the technique of applying the harmonic processing to the transistor output terminal in the region where the amplified output of the transistor is distorted, for example, in the operation region where the harmonic power is large, such as class B operation, class AB operation, class C operation, is F It is a prior art as an approach to class operation.

  When the drain-source capacitance component Cds is large as in the device FET, the reactance component becomes conspicuous as the frequency increases. Therefore, the matching of the desired frequency by the L-type LPF increases as the frequency increases. The impedance is lowered, the impedance conversion ratio ZdS / Rds between the transistor output and the load is increased, and it is difficult to obtain a wide band of power.

The patent documents are as follows.
Japanese Patent Laid-Open No. 7-94974 JP 2001-11362 A Japanese Patent Laid-Open No. 2001-53510

  By simply selecting a large Q of the L-type LPF described in the load impedance reflection coefficient characteristic diagram of FIG. 4 described above, it is not possible to achieve a wide band of power matching. To support this, the power matching approach and the third harmonic processing approach were verified using a model of a nonlinear device FET. The calculation results of matching the L-type LPF using the nonlinear simulation software are as shown in the power matching approach characteristic diagram of FIG. 5 and the third harmonic processing approach characteristic diagram of FIG.

  The device output power Pout shown in the power matching approach characteristic diagram of FIG. 5 and the third harmonic processing approach characteristic diagram of FIG. 6 is the output power of the L-type LPF output to the L-type LPF load connection terminal Tk. The load resistance Rk is constant.

  The L-type LPF is in an optimally matched state in order to obtain an output of 48 [dBm] at a center frequency of 480 [MHz]. In the power matching approach of FIG. 5, when the device output power Pout is 48 [dBm], an efficiency deviation of 5 [%] has already occurred.

  Furthermore, in the third harmonic processing approach of FIG. 6, the efficiency deviation deteriorates to 12 [%], and the gain deviation reaches 3 [dB]. If priority is given to efficiency, the power band characteristics deteriorate, and the efficiency The band characteristics are also affected by this action and deteriorate. Thus, in the conventional L-type LPF, both power matching and high efficiency cannot be widened simultaneously.

  The present invention provides a high-efficiency matching by third harmonic processing that does not affect the power matching in the desired angular frequency band and a power matching that is wider than the L-type LPF in the desired angular frequency band. An object of the present invention is to provide a high-frequency circuit in which a third harmonic resonance coupling circuit is added to a device equivalent output terminal Te of a device FET to obtain power matching and broadband efficiency higher than those of the prior art.

[Common means of means for solving problems]
In contrast to the above-described problem that the impedance conversion ratio Zds / Rds of the prior art increases and it is difficult to obtain a wide band of power, in the present invention, for a transistor having a large drain-source capacitance component Cds, such as a device FET, A means for avoiding a state where the impedance becomes smaller as the frequency becomes higher is adopted. As a means for avoiding this, a resonance matching reactance component Xds1 including a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 is used.

  On the other hand, in the present invention, the Cds reactance component Xds is generated by the drain-source capacitance component Cds at the desired angular frequency ω. The resonance matching reactance component Xds1 is applied as an inductive reactance component for canceling the Cds reactance component Xds. The resonance matching reactance component Xds1 and the Cds reactance component Xds are resonated to increase and increase the Lp direction Tr impedance Zn of the third harmonic parallel resonance circuit 10b connected to the next stage.

  Thus, in order to achieve a wider band than the conventional L-type LPF matching of FIG. 2, the present invention has a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 as shown in FIG. A Cds resonance matching circuit 10a is provided.

  The impedance conversion ratio of the third harmonic parallel resonance circuit 10b is improved by the Cds resonance matching circuit 10a. By improving the impedance conversion ratio ZdS / Rds, it is possible to broaden the power band and to easily adjust the third harmonic of the third harmonic parallel resonance circuit 10b, and to improve the efficiency. It is easy to obtain a wider bandwidth. The improvement of the impedance conversion ratio ZdS / Rds will be qualitatively described with reference to Q equation 8 of the third harmonic parallel resonant circuit 10b.

  When the Q of the resonance circuit is constant and the impedance conversion ratio Zds / Rds increases, it is determined that the impedance conversion ratio Zds / Rds has been improved. For example, the Q of one parallel resonant circuit A in the embodiment is Q = 2, the impedance conversion ratio Zds / Rds is 2, and the Q of the other parallel resonant circuit B is Q = 2, which is the same as the parallel resonant circuit A. When the impedance conversion ratio Zds / Rds of the other parallel resonance circuit B becomes 4, the impedance conversion ratio Zds / Rds of the other parallel resonance circuit B is improved, and a wide band is realized. be able to.

[Explanation of FIG. 1]
In FIG. 1, a Cds resonance matching circuit 10a is connected between the device equivalent output terminal Te and the ground G, and a third circuit is connected between the circuit 10a / circuit 10b connection terminal Tr and the harmonic circuit 10b / network coupling terminal Tn. It is a functional summary explanatory diagram of the present invention in which a harmonic parallel resonant circuit 10b is connected and a third harmonic resonant circuit capacitance Cp2 is connected between the harmonic circuit 10b / network coupling terminal Tn and the ground G.

  In the equivalent circuit diagram of FIG. 7 or FIG. 8 to be described later, since the bias network Bn is omitted, the harmonic circuit 10b and the network coupling terminal Tn are the third harmonic resonance circuit load connection terminal Tc.

  In the present invention, as shown in FIG. 1, a Cds resonance matching circuit 10a formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 is connected between a device equivalent output terminal Te and a ground G, A third harmonic parallel resonant circuit 10b formed by a series impedance functional inductance L1 and an L1 parallel connection capacitance Cs is connected between the device equivalent output terminal Te and the harmonic circuit 10b / network coupling terminal Tn. A third harmonic resonance circuit capacitance Cp2 is connected between the circuit 10b / network coupling terminal Tn and the ground G.

  The bias network BN is a circuit for supplying a direct current DC to the device FET, and the DC current is not supplied to the load side to which the high frequency power is transmitted, but is supplied only to the device side. A circuit through which high-frequency current does not leak in the path through which the

  With the above configuration, it is possible to achieve both high-efficiency matching by third harmonic processing that does not affect power matching in a desired angular frequency band and power matching that achieves a wider band of power than matching by a conventional L-type LPF. By adding a Cds resonance / third harmonic resonance coupling circuit that can be generated to the device equivalent output terminal Te of the device FET, it is possible to obtain power matching and high-efficiency broadband that are higher than those of the prior art using an L-type LPF. Become.

[Specific Means for Solving the Problems (Embodiment)]
In the following, a concrete example in which the above-described examination results are summarized and the means for solving the above-described problems are modified and expanded, with reference to the drawings (mainly, FIG. 7) and the reference numerals of the drawings, embodiments in the form of claims. As described.

  The first embodiment (A) is a high frequency power amplification in which a device equivalent output terminal Te of a high output field effect transistor (device FET) is connected to a Cds resonance matching circuit 10a that produces a resonance action with a drain-source capacitance component Cds. Circuit.

In the first embodiment (B), a Cds resonance matching circuit 10a that causes a resonance action with a drain-source capacitance component Cds is connected to a device equivalent output terminal Te of a high-power field effect transistor (device FET), and
This is a method of widening a high-frequency power amplifier circuit that cancels the Cds reactance component Xds of the drain-source capacitance component Cds at the desired angular frequency ω.

  In the second embodiment (A), the drain equivalent of the drain-source capacitance component Cds and the Cs resonance matching circuit 10a that produces a resonance action at the desired angular frequency ω at the device equivalent output terminal Te of the high output field effect transistor FET An Xds conjugate reactance Xds1 that is conjugate with the Cds reactance component Xds of the inter-source capacitance component Cds is generated, and a resonance action is generated when a large signal is input to the high-power field effect transistor (device FET). This is a high-frequency power amplifier circuit that cancels the component Xds.

In the second embodiment (B), a Cds resonance matching circuit 10a that causes a resonance effect with a drain-source capacitance component Cds is connected to a device equivalent output terminal Te of a high-power field effect transistor (device FET).
This is a method for widening a high-frequency power amplifier circuit that causes a resonance action when a large signal is input to a high-power field effect transistor (device FET) and cancels a reactance component Xds.

   In the third embodiment (A), a resonant matching reactance component that cancels the Cds reactance component Xds of the drain-source capacitance component Cds at the desired angular frequency ω at the device equivalent output terminal Te of the high-power field effect transistor (device FET). (Xds conjugate reactance) A high frequency power amplifier circuit to which Xds1 is connected.

  In the third embodiment (B), a resonant matching reactance component that cancels the Cds reactance component Xds of the drain-source capacitance component Cds at the desired angular frequency ω at the device equivalent output terminal Te of the high-power field effect transistor (device FET). (Xds conjugate reactance) This is a method for widening a high-frequency power amplifier circuit in which Xds1 is connected to cancel a Cds reactance component Xds at a desired angular frequency ω.

   In the fourth embodiment (A), Cds resonance matching is performed on a Cds resonance matching circuit forming inductance Lp that causes a resonance action with a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET). This is a high frequency power amplifier circuit in which a Cds resonance matching circuit 10a formed by a circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding the DC current applied to the MOSFET from flowing is connected.

  In the fourth embodiment (B), Cds resonance matching is performed on a Cds resonance matching circuit forming inductance Lp that causes a resonance action with a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET). A drain-source capacitance component at a desired angular frequency ω is connected by connecting a Cds resonance matching circuit 10a formed by a circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding the DC current applied to the MOSFET from flowing. This is a method of widening a high-frequency power amplifier circuit that cancels the Cds reactance component Xds of Cds.

  In the fifth embodiment (A), Cds resonance matching is performed on a Cds resonance matching circuit forming inductance Lp that causes resonance between the drain-source capacitance component Cds and the device equivalent output terminal Te of the high output field effect transistor (device FET). A Cds reactance component Xds of a drain-source capacitance component Cds at a desired angular frequency ω is formed by a circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding the DC current applied to the device FET from flowing. This is a high frequency power amplifier circuit to which a Cds resonance matching circuit 10a to be canceled is connected.

  In the fifth embodiment (B), Cds resonance matching is performed on a Cds resonance matching circuit forming inductance Lp that causes a resonance action with a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET). A drain-source capacitance at a desired angular frequency ω is connected by connecting a Cds resonance matching circuit 10a formed by a circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding the DC current applied to the device FET from flowing. This is a method of widening a high-frequency power amplifier circuit that cancels the Cds reactance component Xds of the component Cds.

  In the sixth embodiment (A), a series impedance functional inductance L1 functioning as a series impedance and a series impedance functional inductance L1 are provided between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistance Rk. This is a high-frequency power amplifier circuit in which a third harmonic resonance circuit 10b formed by an L1 parallel connection capacitance Cs connected in parallel and a third harmonic resonance circuit capacitance Cp2 functioning as a parallel impedance is connected.

In the sixth embodiment (B), a series impedance functional inductance L1 functioning as a series impedance and a series impedance functional inductance L1 are provided between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistance Rk. A third harmonic resonance circuit 10b formed by the L1 parallel connection capacitance Cs connected in parallel and the third harmonic resonance circuit internal capacitance Cp2 functioning as a parallel impedance is connected.
This is a method of widening a high-frequency power amplifier circuit that performs third harmonic processing on a device FET in a large signal state by adjusting the phase angle by changing the resonance frequency.

  In the sixth embodiment (A) and the sixth embodiment (B), the drain-source capacitance component Cds at the desired angular frequency ω is small due to the characteristics of the device FET, the desired angular frequency band, etc. The present invention can be applied to a case where the Cds resonance matching circuit 10a that cancels the component Xds is not required.

In the seventh embodiment (A), a Cds resonance matching circuit 10a that causes a resonance action at a desired angular frequency ω and a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET) is provided. Connect and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance, an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance function inductance L1, and a third harmonic that functions as a parallel impedance. This is a high frequency power amplifier circuit in which a third harmonic resonance circuit 10b formed by a capacitance Cp2 in the wave resonance circuit is connected.

In the seventh embodiment (B), a Cds resonance matching circuit 10a that causes a resonance action at a desired angular frequency ω and a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET) is provided. Connect and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance, an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance function inductance L1, and a third harmonic that functions as a parallel impedance. The third harmonic resonance circuit 10b formed by the capacitance Cp2 in the wave resonance circuit,
This is a method of widening a high-frequency power amplifier circuit that performs third harmonic processing on a device FET in a large signal state by adjusting the phase angle by changing the resonance frequency.

In the eighth embodiment (A), a Cds resonance matching circuit forming inductance that causes a resonance effect at a device equivalent output terminal Te of a high output field effect transistor (device FET) at a drain-source capacitance component Cds and a desired angular frequency ω. A Cds resonance matching circuit 10a formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding so as not to flow a DC current applied to the device FET is connected to Lp, and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance and a third harmonic resonance that functions as a parallel impedance L1 in parallel with the series impedance functional inductance L1 and a parallel impedance Cs. This is a high-frequency power amplifier circuit that is formed by an in-circuit capacitance Cp2 and performs a third harmonic process connected to a third harmonic resonance circuit 10b that adjusts the phase angle by changing the resonance frequency.

In the eighth embodiment (B), a Cds resonance matching circuit forming inductance that causes resonance at the device equivalent output terminal Te of the high output field effect transistor (device FET) at the drain-source capacitance component Cds and the desired angular frequency ω. A Cds resonance matching circuit 10a formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding so as not to flow a DC current applied to the device FET is connected to Lp, and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance and a third harmonic resonance that functions as a parallel impedance L1 in parallel with the series impedance functional inductance L1 and a parallel impedance Cs. A third harmonic parallel resonant circuit 10b including an in-circuit capacitance Cp2 is connected;
This is a method of widening a high-frequency power amplifier circuit that performs third harmonic processing by adjusting the phase angle by changing the resonance frequency.

In the ninth embodiment (A), a Cds resonance matching circuit 10a that causes a resonance action at a desired angular frequency ω and a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET) is provided. Connect and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance, an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance function inductance L1, and a third harmonic that functions as a parallel impedance. A high frequency formed by a capacitance Cp2 in the wave resonance circuit and connected to a third harmonic resonance circuit 10b that generates a very high impedance when viewed from the device FET with respect to the third harmonic contained in the output of the device FET. This is a power amplifier circuit.

In the ninth embodiment (B), a Cds resonance matching circuit 10a that generates a resonance action at a desired angular frequency ω and a drain-source capacitance component Cds at a device equivalent output terminal Te of a high output field effect transistor (device FET) is provided. Connect and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance, an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance function inductance L1, and a third harmonic that functions as a parallel impedance. The third harmonic resonance circuit 10b formed by the capacitance Cp2 in the wave resonance circuit,
For the third harmonic contained in the output of the device FET, an extremely high impedance is generated when viewed from the device FET, and the phase angle is adjusted by changing the resonance frequency. This is a method of widening a high-frequency power amplifier circuit that performs class F operation by third harmonic processing.

In the tenth embodiment (A), a drain-source capacitance is generated at the device equivalent output terminal Te of the high-power field effect transistor (device FET) with a drain-source capacitance component Cds and a desired angular frequency ω. The Cds resonance matching circuit forming inductance Lp for canceling the Cds reactance component Xds of the component Cds is formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding the DC current applied to the device FET from flowing. And connecting the Cds resonance matching circuit 10a
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance in the third harmonic, and an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance functional inductance L1 and a parallel impedance. It is formed with a functioning third harmonic resonance circuit capacitance Cp2 without changing the magnitude of the reactance component (inductive reactance component) between the L1 parallel connection capacitance Cs and the series impedance functional inductance L1 at the desired angular frequency ω. By changing the resonance frequency of the series impedance functional inductance L1 and the L1 parallel connection capacitance Cs while keeping the load resistance direction Te impedance Zk of the desired angular frequency ω constant, This is a high-frequency power amplifier circuit to which a third harmonic parallel resonant circuit 10b that enables adjustment and independently controls matching between the desired angular frequency ω and the third harmonic is connected.

In the tenth embodiment (B), a Cds resonance matching circuit forming inductance that causes a resonance effect at the device equivalent output terminal Te of the high output field effect transistor (device FET) at the drain-source capacitance component Cds and the desired angular frequency ω. A Cds resonance matching circuit 10a formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 for shielding so as not to flow a DC current applied to the device FET is connected to Lp, and
Between the Cds resonance matching circuit 10a and the load resistor Rk, a series impedance functional inductance L1 that functions as a series impedance in the third harmonic, and an L1 parallel connection capacitance Cs that is connected in parallel to the series impedance functional inductance L1 and a parallel impedance. The third harmonic resonance circuit 10b formed by the functioning capacitance Cp2 in the third harmonic resonance circuit is connected,
Resonance is generated at the drain-source capacitance component Cds and the desired angular frequency ω to cancel the Cds reactance component Xds of the drain-source capacitance component Cds, and
The load resistance of the desired angular frequency ω without changing the magnitude of the reactance component (inductive reactance component) between the L1 parallel connection capacitance Cs of the third harmonic parallel resonant circuit 10b and the series impedance functional inductance L1 at the desired angular frequency ω. The third harmonic can be adjusted by changing the resonance frequency of the series impedance functional inductance L1 and the L1 parallel connection capacitance Cs while keeping the direction Te impedance Zk constant, and the desired angular frequency ω and the third harmonic can be adjusted. This is a method of widening a high-frequency power amplifier circuit in which matching is controlled independently.

  In the eleventh embodiment (A), the series impedance functional inductance L1 that forms the third harmonic parallel resonant circuit 10b between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistor Rk is microscopic. Using the strip line, this microstrip line forms a series impedance functional inductance L1 in a U-shaped pattern, and forms a plurality of inductance adjusting patterns therein, and this “inductance adjusting pattern is formed in a U-shaped pattern. The high-frequency power amplifier circuit adjusts the constant of the L1 parallel connection capacitance Cs.

  In the eleventh embodiment (B), the series impedance functional inductance L1 that forms the third harmonic parallel resonant circuit 10b between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistor Rk is microscopic. Using the strip line, this microstrip line forms a series impedance functional inductance L1 in a U-shaped pattern, and forms a plurality of inductance adjusting patterns therein, and this “inductance adjusting pattern is formed in a U-shaped pattern. High-frequency power amplification that controls the third harmonic processing by changing the resonance frequency of the third harmonic parallel resonance circuit 10b by “connecting to the pattern of the first and second patterns” and “adjusting the constant of the L1 parallel connection capacitance Cs”. This is a circuit widening method.

  In the twelfth embodiment (A), the series impedance functional inductance L1 that forms the third harmonic parallel resonance circuit 10b between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistor Rk is microscopic. Using the strip line, this microstrip line forms a series impedance functional inductance L1 in a U-shaped pattern, and forms a plurality of inductance adjusting patterns therein, and this “inductance adjusting pattern is formed in a U-shaped pattern. And “adjusting the constant of the L1 parallel connection capacitance Cs” are formed from the reactance of the series impedance functional inductance L1 and the reactance of the L1 parallel connection capacitance Cs at the desired angular frequency ω. Electrical reactance components leave this constant value, a high frequency power amplifier circuit for adjusting the resonance frequency of the third harmonic parallel resonance circuit 10b.

In the twelfth embodiment (B), the series impedance functional inductance L1 that forms the third harmonic parallel resonance circuit 10b between the device equivalent output terminal Te of the high output field effect transistor (device FET) and the load resistor Rk is microscopic. Using a stripline, this microstripline has a process of forming a series impedance functional inductance L1 in a U-shaped pattern;
A process of forming a plurality of inductance adjustment patterns therein;
The inductance adjusting pattern is connected to the U-shaped pattern and the constant of the L1 parallel connection capacitance Cs is adjusted.
The inductive reactance component formed from the reactance of the series impedance functional inductance L1 and the reactance of the L1 parallel connection capacitance Cs at a desired angular frequency ω is set to a constant value, and the resonance frequency of the third harmonic parallel resonance circuit 10b is adjusted. This is a method for widening a high-frequency power amplifier circuit that controls third harmonic processing.

  It is not necessary to have all the effects of the present invention described below at the same time, as long as they have one or more effects of the present invention.

  The first effect of the present invention is that a matching circuit (Cds resonance matching circuit 10a in the embodiment) capable of obtaining a power matching wider than that of the L-type LPF in the desired angular frequency band is added to the device equivalent output terminal Te of the device FET. Thus, it is possible to obtain power matching and broadband efficiency higher than those of the prior art.

  In addition, the second effect of the present invention is that a high-efficiency matching (third harmonic parallel resonance circuit 10b in the embodiment) by the third harmonic processing that does not affect the power matching in the desired angular frequency band is performed by the device FET. By adding between the equivalent output terminal Te and the load resistor Rk, it is possible to obtain power matching and broadband efficiency higher than those of the prior art.

  Furthermore, the third effect of the present invention is that high-efficiency matching (third harmonic parallel resonance circuit 10b in the embodiment) by third harmonic processing that does not affect power matching in the desired angular frequency band, and desired angular frequency. A matching circuit (Cds resonance matching circuit 10a in the embodiment) capable of obtaining power matching in a wider band than that of the L-type LPF is added between the device equivalent output terminal Te of the device FET and the load resistor Rk. It is possible to obtain the above power matching and wide bandwidth efficiency.

  The fourth effect of the present invention is that a Cds resonance matching circuit 10a that causes a resonance action with a drain-source capacitance component Cds at a desired angular frequency ω at a device equivalent output terminal Te of a high output field effect transistor (device FET) is provided. The Cds reactance component Xds of the drain-source capacitance component Cds in the large signal state is canceled.

  The fifth effect of the present invention is the impedance conversion of the device output power Pout of the device FET at the next stage load terminal (the circuit 10a / circuit 10b connection terminal Tr of the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b). do.

  The sixth effect of the present invention is that the combined component of the Cds resonance matching circuit 10a functions as an inductive reactance (resonance matching reactance component) Xds1, and the Cds resonance matching circuit with respect to the third harmonic generated from the output of the device FET. The Cds resonance / third harmonic resonance coupling circuit 10 formed by the first harmonic parallel resonance circuit 10b and the third harmonic resonance circuit 10b generates a very high impedance (high impedance) as viewed from the device FET. The phase angle with respect to the third harmonic is adjusted by changing the resonance frequency by the function of adjusting the phase angle with respect to the harmonic.

  By adjusting this phase angle, an appropriate third harmonic can be processed ideally by performing a class F amplification operation in a device FET in a large signal state. Can be obtained.

  In the best mode for carrying out the invention, a device equivalent output terminal Te of a high output field effect transistor (device FET) is connected to a series impedance functional inductance L1 and a series impedance functional inductance L1 which function as a series impedance in the third harmonic. The third harmonic resonance circuit 10b formed by the parallel connected L1 parallel connection capacitance Cs and the third harmonic resonance circuit internal capacitance Cp2 functioning as a parallel impedance is connected, and the Cds resonance matching circuit 10a at the desired angular frequency ω is connected. By adjusting the resonance frequency class F operation without changing the magnitude of the Xds conjugate reactance Xds1, which is conjugate with the Cds reactance component Xds, the matching between the desired angular frequency ω and the third harmonic is independently controlled. A high frequency power amplifier circuit.

  The Cds resonance matching circuit forming inductance Lp and the series impedance functional inductance L1 shown in FIG. 1 described above are inductances, and can be formed by a microstrip line or a winding coil, a surface mounting chip, wire bonding, and the like.

  The DC blocking capacitance Cp1 and the L1 parallel connection capacitance Cs are capacitances, and can be formed by a surface mount chip capacitor (multilayer ceramic, MOS capacitance, etc.).

  If it is intended to be used for widening the desired frequency band of the present invention, the output matching circuit added to the transistor output terminal is described as an approach to class F operation of the prior art 3 in order to widen the band. A second harmonic processing circuit is incorporated.

  However, in the prior art, the influence of the attenuation pole by the second harmonic processing in which the circuit loss on the upper side of the desired frequency band appears near the upper side of the desired frequency band, for example, the pole of the attenuation amount between Te and Tc (the valley of the curve). Deteriorated by receiving. Therefore, the present invention applies the principle of the third harmonic processing in which the degradation is reduced as compared with the class F operation of the prior art 3.

  In addition, harmonic processing that is open to odd-order harmonics is an extremely ideal state. For example, when a device FET and an output matching circuit using a substrate are added, the transistor intrinsic region and the third harmonic processing are used. Since the parasitic reactance component, for example, the drain-source capacitance component Cds is included between the circuits that perform the above, the actual third harmonic processing circuit realizes an ideal opening to the third harmonic. Instead, it is more realistic that the phase angle can be adjusted with respect to the third harmonic, and the present invention has the adjustment function.

  The adjustment function of the present invention does not utilize the inherent impedance characteristic (open and short) with respect to the electrical length of the transmission line as in the prior art, but by the parallel connection of the series impedance function inductance L1 and the L1 parallel connection capacitance Cs. The reactance component can be varied in the vicinity of the third harmonic without changing by matching with the fundamental wave, and the phase angle of the very high impedance of the third harmonic viewed from the device equivalent output terminal Te can be varied. I have to.

[Qualitative Characteristics of Cds Resonance / Third Harmonic Resonance Coupling Circuit According to the Present Invention]
[Explanation of FIG. 7]
FIG. 7 is an equivalent circuit diagram of the Cds resonance / third harmonic resonance coupling circuit 10 including the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b at the device equivalent output terminal Te of the device FET.

  The figure shows an equivalent circuit in which a Cds resonance / third harmonic resonance coupling circuit capable of achieving power matching and high-efficiency broadband is added to the device equivalent output terminal Te of the device FET.

  The Cds resonance / third harmonic resonance coupling circuit 10 includes a Cds resonance matching circuit 10a formed by a Cds resonance matching circuit forming inductance Lp and a DC blocking capacitance Cp1 for blocking a DC component connected in series to the Cds resonance matching circuit 10a. A third harmonic parallel resonance circuit 10b in which an L1 parallel connection capacitance Cs is connected in parallel to the series impedance functional inductance L1 is formed between the Cds resonance matching circuit 10a and the load resistor Rk.

  In the Cds resonance matching circuit 10a, the resonance matching reactance component (Xds conjugate reactance) Xds1 as an inductive reactance component by the Cds resonance matching circuit forming inductance Lp and the DC blocking capacitance Cp1 cancels the Cds reactance component Xds at the desired angular frequency ω. Resonate. Then, the third harmonic parallel resonant circuit 10b converts the impedance of the drain-source resistance Rds having the reactance component 0 at the desired angular frequency ω into an effective load that has the reactance component 0 of the device direction load impedance Zds. .

  Further, the third harmonic processing can be adjusted by adjusting the resonance frequency by the L1 parallel connection capacitance Cs and the series impedance functional inductance L1, and the parallel resonance of the L1 parallel connection capacitance Cs and the series impedance functional inductance L1. When the frequency is in the harmonic direction, the reactance component of the L1 parallel connection capacitance Cs and the series impedance functional inductance L1 is inductive at the desired angular frequency ω.

  If the third harmonic processing is adjusted while keeping the inductive reactance component constant, power matching in the desired angular frequency band is not affected. By adjusting the third harmonic processing, it is possible to achieve both power matching and high-efficiency matching, which are intended to achieve a wider band than was possible with conventional L-type LPFs. The reason for this will be clarified by qualitatively examining the Cds resonance / third harmonic resonance coupling circuit 10.

[Explanation of FIG. 8]
FIG. 8 shows a device direction load impedance in which the reactance component of the equivalent circuit diagram of the Cds resonance / third harmonic resonance coupling circuit 10 including the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b of FIG. FIG. 8 is an equivalent circuit diagram of the Cds resonance / third harmonic resonance coupling circuit 10 developed from FIG. 7 in order to calculate Zds.

  First, the device direction Tr impedance Zm of the reactance component 0 in the Cds resonance matching circuit 10a shown in FIG. 8 is calculated by [Equation 5].

  At the desired angular frequency ω, the device direction Tr impedance Zm when the Cds reactance component Xds is canceled by the resonance matching reactance component Xds1 (of the reactance component by the Cds resonance matching circuit forming inductance Lp and the DC blocking capacitance Cp1) [ It calculates by Formula 6].

  In this case, the device direction Tr impedance Zm is the highest value. Next, when the device direction Tr impedance Zm = Rds, the device direction load impedance Zds of the reactance component 0 is calculated by [Expression 7].

  Further, the Q of the third harmonic parallel resonant circuit 10b when Zm = Rds is calculated by [Equation 8], and the Q calculated at this time is Q2.

  Then, when the Q of the third harmonic parallel resonant circuit 10b is Q2 = 1, a device direction load impedance Zds = 2Rds [Ω] in which the reactance component becomes 0 is obtained. In Q2 = 1, only when the L-type LPF has a drain-source capacitance component Cds = 0 [pF] and the maximum value of the device-direction load impedance Zds, the device-direction load impedance Zds = 2Rds + j0 [Ω] Become. On the other hand, in the matching circuit according to the present invention, the device direction load impedance Zds = 2Rds + j0 [Ω] of Q = 1 can always be obtained.

  As a result, in the matching circuit according to the present invention, in order to obtain the device direction load impedance Zds of the reactance component 0 at the desired angular frequency ω, the problem is that the Q of the L-type LPF becomes larger as the frequency becomes higher than the L-type LPF. As a result, the power can be widened more than the L-type LPF. Next, the load resistance direction Te impedance Zk is calculated by [Equation 9]. The load resistance direction Te impedance Zk calculated by [Equation 9] is defined as a real part (Re) of Zk.

[Explanation of FIG. 8]
The load resistance direction Te impedance Zk shown in FIG. 8 is calculated by [Equation 10]. The imaginary part of the load resistance direction Te impedance Zk calculated by [Equation 10] is defined as Zk (Im).

  The load resistance Rk is a pure resistance load in which the device direction load impedance Zds of the third harmonic resonance circuit load connection terminal Tc becomes the load resistance value Rk at the desired angular frequency ω.

  Here, the device output power Pout of FIG. 8 is supplied to the impedance composed of the load resistance Rds and the drain-source capacitance component Cds. For example, when the device direction load impedance Zds of the desired angular frequency ω is Q2 = 1, 2Rds + j0 [Ω], and at the desired angular frequency ω, the reactance component between the L1 parallel-connected capacitance Cs and the series impedance functional inductance L1 is constant, and the series impedance functional inductance L1 in the vicinity of the third harmonic is The parallel resonance frequency of the L1 parallel connection capacitance Cs is changed back and forth.

  Hereinafter, the characteristics of a circuit (for example, a Cds resonance / third harmonic resonance coupling circuit) in which resonance circuits having different characteristics are coupled will be described with reference to FIGS. 9 to 11, the load resistance direction Te impedance Zk is displayed after being converted into a reflection coefficient Γk (@ Zo = Zk {Re}).

[Explanation of FIG. 9]
FIG. 9 is a frequency / magnitude characteristic diagram showing the relationship between the frequency when the frequency is changed from the desired angular frequency ω in the third harmonic direction and the magnitude of the harmonic load impedance reflection coefficient Γk.

  This figure shows the relationship between the harmonic load impedance reflection coefficient Γk and the magnitude reflection coefficient ΓkMAG when the frequency is changed from 175 [MHz] to 900 [MHz] around the desired angular frequency ω. The characteristic of a 3 harmonic resonance coupling circuit is shown.

  In the figure, with respect to the horizontal axis of the frequency, the fundamental frequency of the desired angular frequency ω is 175 [MHz], and the frequency 3f of the third harmonic indicated by the elliptical dotted line is 500 [MHz]. Further, curve A is when Cs = 0 [pF], curve B is when Cs = 80 [pF], curve C is when Cs = 196 [pF], and curve D is when Cs = 300 [pF]. Magnitude characteristics are shown.

  In the frequency / magnitude characteristic diagram of FIG. 9, even if the L1 parallel connection capacitance Cs increases from Cs = 0 [pF] shown by the curve A to Cs = 300 [pF] shown by the curve D, the load impedance of the harmonics It shows that the magnitude reflection coefficient ΓkMAG of the reflection coefficient Γk has hardly changed. That is, the MAG of the reflection coefficient Γk does not change at the desired angular frequency ω, and is close to 1 at the angular frequency of the third harmonic 3f or higher.

[Explanation of FIG. 10]
FIG. 10 is a frequency / reflection coefficient phase angle characteristic diagram showing the relationship between the frequency when the frequency is changed from the desired angular frequency ω in the third harmonic direction and the phase angle of the harmonic load impedance reflection coefficient Γk. .

  The figure shows the frequency when the desired angular frequency ω is changed from the frequency 175 [MHz] to 900 [MHz] and the phase angle reflection coefficient ΓkANG [deg] of the load impedance reflection coefficient Γk of the harmonic load impedance reflection coefficient Γk. The characteristic of the Cds resonance and the third harmonic resonance coupling circuit showing the relationship is shown.

  In the figure, with respect to the horizontal axis of the frequency, the fundamental frequency of the desired angular frequency ω is 175 [MHz], and the frequency 3f of the third harmonic indicated by the elliptical dotted line is 500 [MHz]. Further, curve A is when Cs = 0 [pF], curve B is when Cs = 80 [pF], curve C is when Cs = 196 [pF], and curve D is when Cs = 300 [pF]. The characteristic of the phase angle reflection coefficient ΓkANG [deg] is shown.

  In the frequency / reflection coefficient phase angle characteristic diagram of the same figure, as the L1 parallel connection capacitance Cs is increased from Cs = 0 [pF] shown by the curve A to Cs = 300 [pF] shown by the curve D, the harmonics The change in the phase angle (ANG) of the load impedance reflection coefficient Γk is large.

  That is, the phase angle (ANG) at the desired angular frequency ω of the fundamental frequency is constant at 80 [deg], while the angular frequency of the third harmonic 3f of the fundamental frequency is the phase angle (ANG) of the reflection coefficient Γk. It fluctuates up and down with respect to the horizontal axis of 0 [deg].

  Using the above-described characteristics that fluctuate vertically, only the load resistance direction Te impedance Zk of the third harmonic can be changed without changing the load resistance direction Te impedance Zk. This load resistance direction Te impedance Zk can be adjusted by changing the parallel resonance frequency by the L1 parallel connection capacitance Cs and the series impedance functional inductance L1.

  By raising and lowering the range of the phase angle (ANG) of the reflection coefficient Γk itself, the Q of the Cds resonance / third harmonic resonance coupling circuit 10 is set to be the same as the Q of the L-type LPF circuit of the prior art. At the desired angular frequency ω, the device direction load impedance Zds (reactance component 0) can be made higher than that of the L-type LPF. Since it is possible to adjust the third harmonic processing while maintaining the state in which the device direction load impedance Zds is increased, it is possible to achieve a wider band of power matching and efficiency matching than the L-type LPF of the prior art.

  The same non-linear device FET model as in the L-type LPF is used to verify that the Cds resonance / third harmonic resonance coupling circuit 10 can achieve a wider band of power matching and efficiency matching than the L-type LPF. The output load is the same as that of the L-type LPF, and the optimum matching is performed by the third harmonic processing and the optimum matching for obtaining the output of 48 [dBm] at the center frequency 480 [MHz].

[Explanation of FIG. 11]
FIG. 11 shows the Cds resonance / third harmonic resonance coupling added to the frequency when the frequency is changed from the desired angular frequency ω in the third harmonic direction and to the drain-source resistance Rds and the drain-source capacitance component Cds. Frequency Te · Tc indicating the relationship between the third harmonic device equivalent output terminal Te of the circuit 10 and the third harmonic resonance circuit load connection terminal Tc (hereinafter referred to as Te · Tc attenuation). FIG.

  This figure shows the relationship between the frequency when the desired angular frequency ω is changed from the frequency 175 [MHz] to 900 [MHz] and the attenuation amount [dB] between Te and Tk of the harmonics. The characteristic of a wave resonance coupling circuit is shown.

  In the figure, with respect to the horizontal axis of the frequency, the fundamental frequency of the desired angular frequency ω is 175 [MHz], and the frequency 3f of the third harmonic indicated by the elliptical dotted line is 500 [MHz]. Further, curve A is when Cs = 0 [pF], curve B is when Cs = 80 [pF], curve C is when Cs = 196 [pF], and curve D is when Cs = 300 [pF]. The characteristic of attenuation amount [dB] between Te and Tk of a harmonic is shown.

  In the same figure, the frequency of the pole of Te-Tk attenuation (the position where the attenuation increases) in curve A is not shown because it is 1000 [MHz] or higher. Next, the frequency of the pole of Te-Tk attenuation (curved position in the drawing) Bm of the curve B is 710 [MHz], and the frequency of the pole Cm of Te-Tk attenuation of the curve C is It is 510 [MHz], and the frequency of the pole Dm of the attenuation amount between Te and Tk of the curve D is 360 [MHz] and sequentially moves in the lower frequency direction. The pole of attenuation between Te and Tk is a resonance point, and affects the parallel resonance frequency due to the series impedance functional inductance L1 and the L1 parallel connection capacitance Cs.

  As described above, the pole of attenuation between Te and Tk is the resonance point and influences the parallel resonance frequency, and the pole of attenuation between Te and Tk sequentially shifts toward the lower frequency, and the series impedance function The parallel resonance frequency due to the inductance L1 and the L1 parallel connection capacitance Cs sequentially moves in the lower direction. Thus, the parallel resonance frequency can be adjusted by moving the pole of the attenuation amount between Te and Tk.

[Explanation of FIG. 12]
FIG. 12 shows the relationship between the device output power Pout [dBm] output from the device FET to the device equivalent output terminal Te, the drain efficiency ηd [%], and the gain (Gain) [dB] with the desired angular frequency ω as a parameter. FIG.

  The device output power Pout shown in the power matching approach characteristic diagram of the figure is the output power of the Cds resonance / third harmonic resonance coupling circuit 10 output to the third harmonic resonance circuit load connection terminal Tc, and the load resistance Rk is constant.

  In the figure, the device output power Pout [dBm] (horizontal axis) output from the device FET to the device equivalent output terminal Te of the third harmonic parallel resonant circuit 10b and the drain efficiency ηd [ %] And a gain (Gain) [dB] (vertical axis).

  This figure shows the result of calculation by nonlinear simulation software by performing optimum matching for obtaining a device output power Pout having a center frequency of 480 [MHz] and optimum matching by third harmonic processing.

  In the third harmonic processing approach of the prior art L-type LPF, the in-band efficiency is 68 to 80 [%] (device output power Pout48 [dBm]), and the in-band gain is 19 to 22 [dB] (device output power Pout48). [DBm]).

  On the other hand, in the Cds resonance / third harmonic resonance coupling circuit 10 of the present invention, as shown in the figure, compared with FIG. 5 of the prior art, almost no gain deviation is obtained in the device output power Pout48 [dBm]. Efficient flattening is achieved without breaking down.

  In particular, the in-band efficiency is 73 [%] ± 0 (device output power Pout48 [dBm]), and the in-band gain is 21.5 to 22 [dB]. As described above, the Cds resonance / third harmonic resonance coupling circuit 10 formed by the Cds resonance matching circuit 10a and the third harmonic parallel resonance circuit 10b has a power matching and a wider bandwidth than the conventional L-type LPF. Can be obtained.

  The embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The technical scope of the present invention is determined based on the claims without being bound by the scope of the above description, and all modifications within the meaning and scope equivalent to the claims are within the technical scope. included.

  In parallel with the device equivalent output terminal Te of the high output field effect transistor (device FET), the series impedance functional inductance L1 functioning as a series impedance in the third harmonic and the L1 parallel connection capacitance Cs connected in parallel to the series impedance functional inductance L1. A third harmonic resonance circuit 10b formed by the third harmonic resonance circuit internal capacitance Cp2 functioning as an impedance is connected, and the L1 parallel connection capacitance Cs of the third harmonic resonance circuit 10b at the desired angular frequency ω and the series impedance are connected. By adjusting the resonance frequency class F operation without changing the reactance component (inductive reactance component) with the functional inductance L1, the high-frequency power that independently controls the matching between the desired angular frequency ω and the third harmonic Amplifier circuit The applicant has already produced a prototype and started a field test for practical use, and the industrial applicability is extremely high.

A Cds resonance matching circuit 10a is connected between the device equivalent output terminal Te and the ground G, and a third harmonic parallel resonance is established between the circuit 10a / circuit 10b connection terminal Tr and the harmonic circuit 10b / network coupling terminal Tn. It is a functional summary explanatory diagram of the present invention in which a circuit 10b is connected and a third harmonic resonance circuit capacitance Cp2 is connected between the harmonic circuit 10b / network coupling terminal Tn and the ground G. It is an L-type LPF equivalent circuit diagram of a prior art in which an L-type LPF is added to a device equivalent output terminal Te of a device FET. It is an L-type LPF equivalent circuit diagram of the prior art which divided | segmented the series impedance functional inductance L1. The relationship between the Q (horizontal axis) of the L-type LPF circuit and the device direction load impedance Zds, the phase angle reflection coefficient ΓkANG of the reflection coefficient gamma, the attenuation between Te and Tk, and the magnitude reflection coefficient ΓkMAG (vertical axis) of the reflection coefficient Γk. It is a load impedance reflection coefficient characteristic view of L type LPF alone in the prior art shown. Prior art power matching approach showing the relationship between the device output power Pout output from the device FET to the device equivalent output terminal Te of the L-type LPF, the drain efficiency ηd and the gain (Gain) using the desired angular frequency ω as a parameter FIG. FIG. 4 is a characteristic diagram of a third harmonic processing approach in the prior art showing a relationship between a third harmonic processed device output power Pout output from a device FET to a device equivalent output terminal Te of an L-type LPF, drain efficiency ηd, and gain. is there. The Cds resonance / third harmonic of the present invention comprising a Cds resonance / third harmonic resonance coupling circuit 10 comprising a Cds resonance matching circuit 10a and a third harmonic parallel resonance circuit 10b at the device equivalent output terminal Te of the device FET. It is a resonance coupling circuit equivalent circuit diagram. FIG. 8 is an equivalent circuit diagram of a Cds resonance / third harmonic resonance coupling circuit of the present invention for calculating a device direction load impedance Zds in which the reactance component of the equivalent circuit diagram of FIG. 7 is zero. FIG. 4 is a frequency / magnitude characteristic diagram according to the present invention showing the magnitude relationship of harmonic load impedance reflection coefficient Γk when the frequency is changed around the desired angular frequency ω. FIG. 4 is a frequency / reflection coefficient phase angle characteristic diagram according to the present invention showing a relationship between phase angles of harmonic load impedance reflection coefficients Γk when the frequency is changed around a desired angular frequency ω. FIG. 4 is a frequency / Te / Tc attenuation characteristic diagram showing the relationship between the Te / Tc attenuation of harmonics when the frequency is changed around the desired angular frequency ω. FIG. 6 is a power matching approach characteristic diagram according to the present invention showing a relationship between a device output power Pout output from a device FET to a device equivalent output terminal Te, a drain efficiency ηd, and a gain (Gain) using a desired angular frequency as a parameter.

Explanation of symbols

L-type LPF L-type LPF circuit third harmonic resonance circuit Third harmonic parallel resonance circuit 10b
LDMOSFET (device FET) High output field effect transistor 10 Cds resonance / third harmonic resonance coupling circuit 10a Cds resonance matching circuit 10b Third harmonic parallel resonance circuit Bn Bias network Cds Drain-source capacitance component Cp Parallel impedance function capacitance Cp1 DC blocking capacitance Cp2 Third harmonic resonance circuit capacitance Cs L1 parallel connection capacitance L1 Series impedance functional inductance La L1 Split device side inductance Lb L1 Split load resistance side inductance Lp Cds Resonance matching circuit formation inductance Pout Device output power Q of resonance circuit Resonance curve sharpness Q1 Q of L-type LPF circuit
Q2 Qds of Cds resonance and third harmonic resonance coupling circuit
Rds Drain-source resistance Rk Load resistance Tc Third harmonic resonance circuit load connection terminal Td Device FET pure output terminal Te Device equivalent output terminal Tk L-type LPF load connection terminal Tn Harmonic circuit 10b / network coupling terminal Tr circuit 10a Circuit 10b connection terminal Ts Inductance division terminal Xb in L-type LPF Lb reactance (ωLb) of desired angular frequency
Xd Cds reactance of desired angular frequency (1 / ωCds)
Xds Cds reactance component Xds1 Resonance matching reactance component / inductive reactance component / Xds conjugate reactance Xe Cds reactance (1 / ωaCds) at an arbitrary angular frequency
Xi L1 reactance (ωL1) of desired angular frequency
Xj L1 reactance (ωaL1) at an arbitrary angular frequency
Xk Lp reactance of desired angular frequency (ωLp)
Xm Lp reactance at any angular frequency (ωaLp)
Xp Cp reactance of desired angular frequency (1 / ωCp)
Xp1 Cp1 reactance of desired angular frequency (1 / ωCp1)
Xp2 Cp2 reactance of desired angular frequency (1 / ωCp2)
Xq Cp reactance of arbitrary angular frequency (1 / ωaCp)
Xq1 Cp1 reactance of arbitrary angular frequency (1 / ωaCp1)
Xq2 Cp2 reactance of arbitrary angular frequency (1 / ωaCp2)
Xs Cs reactance of desired angular frequency (1 / ωCs)
Xt Cs reactance of arbitrary angular frequency (1 / ωaCs)
Zd Device direction Te impedance Zds Device direction load impedance Zk Load resistance direction Te impedance (matching impedance)
Zk * Zk conjugate impedance Zm Device direction Tr impedance Zn Lp direction Tr impedance Zs Device direction Te impedance Zds / Rds Impedance conversion ratio ω Desired angular frequency ωa Arbitrary angular frequency Γk Load impedance reflection coefficient ΓkANG Reflection coefficient phase angle ΓkMAG Reflection coefficient Magnitude ηd Drain efficiency.

Claims (6)

  A high frequency power amplifier circuit in which a Cds resonance matching circuit that causes a resonance action with a drain-source capacitance component is connected to a device equivalent output terminal in consideration of the influence of a drain-source capacitance component Cds of a high-power field effect transistor.   A series impedance functional inductance L1 functioning as a series impedance and a series impedance functional inductance L1 are connected in parallel between the device equivalent output terminal Te and the load resistance Rk in consideration of the influence of the drain-source capacitance component Cds of the high output field effect transistor. A high frequency power amplifier circuit in which a third harmonic resonance circuit 10b formed by the connected L1 parallel connection capacitance Cs and a third harmonic resonance circuit internal capacitance Cp2 functioning as a parallel impedance is connected. A Cds resonance matching circuit that causes a resonance action at a desired angular frequency and a drain-source capacitance component is connected to a device equivalent output terminal in consideration of the influence of the drain-source capacitance component Cds of the high-power field effect transistor,
Between the Cds resonance matching circuit and the load resistor, a series impedance functional inductance that functions as a series impedance, an L1 parallel connection capacitance that is connected in parallel to the series impedance functional inductance, and a capacitance in a third harmonic resonance circuit that functions as a parallel impedance. A high frequency power amplifier circuit connected with a third harmonic resonance circuit formed by A Cds resonance matching circuit that causes a resonance action at a desired angular frequency and a drain-source capacitance component is connected to a device equivalent output terminal in consideration of the influence of the drain-source capacitance component Cds of the high-power field effect transistor,
Between the Cds resonance matching circuit and the load resistor, a series impedance functional inductance that functions as a series impedance, an L1 parallel connection capacitance that is connected in parallel to the series impedance functional inductance, and a capacitance in a third harmonic resonance circuit that functions as a parallel impedance. A high frequency power amplifier circuit formed by connecting a third harmonic resonance circuit that generates a very high impedance when viewed from the device FET with respect to the third harmonic included in the output of the device FET. A device equivalent output terminal considering the influence of the drain-source capacitance component Cds of the high-power field effect transistor causes a resonance effect at a desired angular frequency and a drain-source capacitance component, and a Cds reactance component of the drain-source capacitance. A Cds resonance matching circuit formed by a Cds resonance matching circuit forming inductance and a DC blocking capacitance for shielding the DC current applied to the device FET from flowing without being connected to the Cds resonance matching circuit forming inductance
Between the Cds resonance matching circuit and the load resistor, a series impedance functional inductance that functions as a series impedance in the third harmonic, an L1 parallel connection capacitance that is connected in parallel to the series impedance functional inductance, and a third harmonic that functions as a parallel impedance. The load resistance direction Te of the desired angular frequency without changing the magnitude of the reactance component (inductive reactance component) of the L1 parallel connection capacitance and the series impedance functional inductance at the desired angular frequency. The third harmonic can be adjusted by changing the resonance frequency of the series impedance functional inductance and the L1 parallel connection capacitance while keeping the impedance constant, and matching the desired angular frequency and the third harmonic. High frequency power amplifier circuit connected to the third harmonic parallel resonance circuit controlled independently. A microstrip line is used as a series impedance functional inductance that forms a third harmonic parallel resonant circuit between a device equivalent output terminal and a load resistance in consideration of the influence of the drain-source capacitance component Cds of the high-power field effect transistor. The microstrip line has a process of forming a series impedance functional inductance into a U-shaped pattern;
The process of forming multiple floating patterns inside it,
And connecting the floating pattern to a U-shaped pattern and adjusting the constant of the L1 parallel connection capacitance.
The reactance component formed from the reactance of the series impedance functional inductance at the desired angular frequency and the reactance of the L1 parallel connection capacitance is set to a constant value, and the resonance frequency of the third harmonic parallel resonance circuit is adjusted. A method of widening a high-frequency power amplifier circuit for controlling third harmonic processing.

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