JP2005086250A - Load control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a load control system wherein a control section can surely detect the operating state of a switch at a terminal side even on the occurrence of an event of disturbing data communication using an optical signal between the terminal and the control section. <P>SOLUTION: In the load control system provided with: the terminal for generating an optical signal in response to the operating states of a plurality of switches; the control section for receiving the optical signal generated from the terminal to control the operation of a prescribed load; and a power supply line through which the control section supplies power to the terminal; and a dedicated line through which the terminal transmits a signal in response to the operating state of at least part of switches to the control section, and the control section is provided with: an optical reception circuit for receiving an optical signal generated from the terminal; a first control circuit for controlling the operation of the prescribed load in response to the optical signal received by the optical reception circuit; and a second control circuit for controlling the operation of the load on the basis of the signal transmitted through the dedicated line, and the second control circuit is controlled depending on states of input/output signals of the first control circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a load control system that receives a signal from a terminal unit and controls the operation of a predetermined load.

  In recent years, a load control system that receives a signal from a terminal unit and controls the operation of a predetermined load is widely used in automobiles and the like. This load control system is, for example, a system that controls the operation of various loads such as motors using a LAN system mounted on an automobile, and this type of LAN system generally has a predetermined load. Constructed to connect the control unit that controls the operation and the terminal unit equipped with a plurality of switches and sensors via a wire harness that is a data communication medium, and to send the operation state of the switch and the sensing data by the sensor to the control device Is done.

  By the way, in this type of LAN system, when the number of objects to be controlled increases, the amount of data communication tends to increase and the number of wire harnesses laid tends to increase. Therefore, in order to reduce the number of wire harnesses, for example, when the position and posture of the seat in the vehicle change according to the operating state of the switch incorporated in the seat, from the terminal unit that detects the operating state of the switch An attempt has been made to optically communicate the detected data to a control unit that controls the operation of the seat seat driving motor by spatial propagation using infrared light or the like (see Patent Documents 1 to 4).

  The terminal unit in this system is mainly configured by an arithmetic processing unit (CPU) that drives a light emitting element such as an infrared light emitting diode in accordance with the state of a plurality of switches and transmits an optical signal having a predetermined frame configuration. The control unit receives the optical signal using a light receiving element such as a photodiode or a phototransistor to detect the operating state of the plurality of switches, and controls the operation of the seat seat driving motor according to the detection result. An electronic control unit (ECU) is provided.

JP 2001-144832 A Japanese Patent Laid-Open No. 2001-148685 JP 2001-160777 A JP 2001-160845 A

  However, in such a system, when a situation occurs in which data communication between the terminal unit and the control unit is hindered, it becomes impossible to detect the operation state of the switch in the control unit. As an example of such a situation, the interruption of the optical signal due to the obstacle entering the propagation space of the optical signal between the light emitting element and the light receiving element, the failure of the arithmetic processing unit (CPU) and the light emitting element in the terminal unit, A data communication path between the terminal unit and the control unit in order to detect the operation state of the switch in the control unit regardless of the above situation when there is a failure of the light receiving element or the electronic circuit unit (ECU) in the control unit It is necessary to ensure.

  Therefore, the present invention ensures that the operation state of the switch on the terminal unit side is ensured in the control unit even when a situation occurs in which data communication using the optical signal between the terminal unit and the control unit is hindered. It is an object of the present invention to provide a load control system that can detect the above.

  The invention of claim 1 includes a terminal unit that generates an optical signal corresponding to the operating state of the plurality of switches, and a control unit that receives the optical signal generated by the terminal unit and controls the operation of a predetermined load. In the load control system, a dedicated line for transmitting a signal corresponding to an operating state of at least a part of the switches from the terminal unit to the control unit is provided, and the control unit receives an optical signal generated by the terminal unit. An optical receiver circuit, a first control circuit for controlling the operation of a predetermined load based on an optical signal received by the optical receiver circuit, and at least a part of the optical receiver circuit based on a signal transmitted via the dedicated line. And a second control circuit for controlling the operation of a load corresponding to the switch of the first control circuit, wherein the second control circuit is controlled according to the state of the input / output signal of the first control circuit, To do.

  According to a second aspect of the present invention, in the first aspect of the invention, the first control circuit includes means for receiving a signal of the second control circuit.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the first control circuit compares the output of the optical receiver circuit with the output of the second control circuit. Means is provided for controlling the operation of the load by the output.

  In the present invention, when signals corresponding to the operation states of a plurality of switches are transmitted from the terminal unit to the control unit, at least a signal corresponding to the operation states of some switches is transmitted as a dedicated line in addition to transmission of optical signals And the second control circuit for controlling the operation of the load corresponding to the at least some switches based on the signal transmitted through the dedicated line, to the optical signal received by the optical receiving circuit. Since the control is performed according to the state of the input / output signal of the first control circuit that controls the operation of the predetermined load based on the data communication using the optical signal between the terminal unit and the control unit is hindered. Even if a situation occurs, the operation state of the switch on the terminal unit side can be reliably detected in the control unit by the signal transmitted through the dedicated line, and the optical signal and the dedicated line are further transmitted from the terminal unit to the control unit. From If a signal is transmitted, it is possible to give priority to control by either signal.

  Hereinafter, a load control system according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic configuration diagram illustrating an example of a main part of a load control system according to an embodiment of the present invention, where 1 is a terminal unit, 2 is a control unit, and 3 (3a to 3h) are loads. Further, between the terminal unit 1 and the control unit 2, the power supply line 4 that supplies power (+ B: for example + 12V) from the control unit 2 to the terminal unit 1, the ground (GND) potential of the terminal unit 1 and the control unit 2. In addition to the ground line 5 for matching the ground potentials of the two, a dedicated line 6 for transmitting a signal from the terminal unit 1 to the control unit 2 is connected.

  The terminal unit 1 generates an electrical signal corresponding to the operating state of the switch 11 (11a to 11h) by an arithmetic processing unit (CPU) 12, converts the electrical signal into an optical signal via the optical transmission circuit 13, Transmit to the control unit 2. Here, a light emitting diode (LED), a laser diode, or the like can be used as a light emitting element used in the optical transmission circuit 13. Here, the number of switches 11 is not limited to eight, and can be set as appropriate.

  The terminal unit 1 includes an oscillation circuit 14 that supplies a clock signal to the arithmetic processing unit 12. The arithmetic processing unit 12 normally monitors the states of the switches 11a to 11h periodically. However, when all the switches 11a to 11h are OFF, the operation of the oscillation circuit 14 is stopped or the clock of the oscillation circuit 14 is stopped. It is possible to reduce power consumption by reducing the signal speed.

  The terminal unit 1 includes an abnormality monitoring circuit 15 that generates an alarm when an input signal of the arithmetic processing unit 12 is not detected. Further, during the normal operation, the arithmetic processing unit 12 transmits, for example, a signal with a constant cycle to the abnormality monitoring circuit 15, and the abnormality monitoring circuit 15 detects when the signal from the arithmetic processing unit 12 is stopped or the predetermined period. If the signal is not in a predetermined cycle, it is possible to prevent malfunction of the load control system by outputting an initialization signal to the arithmetic processing unit 12.

  Of the signals transmitted from the terminal unit 1 to the control unit 2, electrical signals corresponding to the operating states of some of the switches 11 g and 11 h among the switches 11 a to 11 h are transmitted via the dedicated line 6. The electrical signal transmitted through the dedicated line 6 does not need to be an electrical signal corresponding to the operating state of some of the switches 11g and 11h, and depends on the operating state of at least some of the switches 11. The electrical signal may be any electrical signal corresponding to the operating state of all the switches.

  Pull-up resistors R11a to R11f are connected to the arithmetic processing unit 12 side of the switches 11a to 11f, respectively. As a result, the input voltage of the arithmetic processing unit 12 corresponding to the switch turned on among the switches 11a to 11f becomes a low level (almost GND level), and the input voltage of the arithmetic processing unit 12 corresponding to the switch turned off is Since the level is high (substantially the power supply voltage level), the arithmetic processing unit 12 can reliably determine the ON / OFF states of the switches 11a to 11f and reflect them in the output signal.

  Also, resistors R1 and R2 are connected to the arithmetic processing unit 12 side of the switches 11g and 11h, respectively, and the other ends of the resistors R1 and R2 are connected to the dedicated line 6. The potential of the dedicated line 6 is a potential set in the control unit 2, and the input voltage of the arithmetic processing unit 12 corresponding to the switch that is turned on among the switches 11g and 11h is low level (almost GND level). Since the input voltage of the arithmetic processing unit 12 corresponding to the switch that is turned off is at a high level (almost the potential of the dedicated line 6), the arithmetic processing unit 12 can be switched by appropriately setting the potential of the dedicated line 6. The ON / OFF state of 11g and 11h can be reliably determined and reflected in the output signal. Note that the circuit on the side of the arithmetic processing unit 12 of the switches 11g and 11h is exemplified in FIG. 1 as long as it can reliably determine the ON / OFF state of the switches 11g and 11h by the arithmetic processing unit 12. For example, a pull-up resistor may be added without limiting to the circuit.

  The control part 2 receives the signal which the terminal part 1 generate | occur | produced, and controls the action | operation of the predetermined load 3 (3a-3h). The control unit 2 receives an optical signal transmitted from the terminal unit 1 and converts it into an electrical signal, and controls the operation of predetermined loads 3a to 3h according to the output of the optical receiving circuit 21. A first control circuit 22 that generates a signal and load drive circuits 23a to 23h connected to the output side of the first control circuit 22 are provided.

  Here, the 1st control circuit 22 is comprised by arithmetic processing units (CPU) etc. similarly to the terminal part 1, for example. The load drive circuits 23a to 23h may be a combination of a relay drive circuit and a relay, for example, or may be a semiconductor switch circuit. In general, the load driving circuit 23 is configured to operate the load when the input signal is at a high level and not to operate the load when the input signal is at a low level. Although the description will be made assuming the load driving circuit 23, an actual example of the load driving circuit 23 is not limited to this example.

  In addition, the control unit 2 includes a second control circuit 24 that generates a signal for controlling the operation of the predetermined loads 3g and 3h in accordance with a signal transmitted from the terminal unit 1 via the dedicated line 6. In the second control circuit 24, A is a signal input port from the dedicated line 6, B is a control signal input port, C1 and C2 are comparator output ports, and D1 and D2 are control output ports.

  Logic circuits 25a and 25b are provided on the input side of the load driving circuits 23g and 23h. Here, one of the output signals of the first control circuit 22 and the output signal of the second control circuit 24 is provided. OR circuits are used as the logic circuits 25a and 25b so that the input signal of the load driving circuit 23 is at a high level when is at a high level. The logic circuits 25 a and 25 b can be changed according to the configuration of the load driving circuit 23.

  The first control circuit 22 includes means for controlling the operation of the second control circuit 24. Specifically, as illustrated in FIG. The control signal can be transmitted toward the control signal input port B of the control circuit 24, but other configurations may be employed.

  In addition to the above-described configuration, the control unit 2 includes an oscillation circuit 26 that supplies a clock signal to the first control circuit 22 and an abnormality monitoring circuit that generates an alarm when an input signal of the first control circuit 22 is not detected. 27 and the like. Further, the entire control unit 2 can be configured as an electronic control unit (ECU), for example.

  As mentioned above, although an example of the principal part of the load control system which concerns on embodiment of this invention was demonstrated, the load control system which concerns on embodiment of this invention is good also as a structure further provided with the following characteristic.

  In the case where an optical signal and a signal from the dedicated line 6 are transmitted from the terminal unit 1 to the control unit 2, the first control circuit 22 is a second control circuit from the viewpoint of giving priority to control by any one of the signals. It is desirable to have means for receiving 24 signals. Although FIG. 1 shows an example in which the first control circuit 22 receives signals from the comparator output ports C1 and C2 of the second control circuit 24, other configurations may be used.

  Further, from the same viewpoint, the first control circuit 22 includes means for comparing the output of the optical receiving circuit 21 and the output of the second control circuit 24 and controlling the operation of the load by one of the outputs. It is desirable that

  Next, a specific example of the second control circuit 24 will be described. FIG. 2 is a schematic configuration diagram illustrating an example of the second control circuit. The second control circuit 24 includes comparators 241 and 242 and logic circuits 243 to 245 therein. Of the logic circuits 243 to 245, 243 is an OR circuit, and 244 and 245 are NOR circuits.

The input voltages of the comparators 241 and 242 are voltages obtained by dividing the input voltage of the second control circuit by the resistors R22 and R23. The threshold voltages Vcomp1 and Vcomp2 of the comparators 241 and 242 are divided into power supply voltages (+ Vcc: for example + 5V) by resistors R24, R25, and R26, respectively, to be the following voltages.
Vcomp1 = + Vcc {(R25 + R26) / (R24 + R25 + R26)}
Vcomp2 = + Vcc {(R26) / (R24 + R25 + R26)}

  Then, the outputs of the comparators 241 and 242 are set, for example, as in the following (1) to (3) according to the states of the switches 11g and 11h.

(1) When both the switches 11g and 11h are OFF: The outputs of the comparators 241 and 242 are both set to a high level so that the input voltage Voff of the comparators 241 and 242 satisfies Voff>Vcomp1> Vcomp2.

(2) When Switch 11g is ON The input voltage Vg of the comparators 241 and 242 is set to Vcomp1>Vg> Vcomp2, and the output of the comparator 241 is set to the low level and the output of the comparator 242 is set to the high level.

(3) When the switch 11h is ON: The outputs of the comparators 241 and 242 are both set to the low level so that the input voltage Vh of the comparators 241 and 242 satisfies Vcomp1>Vcomp2> Vh.

  Next, changes in the control output ports D1 and D2 due to the control signal from the first control circuit 22 input to the control signal input port B will be described. Here, the control signal input to the control input port B is high level (almost power supply voltage level) when the first control circuit 22 can operate the load drive circuits 23a to 23h, and the first When the control circuit 22 cannot operate the load driving circuits 23a to 23h, an example in which the control circuit 22 is set to be at a low level (almost GND level) is shown. The control signal input to the control input port B is not limited to the above example, and any signal may be used as long as it is a control signal suitable for the configuration of the second control circuit 24.

  When the control signal is input to the control input port B and the first control circuit 22 can operate the load driving circuits 23a to 23h, the outputs of the control output ports D1 and D2 are both low level. When the first control circuit 22 cannot operate the load drive circuits 23a to 23h, in the case of (1), the outputs of the control output ports D1 and D2 are both low level and the load is driven. In the case of (2), the output of the control output port D1 is high level, the output of the control output port D2 is low level, the load driving circuit 23g operates the load 3g, and (3) ), The output of the control output port D1 is low level, the output of the control output port D2 is high level, and the load driving circuit 23h operates the load 3h. . The results are shown in Table 1.

  In the above description, when both the switches 11g and 11h are turned on at the same time, the input voltage of the comparators 241 and 242 is lower than Vh, and the state is the same as the above (3). If it is necessary to discriminate when both the switches 11g and 11h are turned on at the same time, the discrimination can be made by adding one comparator.

  As mentioned above, although an example of the principal part of the load control system which concerns on embodiment of this invention was demonstrated, this load control system is the operation state of the switch integrated in this seat seat, for example, the position and attitude | position of a seat seat of a motor vehicle. It can be specifically applied to a system that changes according to the conditions. Specific examples will be described below.

  In general, a system that changes the position and posture of a seat of an automobile in accordance with the operating state of a switch supports the following changes in the position and posture of the seat.

(A) The operation of sliding the seat cushion back and forth (hereinafter, the operation of sliding the seat cushion forward is referred to as SLD +, and the operation of sliding backward is referred to as SLD-).
(B) An operation of moving the cushion front portion up and down (hereinafter, an operation of moving the cushion front portion upward is referred to as FRV +, and an operation of moving the cushion front portion downward is referred to as FRV-).
(C) An operation of moving the rear portion of the cushion up and down (hereinafter, an operation of moving the rear portion of the cushion up is LFT +, and an operation of moving the lower portion of the cushion down is LFT-).
(D) An operation of reclining the backrest back and forth (hereinafter, an operation of moving the backrest forward is referred to as RCL +, and an operation of moving the backrest backward is referred to as RCL-).

  The adjustment of the position and posture of the seat is performed by the load 3 (3a to 3h) through the control unit 2 by operating the switch 11 (11a to 11h) provided in the terminal unit 1 of FIG. This is done by operating a motor.

  Hereinafter, the switches 11a to 11h will be described in correspondence with FRV +, FRV−, LFT +, LFT−, RCL +, RCL−, SLD +, and SLD−, respectively. Here, the switches 11g and 11h connected to the dedicated line 6 correspond to the operation (SLD +, SLD−) of (A).

  FIG. 3 is an explanatory diagram showing an example of the ON / OFF state of the switch and the data state of the serial communication frame configuration corresponding to the switch ON / OFF state. As shown in FIG. 3, when the ON / OFF states of the switches 11a to 11h change, chattering may occur and then change to the final state (high level or low level). In this embodiment, when the result of periodically monitoring the state of the switch whose ON / OFF state has changed by the arithmetic processing unit 12 is recognized to be in the same state for a certain period of time, the ON / OFF after the change of the switch is detected. The OFF state is determined as the input high level / low level.

  When the arithmetic processing unit 12 recognizes a change in the ON / OFF state of the switch, the arithmetic processing unit 12 converts the state of each of the switches 11a to 11h into serial communication frame configuration data and sends the data to the optical transmission circuit 13. The optical transmission circuit 13 converts frame-structured data into an optical signal and transmits it. FIG. 3 shows an example of the relationship between the ON / OFF state of the switch and the communication frame of the output optical signal of the optical transmission circuit. Here, the SW input confirmation time means the time from when the switch is turned ON / OFF until the arithmetic processing unit 12 determines the ON / OFF state after the switch change as the input high level / low level. .

  Details of the frame configuration will be described. FIG. 4 is an explanatory diagram illustrating an example of details of data of a frame configuration of serial communication. In FIG. 4, the communication frame is composed of four areas: a leader pulse, a data area, an error check area, and an idle area.

  The leader pulse indicates the start of a frame and is a data area for stabilizing the operation of the optical receiving circuit 21 of the control unit 2.

  In the data area, one bit is associated with each switch 11a to 11h, and the state of each switch is configured as logic 1 or logic 0. Here, the switch ON state is logic 0, the switch OFF state is logic 1, and the data area is composed of 8-bit data. FIG. 4 shows an example in which only the switch 11g is in the ON state, only the corresponding SLD + data is logic 0, and the other data is logic 1.

  The error check area is an area in which error check codes such as parity check and CRC check are accommodated.

  The idle area is a preparation period for transmission / reception when frames are continuously transmitted, and is an area representing a time during which nothing is transmitted.

  The data having the frame configuration shown in FIG. 4 is converted into an optical signal by the optical transmission circuit 13. This optical signal is an optical signal obtained by modulating an infrared ray generated by a light emitting element such as a light emitting diode having a wavelength of 850 nm to 950 nm with data of a frame configuration, and is modulated by repeatedly energizing and deenergizing the light emitting element. FIG. 5 shows a specific example of the output optical signal of the optical transmission circuit 13. In FIG. 5, the right side of the arrow is an enlarged view of the modulated signal, and the frequency of the pulse in the right side is, for example, about 30 to 50 kHz.

  Here, the logic 0 and logic 1 bits are distinguished by the time interval of the modulation output having a constant width. For example, the logic 1 bit length is 1 ms and the logic 0 bit length is 2 ms.

  The terminal unit 1 periodically transmits a signal having the frame configuration shown in FIGS. 3 and 4 to the control unit 2 at intervals longer than the frame length (for example, about several times). For example, if the bit length of logic 1 is 1 ms, the bit length of logic 0 is 2 ms, the leader pulse length is 10 ms, and the error check area length is about 30 ms, the frame length (excluding the idle area) is about 50 to 60 ms, When a specific switch among the switches 11a to 11h is in an ON state, frames are periodically transmitted at intervals (for example, 200 ms to 300 ms) several times the frame length. When all the switches 11a to 11h are OFF, the energization time of the light emitting elements constituting the optical transmission circuit 13 is shortened to prevent the light emission efficiency from deteriorating by not performing periodic transmission.

  The optical signal generated by the optical transmission circuit 13 is converted into an electric signal by the light receiving element of the optical reception circuit 21, amplified, and input to the first control circuit 22. The first control circuit 22 periodically samples the input signal from the optical receiving circuit 21 and determines whether the signal matches a predetermined frame configuration or whether the error check code is correct. When it is determined that the input signal from the optical receiving circuit 21 is normal, an output signal for operating the load driving circuits 23a to 23h is generated based on the data of the received frame.

  Here, based on the data shown in FIG. 4, when data is periodically received every 200 ms, it is desirable to operate the load driving circuit 23 for about 500 ms, for example. In this case, even if one frame of data cannot be received, the loads 3a to 3h can be operated smoothly. FIG. 6 shows an example of the relationship between the output signal of the optical receiving circuit 21 and the operating state of the load control circuit 23.

  By the way, a time lag occurs between the output signal of the first control circuit 22 and the output signal of the second control circuit 24. An example of this state is shown in FIG.

  As shown in FIG. 7, when the switch 11g (SLD + switch) is turned on, a signal is transmitted from the terminal unit 1 through the dedicated line 6 with almost no delay. Processing is performed to generate a high level output at the control output port D1. On the other hand, the output signal of the first control circuit 22 transmitted through the optical signal is shown in FIGS. 3 and 7 at the stage of generating the optical signal from the terminal unit 1 through the arithmetic processing unit 12. As described above, since a delay occurs in the frame signal by the SW input confirmation time, a time lag occurs with respect to the output signal of the second control circuit 24.

  Therefore, in order to prevent the influence of this time lag, the first control circuit 22 compares the output of the optical receiving circuit 21 with the output of the second control circuit 24, and the output signal of the optical receiving circuit 21 is normally received. When possible, the influence of the time lag can be prevented by stopping the output of the second control circuit 24.

  As described above, when the first control circuit 22 can normally receive the input signal from the optical receiving circuit 21, the load control circuit 23 is activated by the signal from the dedicated line 6 as described above. There is no.

  On the other hand, when the first control circuit 22 cannot normally receive the input signal from the optical receiving circuit 21, the signal from the dedicated line 6 is processed by the second control circuit 24 as described above. The load control circuit 23g (or 23h) is activated by a signal from the dedicated line 6.

  When the operation state of the first control circuit 22 is abnormal, the first monitoring circuit 22 is reset by the abnormality monitoring circuit 27, and only the output of the second control circuit 24 becomes valid, and the control output ports D1, D2 The load drive circuits 23g and 23h are operated only by the output signal from.

  Further, when the arithmetic processing unit 12 of the terminal unit 1 is in a low power consumption state such as during standby, no optical signal is transmitted from the terminal unit 1 to the control unit 2, so only the output of the second control circuit 24 is received. The load driving circuits 23g and 23h are activated only by the output signals from the control output ports D1 and D2.

  Even when there is no input signal of the optical receiving circuit 21, only the output of the second control circuit 24 is valid. In this case, the outputs of the direct control output ports D1 and D2 are not validated, and the comparator When the outputs of the output ports C1 and C2 are input to the first control circuit 22 and the load control circuits 23g and 23h are operated using the output signal of the first control circuit 22, the input signal of the optical reception circuit 21 is When returning, it is desirable from the viewpoint of preventing the influence of the time lag shown in FIG. In this case, a control signal is transmitted from the first control circuit 22 to the control signal input port B of the second control circuit 24, and the outputs of the control output ports D1 and D2 of the second control circuit 24 are both Become low level.

  Here, the criterion for determining that the first control circuit 22 does not have an input signal of the optical receiving circuit 21 is that the signal from the dedicated line 6 passes through the comparator output ports C1 and C2 of the second control circuit 24. It is assumed that a communication frame cannot be received for a certain period of time while being input to the first control circuit 22. This fixed time is set to a time slightly shorter than the retrigger driving after receiving the data indicating that the switch 11g (11h) is turned ON, so that the output signal of the optical receiving circuit 21 is output from the load driving circuits 23g and 23h. Even when shut off during driving, it is possible to smoothly switch from control using an optical signal to control using a signal transmitted via the dedicated line 6.

  When the output signal of the first control circuit 22 based on the output signal of the optical receiving circuit 21 and the output signals of the comparator output ports C1 and C2 of the second control circuit 24 do not match, the terminal unit 1 or the control unit 2 is considered to have some abnormality, the first control circuit 22 performs control to stop the output signal of the first control circuit 22 and the output signal of the second control circuit 24. It is desirable to do.

  Note that the embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope described in the claims.

It is a schematic structure figure showing an example of the principal part of the load control system concerning the embodiment of the present invention. It is a schematic block diagram which shows an example of a 2nd control circuit. It is explanatory drawing which shows an example of the relationship between the ON / OFF state of a switch, and the communication frame of the output optical signal of an optical transmission circuit. It is explanatory drawing which shows an example of the detail of the data of the frame structure of serial communication. It is explanatory drawing which shows a specific example of the output optical signal of the optical transmission circuit. 3 is an explanatory diagram showing a relationship between an output signal of an optical receiver circuit 21 and an operating state of a load control circuit 23. 3 is an explanatory diagram illustrating an example of a time lag that occurs between an output signal of a first control circuit 22 and an output signal of a second control circuit 24. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Terminal part 2 Control part 3, 3a-3h Load 4 Power supply line 5 Ground line 6 Dedicated line 11, 11a-11h Switch 12 Processing unit (CPU)
DESCRIPTION OF SYMBOLS 13 Optical transmission circuit 14 Oscillation circuit 15 Abnormality monitoring circuit 21 Optical reception circuit 22 1st control circuit 23, 23a-23h Load drive circuit 24 2nd control circuit 25a, 25b Logic circuit (OR circuit)
26 Oscillation circuit 27 Abnormality monitoring circuit 241, 242 Comparator 243 Logic circuit (OR circuit)
244, 245 Logic circuit (NOR circuit)

Claims (3)

A terminal unit that generates an optical signal according to the operating state of a plurality of switches;
In a load control system comprising a control unit that receives an optical signal generated by the terminal unit and controls the operation of a predetermined load,
A dedicated line for transmitting a signal corresponding to the operating state of at least some of the switches from the terminal unit to the control unit;
The control unit includes an optical receiver circuit that receives an optical signal generated by the terminal unit, a first control circuit that controls an operation of a predetermined load based on the optical signal received by the optical receiver circuit, and the dedicated unit. A second control circuit for controlling the operation of a load corresponding to the at least some of the switches based on a signal transmitted via a line;
The load control system, wherein the second control circuit is controlled according to a state of an input / output signal of the first control circuit.   The load control system according to claim 1, wherein the first control circuit includes means for receiving a signal of the second control circuit. The first control circuit includes means for comparing the output of the optical receiver circuit with the output of the second control circuit and controlling the operation of the load by one of the outputs. The load control system according to claim 1 or 2.

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