JP2005084732A - Logic integrated circuit and its information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic integrated circuit and its information processing method for reducing power consumption, and for shortening a time required for designing, and for changing system configuration for a plurality of usages. <P>SOLUTION: This logic integrated circuit 1 is configured of a component group being the group of components being a functional block having specific functions, a storage part in which parameters including the operation conditions of the respective components of the component group and inter-component connection information are stored, a control part for setting the parameters including the operation conditions of the respective components of the component group and the inter-component connection information, a clock generating part for generating a clock to specify the operation of the component group, and for supplying it to each part and a timing controlling part for controlling the operation timing of the component group. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a logic integrated circuit and an information processing method thereof.

Conventionally, there is a technique related to reconfiguration of a programmable logic circuit.
For example, Patent Document 1 includes information for configuring a circuit to be reconfigured on a programmable logic circuit having a plurality of logic blocks arranged in a matrix and information for configuring a circuit that is not reconfigured. Circuit information is stored, and a circuit to be reconfigured on the programmable logic circuit based on the circuit information is configured by a column area or one or more logic block rows configured by one or more logic block columns of the programmable logic circuit It is disclosed that they are configured in a row area. As a result, the time required for reconfiguring the programmable logic circuit can be shortened, and processing can be performed efficiently.
Patent Document 2 discloses an S cell group composed of a plurality of small cells (small granularity) S cells in order to reduce unused resource areas in a reconfigurable programmable logic circuit device and to reduce global wiring delay. It is disclosed that a programmable logic circuit device is configured by two-dimensionally arranging an L cell group composed of a plurality of large size (large granularity) L cells. As a result, the unused resource area can be reduced as compared with the case where the cell granularity is large, and the number of global wirings can be reduced as compared with the case where the cell granularity is small, thereby reducing the delay time caused by the global wiring. .
JP 2002-208638 A JP 2002-16489 A

However, the programmable logic circuit as described above has a problem that it is difficult to reduce power consumption.
In addition, there is a problem that the cost is increased when the usage is more limited or when it can be changed to a plurality of specific usages.

The present invention has been made in view of such circumstances, and a first object is to reduce the power consumption, shorten the design period, and change the system configuration for a plurality of applications. To provide a logic integrated circuit and an information processing method thereof.
A second object is to provide a logic integrated circuit and an information processing method thereof that can be applied to a plurality of systems whose applications are limited by simplifying a communication procedure having high functions, downsizing and simplifying its configuration. It is to provide.

  The present invention has been made to solve the above-mentioned problems, and the present invention relates to a component group that is a set of components that are functional blocks having a specific function, operation conditions of each component of the component group, and A storage unit that stores parameters including connection information, a control unit that sets parameters including operation conditions and connection information between components in each component of the component group, and a clock that defines the operation of the component group And a clock generation unit supplied to each unit, and a timing control unit for controlling the operation timing of the component group.

  Further, according to the present invention, each of the components includes an input interface unit that captures, temporarily holds, and outputs an input signal, a storage unit that holds the parameter set by the control unit, and the input interface unit. A calculation unit that processes data input via the function assigned by the parameter held in the storage unit, and an output interface unit that temporarily holds data output from the calculation unit and outputs the data to the outside And the input interface unit, the arithmetic unit, or the output interface unit includes an input control signal, an arithmetic control signal, and an output that are output by the timing control unit after adding a processing delay in the arithmetic unit. It operates based on a control signal.

  Further, according to the present invention, each of the components includes an input interface unit that captures, temporarily holds, and outputs an input signal, a storage unit that holds the parameter set by the control unit, and the input interface unit. Processing the data input via the function assigned by the parameters held in the storage unit, and output to the outside, the input interface unit, or the calculation unit, The timing control unit operates based on an input control signal, a calculation control signal, and an output control signal that are output with a processing delay added in the calculation unit.

  Further, according to the present invention, each of the components includes a storage unit that holds the parameter set by the control unit, and an operation that takes in an input signal and processes the function assigned by the parameter held in the storage unit And an output interface unit that temporarily holds data output from the calculation unit and outputs the data to the outside. The calculation unit or the output interface unit includes the timing control unit. An operation is performed based on an input control signal, an arithmetic control signal, and an output control signal that are output with a processing delay added in the arithmetic unit.

  Further, according to the present invention, the input interface unit temporarily stores input data and outputs an RAM, and an input address for generating an input address for designating a memory area in which the data is input to the RAM A generation unit, and an output address generation unit that generates an output address for designating a memory area in which data output from the RAM is stored, the input address generation unit, the output address generation unit Is characterized in that the timing control unit operates based on an input control signal and a calculation control signal output by adding a processing delay in the calculation unit.

  Further, according to the present invention, the output interface unit temporarily stores input data and outputs an RAM, and an input address for generating an input address for designating a memory area in which the data is input to the RAM A generation unit, and an output address generation unit that generates an output address for designating a memory area in which data output from the RAM is stored, the input address generation unit, the output address generation unit Is characterized in that the timing control unit operates on the basis of a calculation control signal and an output control signal output with the processing delay added in the calculation unit.

  In addition, the present invention provides a component group that is a set of components that are functional blocks having a specific function, and a storage unit that stores parameters including operation conditions of each component of the component group and connection information between the components. A control unit that sets a parameter including an operation condition and connection information between components in each component of the component group, and a clock generation unit that generates a clock that defines the operation of the component group and supplies the clock to each unit An information processing method in an integrated circuit, wherein a timing control unit controls operation timing of the component group.

  Further, according to the present invention, each of the components includes an input interface unit that captures, temporarily holds, and outputs an input signal, a storage unit that holds the parameter set by the control unit, and the input interface unit. A calculation unit that processes data input via the function assigned by the parameter held in the storage unit, and an output interface unit that temporarily holds data output from the calculation unit and outputs the data to the outside And the input interface unit, the arithmetic unit, or the output interface unit includes an input control signal, an arithmetic control signal, and an output that are output by the timing control unit after adding a processing delay in the arithmetic unit. It operates based on a control signal.

  Further, according to the present invention, each of the components includes an input interface unit that captures, temporarily holds, and outputs an input signal, a storage unit that holds the parameter set by the control unit, and the input interface unit. Processing the data input via the function assigned by the parameters held in the storage unit, and output to the outside, the input interface unit, or the calculation unit, The timing control unit operates based on an input control signal, a calculation control signal, and an output control signal that are output with a processing delay added in the calculation unit.

  Further, according to the present invention, each of the components includes a storage unit that holds the parameter set by the control unit, and an operation that takes in an input signal and processes the function assigned by the parameter held in the storage unit And an output interface unit that temporarily holds data output from the calculation unit and outputs the data to the outside. The calculation unit or the output interface unit includes the timing control unit. An operation is performed based on an input control signal, an arithmetic control signal, and an output control signal that are output with a processing delay added in the arithmetic unit.

  Further, according to the present invention, the input interface unit temporarily stores input data and outputs an RAM, and an input address for generating an input address for designating a memory area in which the data is input to the RAM A generation unit, and an output address generation unit that generates an output address for designating a memory area in which data output from the RAM is stored, the input address generation unit, the output address generation unit Is characterized in that the timing control unit operates based on an input control signal and a calculation control signal output by adding a processing delay in the calculation unit.

  Further, according to the present invention, the output interface unit temporarily stores input data and outputs an RAM, and an input address for generating an input address for designating a memory area in which the data is input to the RAM A generation unit, and an output address generation unit that generates an output address for designating a memory area in which data output from the RAM is stored, the input address generation unit, the output address generation unit Is characterized in that the timing control unit operates on the basis of a calculation control signal and an output control signal output with the processing delay added in the calculation unit.

As described above, according to the present invention, a component group that is a set of components that are functional blocks having a specific function, and parameters including operation conditions of each component of the component group and connection information between components are stored. A storage unit, a control unit that sets parameters including operation conditions and connection information between components in each component of the component group, a clock generation unit that generates a clock that defines the operation of the component group, and supplies the clock to each unit And a timing control unit for controlling the operation timing of the component group.
Therefore, since the operation timing of each component can be controlled collectively, there is an effect that the system configuration can be changed for a plurality of uses. In addition, since finer synchronization control is realized compared to the past, unnecessary power can be stopped reliably, power consumption can be reduced, and the design period can be shortened by increasing the independence of each component. The effect which can aim at is acquired.

  Hereinafter, the best mode for carrying out the present invention will be described.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a logic integrated circuit 1 according to an embodiment of the present invention. In the figure, the logic integrated circuit 1 according to the present embodiment includes a CPU 100, a component group 102 that is an assembly of components 20 that are functional blocks, a ROM 104, a RAM 106, interface converters 108 and 110, and each unit. And a clock generation circuit (CLK) 112 that generates a clock to be supplied.
The CPU 100 sets, for each component 20, parameters including operation conditions of each component and connection information between components, and performs operation management of each component. The ROM 104 stores various control programs and fixed data. The RAM 106 stores parameters set for each component 20.
The interface converter 108 performs input / output data format conversion processing between the CPU 100 and the outside. The interface converter 110 performs input / output data format conversion processing between the component group 102 and the outside without using the CPU 100.
As shown in FIG. 2, the component group 102 is an aggregate of a plurality of components 20 (for example, A to H) each having a specific function, and the logical connection relationship of these components A to H is determined by the CPU 100. Build multiple types of systems by setting parameters.
As a specific method of using the components in the logic integrated circuit 1, for example, the components A, B, C, and D are logically connected and operated, or the parameters indicating the logical connection state of each component are changed. , A, F, G, D are logically connected.
As described above, by selecting the operation and the connection line from the outside of the component group 102, specifically by the parameters set by the CPU 100, a plurality of types of systems having a plurality of functions and different functions are constructed.

Next, FIG. 3 shows a specific configuration of components constituting the component group in the logic integrated circuit 1 according to the embodiment of the present invention. In the figure, the component 20 includes an input interface (I / F) unit 200, a calculation unit 202, an output interface unit 204, a control unit 206, and a parameter storage RAM 208. The input side and the output side are clearly distinguished. Has been.
The bus connected to the CPU 100 in FIG. 1 is connected to the parameter storage RAM 208, and the CPU 100 executes reading and writing with respect to the parameter storage RAM 208. Then, when the CPU 100 sets a parameter in the parameter storage RAM 208, the component 20 selects a function.

FIG. 4 shows the configuration of the input interface (I / F) unit 200 inside the component 20 shown in FIG. The input interface unit 200 includes a RAM 2000, an input address generator 2001, an output address generator 2002, and a timing control unit 2003. The RAM 2000 may be a dual port RAM. The input data is temporarily stored in the RAM 2000 so that it can be input into the component 20.
The input address generator 2001 and the output address generator 2002 set the number of addresses by parameter setting from the CPU 100. The timing control unit 2003 generates an input / output address based on an external control signal and a command from the control unit 206 inside the component 20, and inputs data and outputs data inside the component 20.

FIG. 5 shows the configuration of the output interface unit 204 inside the component 20. The output interface unit 204 includes a RAM 2040, an input address generator 2041, an output address generator 2042, and a timing control unit 2043. The RAM 2040 may be a dual port RAM. Data from inside the component 20 is temporarily stored in the RAM 2040 so that it can be output to the outside of the component 20.
The input address generator 2041 and the output address generator 2042 set the number of addresses according to parameter settings from the CPU 100.
The timing control unit 2043 generates an input / output address based on a control signal from the outside of the component 20 and a command from the control unit 206 inside the component 20, inputs data from the inside of the component 20, and outputs data to the outside of the component 20 I do.

FIG. 6 shows an example of instruction flow of the external input, the input interface (I / F) unit 200, the output interface (I / F) unit 204, the external output, and the control unit 206 inside the component 20. In the figure, a circle indicates a command from the control unit 206. The control unit 206 controls the flow shown in FIG.
In FIG. 4, first, the control unit 206 issues an input permission command to the input interface unit 200. The input interface (I / F) unit 200 indicates permission upon receiving an external write request signal. However, when input is not permitted, the input interface (I / F) unit 200 does not return a confirmation message ACK to the outside.
When the confirmation message ACK is returned to the outside, data is sent from the outside to the input interface (I / F) unit 200 together with the write address reset signal.
In the input interface unit 200, the input address generator 2001 is reset by a write address reset signal and written to the RAM 2000. When the predetermined number of data is written in the RAM 2000, the control unit 206 issues an input non-permission command to the input interface unit 200.

Next, the control unit 206 sends an output command to the RAM 2000 in the input interface unit 200, and outputs data from the RAM 2000 of the input interface unit 200 to the arithmetic unit 202 using the output address generator 2002. The arithmetic unit 202 processes the data, and the processed data reaches the RAM 2040 of the output interface unit 204 with a predetermined delay time.
The control unit 206 issues an input command to the output interface unit 204 so that the arrival time of the data matches, operates the output address generator 2002 in the input interface unit 200, and inputs the input command to the RAM 2040 of the output interface unit 204. .
When the predetermined number of data is written in the RAM 2040 of the output interface unit 204, the control unit 206 sends an input stop command to the output interface unit 204.

Next, the control unit 206 sends an output command to the outside to the RAM 2040 of the output interface unit 204. The output interface unit 204 sends an output request signal to the outside, and waits until a confirmation message ACK is returned from the outside.
If the confirmation message ACK is returned from the outside, an output address reset signal is output to the output address generator 2042 to reset the output address.
Then, the output address generator 2042 is used to output data to the RAM 2040 of the output interface unit 204. When the predetermined number of data is output from the RAM 2040, the control unit 206 sends an output stop command to the output interface unit 204.
External input / output is connected by components having the same configuration. As described above, the logic integrated circuit 1 operates.

As described above, the logic integrated circuit 1 according to the present embodiment includes the component group 102 that is a set of components that are functional blocks having specific functions, the operating conditions of each component in the component group 102, and the connection information between the components. The CPU 106 that stores parameters including parameters, the CPU 100 that sets parameters including operation conditions and connection information between components in each component of the component group 102, and a clock that defines the operation of the component group 102 are generated and supplied to each unit. In the logic integrated circuit including the clock generation unit 112, the control unit 206 and the timing control units 2003 and 2043 are provided in each component, and each unit executes synchronous control based on the control signal.
Therefore, the effect that the system configuration can be changed for a plurality of uses is obtained. In addition, since finer synchronization control is realized compared to the past, unnecessary power can be stopped reliably, power consumption can be reduced, and the design period can be shortened by increasing the independence of each component. The effect which can aim at is acquired.

Next, another embodiment of the logic integrated circuit 1 of the present invention will be described.
FIG. 7 shows the component group 102 of this embodiment. In the present embodiment, a timing control unit 2063 is provided in addition to the components (for example, A to H). The timing control unit 2063 controls the timing of all components at once.
FIG. 8 shows the inside of each component 20 of this embodiment. Compared with the components shown in FIG. 2 described above, the control unit 206 is omitted in each component 20 shown in FIG. 8, and the control signal of each component is supplied from the timing control unit 2063.
That is, the input interface unit 200 takes in data from the outside (other components, etc.) at the timing when the input control signal output from the timing control unit 2063 provided outside the component 20 is input, and the arithmetic control signal is input. The data is output to the calculation unit 202 at the timing.
The calculation unit 202 executes processing by the function set in the parameter storage RAM 208 at the timing when the calculation control signal supplied from the timing control unit 2063 is input.
The output interface 204 takes in the processed data from the calculation unit 202 at the timing when the calculation control signal output from the timing control unit 2063 is input, and externally (at other components, etc.) at the timing when the output control signal is input. Output data to.

Similarly, FIG. 9 is a modification of the component 20 of this embodiment. Compared with the component 20 shown in FIG. 8, the output interface unit 204 is omitted in the modification.
That is, the input interface unit 200 is externally provided at the timing when the input control signal output from the timing control unit 2063 provided outside the component 20 is input, as in the case of the component 20 illustrated in FIG. The data is taken in, and the data is output to the calculation unit 202 at the timing when the calculation control signal is input.
The calculation unit 202 executes processing by the function set in the parameter storage RAM 208 at the timing when the calculation control signal supplied from the timing control unit 2063 is input, and externally (others) at the timing when the output control signal is input. Data to the component).
Therefore, in this modification, even if the output interface unit 204 is omitted, the same function can be realized, and the delay time of the entire component group 102 can be shortened.

FIG. 10 shows an input interface (I / F) unit 200 in the component 20 of this embodiment. In the present embodiment, as with the control unit 206, the timing control unit 2003 is omitted, a dual-port RAM 3000 is used instead of the RAM 2000, input data is temporarily held, and the arithmetic unit 202 stores the input data. Output. Note that if the processing delay time may be large, a RAM may be substituted.
At this time, an input control signal and an arithmetic control signal are input from the timing control unit 2063 to the dual port RAM 3000 as control signals.
The input address generator 2001 and the output address generator 2002 are configured by, for example, counters. That is, the input address generator 2001 and the output address generator 2002 count the pulses of the input control signal and the arithmetic control signal, count them up, and sequentially output the values as write / read addresses to the dual port RAM 3000.

Similarly, FIG. 11 shows an output interface (I / F) unit 204 in the component 20 of this embodiment. In the present embodiment, as with the input interface (I / F) unit 200, the timing control unit 2043 is omitted, a dual-port RAM 3040 is used instead of the RAM 2040, and processed data from the arithmetic unit 202 is processed. Is input, temporarily held, and output to the outside. Note that if the processing delay time may be large, a RAM may be substituted.
At this time, an arithmetic control signal and an output control signal are input from the timing control unit 2063 to the dual port RAM 3040 as control signals.
Similarly to the input address generator 2001 and the output address generator 2002, the input address generator 2041 and the output address generator 2042 are configured by, for example, counters. That is, the input address generator 2041 and the output address generator 2042 count the pulses of the input control signal and the arithmetic control signal, count them up, and sequentially output the values to the dual port RAM 3040 as write / read addresses.

Hereinafter, various control signals generated by the logic integrated circuit 1 of the present embodiment will be described.
FIG. 12 shows an example of signals from the timing control unit 2063 and the like.
As shown in FIG. 13, it is assumed that there are three components logically connected in the component group 102, one of which is data generation, and the other is that processing 1 and processing 2 are set with parameters. At this time, the data generated by the data generation component is processed by the process 1 component and further processed by the process 2 component. At this time, various control signals for each component are supplied from the timing control unit 2063 as shown in FIG.
This state will be described with reference to FIG. 12. A data generation burst signal and a data generation output control signal are supplied from the timing control unit 2063 to the data generation component. In this example, since data generation is a generation source, only output is performed.
When the communication has a frame structure, the start and length of the frame are necessary information for each component. The burst signal for data generation is a signal that informs the start and length of these frames.
Similarly, the data generation output control signal is a signal for informing the start and stop of the data transmission operation. That is, in the section where this signal is “1”, the data generation component is in the transmission operation mode. At this time, the input control signal of the process 1 is also “1”, and the component of the process 1 is in the reception operation mode. Hereinafter, these communication procedures will be described.

FIG. 15 shows a communication procedure from data generation to processing 1.
As shown in FIG. 16A, a burst signal is supplied from the timing controller 2063 to the data generation component as an output control signal for data generation. However, in FIG. 16A, the burst signal is “1”.
At this time, when the output control signal for data generation becomes “1”, the output address for data generation increases by incrementing by 1 from 0 in the reset state. Data corresponding to the output address is output from the RAM 2040 of the output interface 204 for data generation. The data output at this time is output with a predetermined clock (for example, one clock) delay with respect to the output address.
FIG. 16A shows a case where the number of data output from data generation to process 1 is six. Here, among the addresses 0 to 6, the remaining one address, for example, the last address 6 is not valid data but has meaningless data X inserted therein. Accordingly, D0 to D5 and X are sequentially written in the addresses 0 to 6, but the actual effective output data is D0 to D5.

Then, as illustrated in FIG. 16B, an input control signal for the component of process 1 is supplied from the timing control unit 2063. As shown in FIG. 12, this input control signal matches the output control signal for data generation.
The address generator 2001 of the input I / F part of processing 1 starts with a delay (one clock in FIG. 16B) with respect to the output address of the output data from the rising edge of the input control signal.
Then, in FIG. 16B, the output data is delayed by one clock and the address matches. Then, data is input to the RAM 2000 of the input interface unit 200 in the process 1.
When the output control signal, output address, output data, input control signal, and input address shown in FIGS. 16A and 16B are viewed along the axis of the clock signal shown in FIG. It can be seen that it is executed by supplying a control signal that is one clock longer than the number of data.
That is, the component of the processing 1 on the output side operates at the same time as the control signal becomes “1”, like the data generation component on the input side. Since the output data is delayed by one clock with respect to the start of the input control signal, on the input side, a delay for the output address of the output data from the rising edge of the input control signal (1 clock delay in FIG. 16B) is set in advance. It is configured to input data.

FIG. 17 shows the inside of the component 20 of the process 1.
As shown in FIG. 18A, a burst signal is supplied as a calculation control signal from the timing control unit 2063 to the component of the process 1. However, in FIG. 18A, the burst signal is “1”.
At this time, when the operation control signal of the component of the process 1 becomes “1”, the output address of the input interface unit 200 increases by counting up from 0 in the reset state by one. Then, data corresponding to the output address is output from the RAM 2000 of the input interface unit 200 of the process 1 to the arithmetic unit 202. The data output at this time is output with a predetermined clock (for example, one clock) delay with respect to the output address.
The arithmetic unit 202 processes data input from the input interface unit 200 and stores the data in the RAM 2040 of the output interface unit 204.

At this time, a processing delay occurs in the arithmetic unit 202. Therefore, the timing control unit 2063 extends the calculation control signal in advance by the processing delay time as shown in FIG. FIG. 18B shows an example in which the operation control signal is extended by one clock.
The arithmetic unit 202 receives the arithmetic control signal that has been previously extended by the processing delay time by the timing control unit 2063, processes the data D0 to D5 input from the input interface unit 200, and outputs processed data S0 to S5. The data is output to the interface unit 204.
Since the output interface unit 204 knows in advance the processing delay time in the arithmetic unit 202 (1 clock delay in FIG. 18B), the delay from the rising edge of the arithmetic control signal to the output address of the output data, and the processing delay The input address of the output interface unit 204 is delayed by the amount added to time (1 clock + 1 clock, 2 clocks in total along the clock axis shown in FIG. 18C), and processed data S0 to S5 Is stored in the RAM 2040.
As described above, in the logic integrated circuit 1 of the present embodiment, the timing control unit 2063 stores data from the input interface unit 200 to the output interface unit 204 using a calculation control signal to which a calculation delay is added in advance.

FIG. 19 shows an example in which the output interface unit 204 does not exist in the component 20 of the process 1 corresponding to the modification shown in FIG. 9, that is, in this case. In this case, in order to perform delay adjustment with the input interface unit The timing control unit 2063 uses a control signal that is delayed by a delay time with respect to a component for which the calculation unit 202 outputs processed data.
That is, similarly to the signal processing shown in FIGS. 18A and 18B, the input interface unit 200 inputs the operation control signal shown in FIG. 20A from the timing control unit 2063 and sets the output address by one. Count up, and output data corresponding to the output address to the arithmetic unit 202. The data output at this time is output with a predetermined clock (for example, one clock) delay with respect to the output address.
The calculation unit 202 processes the data input from the input interface unit 200 and outputs it to the next logically connected component.

At this time, as in the case shown in FIG. Therefore, the timing control unit 2063 extends the calculation control signal in advance by the processing delay time, as shown in FIGS.
The arithmetic unit 202 inputs the arithmetic control signal that has been extended by the processing delay time in advance by the timing control unit 2063, processes the data D0 to D5 input from the input interface unit 200, and logically processes the processed data S0 to S5. To the next connected component.
This next component, like the output interface 204, is supplied with a control signal delayed from the timing control unit 2063 by the processing delay time, so that the processing delay time in the arithmetic unit 202 (FIG. 20B) (1 clock delay).
Therefore, in the input control signal shown in FIG. 20C, the next component is the sum of the delay from the rising edge of the operation control signal to the output address of the output data and the processing delay time (FIG. 20D). 2), the input address of the input interface unit 200 is delayed and the processed data S0 to S5 are input.
As described above, in the logic integrated circuit 1 of this embodiment, the timing control unit 2063 performs data transmission / reception between components without using the output interface unit 204 by using the calculation control signal to which the calculation delay is added in advance.

21 and 22 show signal examples when the internal configuration of the component 20 is the same, but the number of input data is different from the number of output data. As shown in FIGS. 22A and 22B, in addition to the input data D0 to D5, the data D2 stored at the output address 2 is processed and output as processed data S6, so that the output data is 1. One has been inserted.
In this case, the input interface unit 200 stops for a time when the output address is to be inserted. FIG. 22A shows an example in which the output address 2 is output to the address bus for one clock longer. The calculation unit 202 inserts the data S6 to be inserted into the data D2 portion (the latter half of the two D2s in FIG. 22A), and processes the processed data S0 through S0 at the input addresses 0 to 6 of the output interface unit 204. S2, S6, S3 to S5 are stored. In this way, the number of output data changes from 6 to 7 with respect to the input data.
As a specific example in which the number of data changes, for example, a pilot signal (48 data channels, 4 pilot channels) in the wireless LAN standard IEEE802.11a can be considered. When the number of pilot channels is added to the data channel 48 to be 52 channels, the configuration shown in FIGS. 21 to 31 corresponds to the case where the number of output data changes with respect to the input data. I can do it.

As described above, since the output interface 204 is supplied with the control signal delayed by the processing delay time from the timing control unit 2063, the processing delay time in the arithmetic unit 202 (in FIG. 22A) (1 clock delay) is known in advance.
Therefore, the output interface 204 is equivalent to the addition of the delay with respect to the output address of the output data and the processing delay time from the rise of the arithmetic control signal (1 clock as viewed along the clock axis shown in FIG. 22C). Processed data S0 to S2, S6, and S3 to S5 are input by delaying the input address.

FIG. 23 shows an example of establishing synchronization for reception in the logic integrated circuit 1 of this embodiment.
For the receiving component, the timing control unit 2063 needs to obtain synchronization information from the received signal. For this reason, as shown in FIG. 23, the logic integrated circuit 1 is provided with means for detecting synchronization from the received signal, and the synchronization detection signal is input to the reception timing control unit. As a result, each component on the receiving side operates.
As an example of the synchronization detection means, IEEE802.11a of the wireless LAN has a preamble signal for synchronization detection, and the synchronization detection is performed by detecting the correlation with this preamble signal.

As described above, according to the logic integrated circuit 1 of the present embodiment, a configuration in which the simplified communication procedure and the collective timing control unit 2063 are integrated into one is adopted.
Therefore, it is possible to reduce the power consumption by suppressing the circuit scale, and to obtain an effect capable of supporting a plurality of uses.

A series of processes related to the data input / output process described above is stored in a computer-readable recording medium in the form of a program, and the above process is performed by the computer reading and executing the program.
That is, each processing means and processing unit in the logic integrated circuit 1 is executed by a central processing unit such as a CPU reading the above program into a main storage device such as a ROM or RAM and executing information processing / calculation processing. Is realized.
Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

1 is a configuration diagram of a logic integrated circuit 1. FIG. 2 is a configuration diagram of a component group 102. FIG. FIG. 1 is a configuration diagram of an input interface unit 200. FIG. The block diagram of the output interface part 204. FIG. 7 is an instruction flowchart of an external input, an input interface (I / F) unit 200, an output interface (I / F) unit 204, an external output, and a control unit 206 inside the component 20. The block diagram of the component group 102 which provided the timing control part 2063. FIG. The block diagram of the component 20 controlled by the timing control part 2063. FIG. A modification of the component 20. The block diagram of the input interface part 200 controlled by the timing control part 2063. FIG. The block diagram of the output interface part 204 controlled by the timing control part 2063. FIG. 7 is a control signal example output by the timing control unit 2063. The figure which shows the connection relation of each component. The figure which shows the timing control part 2063. FIG. The figure which shows a mode that data are output to the component of the process 1 from the component of data generation. The figure which shows the delay between an output control signal, an output address, output data, an input control signal, the delay between input addresses, and its clock timing. The figure which shows the component 20 inside of the process 1. FIG. The figure which shows the arithmetic control signal, the output address, the delay between output data, the arithmetic control signal, the delay (processing delay) between input addresses, and its clock timing. The figure which shows the connection relation of the component 20 of the process 1 which abbreviate | omitted the output interface 204, and the component of an output destination. The figure which shows the operation control signal, the output address, the delay between the output data, the operation control signal, the delay between the input addresses (processing delay), the input control signal and the input address of the output destination component delayed by the processing delay, and the clock timing thereof. . The figure which shows the component 20 inside of the process 1. FIG. The figure which shows the arithmetic control signal, the output address, the delay between output data, the arithmetic control signal, the delay (processing delay) between input addresses, and its clock timing. 2 is a diagram showing an example of establishment of synchronization for reception in the logic integrated circuit 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Logic integrated circuit 100 ... CPU (control means)
102: Component group 104: ROM
106 ... RAM (storage means)
108, 110 ... interface converter 112 ... clock generation circuit (clock generation unit)
DESCRIPTION OF SYMBOLS 20 ... Component 200 ... Input interface (I / F) part 202 ... Core part 204 ... Output interface (I / F) part 206 ... Control part 208 ... RAM for parameter storage

Claims (12)

A component group that is a set of components that are functional blocks having specific functions;
A storage unit storing parameters including operation conditions of each component of the component group and connection information between the components;
A control unit configured to set parameters including operation conditions and connection information between components in each component of the component group;
A clock generation unit that generates a clock that defines the operation of the component group, and supplies the clock to each unit;
And a timing control unit that controls operation timing of the component group. Each of the components is
An input interface unit that captures, temporarily holds and outputs an input signal; and
A storage unit for holding the parameters set by the control unit;
An arithmetic unit that processes data input through the input interface unit by a function assigned by the parameter held in the storage unit;
An output interface unit that temporarily holds data output from the arithmetic unit and outputs the data to the outside;
The input interface unit, the calculation unit, or the output interface unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit after adding a processing delay in the calculation unit. The logic integrated circuit according to claim 1. Each of the components is
An input interface unit that captures, temporarily holds and outputs an input signal; and
A storage unit for holding the parameters set by the control unit;
A processing unit that processes data input through the input interface unit by a function assigned by the parameter held in the storage unit and outputs the processed data to the outside.
The input interface unit or the calculation unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit after adding a processing delay in the calculation unit. The logic integrated circuit according to claim 1. Each of the components is
A storage unit for holding the parameters set by the control unit;
An arithmetic unit that takes in an input signal and processes it according to a function assigned by the parameter held in the storage unit;
An output interface unit that temporarily holds data output from the arithmetic unit and outputs the data to the outside;
The calculation unit or the output interface unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit with a processing delay added in the calculation unit. The logic integrated circuit according to claim 1. The input interface unit
RAM that temporarily stores and outputs input data;
An input address generation unit for generating an input address for designating a memory area in which data is input to the RAM;
An output address generation unit for generating an output address for designating a memory area in which data output from the RAM is stored;
The input address generation unit and the output address generation unit operate based on an input control signal and a calculation control signal output by the timing control unit after adding a processing delay in the calculation unit. The logic integrated circuit according to claim 4. The output interface unit is
RAM that temporarily stores and outputs input data;
An input address generation unit for generating an input address for designating a memory area in which data is input to the RAM;
An output address generation unit for generating an output address for designating a memory area in which data output from the RAM is stored;
2. The input address generation unit and the output address generation unit operate based on an operation control signal and an output control signal output by the timing control unit after adding a processing delay in the operation unit. The logic integrated circuit according to claim 4. A component group that is a set of components that are functional blocks having a specific function; a storage unit that stores operation conditions of each component of the component group and connection information between the components; and each of the component group An information processing method in a logic integrated circuit, comprising: a control unit that sets parameters including operation conditions and connection information between components in a component; and a clock generation unit that generates a clock that defines the operation of the component group and supplies the clock to each unit Because
An information processing method, wherein a timing control unit controls operation timing of the component group. Each component captures, temporarily holds and outputs an input signal, a storage unit that holds the parameter set by the control unit, and data input via the input interface unit A calculation unit that processes the function assigned by the parameter held in the storage unit, and an output interface unit that temporarily holds data output from the calculation unit and outputs the data to the outside ,
The input interface unit, the calculation unit, or the output interface unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit after adding a processing delay in the calculation unit. The information processing method according to claim 7. Each component captures, temporarily holds and outputs an input signal, a storage unit that holds the parameter set by the control unit, and data input via the input interface unit An arithmetic unit that processes the function assigned by the parameter held in the storage unit and outputs the processed data to the outside,
The input interface unit or the calculation unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit after adding a processing delay in the calculation unit. The information processing method according to claim 7. Each of the components includes a storage unit that holds the parameter set by the control unit, an arithmetic unit that takes in an input signal and processes the function according to the function assigned by the parameter held in the storage unit, and the arithmetic unit An output interface unit that temporarily holds data output from the device and outputs the data to the outside.
The calculation unit or the output interface unit operates based on an input control signal, a calculation control signal, and an output control signal output by the timing control unit with a processing delay added in the calculation unit. The information processing method according to claim 7. The input interface unit temporarily stores input data and outputs a RAM;
An input address generation unit that generates an input address for designating a memory area in which data is input to the RAM, and an output address for designating a memory area in which data output from the RAM is stored An output address generation unit,
The input address generation unit and the output address generation unit operate based on an input control signal and a calculation control signal output by the timing control unit after adding a processing delay in the calculation unit. The information processing method according to claim 10. The output interface unit temporarily stores and outputs input data, an input address generation unit that generates an input address for designating a memory area in which data is input to the RAM, and the RAM And an output address generation unit for generating an output address for designating a memory area in which data output from is stored,
8. The input address generation unit and the output address generation unit operate based on a calculation control signal and an output control signal output by the timing control unit after adding a processing delay in the calculation unit. The information processing method according to claim 10.

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