JP2005080077A - Image reproducing device and frame memory control method of image reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image reproducing device in which a signal processing circuit block is separated from the display output processing circuit block and capable of performing smooth image reproduction without a sense of incongruity such as a boundary line even when storage capacity and throughput of a frame memory to be used by every circuit are restricted. <P>SOLUTION: The image reproducing device is provided with an image decoding part 2 which outputs decoding completion information at the time of decoding completion of encoded image data, a frame memory 3, an image output part 4 which sets a reading starting address by input of the decoding completion information, outputs writing prohibition information with writing permission information, reads the decoded image data at the time of input of an image reproduction request and output the decoded image data based on vertical/horizontal synchronizing signals to be inputted, a graphic memory which stores graphic data, a display data output part 6 which outputs the vertical/horizontal synchronizing signal to an image output part, compounds the graphic data to the decoded image data by every frame to be inputted from the image output part and outputs the resultant data and a display part 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image reproducing apparatus that decodes encoded image data and displays and outputs image data reproduced for each frame, and more particularly to processing for storing decoded image data in a frame memory and image data from the frame memory. Is related to the process of reading and outputting.

  A conventional image reproducing apparatus is an image data obtained by encoding a television broadcast image taken from a video input terminal or the like or a video image taken by a small camera using an encoding means such as MPEG4, for example, an SD card or a memory. The recorded television broadcast image and video image can be reproduced by temporarily recording on a recording medium such as a stick and recording, reading out the encoded image data from the recording medium, decoding and displaying it.

  Since the conventional image reproducing apparatus has a frame memory having a capacity sufficient to store a large number of frames of image data, the decoded image data obtained by decoding the encoded image data is temporarily stored in the frame memory for a plurality of frames. By reading out the decoded image data in accordance with the time stamp included in the encoded image data, smooth image reproduction without frame delay or frame advance during reproduction is performed. Here, the frame delay means that the decoding process is slow or the subsequent output process is slow, so that the image is reproduced later than the time stamp. The frame advance means that the decoding process is fast. This indicates a state where the memory is overwritten or overflowed when trying to keep the time stamp.

  As a frame memory control technique for switching an output image for each image frame, there is a technique for suppressing unnaturalness of an image accompanying error concealment at the time of decoding, for example, when the number of error processing blocks exceeds a certain threshold value, Memory output is stopped and still images are output. Conversely, when the value falls below the threshold value, the memory output is updated and moving images are output. Depending on the error rate, either the moving image display or still image display with the higher image quality is displayed. There is known an image decoding apparatus in which is selected and an image that is favorable for a viewer can be reproduced. (For example, refer to Patent Document 1.)

Japanese Patent Laid-Open No. 2003-116136 (pages 4-6, FIG. 1)

  However, in a device such as a mobile phone or PDA (Personal Digital Assistant) whose outer dimensions and power consumption are limited, the decoding processing circuit block and the display output processing circuit block may have a separated hardware configuration. In many cases, the storage capacity of a memory that can be used for each decoding processing circuit and display output processing circuit is limited, and the processing capability is also limited. In this case, there is a problem that it is difficult to perform smooth image reproduction without frame delay or frame advance during reproduction as described above.

  The present invention has been made to solve the above-described problem, and the decoding processing circuit block and the display output processing circuit block are separated, and the storage capacity of the frame memory used for each of the decoding processing circuit and the display output processing circuit. Even when the processing capability is limited, the frame memory used for the decoding process of encoded image data and the output process of decoded image data is efficiently used, and there is no frame delay or frame advance during playback. An object of the present invention is to provide a method that can reproduce images smoothly.

  In order to achieve the above object, an image reproduction apparatus of the present invention includes a control unit that performs a decoding process control that outputs a decoding process request for encoded image data, and an output process control that outputs an image reproduction request for decoded image data; In response to a decoding processing request from the unit, the encoded image data is decoded to generate decoded image data for each frame, and each time decoding is completed, an image decoding unit that outputs decoding completion information, and the decoded image data It has a storage area for storing the number of frames and sets a frame memory for storing decoded image data for each frame, and a read start address for reading readable decoded image data from the frame memory by inputting decoding completion information In addition, information prohibiting writing to the storage area corresponding to the decoded image data in the unoutput state or the hold state Based on the input vertical / horizontal synchronization signal when an image reproduction request from the control unit is input, which is output together with information permitting writing to the storage area corresponding to the decoded image data in the discardable state. An image output unit that reads out and outputs one frame of decoded image data set as a read start address from the frame memory, and generates a vertical / horizontal synchronization signal for outputting the image data from the image output unit in accordance with the display means A display data output unit.

  Further, in the frame memory control method of the image reproducing device of the present invention, the image decoding unit decodes the encoded image data to generate decoded image data for each frame, stores the decoded image data in the frame memory for each frame, When an image reproduction request is input, the image output unit reads out the decoded image data for each frame from the frame memory for each frame and outputs it to the display data output unit. The display data output unit from the image output unit in accordance with the display means A frame memory control method of an image reproducing device for generating a vertical / horizontal synchronization signal for output, and when decoding an image by an image decoding unit, decoding completion information every time decoded image data is generated for each frame The image output unit reads the decoded image data that can be read out from the frame memory by inputting the decoding completion information. Information for prohibiting writing to the storage area corresponding to the decoded image data in the non-output state or holding state is written to the storage area corresponding to the decoded image data in the discardable state. When the image reproduction request is input from the control unit, the decoded image data set as the read start address is read from the frame memory based on the input vertical / horizontal synchronization signal. Frames are read and output, and the display data output unit outputs a vertical / horizontal synchronization signal for displaying image data to the image output unit.

  In the present invention, when an image is decoded by an image decoding unit, decoding completion information is output every time decoded image data is generated for each frame, and the image output unit stores a storage area of a frame memory corresponding to the decoding completion information A read start address is set, and write prohibition to the storage area is output together with information on the storage area to which writing is permitted. When an image reproduction request is input, the decoded image data for each frame is read from the frame memory for each frame. The display data output unit outputs the vertical / horizontal synchronization signal for displaying the image data to the image output unit. For example, the decoding processing circuit block and the display output process Even if the circuit block is separated and the frame memory has a small storage capacity such as 3 frames, frame delay or Because only it is possible that there is no smooth image playback, smooth and excellent display output is made possible. In addition, since the image decoding unit and the image output unit operate independently, the use of the frame memory is communicated by the handshake method to decode and display the image, so that the frame memory can be used efficiently and wasted. Thus, the decoded image data can be reproduced.

Embodiment 1 FIG.
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
FIG. 1 is a block diagram showing a schematic configuration of an image reproduction apparatus according to Embodiment 1 of the present invention.
The control unit 1 is a circuit capable of controlling other circuit units such as a microprocessor, a CPU (central processing unit), a DSP (digital signal processing unit), and the like. By transmitting and receiving various types of information and control signals, the encoded image data is decoded and combined with pre-input graphic data for display. The image decoding unit 2 is connected to the control unit 1, the frame memory 3, and the image output unit 4. The image decoding unit 2 is input with encoded data of an image encoded according to a standard such as MPEG4 or H263, and the encoded image data is transmitted for each frame. And the decoding completion information is output each time the decoding is completed.

  The frame memory 3 is connected to the image decoding unit 2 and the image output unit 4, has a capacity for a predetermined number of frames of decoded image data, and is decoded image data in units of frames (hereinafter referred to as “decoded image data”) decoded by the image decoding unit 2. (Also referred to as frame data) is stored for each frame, and the stored frame data is output by a memory control signal including a read start address. The image output unit 4 is connected to the control unit 1, the image decoding unit 2, the frame memory 3, and the LCD (liquid crystal display) output unit 6, and is a circuit that reads out and outputs the decoded image data stored in the frame memory 3. In response to the input of the decoding completion information from the image decoding unit 2, a read start address for reading the decoded image data from the frame memory 3 is set, and writing to a storage area for one frame from the read start address in the frame memory 3 is performed. When the image reproduction request from the control unit 1 is input, the decoded image data (frame data) for each frame is output from the frame memory 3 to the frame. Each frame is read and output as display frame data based on the input vertical / horizontal synchronization signal.

  The graphic memory 5 is connected to the control unit 1 and the LCD data output unit 6 and stores graphic data input in advance by an input unit (not shown) or the like for synthesis with the decoded image data. The LCD data output unit (display data output unit) 6 is connected to the control unit 1, the image output unit 4, the graphic memory 5, and the LCD data display unit 7, and based on the frame synchronization signal input from the LCD data display unit 7. A vertical / horizontal synchronizing signal for displaying image data is generated and output to the image output unit 4, and the graphic data read from the graphic memory 5 is combined with the decoded image data for each frame input from the image output unit 4. Then, the combined display data is output to the LCD data display unit 7 as LCD data (display data) for forming an LCD image.

  The LCD data display unit (display unit) 7 is a liquid crystal panel unit that displays an image based on the LCD data output from the LCD data output unit 6, and is a display unit using liquid crystal, and therefore is based on the refresh timing of the liquid crystal. Output frame sync signal. The audio decoding unit 8 is connected to the control unit 1 and the audio output unit 9 and receives encoded audio data encoded according to standards such as MPEG4 and H263, and decodes the encoded audio data into decoded audio data. . The audio output unit 9 is connected to the audio decoding unit 8 and is an audio output unit such as a speaker that outputs decoded audio.

  When the frame memory 3 includes a plurality of frame buffers, the decoding completion information output from the image decoding unit 2 includes frame buffer number information that can be displayed and output. When there is a possible frame buffer, the decoded image data stored by the memory control signal including the read start address of the display output capable frame buffer is read out and output, and the prohibition of writing in the frame memory 3 and the permitted storage area The information includes a writable frame buffer number, and the image decoding unit 2 executes image decoding processing when there is a writable frame buffer.

  When the image playback request is a normal playback request and there is a display output capable frame buffer, the image output unit 4 sets the read start address of the decoded image data to the next time each time the normal playback request is input. When the image playback request is an interlaced playback request and there are a plurality of display output-capable frame buffers, the decoded image data is read out every time an interlaced playback request is input. The start address is updated to the head of the frame buffer in the order advanced by the number of skipped frames.

  When the frame memory 3 is composed of a plurality of frame buffers, the frame buffer is composed of a frame buffer having a storage capacity capable of storing decoded image data of at least three reproduction image sizes. Thus, the writing and reading of the decoded image data are controlled cyclically.

  The operation in which the image decoding unit 2 writes the decoded image data into the frame memory 3 and the operation in which the image output unit 4 reads the decoded image data from the frame memory 3 are performed independently of each other. Is used, the decoding completion information and the memory write prohibition / permission information are communicated between the image decoding unit 2 and the image output unit 4 by the handshake method, so that the next decoded image data in the area before reading is transmitted. It manages writing prohibition and reading from the area where the decoded image data is written.

  The image output unit 4 receives the decoded image data from the frame buffer capable of display output when there is a frame buffer capable of display output and when an image reproduction request is input from the control unit 1 after the decoding completion information is input. Before reading, a display ready signal indicating that an image can be output to the display unit is output. The display data output unit 6 generates a vertical / horizontal synchronization signal based on the input of the frame synchronization signal in response to the display ready signal and outputs it to the image output unit 4, thereby obtaining display data for liquid crystal and LCD data. Output to the display unit 7.

  When the graphic data in the graphic memory 5 is updated, the LCD data output unit 6 outputs a re-output request signal to the image output unit 4. When the re-output request signal is input, the image output unit 4 reads out the decoded image data of the requested frame from the frame memory 3 and outputs it to the LCD data output unit 6.

FIG. 2 is a block diagram showing an internal configuration of the image output unit 4 of FIG.
The input terminal 40 is a terminal that receives a pixel clock for reading decoded image data (frame data) from the LCD data output unit 6 or is output from a clock oscillation unit (not shown) in the image output unit 4. is there. The input terminal 41 is a terminal to which a vertical synchronization signal for reading frame data is input from the LCD data output unit 6. The input terminal 42 is a terminal to which a horizontal synchronization signal for reading frame data is input from the LCD data output unit 6. The input terminal 43 is a terminal to which a control signal for setting display image parameters such as the number of horizontal pixels and the number of vertical pixels is input from the control unit 1.

  The line number counter 44 is a counter that counts the number of lines of frame data. The horizontal pixel number counter 45 is a counter that counts the number of horizontal pixels of the frame data.

  The input terminal 46 is a terminal to which decoding completion information indicating that decoded image data for an arbitrary frame has been output from the image decoding unit 2 to the frame memory 3 is input from the image decoding unit 2.

  The memory read control unit 47 controls reading of frame data from the frame memory 3. The all reading start address storage unit 47 b in the memory reading control unit 47 stores the entire reading start address for each frame in the frame memory 3. The read start address storage unit 47a stores the read start address of the frame data corresponding to the decoding completion information.

  The output terminal 48 is information about writing prohibition to an unread area after the decoded image data is written in the frame memory 3 and writing permission to an area before the decoded image data is written or after the decoded image data is read. A terminal for outputting certain memory write prohibition / permission information. The output terminal 49 is a terminal that outputs a memory control signal for reading frame data from the frame memory 3. The input terminal 50 is a terminal to which frame data read from the frame memory 3 is input.

  The output terminal 51 is a terminal that outputs to the LCD data output unit 6 a display ready signal indicating that the frame data corresponding to the decoding completion information is ready for display. The output terminal 52 is a terminal through which frame data read from the frame memory 3 is output to the LCD data output unit 6. The input terminal 53 is a terminal to which a re-output request signal such as when graphic data is updated is input from the LCD data output unit 6.

FIG. 3 is a flowchart showing a schematic operation flow of the image decoding unit 2.
First, the image decoding unit 2 determines whether or not a control signal for requesting initialization is input from the control unit 1 (S1). If a request is input (S1: YES), the image decoding unit 2 Initialization is performed to set the various setting values of (1) to initial values (S2), and the process returns to step S1. When there is no initialization request (S1: NO), it is determined whether or not a control signal for requesting a decoding process is input from the control unit 1 (S3), and when there is no decoding process request (S3: NO). Returns to step S1. If a decoding process request is input (S3: YES), whether or not decoding completion information for indicating that the corresponding encoded image data has been decoded and stored in the frame memory 3 is an initial value. Whether the decoding completion information is not the initial value (S4: NO), the decoding completion information is reset to the initial value (S5).

  When the decoding completion information is the initial value (S4: YES) and when the decoding completion information is reset to the initial value (S5), the image decoding unit 2 adds the encoded image data input according to the decoding processing request. Decoding processing is performed for the decoded image data, and the decoded image data is output to a storage area (frame buffer) at a predetermined address in the frame memory 3 (S6). In addition, the decoding process in step S6 is performed and it is determined whether or not the decoding process is completed (S7). If the decoding process is not completed (S7: NO), the process returns to step S6. When the decoding process is completed (S7: YES), decoding completion information is output to the image output unit 4 (S8). Thereafter, it is determined whether or not the data requested for the decryption process has ended (S9). If the data does not end (S9: NO), the process returns to step S4, and if the data ends (S9: YES). End the process.

  Whether or not the decoding completion information in step S4 is an initial value may be determined, for example, by storing the initial value and comparing it with the current value, or decoded image data. If the numerical value of the order of the decoded image data stored after initialization is smaller than the numerical value of the storage area based on the numerical value of the storage area (frame buffer) of the frame memory 3 in which the Use, that is, an initial value may be determined.

FIG. 4 is a flowchart showing a schematic operation flow of the image output unit 4.
First, the image output unit 4 determines whether or not a control signal requesting initialization is input from the control unit 1 (S11). If a request is input (S11: YES), the image output unit 4 Initialization is performed to set the various setting values of (1) to initial values (S12), and the process returns to step S11. If there is no initialization request (S11: NO), it is determined whether or not decoding completion information is input from the image decoding unit 2 (S13). If there is no decoding completion information (S13: NO), step S11 is performed. Return to. When the decoding completion information is input (S13: YES), the content of the decoding completion information, the numerical value of the decoding completion information after initialization, and the start of reading out the corresponding frame data by the all reading start address storage unit 47b, etc. Address write information is acquired (S14), and writing to the storage area of the read start address is prohibited, and memory write prohibition / permission information that permits writing for areas that have been read in other storage areas Is output to the image decoding unit 2 (S15).

  The image output unit 4 determines whether or not a control signal requesting reproduction of image data (frame data) from the control unit 1 has been input (S16). If there is no reproduction request (S16: NO), the image output unit 4 again. When the determination in step S16 is repeated and there is a reproduction request (S16: YES), the read start address is stored and set in the read start address storage unit 47a (S17), and output of decoded image data to be displayed is ready for output. A display ready signal indicating this is output to the LCD data output unit 6 (S18), and the memory write inhibition / permission information is updated (S19).

  The image output unit 4 determines whether or not the vertical / horizontal synchronization signal is input from the LCD data output unit 6 (S20). If the synchronization signal is not input (S20: NO), the determination in step S20 is performed again. When the synchronization signal is input (S20: YES), the decoded image data (frame data) is read from the storage area (frame buffer) corresponding to the read start address in the frame memory 3, and the frame data is displayed on the LCD. The data is output to the LCD data output unit 6 as display frame data in accordance with the vertical / horizontal synchronization signal input from the data output unit 6 (S21). Thereafter, it is determined whether or not the data requested for reproduction has ended (S22). If the data does not end (S22: NO), the process returns to step S21, and if the data ends (S22: YES), the process is performed. Exit. In addition, what is necessary is just to implement the process after step S18 with respect to the re-output request signal from the LCD data output part 6, for example.

FIG. 5 is a timing chart showing an example of the relationship between the vertical / horizontal synchronization signal input from the LCD data output unit 6 to the image output unit 4 and the frame data output from the image output unit 4.
5 is input from the LCD data output unit 6 to the image output unit 4 at every vertical synchronization signal interval Tvss. The horizontal synchronization signal shown in the (n) row in FIG. 5 is output with a delay from the first vertical synchronization signal in the (m) row to the horizontal synchronization signal head position Phsst. The horizontal synchronization signal is input or set every horizontal synchronization signal interval Thss. Each effective pixel of the frame data shown in the row (o) of FIG. 5 is the first horizontal effective pixel that is delayed from the horizontal effective pixel head position Pept with respect to the horizontal synchronizing signal of the row (n) of FIG. The output is output for several Nheps, and thereafter, the frame data for the horizontal effective pixel number Nhep is output every horizontal synchronization interval Thss until the vertical effective line number Nvel is reached.

  In the row (m) of FIG. 5, when the vertical synchronization signal interval Tvss elapses and the next vertical synchronization signal is input to the image output unit 4, the horizontal synchronization signal shown in the row (n) of FIG. Are input or set, and each effective pixel of the frame data shown in the row (o) of FIG. Note that the timing of each signal and the method for defining the signal timing shown in FIGS. 5 (m) to 5 (o) are not limited to this, and it is sufficient that the frame data is output triggered by the synchronization signal. For example, the signal polarities shown in FIGS. 5 (m) to (o) may be reversed, and there may be dummy signals in each synchronization signal and dummy data in the frame data.

The overall operation of the image reproduction apparatus according to the first embodiment shown in FIG. 1 will be described below with reference to FIGS.
The encoded image data is input to the image decoding unit 2 from a memory or another device via a CPU bus or a dedicated bus. The image decoding unit 2 performs a decoding process according to the image encoding method of the input encoded image data according to the control signal from the control unit 1, stores the decoded image data in the frame memory 3, and stores the decoding completion information. In addition to outputting to the image output unit 4, the decoding information is output to the control unit 1. Decoding information includes the number of horizontal pixels and the number of vertical pixels.

  In the image output unit 4, based on the decoding completion information input from the image decoding unit 2 via the input terminal 46, the memory read control unit 47 sets the read start address of the decoded image data from the frame memory 3. The memory write prohibition / permission information is updated and output to the image decoding unit 2 via the output terminal 48. Further, the normal reproduction request and the interlaced reproduction request are input as control signals from the control unit 1 to the memory read control unit 47 via the input terminal 43, and an image to be displayed and updated on the LCD data output unit 6 is displayed. A display ready signal notifying that the device has been prepared is output via the output terminal 51.

  When receiving the display ready signal from the image output unit 4, the LCD data output unit 6 receives a frame synchronization signal indicating the refresh timing of the LCD output from the LCD data display unit 7, and internally generates a vertical synchronization signal / horizontal synchronization signal. Is output to the image output unit 4. The vertical sync signal start position from the frame sync signal, the vertical sync signal interval, the horizontal sync signal start position from the vertical sync signal, the horizontal sync signal interval, the effective pixel start position from the horizontal sync signal, etc. It can be adjusted.

  The horizontal synchronization signal input from the LCD data output unit 6 via the input terminal 42 in FIG. 2 is input to the horizontal pixel number counter 45, and the horizontal pixel number counter 45 is initialized at the horizontal synchronization timing. Similarly, the vertical synchronization signal input from the LCD data output unit 6 via the input terminal 41 is input to the line number counter 44, and the line number counter 44 is initialized at the vertical synchronization timing. The pixel clock input from the input terminal 40 is input to the horizontal pixel number counter 45 and the line number counter 44. Further, the control unit 1 also expresses the horizontal synchronization signal start position from the vertical synchronization signal, the number of vertical effective pixels (also expressed as the number of vertical lines), and the effective pixel start position (horizontal effective pixel start position from the horizontal synchronization signal). The number of horizontal effective pixels is input via the input terminal 43. The horizontal pixel number counter 45 counts up from the horizontal effective pixel number start position to the horizontal effective pixel number, and when counting up to the horizontal effective pixel number, the line counter 44 is incremented by one. The line number counter 44 counts up from the horizontal synchronization signal head position with respect to the vertical synchronization signal to the number of vertical effective pixels. The count values of the horizontal pixel number counter 45 and the line number counter 44 are input to the memory read control unit 47, and the count values of the line number counter 44 and the horizontal pixel number counter 45 are set to the vertical effective pixel number and the horizontal effective pixel number, respectively. Until this time, the memory reading is made valid and the decoded image data is read from the frame memory 3. The read start address of the decoded image data at this time is an address set when the decoding completion information is received.

  The decoded image data read from the frame memory 3 via the input terminal 50 in FIG. 2 is output to the LCD data output unit 6 via the output terminal 52. The LCD data output unit 6 has only a memory equivalent to a line memory, and reads and synthesizes a graphic image from the graphic memory 5 in accordance with the timing read from the image output unit 4. The graphic image 5 is stored in advance in the graphic memory 5 from the control unit 1 before image composition processing in the LCD data output unit 6. The decoded image data and the graphic image synthesized by the LCD data output unit 6 constitute an LCD image and are output to the LCD data display unit 7 as LCD data.

  The speech encoded data is input to the speech decoding unit 8 from a memory or other device via a CPU bus or a dedicated bus. The speech decoding unit 9 performs decoding processing on the input speech encoded data according to the speech encoding method in accordance with a control signal from the control unit 1, outputs the decoded speech data to the speech output unit 9, and outputs decoded information to the control unit 1. Output to. The audio output unit 9 outputs the input audio decoded data as audio data.

  By the way, since the frame memory 3 of the present embodiment is composed of only three (3 frames) frame buffers, when a reproduction request is input from the control unit 1 to the image output unit 4, the frame memory 3 being displayed is displayed. After securing the frame buffer, it is necessary to proceed with the image decoding process independently of the display output process using the remaining two frame buffers. In the image reproduction apparatus of the present embodiment, the image decoding unit 2 and the image output unit 4 are independently operated by communicating with each other by the handshake method between the image decoding unit 2 and the image output unit 4.

  The reason for securing the frame buffer to be displayed is, for example, to cope with the re-output operation. The LCD data output unit 6 of the present embodiment has only a memory equivalent to a line memory in order to reduce the memory capacity, so there is no means for internally holding the decoded image data (frame data) output from the image output unit 4. . Therefore, when the content of the graphic memory 5 is changed, it is necessary to re-output the decoded image data from the image output unit 4 in order to reflect the changed content on the LCD data display unit 7. Therefore, when the image output unit 4 receives the re-output request signal accompanying the graphic image update from the LCD data output unit 6, the image output unit 4 re-outputs the contents of the reserved frame buffer. Another reason for securing the frame buffer to be displayed is, for example, when rewinding during image reproduction, discarding other than the decoded image data being reproduced, and displaying new decoded image data there This is because it is necessary to prepare while retaining the decoded image.

  FIG. 6 is a timing chart showing the signals related to the handshake communication between the image decoding unit 2 and the image output unit 4 and the processing timing. The reproduction input as a control signal from the control unit 1 to the image output unit 4 The request is a timing chart when only a normal reproduction request is made.

  6A shows a control signal input from the control unit 1 to the image output unit 4. In the case of FIG. 6, only a request for normal reproduction is input to the image output unit 4 as a control signal. FIG. 6B shows signals and processing timings related to handshake communication between the image decoding unit 2 and the image output unit 4. FIG. 6C shows the timing at which the encoded image data is decoded by the image decoding unit 2, and the numbers shown in the timing indicate the numbers of the frame buffers in which the decoded image data are stored. In the case of FIG. 6, since the frame memory 3 is composed of three frame buffers, frame buffer 0, frame buffer 1, and frame buffer 2, numbers 0, 1, and 2 are assigned cyclically. It is done.

  FIG. 6 (d) is one piece of decoding completion information output from the image decoding unit 2 to the image output unit 4, and the decoding state of the decoded image data stored in the frame buffer 0 is shown as decoding completion information (FLAG0). The low level indicates a state before or during decoding, and the high level indicates that the decoding is complete. That is, the high level indicates that the decoded image data is stored in the frame buffer 0 and display output is possible, and the low level indicates that the decoded image data is not stored in the frame buffer 0 and display output is not possible. ing.

  FIG. 6 (e) is one piece of decoding completion information output from the image decoding unit 2 to the image output unit 4, and the decoding state of the decoded image data stored in the frame buffer 1 is represented by decoding completion information (FLAG 1). The low level indicates a state before or during decoding, and the high level indicates that the decoding is complete. That is, the high level indicates that the decoded image data is stored in the frame buffer 1 and display output is possible, and the low level indicates that the decoded image data is not stored in the frame buffer 1 and display output is not possible. ing.

  FIG. 6 (f) is one piece of decoding completion information output from the image decoding unit 2 to the image output unit 4, and shows the decoding state of the decoded image data stored in the frame buffer 2 as decoding completion information (FLAG 2). The low level indicates a state before or during decoding, and the high level indicates that the decoding is complete. That is, the high level indicates that the decoded image data is stored in the frame buffer 2 and display output is possible, and the low level indicates that the decoded image data is not stored in the frame buffer 2 and cannot be displayed and output. Show.

  FIG. 6G is one of the memory write prohibition / permission information output from the image output unit 4 to the image decoding unit 2, and write prohibition or permission information for the frame buffer 0 is designated as memory write prohibition / permission. It is shown as information (CLR0), and a high level indicates that writing is permitted and a low level indicates that writing is prohibited.

  FIG. 6 (h) is one of memory write prohibition / permission information output from the image output unit 4 to the image decoding unit 2, and write prohibition / permission information for the frame buffer 1 is designated as memory write prohibition / permission. It is shown as information (CLR1), and the high level indicates that writing is permitted and the low level indicates that writing is prohibited.

  FIG. 6 (i) is one of memory write prohibition / permission information output from the image output unit 4 to the image decoding unit 2, and write prohibition or permission information for the frame buffer 2 is memory write prohibition / permission. It is shown as information (CLR2), and the high level indicates that writing is permitted and the low level indicates that writing is prohibited.

  Specifically, the memory write inhibit / permit information (CLR 0, CLR 1, CLR 2) is in a write inhibit state because the frame buffer that can be output next is prepared and the contents of the frame buffer that is currently output Is no longer needed, that is, when it can be discarded. In addition, the write-inhibited state is a state where the contents of the frame buffer have not been output yet, that is, in a non-output state, or there is no content of the frame buffer that can be output next, that is, the current This is a case where the contents of the frame buffer must be held (held state).

  FIG. 6 (j) shows the read start address stored in the read start address storage unit 47a in the image output unit 4, and the number shown in the timing indicates the number of the frame buffer in which the decoded image data is stored. Show. In the case of FIG. 6, any number of 0, 1, 2 corresponding to three frame buffers of frame buffer 0, frame buffer 1, and frame buffer 2 is assigned. This read start address is basically cyclically assigned as shown in FIG. 6C, but if the decoding process of the encoded image data in the image decoding unit 2 does not end by the read timing, the previous address Are assigned repeatedly.

  FIG. 6K shows a display ready signal output from the image output unit 4 to the LCD data output unit 6 when assigning the read start address in FIG. FIG. 6L shows the refresh timing of the LCD that is output from the LCD data display unit 7 to the LCD data output unit 6 as a frame synchronization signal. FIG. 6 (m) shows a vertical synchronization signal corresponding to FIG. 5 (m), which is output at the same timing as any of the frame synchronization signals in FIG. 6 (l). FIG. 6 (n) shows a horizontal synchronization signal corresponding to FIG. 5 (n). FIG. 6 (o) shows the frame data corresponding to FIG. 5 (o), and the numbers shown in the timing indicate the frame buffer numbers for reading the decoded image data. In the case of FIG. 6, the number is one of 0, 1, and 2 corresponding to the three frame buffers of the frame buffer 0, the frame buffer 1, and the frame buffer 2. Since the frame data is read from the number of the read start address in FIG. 6J, if the decoding process of the encoded image data in the image decoding unit 2 does not end by the read timing, the frame data of the previous number Are repeatedly read out.

  Next, each operation and each processing timing based on the timing of FIG. 6B will be described from the initial state of image reproduction. First, the initial state at the time of image reproduction in the case of FIG. 6 is FLAG0 which is decoding completion information corresponding to the frame buffer 0, FLAG1 which is decoding completion information corresponding to the frame buffer 1, and decoding completion information corresponding to the frame buffer 2. FLAG2 is low level, that is, display is disabled, CLR0 which is memory write prohibition / permission information corresponding to frame buffer 0, CLR1 which is memory write prohibition / permission information corresponding to frame buffer 1, frame buffer 2 CLR2 which is the memory write prohibition / permission information corresponding to is at a high level, that is, a write permission state to the memory.

  At timing t = t1, a decoding process request for the first encoded image data after initialization is output from the control unit 1 to the image decoding unit 2. When the first encoded image data decoding process after initialization is completed in the image decoding unit 2 at the timing t = t2, the image decoding unit 2 includes three frame buffers: a frame buffer 0, a frame buffer 1, and a frame buffer 2. Are assigned cyclically. First, FLAG0 is set to high level and output to the image output unit 4 (1-a). Then, after the initial state of image reproduction, the result of the first decoding process is written in the frame buffer 0.

  On the other hand, the image output unit 4 obtains information that the read start address is the frame buffer 0 in response to the FLAG0 becoming high level, and outputs the information to the image decoding unit 2 with CLR0 set to low level (2). -A) Thus, the writing to the frame buffer 0 by the image decoding unit 2 is prohibited until the display on the LCD data display unit 7 is completed and the memory contents of the frame buffer 0 become unnecessary.

  In this state, when a normal reproduction request is input from the control unit 1 (3-a), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 0 (4-a) and the LCD A display ready signal is output to the data output unit 6 (5-a). The decoding completion information and the memory writing prohibition / permission information are communicated between the image decoding unit 2 and the image output unit 4 by the handshake method, thereby linking the writing and reading about the use of the frame buffer. However, the process in which the image decoding unit 2 decodes the encoded image data and stores it in the frame memory 3 and the process in which the image output unit 4 reads out the decoded image data from the frame memory 3 and outputs them are in separate frames. It can be processed independently.

  On the other hand, the LCD data display unit 7 refreshes the LCD independently of the decoding process so that the display content does not disappear from the screen, for example, 60 times per second, that is, 60 Hz. Note that the refresh interval is not limited to 60 Hz. This refresh timing is input to the LCD data output unit 6 as a frame synchronization signal. By synchronizing the LCD data output with this timing, including a delay of a certain period, it is possible to transfer the image to the LCD at a timing shifted from the screen update timing, and as a result hide the switching of images Can do.

  The LCD data output unit 6 creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-a). The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-a).

  At timing t = t3, a decoding process request for the second encoded image data after initialization is output from the control unit 1 to the image decoding unit 2. The image decoding unit 2 performs the decoding process of the second encoded image data in response to the decoding process request, and sets FLAG1 to the high level at timing t = t4 (1-b). At this time, during the decoding process of the second encoded image data in the image decoding unit 2 shown in FIG. 6C, the image output unit 4 reads out the decoded image data corresponding to the first encoded image data. A process (4-a) for setting a start address in the frame buffer 0 and a display ready signal corresponding to the first encoded image data decoded image data are output to the LCD data output unit 6 (5-a). That is, the image decoding unit 2 performs the decoding process of the second encoded image data, and the image output unit 4 performs the decoding process of the decoded image data corresponding to the first encoded image data independently. .

  In response to the FLAG1 becoming high level, the image output unit 4 changes CLR1 to low level (2-b). When the normal reproduction request is input from the control unit 1 (3-b), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 1 (4-b) and the LCD data output unit 6 A display ready signal is output to (5-b). At this time, CLR0 is changed to high level, and the frame buffer 0 is made writable (6-b). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-b). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-b).

  At timing t = t5, a decoding process request for the third encoded image data after initialization is output from the control unit 1 to the image decoding unit 2. The image decoding unit 2 performs the decoding process of the third encoded image data in response to the decoding process request, and sets FLAG2 to the high level at timing t = t6 (1-c). In response to FLAG2 becoming high level, the image output unit 4 sets CLR2 to low level (2-c). Thereafter, before the normal reproduction request from the control unit 1 comes, the image decoding unit 2 further performs the next (fourth encoded image) in response to the decoding processing request from the control unit 1 at timing t = t7. Data) is decoded, and FLAG0 is set to the high level at timing t = t8 (1-d). This decoding process is possible because CLR0 changes from low level to high level at 6-b, and the frame buffer 0 is in a writable state. That is, the image decoding unit 2 determines whether to execute the decoding process based on the memory write prohibition / permission information from the image output unit 4.

  Thereafter, when a normal reproduction request is input from the control unit 1 to the image output unit 4 (3-c), the latest decoded image data is stored in the frame buffer 0, but the previous decoded image is stored in the frame Since it is in the buffer 2, the image output unit 4 sets the read start address of the decoded image data in the frame buffer 2 (4-c), and outputs a display ready signal to the LCD data output unit 6 (5-c). At this time, CLR1 is changed to high level, and the frame buffer 1 is made writable (6-c). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal output from the LCD data display unit 7, and outputs it to the image output unit 4 (7-c). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 2 (8-c).

  Next, when a normal reproduction request is input from the control unit 1 to the image output unit 4 (3-d), the image output unit 4 sets the stacked frame buffer 0 as a read start address of the decoded image ( 4-d) A display ready signal is output to the LCD data display section 6 (5-d). At this time, CLR2 is changed to high level, and the frame buffer 2 is made writable (6-d). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal output from the LCD data display unit 7, and outputs it to the image output unit 4 (7-d). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-d).

  During this time, at timing t = t9, the image decoding unit 2 receives a decoding processing request from the control unit 1 and performs the next (fifth encoded image data) decoding processing again, and timing t = t10. Then, FLAG1 is set to the high level (1-e). In response to FLAG1 becoming high level, the image output unit 4 sets CLR1 to low level (2-e). When the normal reproduction request is input from the control unit 1 (3-e), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 1 (4-e) and the LCD data output unit 6 The display ready signal is output to (5-e). At this time, CLR0 is changed to high level, and the frame buffer 0 is made writable (6-e). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-e). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-e).

  Further, during this time, at timing t = t11, the image decoding unit 2 receives a decoding processing request from the control unit 1 and performs the next (sixth encoded image data) decoding processing, and at timing t = t12. FLAG2 is set to high level (1-f). In response to FLAG2 becoming high level, the image output unit 4 sets CLR2 to low level (2-f). When the normal reproduction request is input from the control unit 1 (3-f), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 2 (4-f) and the LCD data output unit 6 A display ready signal is output to (5-f). At this time, CLR1 is changed to high level, and the frame buffer 1 is made writable (6-f). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-f). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 2 (8-f).

  Thereafter, at timing t = t13, a decoding process request is received from the control unit 1 and the image decoding unit 2 performs the next (seventh encoded image data) decoding process, but before the decoding process is completed. When a normal reproduction request is input from the control unit 1 (3-g), a frame buffer that can be output by looking at the previous decoded image read start address and the current frame buffer status (CLR0, CLR1, CLR2) To decide. Since CLR0 has not yet changed from the high level to the low level, the decoded image read start address is set (4-g) in the frame buffer 2 and the display ready signal is output to the LCD data output unit 6 as in the previous case. (5-g). However, at this time, since CLR0 is not at a low level, that is, it is not ready for the next display, CLR2 is kept at a low level (6-g). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-g). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 2 (8-g).

  When the decoding process in the image decoding unit 2 is completed at timing t = t14, FLAG0 is set to the high level (1-h). In response to FLAG0 becoming high level, the image output unit 4 sets CLR0 to low level (2-h). When the normal reproduction request is input from the control unit 1 (3-h), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 0 (4-h) and the LCD data output unit 6 The display ready signal is output to (5-h). At this time, CLR2 is changed to high level, and the frame buffer 2 is made writable (6-h). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-h). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-h).

  As described above, in the image decoding unit 2 and the image output unit 4 of the present embodiment, when only three normal reproduction requests are input from the control unit 1 to the image output unit 4 by preparing three frame buffers. After securing the frame buffer being displayed, the remaining two frame buffers can be used to proceed with the image decoding process independently of the display output process.

  Further, as described above, when the image output unit 4 receives the re-output request signal accompanying the graphic image update from the LCD data output unit 6, the image output unit 4 re-outputs the contents of the reserved frame buffer. The displayed frame buffer is ready for the next decoded image data, and is released when a request to reproduce the decoded image data is received, so that the memory can be written.

  Incidentally, in the case of FIG. 6 described above, the case where only the normal reproduction request is input from the control unit 1 to the image output unit 4 is shown, but not only the normal reproduction request is transmitted from the control unit 1 to the image output unit 4. A request for interlaced playback may be input. The case where the interlaced reproduction is input is, for example, that the image decoding process in the image decoding unit 2 is fast, while the image output unit 4 including the interface with the LCD data display unit 7 and the LCD data output unit 6 is used. This is a case where the image output processing is slow. In that case, it is necessary to adjust the reproduction timing of the decoded image data decoded by the image decoding unit 5 and the decoded audio data decoded by the audio decoding unit 8 by the control unit 1. At this time, the display ready signal from the image output unit 4 to the LCD output, the LCD refresh timing of the LCD data display unit 7, the vertical synchronization signal / horizontal synchronization signal from the LCD data output unit 6 to the image output unit 4, Depending on the timing, a delay may occur, and synchronization with the audio playback timing may not be achieved. At this time, by skipping the reproduction of the decoded image data by one frame, the timing of audio reproduction and image reproduction can be achieved, and natural reproduction becomes possible. In the present embodiment, since the frame memory 3 is composed of three frame buffers, only one frame can be skipped during reproduction, but the image decoding process of the image decoding unit 4 and the LCD The image output unit 4 including the interface with the data display unit 7 and the LCD data output unit 6 increases the number of frame buffers according to the speed of the image output process, thereby realizing efficient use of the memory. The decoding process and the image output process can be linked to realize natural image reproduction.

FIG. 7 is a timing chart for performing interlaced reproduction when the control signal of FIG. 6 is mixed with not only normal reproduction requests but also interlaced reproduction requests.
The difference between FIG. 7 and FIG. 6 is that the third control signal from the control unit 1 to the image output unit 4 is not a normal reproduction request but an interlaced reproduction request (3-C). 3-C) The frame data output after the input is not the decoded image data stored in the frame buffer 2, but becomes the decoded image data stored in the frame buffer 0, and the accompanying image output unit 4 The processing content is changed.

The operation by the input from timing t = t1 to t8 and the input from timing t = t10 to t14 is the same as the case where the control signal from the control unit 1 described above with reference to FIG. Therefore, the overlapping description is omitted.
At the time when the interlace playback request (3-C) is input, FLAG0 is high level, FLAG1 is high level, FLAG2 is high level, CLR0 is low level, CLR1 is low level, and CLR2 is low level. The start address is set in the frame buffer 1.

  When a skip reproduction request is input from the control unit 1 at the timing (3-C) in FIG. 7, the image decoding unit 4 has a decoded image that has not been read yet in the frame buffer 2, but discards the decoded image. Since the next decoded image is in the frame buffer 0, the read start address of the decoded image data is set in the frame buffer 0 (4-C), and a display ready signal is output to the LCD data output unit 6 (5). -C). At this time, CLR1 is changed to high level in order to put the frame buffer 1 that is no longer necessary for display output into the memory write state, and CLR2 is also changed to high level for the frame buffer 2 that is no longer required to be output. The frame buffer 2 is made writable (6-C). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal output from the LCD data display unit 7, and outputs it to the image output unit 4 (7-c). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-c).

  Next, when a normal reproduction request is input from the control unit 1 (3-d), the image decoding unit 4 has not yet completed the decoding process of the decoded image corresponding to the next frame buffer 1, so that the frame buffer 0 is set as the read start address of the decoded image (4-d), a display ready signal is output to the LCD data output unit 6 (5-d), and since there is no new decoded image in the frame buffer 1, CLR0 is set to low. Hold the level (6-d). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal output from the LCD data display unit 7, and outputs it to the image output unit 4 (7-d). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-d).

During this time, at timing t = t9, the image decoding unit 2 receives a decoding processing request from the control unit 1 and performs decoding processing of the next encoded image data. At timing t = t10, FLAG1 is set to the high level. (1-e). The subsequent processing is the same as when the control signal from the control unit 1 is only a normal reproduction request.
As described above, in the image decoding unit 2 and the image output unit 4 of the present embodiment, three frame buffers are prepared so that one frame is skipped in the normal reproduction request from the control unit 1 to the image output unit 4. Even when playback requests are mixed, it is possible to secure the frame buffer being displayed and to use the remaining two frame buffers to proceed with the image decoding process independently of the display output process.

  In the case of FIGS. 6 and 7 described above, the normal reproduction request or the interlaced reproduction request is input from the control unit 1 to the image output unit 4. A request to initialize the frame buffer of all frames may be input. Normally, all frame buffers are initialized before starting image reproduction. However, in the case of FIG. 8 described below, timing when all the frame buffers are initialized during image reproduction. It is.

FIG. 8 is a timing chart when all the three frame buffers in FIG. 6 are initialized.
The difference between FIG. 8 and FIG. 6 is that the third control signal from the control unit 1 to the image output unit 4 is not a normal reproduction request but an initialization request (3-α) for all frame buffers. Until the decoding process of the next encoded image data ends after the input of the initialization request (3-α), an output indefinite period during which no frame data is output, and the accompanying image decoding unit 2 and image output unit 4 is that the processing content is changed. More specifically, since the third control signal from the control unit 1 to the image output unit 4 is an initialization request for the frame buffer for all frames, the frame buffer output after the initialization request is shifted as a result. Accordingly, the processing contents of the image decoding unit 2 and the image output unit 4 are changed.

The operation by the input from timing t = t1 to t8 is the same as the case where the control signal from the control unit 1 described above with reference to FIG.
At the time when the initialization request (3-α) for all frame buffers is input, FLAG0 is high level, FLAG1 is high level, FLAG2 is high level, CLR0 is low level, CLR1 is low level, and CLR2 is low level The read start address is set in the frame buffer 1.

  When the all-frame buffer initialization request is input from the control unit 1 at the timing (3-α) in FIG. 8, the image output unit 4 sets all the CLR0, CLR1, and CLR2 to the high level and configures the frame memory 3. All frame buffers are set in a memory write enabled state, and the read start address is initialized and set in the frame buffer 0. On the other hand, the image decoding unit 2 sets all of FLAG0, FLAG1, and FLAG2 to the low level, and puts the next encoded image data from the control unit 1 into a waiting state for a decoding process request (6-α). Thereafter, the normal reproduction request (3-d) from the control unit 1 is ignored until the decoding process is completed and the decoded image writing to the frame buffer 0 is completed.

  After all initialization, the image decoding unit 2 and the image output unit 4 execute the image decoding process and the image output process in the order of the frame buffer 0, the frame buffer 1, and the frame buffer 2. At timing t = t9, the image decoding unit 2 receives the decoding processing request from the control unit 1 and performs decoding processing on the next encoded image data. At timing t = t10, FLAG0 is set to the high level (1). -E). In response to FLAG0 becoming high level, the image output unit 4 sets CLR0 to low level (2-e). When the next normal reproduction request is input from the control unit 1 (3-e), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 0 (4-e) and outputs the LCD data. A display ready signal is output to the unit 6 (5-e). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-e). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-e).

  Further, during this period, at timing t = t11, the image decoding unit 2 receives a decoding processing request from the control unit 1 and performs decoding processing of the next encoded image data. At timing t = t12, FLAG1 is set to the high level. (1-f). In response to the FLAG1 becoming high level, the image output unit 4 sets CLR1 to low level (2-f). When the normal reproduction request is input from the control unit 1 (3-f), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 1 (4-f), and the LCD data output unit 6 A display ready signal is output to (5-f). At this time, CLR0 is changed to high level, and the frame buffer 0 is made writable (6-f). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-f). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-f).

  Thereafter, at timing t = t13, a decoding process request is received from the control unit 1, and the image decoding unit 2 performs the decoding process of the next encoded image data. However, before the decoding process is completed, the control unit 1 When a normal reproduction request is input from (3-g), a frame buffer that can be output is determined by referring to the previous decoded image read start address and the current frame buffer status (CLR0, CLR1, CLR2). Since CLR2 has not yet changed from the high level to the low level, the decoded image reading start address is set (4-g) in the frame buffer 1 and the display ready signal is output to the LCD data output unit 6 as in the previous case. (5-g). However, at this time, since CLR2 is not at a low level, that is, it is not ready for the next display, CLR1 is kept at a low level (6-g). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-g). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-g).

  When the decoding process in the image decoding unit 2 is completed at timing t = t14, FLAG2 is set to the high level (1-h). In response to the FLAG2 becoming high level, the image output unit 4 sets CLR2 to low level (2-h). When the normal reproduction request is input from the control unit 1 (3-h), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 2 (4-h) and the LCD data output unit 6 The display ready signal is output to (5-h). At this time, CLR1 is changed to high level, and the frame buffer 1 is made writable (6-h). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-h). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 2 (8-h).

  In the case of FIG. 8 described above, a case where a request for initializing the frame buffer of all frames is input from the control unit 1 to the image output unit 4 is shown. A request to initialize all frame buffers other than the currently displayed frame (current frame) may be input. In the case of FIG. 9 described below, the timing is when all the frame buffers other than the current frame are initialized during image reproduction. The case other than the current frame buffer is initialized, for example, when fast-forwarding or rewinding during image reproduction, if the already decoded image is not discarded, the display is strange.

FIG. 9 is a timing chart when all the frame buffers other than the current frame among the three frame buffers of FIG. 6 are initialized.
The difference between FIG. 9 and FIG. 6 is that the third control signal from the control unit 1 to the image output unit 4 is not a normal reproduction request but an initialization request (3-β) for all frame buffers other than the current frame. Therefore, until the decoding process of the next encoded image data ends after the input of the initialization request (3-β), and the point that the read start address of the frame data becomes the read start address of the current frame, and The processing contents of the accompanying image decoding unit 2 and image output unit 4 are changed. More specifically, the third control signal from the control unit 1 to the image output unit 4 is an initialization request for all frame buffers other than the current frame. As a result, the frame buffer output after the initialization request is output. Accordingly, the processing contents of the image decoding unit 2 and the image output unit 4 are changed accordingly.

The operation by the input from timing t = t1 to t8 is the same as the case where the control signal from the control unit 1 described above with reference to FIG.
At the time when an initialization request (3-β) for all frame buffers other than the current frame is input, FLAG0 is high level, FLAG1 is high level, FLAG2 is high level, CLR0 is low level, CLR1 is low level, and CLR2 is at a low level, and the read start address is set in the frame buffer 1.

  When the initialization request other than the current frame buffer is input from the control unit 1 at the timing (3-β) in FIG. 9, the image output unit 4 sets all except CLR1 to the high level, and the frame buffer constituting the frame memory 3 Among them, the frame buffers other than the frame buffer 1 set for display output are made writable, and the read start address of the decoded image data is set in the frame buffer 1 of the current frame (4-c). On the other hand, the image decoding unit 2 sets all except FLAG1 corresponding to the current frame buffer to a low level, and enters a decoding process request standby state for the next encoded image data from the control unit 1 (6-β). When the normal reproduction request is input before the decoding process of the next encoded image data is completed (3-d), the image output unit 4 sets the read start address of the decoded image data in the currently displayed frame buffer 1. In addition to setting (4-d), a display ready signal is output to the LCD data output unit 6 (5-d). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-d). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-d).

  After initialization other than the current frame buffer, the image decoding unit 2 and the image output unit 4 execute an image decoding process and an image output process in order from the frame buffer next to the frame buffer 1 which is the current frame buffer. At timing t = t9, the image decoding unit 2 receives the decoding processing request from the control unit 1 and performs decoding processing on the next encoded image data. At timing t = t10, FLAG2 is set to the high level (1). -E). In response to FLAG2 becoming high level, the image output unit 4 sets CLR2 to low level (2-e). When the normal reproduction request is input from the control unit 1 (3-e), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 2 (4-e) and the LCD data output unit 6 The display ready signal is output to (5-e). At this time, CLR1 is changed to high level and the frame buffer 1 held for display output is made writable (6-f). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-e). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 2 (8-e).

  Further, during this period, at timing t = t11, the image decoding unit 2 receives a decoding processing request from the control unit 1 and performs decoding processing of the next encoded image data. At timing t = t12, FLAG0 is set to a high level. (1-f). In response to FLAG0 becoming high level, the image output unit 4 sets CLR0 to low level (2-f). When the normal reproduction request is input from the control unit 1 (3-f), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 0 (4-f) and the LCD data output unit 6 A display ready signal is output to (5-f). At this time, CLR2 is changed to high level, and the frame buffer 2 is made writable (6-f). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-f). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-f).

  Thereafter, at timing t = t13, a decoding process request is received from the control unit 1, and the image decoding unit 2 performs the decoding process of the next encoded image data. However, before the decoding process is completed, the control unit 1 When a normal reproduction request is input from (3-g), a frame buffer that can be output is determined by referring to the previous decoded image read start address and the current frame buffer status (CLR0, CLR1, CLR2). Since CLR1 is not yet changed from the high level to the low level, the decoded image read start address is set in the frame buffer 0 (4-g) and the display ready signal is output to the LCD data output unit 6 as in the previous case. (5-g). However, at this time, since CLR1 is not at the low level, that is, it is not ready for the next display, CLR0 is kept at the low level (6-g). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-g). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 0 (8-g).

  When the decoding process in the image decoding unit 2 is completed at timing t = t14, FLAG1 is set to the high level (1-h). In response to FLAG1 becoming high level, the image output unit 4 sets CLR1 to low level (2-h). When the normal reproduction request is input from the control unit 1 (3-h), the image output unit 4 sets the read start address of the decoded image data in the frame buffer 1 (4-h) and the LCD data output unit 6 The display ready signal is output to (5-h). At this time, CLR0 is changed to high level, and the frame buffer 0 is made writable (6-h). The LCD data output unit 6 receives the display ready signal, creates a vertical synchronization signal / horizontal synchronization signal from the frame synchronization signal input from the LCD data display unit 7, and outputs it to the image output unit 4 (7-h). . The image output unit 4 receives the vertical synchronization signal / horizontal synchronization signal and outputs the frame data of the frame buffer 1 (8-h).

  As described above, the image reproducing apparatus according to the first embodiment shares the frame memory 3 between the image decoding process performed by the image decoding unit 2 and the image output process performed by the image output unit 4, and communicates using the handshake method. Image decoding processing performance in the image decoding unit 2, image output processing performance in the image output unit 4, components after the image output unit 4 and their timing (graphic memory 5, LCD data output unit 6, LCD data display unit 7) Accordingly, the capacity of the frame memory 3 can be configured with a minimum of three frame buffers, for example, and smooth image reproduction without frame delay or frame advance during reproduction can be obtained. . In addition, since the image reproduction apparatus according to the first embodiment communicates with the handshake method regarding the use of the frame memory, the image decoding unit 2 and the image output unit 4 operate independently to decode and display an image. In addition to using the frame memory efficiently, the image decoding unit 2 and the image output unit 4 can also be individually processed efficiently.

  In addition, the image reproduction apparatus according to the first embodiment re-outputs the updated contents of the graphic memory 5 to the image output unit 4 from the LCD data output unit 6 in order to reflect the updated contents of the graphic memory 5 on the LCD display image on the LCD data display unit. Even if the request signal is output and the decoded image data is not output from the image decoding unit 2, the image can be output, so that the graphic data displayed at a necessary timing can be updated.

  In addition, the image reproduction apparatus according to the first embodiment controls a plurality of frame buffers constituting the frame memory 3 that performs communication by the handshake method in the image decoding unit 2 and the image output unit 4 as ring buffers. Continuous processing is possible for each of the unit 2 and the image output unit 4.

  In addition, in the image reproduction apparatus according to the first embodiment, in the image output unit 4 in the case where there is a display output capable frame buffer, reading of decoded image data is started each time a normal reproduction request is made as a control signal from the control unit 1. Since the address is updated to the head of the next frame buffer, the reproduction timing can be controlled by the normal reproduction request from the control unit 1 to the image output unit 4.

Further, in the image reproduction apparatus according to the first embodiment, in the image output unit 4 in the case where there are a plurality of display output-capable frame buffers, readout of decoded image data is started each time a jump playback request is made as a control signal from the control unit 1 Since the address is updated to the head of the frame buffer advanced by the necessary number of interlaced frames, the decoded image data output is changed to the audio decoded data output / display output, or by the interlaced reproduction request from the control unit 1 to the image output unit 4. The timing can be adjusted when it is output at an earlier timing than the image display output.
In the image reproducing apparatus of the first embodiment, the decoding processing circuit block and the display output processing circuit block are separated, and even with a frame memory having a small storage capacity such as three frames, frame delay and frame advance during reproduction. As a result, smooth image reproduction with no image can be achieved, so that smooth and good display output can be achieved.

  Note that in the image reproduction device of the present embodiment, the LCD data display unit 7 creates and combines the decoded image data output from the image output unit 4 and the graphic image read from the graphic memory 5, and finally The description has been made assuming that a memory for holding LCD data constituting a typical display image is provided, but the present embodiment is not limited to this. For example, conversely, the LCD data display unit 7 has been described above. The present invention can be applied even when there is no memory and the LCD data output unit 6 has a memory for holding LCD data.

Embodiment 2. FIG.
In the first embodiment described above, the case of an image reproducing device having the LCD data display unit 7 using a liquid crystal panel as a display unit and the LCD data output unit 6 as a display data output unit as constituent elements has been described. For example, a television (TV) signal display unit that displays a signal that complies with the standard of the television signal is known, and even if a television (TV) signal output unit for that purpose is used, the signal is read from the frame memory 3. The decoded image data can be displayed. At this time, in the combination of the LCD data output unit 6 and the LCD data display unit 7 of the first embodiment, the memory for holding the LCD data constituting the final display image is the LCD data output unit 6 and the LCD data display unit 7. In the second embodiment, the LCD data is updated at the LCD refresh timing triggered by the display ready signal. However, in the second embodiment, the TV signal is always output at the timing compliant with the television signal standard. Image data is output from the display unit and displayed on the TV phone display unit. Therefore, in Embodiment 2 described below, a case where a TV signal output unit is used as the display data output unit and a TV signal display unit is used as the display unit will be described.

FIG. 10 is a block diagram showing a schematic configuration of the image reproduction apparatus according to the second embodiment of the present invention.
The difference between the image reproducing apparatus of the second embodiment shown in FIG. 10 and the image reproducing apparatus of the first embodiment shown in FIG. 1 is that the LCD data output unit 6 of the first embodiment outputs a TV signal. And the LCD data display unit 7 is changed to the TV signal display unit 17. Accordingly, the display ready signal input from the image output unit 4 to the LCD data output unit 6 and the image from the LCD data output unit 6 are changed. The re-output request signal input to the output unit 4 and the frame synchronization signal input to the LCD data output unit 6 from the LCD data display unit 7 are deleted. The image output unit 4a also has no display ready signal, re-output request signal, and frame synchronization signal, and therefore has different internal processing from the image output unit 4 of the first embodiment. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  The TV signal output unit 16 internally generates a vertical / horizontal synchronization signal at a timing compliant with a television signal standard such as NTSC or PAL, and outputs it to the image output unit 4a. The display frame data is received at a timing compliant with the above and is output to the TV signal display unit 17. The TV signal display unit 17 is a display unit that displays image data that conforms to the standard of television signals.

  The image output unit 4a is the same as the image output unit 4 of the first embodiment in the exchange of information and data among the control unit 1, the image decoding unit 2, and the frame memory 3, but the TV signal output unit 16 The transmission and reception of information and data is different from that of the image output unit 4 of the first embodiment. As for the internal processing of the image output unit 4a, for example, there is no processing for generating and outputting the display ready signal shown in step S18 of FIG. 4, and the re-output request signal is received and the decoded image data is re-generated. There is no processing to output, while the timing of the vertical synchronization signal / horizontal synchronization signal is based on the LCD refresh timing in the first embodiment, whereas it is based on the timing compliant with the standard of the television signal, Other than that, the same applies.

  In the internal block diagram of FIG. 2, the image output unit 4 a does not have the display ready signal and the re-output request signal, and therefore does not have the output terminal 51 and the input terminal 53. Other configurations are the same. The image output unit 4a eliminates step S18 in the flowchart of FIG. Other operations are the same. In the timing charts of the normal reproduction request, the interlaced reproduction request, the all frame buffer initialization request, and the initialization request other than the current frame buffer shown in FIGS. 6 to 9, the display ready signal of (k) is lost. Instead of the LCD refresh timing, the frame synchronization timing generated inside the TV signal output unit 16 or the field synchronization timing similarly generated internally is used.

The overall operation of the image reproduction apparatus of the present embodiment will be described with reference to FIGS. 10 and 2 as follows.
The horizontal synchronization signal input from the TV signal output unit 16 via the input terminal 42 in FIG. 2 is input to the horizontal pixel number counter 45, and the horizontal pixel number counter 45 is initialized at the horizontal synchronization timing. Similarly, the vertical synchronization signal input from the TV signal output unit 16 via the input terminal 41 is input to the line number counter 44, and the line number counter 44 is initialized at the vertical synchronization timing. The pixel clock input from the input terminal 40 is input to the horizontal pixel number counter 45 and the line number counter 44. Further, from the control unit 1, the horizontal synchronization signal start position from the vertical synchronization signal, the number of vertical effective pixels (also expressed as the number of vertical lines), the effective pixel start position from the horizontal synchronization signal, and the number of horizontal effective pixels are input terminals. 43 is input. The horizontal pixel number counter 45 counts up from the effective pixel number start position from the horizontal synchronization signal to the horizontal effective pixel number, and when counting up to the horizontal effective pixel number, the line counter 44 is incremented by one. The line number counter 44 counts up from the vertical synchronizing signal to the number of vertical effective pixels from the horizontal synchronizing signal head position. The count values of the horizontal pixel number counter 45 and the line number counter 44 are input to the memory read control unit 47, and the count values of the line number counter 44 and the horizontal pixel number counter 45 are set to the vertical effective pixel number and the horizontal effective pixel number, respectively. Until this time, the memory reading is made valid, and the decoded image data is read from the frame memory 3. The read start address of the decoded image data at this time is an address set when the decoding completion information is received.

  The decoded image data read from the frame memory 3 through the input terminal 50 in FIG. 2 is output to the TV signal output unit 16 through the output terminal 52. The TV signal output unit 16 reads and synthesizes a graphic image from the graphic memory 5 in accordance with the timing read from the image output unit 4a. The graphic image 5 is stored in advance in the graphic memory 5 from the control unit 1 before image synthesis processing in the TV signal output unit 16. The decoded image data and the graphic image synthesized by the TV signal output unit 16 constitute a TV image and are output to the TV signal display unit 17 as TV data.

  As described above, the image reproduction apparatus according to the second embodiment shares the frame memory 3 between the image decoding process performed by the image decoding unit 2 and the image output process performed by the image output unit 4a, and performs communication using the handshake method. Image decoding processing performance in the image decoding unit 2, image output processing performance in the image output unit 4a, components after the image output unit 4a and their timing (graphic memory 5, TV signal output unit 16, TV signal display unit 17) Accordingly, the capacity of the frame memory 3 can be configured with a minimum of three frame buffers, for example, and smooth image reproduction without frame delay or frame advance during reproduction can be obtained. . In addition, since the image reproduction apparatus according to the second embodiment performs the image decoding unit 2 and the image output unit 4a operate independently while performing communication by the handshake method regarding the use of the frame memory, The frame memory can be used efficiently, and the image decoding unit 2 and the image output unit 4a can be individually processed efficiently.

  In each of the above embodiments, the frame memory 3 is composed of three frame buffers. However, the present invention is not limited to this. For example, the image decoding process by the image decoding unit 2 and the image output unit 4 (or the image output unit 4a), the LCD data output unit 6, and the LCD data display unit 7, the number of frame buffers may be increased or decreased according to the processing time of the image output process (image display process). For example, when the image output processing is slower than the image decoding processing, more image thinning processing by interlaced frames is required, so the number of frame buffers may be increased.

  Further, in each of the above-described embodiments, the case where the image to be reproduced is a moving image has been described. However, the present invention is not limited to this, and the above-described effect can be obtained even with a quasi-moving image such as Motion JPEG. In addition, the effect can be obtained even when it is applied at the time of switching the display of a still image such as JPEG.

  Further, the method of communication using the handshake method of the present invention is not limited to the method described in each of the above embodiments, and for example, the bit polarity may be reversed. Further, the decoding completion information of the present invention is described as being generated on the image decoding unit 2 side and holding the output in each of the above-described embodiments, but the present invention is not limited to this configuration. The subsequent decoding completion information may be held on the image output unit 4 (or image output unit 4a) side. The memory write prohibition / permission information of the present invention is configured to be held on the image output unit 4 (or image output unit 4a) side in each of the above-described embodiments. For example, the updated memory writing prohibition / permission information may be held on the image decoding unit 2 side.

It is a block diagram which shows schematic structure of the image reproduction apparatus of Embodiment 1 of this invention. It is a block diagram which shows the internal structure of the image output part 4 of FIG. 4 is a flowchart showing a schematic operation flow of the image decoding unit 2. 4 is a flowchart showing a general operation flow of the image output unit 4. 6 is a timing chart showing an example of a relationship between a vertical synchronization signal / horizontal synchronization signal input from the LCD data output unit 6 to the image output unit 4 and frame data output from the image output unit 4. Signals related to handshake communication between the image decoding unit 2 and the image output unit 4 when the reproduction request input as a control signal from the control unit 1 to the image output unit 4 is only a normal reproduction request, and processing timing It is a timing chart which shows. FIG. 7 is a timing chart for performing interlaced reproduction when the control signal of FIG. 6 is mixed with not only normal reproduction requests but also interlaced reproduction requests. 7 is a timing chart when all three frame buffers in FIG. 6 are initialized. 7 is a timing chart when all the frame buffers other than the current frame among the three frame buffers in FIG. 6 are initialized. It is a block diagram which shows schematic structure of the image reproduction apparatus of Embodiment 2 of this invention.

Explanation of symbols

1 control unit, 2 image decoding unit, 3 frame memory, 4, 4a image output unit, 5 graphic memory, 6 LCD data output unit, 7 LCD data display unit, 8 audio decoding unit, 9 audio output unit, 16 TV signal output Unit, 17 TV signal display unit, 40 to 43, 50, 53 input terminal, 44 line number counter, 45 horizontal pixel number counter, 47 memory read control unit, 47a (display frame) read start address storage unit, 47b (frame) Unit) All read start address storage section, 48, 49, 51, 52 Output terminal.

Claims (11)

A control unit that performs a decoding process control for outputting a decoding process request for encoded image data and an output process control for outputting an image reproduction request for decoded image data;
In response to a decoding process request from the control unit, the encoded image data is decoded to generate decoded image data for each frame, and an image decoding unit that outputs decoding completion information every time the decoding is completed;
A frame memory for storing the decoded image data for a predetermined number of frames, and storing the decoded image data for each frame;
By inputting the decoding completion information, a read start address for reading the readable decoded image data from the frame memory is set, and writing to the storage area corresponding to the decoded image data in the unoutput state or the hold state is performed. Is output together with information that permits writing to the storage area corresponding to the decoded image data in a discardable state, and is input when an image reproduction request from the control unit is input. An image output unit that reads out and outputs one frame of decoded image data set as a read start address from the frame memory based on a vertical / horizontal synchronization signal;
An image reproduction apparatus comprising: a display data output unit that generates the vertical / horizontal synchronization signal for outputting image data from the image output unit in accordance with display means. The frame memory is composed of a plurality of frame buffers,
The decoding completion information includes frame buffer number information that can be displayed and output,
When there is a frame buffer capable of display output, the image output unit reads out and outputs decoded image data from the display output capable frame buffer,
The information of the storage area where writing in the frame memory is permitted includes a writable frame buffer number,
The image reproduction apparatus according to claim 1, wherein the image decoding unit executes an image decoding process when there is the writable frame buffer. When the image reproduction request is a normal reproduction request and there is a display output capable frame buffer, the image output unit sets the read start address of the decoded image data every time the normal reproduction request is input. The image reproducing apparatus according to claim 2, wherein the frame buffer is updated to the top of the frame buffer in the order of. When the image reproduction request is an interlaced reproduction request and there are a plurality of display output capable frame buffers, the image output unit sets a read start address of decoded image data every time an interlaced reproduction request is input. The image reproducing apparatus according to claim 2, wherein the image is updated to the head of the frame buffer in the order advanced by the number of skipped frames. 5. The image reproduction device according to claim 2, wherein the frame buffer includes a frame buffer having a storage capacity capable of storing decoded image data of at least three reproduction image sizes. 5. The image reproduction according to claim 2, wherein the frame buffer number is cyclically controlled by the image decoding unit and the image output unit to write and read decoded image data. apparatus. The operation in which the image decoding unit writes the decoded image data into the frame memory and the operation in which the image output unit reads out the decoded image data from the frame memory can operate independently of each other. The image reproduction apparatus according to any one of claims 1 to 6, wherein the use of a region is managed by communication using a handshake method between the image decoding unit and the image output unit. A display unit for displaying the display data output from the display data output unit;
The display unit is a display unit using liquid crystal, and outputs a frame synchronization signal based on the refresh timing of the liquid crystal,
The image output unit, when there is a frame buffer capable of display output, and when an image reproduction request is input from the control unit after input of the decoding completion information, decodes image data from the display output possible frame buffer. Before reading, output a display ready signal indicating that the image output to the liquid crystal display unit is possible,
The display data output unit generates display data for liquid crystal by generating the vertical / horizontal synchronization signal based on the input of the frame synchronization signal and outputting the generated signal to the image output unit by inputting the display ready signal. The image reproduction device according to claim 2, wherein the image reproduction device outputs the image to a display unit. A graphic memory for storing graphic data to be combined with the decoded image data output from the image output unit;
The display data output unit combines the decoded image data for each frame output from the image output unit with the graphic data read from the graphic memory, and displays the combined display data on the liquid crystal display unit. Output,
When the graphic data of the graphic memory is updated, the display data output unit outputs a re-output request signal to the image output unit,
9. The image reproducing apparatus according to claim 8, wherein when the re-output request signal is input, the image output unit reads out and outputs decoded image data of a requested frame from the frame memory. A display unit for displaying the display data output from the display data output unit;
The display unit is a display unit that displays a signal that conforms to the standard of a television signal,
The display data output unit generates display data compliant with the television signal standard by generating the vertical / horizontal synchronization signal at a timing compliant with the television signal standard and outputting the generated signal to the image output unit. The image reproduction apparatus according to claim 1, wherein the image reproduction apparatus outputs the image to a display unit. The image decoding unit decodes the encoded image data to generate decoded image data for each frame, stores the decoded image data for each frame in a frame memory, and when an image reproduction request is input, the image output unit Decoded image data for each frame is read from the frame memory for each frame and output to a display data output unit. The display data output unit outputs a vertical / horizontal synchronization signal for output from the image output unit in accordance with display means. A frame memory control method for an image reproducing device to be generated, comprising:
When the image decoding unit decodes the image, the decoding completion information is output every time the decoded image data for each frame is generated,
The image output unit sets a read start address for reading out the readable decoded image data from the frame memory by inputting the decoding completion information, and corresponds to decoded image data in an unoutput state or a holding state. When information prohibiting writing to the storage area is output together with information permitting writing to the storage area corresponding to the decoded image data in the discardable state, and an image reproduction request is input from the control unit In addition, based on the input vertical / horizontal synchronization signal, the decoded image data set as the read start address is read out from the frame memory for one frame, and output.
A display data output unit outputs the vertical / horizontal synchronization signal for displaying image data to the image output unit.

Images