JP2005079200A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variations in an etching rate in an arranged state, and to reduce variations in the shape in the depthwise direction of a recessed pattern by the variations of the etching rate in a semiconductor device. <P>SOLUTION: A group of through holes 112 including a plurality of through holes 102, and an isolated through hole 114 that is not surrounded by other through holes 102, are formed on an interlayer insulating film 110 made of SiOC, or the like. A plurality of dummy through holes 104 are formed around the group of through holes 112 and the isolated through hole 114. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a plurality of concave patterns are formed in an insulating film and a manufacturing method thereof.

In recent years, miniaturization of multilayer wiring has been advanced as one solution to the problems of high-speed operation of semiconductor devices and reduction of manufacturing costs. At the same time, the problem of interconnect delay (RC delay) accompanying the increase in electrical resistance of interconnects and electrical capacitance between interconnects has surfaced, and the operation speed of semiconductor devices has been limited. Therefore, in order to reduce the electrical resistance of the wiring, the wiring material copper (Cu) is used, or in order to reduce the capacitance between the wirings, a low dielectric constant material having a lower relative dielectric constant than that of the conventional SiO ₂ is used for the insulating film. Measures such as use have become widely known.

As such a low dielectric constant material, SiOC, MSQ (Methyl Silsesquioxane), etc. are examined. These materials are expected to be diverted from conventional SiO ₂ technology, and are being developed as easy-to-handle materials.

However, when a through hole is formed in the SiO ₂ film, if an attempt is made to form a through hole in the SiOC film using a fluorocarbon-based gas that has been conventionally used as an etching gas, the SiO ₂ film has a difference in characteristics of the film. Problems that did not occur may occur.

For example, Patent Document 1 describes a phenomenon in which, when a SiOC film is etched using a fluorocarbon-based gas, the progress of the etching stops during the etching. In addition, when the oxygen content is increased to prevent such a phenomenon, there is a problem that the ratio of the etching rate of the resist film and the SiOC film is lowered. To solve these problems, the etching gas contains CO 2. A technique for adding is described.
JP 2002-83798 A

  The inventor of the present application, when forming a through hole in the SiOC film by etching, varies the etching rate depending on the arrangement state of the through hole, and the phenomenon that the shape in the depth direction of the plurality of through holes varies. I found it.

FIG. 8 is a diagram schematically showing this phenomenon.
As shown in FIG. 8A, the interlayer insulating film 10 is formed with a plurality of through hole groups 12 arranged in a matrix and isolated through holes 14 around which no other through holes are formed. Yes. When a through hole having such a pattern is formed by etching using a fluorocarbon-based gas, a through hole as shown in FIG. 8B is formed. FIG. 8B is a cross-sectional view taken along the line CC ′ of FIG. As shown in FIG. 8B, the through hole c and the through hole d formed in the outer peripheral portion of the through hole group 12 as compared with the through hole a and the through hole b formed in the central portion of the through hole group 12. Will decrease the etching rate. In addition, the etching rate of the isolated through hole 14 (through hole f) is further reduced as compared with the through hole included in the through hole group 12. In addition, depending on the type of etching gas, a phenomenon may occur in which the etching rate of through holes formed in the outer periphery of a plurality of through holes arranged in a matrix is higher than the etching rate of the through holes formed in the center. . Thus, when a through hole is formed in an SiOC film by etching, the outer peripheral portion of the plurality of through holes arranged in a block shape varies compared to the etching rate of the through hole formed in the central portion. A phenomenon occurs.

FIG. 9 is a diagram showing the etching rate ratio of each through hole when a mixed gas of Ar / CF ₄ / CH ₂ F ₂ / N ₂ is used as the fluorocarbon-based etching gas. If the etching rate of the through hole a formed at the center of the through hole group 12 is 1, the etching rate of the through hole d located at the outermost side of the through hole group 12 is about 0.7, and the through hole located at the outermost angle is The etching rate of the hole g is about 0.6, and the etching rate of the isolated through hole f is about 0.3. In FIG. 8, the through hole a is formed adjacent to the through hole b, but a plurality of (for example, about 10) through holes are formed between the through hole a and the through hole b. The etching rate of the through hole a in FIG. 9 is a value when the through hole a is surrounded by 10 or more through holes in both the vertical and horizontal directions. The same applies to FIG. 10 below.

FIG. 10 is a diagram showing the etching rate when the type of interlayer insulating film and the etching gas are different.
here,
(1) When SiO ₂ is used as an interlayer insulating film and gas A is used as an etching gas,
(2) When SiOC is used as an interlayer insulating film and gas A is used as an etching gas,
(3) The etching rate when SiOC is used as the interlayer insulating film and gas B is used as the etching gas.

The conditions for the etching gas are as follows.
Gas A: Flow rate Ar / CF ₄ / CH ₂ F ₂ / N ₂ = 500/30/10/90 sccm, pressure 50 mTorr, RF power 1300 W;
Gas B: Flow rate Ar / C ₄ F ₈ / N ₂ = 500/8/50 sccm, pressure 50 mTorr, RF power 1300 W.

Here, the hole diameter of the through hole was 0.2 μm. When SiO ₂ was used as the interlayer insulating film, there was almost no difference in the etching rate depending on the through hole arrangement. On the other hand, when SiOC is used as the interlayer insulating film, it has been found that the etching rate varies depending on the arrangement position of the through holes regardless of the type of etching gas. From the above results, it is considered that the difference in the etching rate depending on the arrangement state of the through holes is not due to the type of resist at the time of etching or the type of etching gas but to the type of interlayer insulating film.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique capable of reducing the shape variation in the depth direction of the concave pattern in the semiconductor device.

  A semiconductor device according to the present invention includes an insulating film, a plurality of concave patterns formed in the insulating film, and a plurality of dummy concave patterns formed in the insulating film and arranged around the plurality of concave patterns. It is characterized by that.

  Here, the concave pattern can be a through hole or a wiring groove. When a plurality of concave patterns are provided as adjacent concave pattern groups, the periphery can be the outer periphery of the plurality of concave pattern groups. In addition, when the plurality of concave patterns include an isolated concave pattern not surrounded by other concave patterns, the periphery can be the periphery of the isolated concave pattern. Furthermore, the dummy concave pattern can be formed so as to surround all the concave patterns. Here, the surroundings can be four directions. When each concave pattern is divided into approximately four equal parts with the concave pattern as the center, dummy concave patterns are formed so that other concave patterns exist within a predetermined distance from the concave pattern on all divided planes. can do.

  The insulating film can include at least Si, O, and C. The insulating film may contain H. The insulating film can be, for example, SiOC, SiOCN, or MSQ. SiOC or SiOCN can be deposited by CVD or spin coating. MSQ can be deposited by spin coating. As an etching gas for forming these concave patterns, a fluorocarbon-based gas can be used.

  In this way, each concave pattern can be configured to be surrounded by other concave patterns or dummy concave patterns, so that variation in etching rate in the concave pattern can be reduced. By adopting such a configuration, the phenomenon of decreasing or increasing the etching rate originally generated in the concave pattern arranged on the outer periphery of the plurality of concave patterns or the isolated concave pattern is transferred to the dummy concave pattern. Therefore, variation in the etching rate of the plurality of concave patterns can be reduced.

  In the semiconductor device according to the present invention, the plurality of concave patterns may be formed in a block shape, and the dummy concave pattern can be formed along the outermost region of the plurality of concave patterns. Here, the block shape means a matrix shape, that is, a matrix shape arranged in the vertical and horizontal directions, a column shape arranged in either the vertical direction or the horizontal direction, a plurality of randomly arranged concave patterns, and a sparse / dense pattern. It includes a plurality of different concave patterns, a plurality of concave patterns arranged in a comb shape, and the like.

  A dummy concave pattern can be disposed around a region where a plurality of through holes contributing to the electrical operation of the semiconductor device are provided as a block. Further, when a short-circuit region that is electrically connected to the upper and lower wiring layers is provided in the vicinity of the plurality of concave patterns, a dummy concave pattern is provided around the plurality of concave patterns and the short-circuit region. You can also.

  By adopting such a configuration, the concave pattern placed on the outer periphery of the concave pattern formed in a matrix form or the phenomenon of decreasing or increasing the etching rate that has occurred in the isolated concave pattern is eliminated by the dummy concave shape. Since the pattern can be passed on, variations in the etching rate of the plurality of concave patterns can be reduced.

  In the semiconductor device of the present invention, the dummy concave pattern can be formed shallower than the depth of the plurality of concave patterns. In this way, when the conductive material is embedded in the plurality of concave patterns, even if the conductive material is embedded in the dummy concave pattern, the conductive material in the dummy concave pattern is electrically connected to the lower layer wiring. Therefore, it is possible to form a dummy concave pattern without being limited in place. When the etching rate of the concave pattern provided on the outer periphery of the plurality of concave patterns increases depending on the type of etching gas, the dummy concave pattern can be formed deeper than the depth of the plurality of concave patterns.

  In the semiconductor device of the present invention, the aspect ratio of the dummy concave pattern can be formed lower than the aspect ratio of the plurality of concave patterns. In this way, when the conductive material is embedded in the plurality of concave patterns, even if the conductive material is embedded in the dummy concave pattern, the conductive material in the dummy concave pattern is electrically connected to the lower layer wiring. Therefore, it is possible to form a dummy concave pattern without being limited in place. When the etching rate of the concave pattern provided on the outer periphery of the plurality of concave patterns increases depending on the type of etching gas, the aspect ratio of the dummy concave pattern is formed higher than the aspect ratio of the plurality of concave patterns. be able to.

  In the semiconductor device of the present invention, the opening width of the dummy concave pattern can be formed substantially equal to the opening width of the plurality of concave patterns. In this way, since the dummy concave pattern can be formed with the same pattern diameter as the plurality of concave patterns, design design can be easily performed.

  In the semiconductor device of the present invention, the opening width of the dummy concave pattern can be formed wider than the opening width of the plurality of concave patterns. In this way, even if the number of dummy concave patterns is reduced, variations in the etching rate of the plurality of concave patterns can be suppressed.

  In the semiconductor device of the present invention, the opening width of the dummy concave pattern can be formed narrower than the opening widths of the plurality of concave patterns. In this way, the etching rate in the dummy through hole can be lowered. Accordingly, when the conductive material is embedded in the plurality of concave patterns, the conductive material in the dummy concave pattern is not electrically connected to the lower layer wiring even if the conductive material is embedded in the dummy concave pattern. Therefore, it is possible to form a dummy concave pattern without being restricted in place.

  The semiconductor device of the present invention includes an insulating film and a plurality of concave patterns formed in the insulating film, and among the plurality of concave patterns, the opening width of the concave pattern that is not surrounded by the other concave patterns is different. The opening width of the concave pattern surrounded by the concave pattern is different from that of the concave pattern.

  The insulating film can include at least Si, O, and C. The insulating film may contain H. The insulating film can be, for example, SiOC, SiOCN, or MSQ. SiOC or SiOCN can be deposited by CVD or spin coating. MSQ can be deposited by spin coating. As an etching gas for forming these concave patterns, a fluorocarbon-based gas can be used.

  The magnitude relationship between the opening width of the concave pattern not surrounded by other concave patterns and the opening width of the concave pattern surrounded by the other concave patterns is appropriately set according to the type of etching gas. If the etching rate of a concave pattern not surrounded by another concave pattern is lower than that of a concave pattern surrounded by another concave pattern, the opening width of the concave pattern not surrounded by the other concave pattern Can be made wider than the opening width of the concave pattern surrounded by other concave patterns. Thereby, the etching rate of the concave pattern not surrounded by other concave patterns can be increased by the microloading effect. Therefore, the phenomenon of decreasing the etching rate in the outer peripheral portion of the plurality of concave patterns and the isolated concave pattern as described above can be canceled, and variations in the etching rate in the plurality of concave patterns can be reduced.

  On the other hand, when the etching rate of the concave pattern not surrounded by other concave patterns is higher than the concave pattern surrounded by other concave patterns, the concave pattern not surrounded by other concave patterns The opening width can be made narrower than the opening width of the concave pattern surrounded by other concave patterns. Thereby, the etching rate of the concave pattern not surrounded by other concave patterns can be lowered. Therefore, the phenomenon of the increase in the etching rate in the outer peripheral portion of the plurality of concave patterns and the isolated concave pattern as described above can be canceled, and the variation in the etching rate in the plurality of concave patterns can be reduced.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film, and a step of forming a plurality of concave patterns and a plurality of dummy concave patterns on the insulating film, wherein the concave pattern is formed. The plurality of dummy concave patterns are arranged around the plurality of concave patterns.

  In the method for manufacturing a semiconductor device of the present invention, in the step of forming the concave pattern, the plurality of concave patterns may be formed in a block shape, and a plurality of dummy concave patterns are formed along the outermost region of the plurality of concave patterns. can do.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film and a step of forming a plurality of concave patterns on the insulating film, wherein the step of forming the plurality of concave patterns includes: The opening width of the concave pattern not surrounded by the other concave patterns is formed to be different from the opening width of the concave pattern surrounded by the other concave patterns.

  As mentioned above, although the structure of this invention was demonstrated, what combined these structures arbitrarily is effective as an aspect of this invention. Moreover, what converted the expression of this invention into the other category is also effective as an aspect of this invention.

  According to the present invention, in the semiconductor device, the shape variation in the depth direction of the concave pattern can be reduced.

Next, preferred embodiments of the present invention will be described with reference to the drawings.
In the following embodiments, an example will be described in which an SiOC film or SiOCN film formed by a CVD method or an MSQ film formed by a spin coating method is used as a material for an interlayer insulating film. Note that the SiOC film is sometimes referred to as a SiOCH film, and usually contains Si, O, C, and H as constituent elements. Note that the interlayer insulating film can have a laminated structure including a SiO ₂ film, a SiN film, a SiON film, and the like in addition to the SiOC film and the MSQ film.

(First embodiment)
FIG. 1 is a diagram showing the configuration of the semiconductor device according to the first embodiment of the present invention.
Although only the interlayer insulating film 110 is illustrated here, the semiconductor device includes a substrate such as silicon, and a diffusion prevention film, an etching stopper film, an antireflection film, a lower wiring layer, and the like are appropriately formed thereon. It has a configuration. Further, an upper wiring layer or the like is formed on the interlayer insulating film 110.

  In the interlayer insulating film 110, a through hole group 112 in which a plurality of through holes 102 are arranged in a matrix and an isolated through hole 114 in which one through hole 102 is arranged in isolation are formed. A plurality of dummy through holes 104 are formed around the through hole group 112. A plurality of dummy through holes 104 are also formed around the isolated through hole 114. Here, the through hole 102 is a through hole that is electrically connected to the upper layer wiring and the lower layer wiring and contributes to the electrical operation of the semiconductor device. On the other hand, the dummy through hole 104 is a through hole that does not contribute to the electrical operation of the semiconductor device. The dummy through hole 104 may be connected to either the upper layer wiring or the lower layer wiring, but is configured not to electrically connect the upper layer wiring and the lower layer wiring.

  In the present embodiment, the dummy through holes 104 are arranged so that all the through holes 102 are surrounded by at least two through holes (through hole 102 or dummy through hole 104) in the vertical direction, the horizontal direction, and the oblique direction. Is done. The arrangement pattern of the dummy through holes 104 includes the material of the interlayer insulating film 110, the type of etching gas used when forming the through holes 102 in the interlayer insulating film 110, the opening width of the through holes 102, the interval between the through holes 102, and the like. It can be set appropriately depending on the situation.

  FIG.1 (b) is A-A 'sectional drawing of Fig.1 (a). As shown in FIG. 1B, by forming a dummy through hole 104 around the through hole 102, a phenomenon of decreasing the etching rate originally generated in the through hole 102 disposed in the outer peripheral portion of the through hole group 112 is achieved. The increase phenomenon is passed on to the dummy through hole 104. Thereby, the difference in the depth of the through hole 102 caused by the difference in the etching rate is reduced, and the shape of the through hole 102 electrically connected to the lower layer wiring and the upper layer wiring can be stably and equally formed. .

  In addition, when an etching gas that lowers the etching rate of the through hole formed in the outer peripheral portion is used, the etching rate in the dummy through hole 104 is lower than the etching rate of the through hole 102, so that the depth of the through hole 102 is reduced. The dummy through hole 104 does not reach the lower wiring layer at the stage when the lower wiring layer reaches the lower wiring layer. Therefore, when the depth of the through hole 102 reaches the lower wiring layer, the etching is terminated, whereby the dummy through hole 104 can be prevented from being opened to the lower wiring layer. Thereby, after the through hole 102 and the dummy through hole 104 are formed, the conductive material is embedded in the through hole 102, and the dummy through hole is electrically connected to the lower layer wiring and the conductive material embedded in the through hole 102. Even if a conductive material is embedded in 104, the dummy through hole 104 can be prevented from being electrically connected to the lower layer wiring.

FIG. 2 is a top view showing another example of the arrangement pattern of the dummy through holes 104.
Hereinafter, the case where the etching rate of the through hole formed in the outer peripheral portion is reduced will be described, but the same arrangement pattern is also used when the etching rate of the through hole formed in the outer peripheral portion is increased. Can do.
As shown in FIG. 2A, the opening width of the dummy through hole 104 can be formed substantially equal to the opening width of the through hole 102. In this way, since the dummy through hole 104 can be formed with the same pattern diameter as the through hole 102, design design can be easily performed. In addition, when the etching rate in the through hole formed in the outer peripheral portion of the plurality of through holes is lower than the etching rate in the through hole formed in the central portion, the etching is finished when the through hole 102 reaches the lower wiring layer. By doing so, the dummy through hole 104 can be prevented from being opened to the lower wiring layer. As a result, after the through hole 102 and the dummy through hole 104 are formed, even when the conductive material is embedded in the through hole 102 when the conductive material is embedded in the through hole 102, the dummy through hole 104 is connected to the lower layer wiring. It can be prevented from being electrically connected. Therefore, the dummy through hole 104 can be formed without being restricted in place.

  Further, as shown in FIG. 2B, the opening width of the dummy through hole 104 can be formed to be wider than the opening width of the through hole 102. By increasing the opening width of the dummy through hole 104 in this way, it is possible to suppress a decrease in the etching rate of the through hole 102 formed in the vicinity of the dummy through hole 104 even if the number of dummy through holes 104 is reduced. . In this case, the dummy through hole 104 is provided in a region where a wiring or the like is not formed in the lower layer and the upper layer of the interlayer insulating film 110.

  On the other hand, as shown in FIG. 2C, the opening width of the dummy through hole 104 can be formed to be narrower than the opening width of the through hole 102. In general, the etching rate of a through hole tends to decrease as the aspect ratio of the through hole increases. Therefore, the etching rate of the dummy through hole 104 can be made lower than the etching rate of the through hole 102 by making the opening width of the dummy through hole 104 narrower than the opening width of the through hole 102. Thereby, even when the dummy through hole 104 is formed in the upper part of the lower layer wiring, the conductive material embedded in the dummy through hole 104 and the lower layer wiring can be prevented from being electrically connected. In this case, the dummy through-hole 104 can be formed without being limited in place.

  In addition, as shown in FIG. 2D, two layers of dummy through holes 104 can be provided around the through hole 102. In this case, for example, the opening width of the dummy through hole 104 in the inner layer can be reduced, and the opening width of the dummy through hole 104 in the outer layer can be made larger than the opening width of the dummy through hole 104 in the inner layer. Since the dummy through hole 104 provided on the outer side has a lower etching rate, it can be prevented from reaching the lower layer wiring even if the opening width is increased.

  In the above example, only the through hole group 112 is shown, but the same can be applied to the dummy through hole 104 formed around the isolated through hole 114.

  Further, even when the etching rate of the through hole formed in the outer peripheral portion increases, by providing the dummy through hole 104 around the periphery, the variation in the etching rate can be transferred to the dummy through hole 104, so that the semiconductor Variation in the etching rate in the through hole 102 that contributes to the electrical operation of the apparatus can be reduced.

  Further, as shown in FIG. 3, the dummy through holes 104 are arranged at a wider interval than the arrangement interval in the through hole group 112 if the dummy through holes 104 are arranged within a predetermined distance from the through hole 102 included in the through hole group 112. You can also Even in this case, it is possible to suppress a decrease or increase in the etching rate in the through hole 102 arranged on the outer peripheral portion of the through hole group 112. Thereby, the variation in the shape of the through hole 102 in the depth direction can be reduced.

  As shown in FIG. 4, when the dummy through holes 104 are provided with all the through holes 102 and a short circuit region electrically connected to the upper and lower wiring layers in the vicinity of the through holes 102, the periphery of these through holes 102 is arranged. It can be arranged to surround. Here, the hatched area in the figure is an area where both the lower layer wiring and the upper layer wiring are provided. As described above, when there is a short-circuit region in which both the lower-layer wiring and the upper-layer wiring are formed, the dummy through hole 104 is provided around the short-circuit region.

(Second embodiment)
FIG. 5 is a diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention.
In the present embodiment, dummy through holes are not provided, but the through holes 102 included in the through hole group 112 are formed so that the opening width is wider as the through holes 102 are provided in the outer peripheral portion.

  For example, the opening width of the through hole 102c arranged in the outermost region of the through hole group 112 is formed to be wider than the opening width of the through hole 102b arranged inside thereof. In addition, the opening width of the through hole 102b is formed to be wider than the opening width of the through hole 102a disposed in the center. Furthermore, the opening width of the isolated through hole 114 is formed wider than the opening width of the through hole 102 c arranged in the outermost region of the through hole group 112.

  In this case, the etching rate of the through hole 102b and the through hole 102c arranged in the outer peripheral portion of the isolated through hole 114 and the through hole group 112 is set to the through hole arranged in the central portion of the through hole group 112 by the microloading effect. The etching rate of the hole 102a can be made higher. As a result, the phenomenon of a decrease in etching rate due to the through hole 102b and the through hole 102c formed in the outer peripheral portion of the through hole group 112 and the isolated through hole 114 can be canceled, and all the through holes included in the through hole group 112 can be eliminated. Variations in the etching rate of the holes 102a, 102b, and 102c and the isolated through hole 114 can be reduced. Thereby, the variation in the shape of the plurality of through holes 102 in the depth direction can be reduced.

  Further, when the etching rate of the through hole formed in the outer peripheral portion increases, the opening width can be formed so that the through hole 102 provided in the outer peripheral portion becomes narrower. By reducing the opening width of the through hole 102 in the outer peripheral portion, an increase in the etching rate of the through hole 102 in the outer peripheral portion can be reduced. Thereby, the variation in the etching rate of the plurality of through holes 102 can be reduced.

FIG. 6 is a diagram showing a pattern in which dummy through holes 104 are formed around a through hole group including a plurality of through holes 102.
An interlayer insulating film 110 made of SiOC is formed on a silicon substrate by CVD, and through holes 102 and dummy through holes 104 (both having a hole diameter of 0. 2 μm, 1 μm interval).
Etching gas: flow rate Ar / CF ₄ / CH ₂ F ₂ / N ₂ = 500/30/10/90 sccm, pressure 50 mTorr, RF power 1300 W

  FIG. 7 is a diagram showing the results. When the dummy through hole 104 was not formed, the etching rate of the through hole c and the through hole d arranged on the outer peripheral portion of the through hole group formed in a matrix and the through hole e formed in a row decreased. . On the other hand, by forming the dummy through holes 104 around these through holes, it is possible to suppress a decrease in the etching rate in the through hole c, the through hole d, and the through hole e. Can be made substantially even. As a result, the shape variation in the depth direction of the plurality of through holes a, through holes b, through holes c, through holes d, and through holes e can be reduced and made substantially equal.

  Although not shown here, by forming dummy through holes 104 around the isolated through holes as well, a decrease in the etching rate can be suppressed, and a through hole arranged at the center of the through hole group can be suppressed. The etching rate in a and through hole b can be made equal, and the shape variation in the depth direction can be reduced.

  As described above, the mechanism by which the variation in the etching rate of the through-hole 102 can be reduced by forming the dummy through-hole 104 around the through-hole 102 is not clear, but it is presumed as follows. Can do.

In the literature (Applied Physics, Vol. 70, No. 4, pp. 387 to 397, 2001), in etching of SiO ₂ film using fluorocarbon plasma, a polymer layer is formed on the etching surface, and this thickness is It is described that it is determined mainly by the amount of incident etching active species CF _{x and} the amount of oxygen (O) in the film. Considering this result, in the case of the SiOC film, the composition ratio of oxygen is low, and carbon (C) is present in the film, so that the polymer layer may be formed thicker than the SiO ₂ film. Inferred.

The amount of the etching active species CF _x incident from the plasma does not depend on the pattern. On the other hand, when the insulating film is etched, an etching gas reaction product having an action of removing the polymer is generated. Here, the etching gas reaction product is a compound of Si and F, a compound of C and F, and a compound of O. This etching gas reaction product is released from the region to be etched and stays immediately above the pattern. Therefore, it is estimated that the concentration of the etching gas reaction product is high at the center of the pattern group and low at the outer periphery of the pattern or the isolated pattern. As a result, the outer periphery of the pattern group and the polymer layer of the isolated pattern are formed thicker than the pattern group center. It is considered that the range in which the effect of the etching gas reaction product is within about several hundred μm from the etched region. Therefore, by forming the dummy through hole 104 around the through hole 102, the amount of the etching gas reaction product that reaches the through hole 102 provided in the outer peripheral portion can be increased, and the through hole provided in the central portion can be increased. It is considered that variation in the etching rate in the hole 102 could be reduced.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  In the first embodiment, an example in which a plurality of through holes 102 are formed in a matrix is shown. However, the through holes 102 may be arranged as shown in FIGS. In this case, the dummy through hole 104 can be configured as shown in FIGS. Hereinafter, each figure will be described.

  As shown in FIG. 11, the plurality of through holes 102 can include randomly arranged regions, regions arranged at a wide interval, and regions arranged in an uneven shape. In this case, dummy through holes 104 can be arranged around these regions.

  Further, as shown in FIG. 12A, the through hole 102 can be arranged other than a square. Also in this case, the dummy through holes 104 can be arranged around the plurality of through holes 102. Furthermore, as shown in FIG. 12 (b), the arrangement can be such that the interval between the through holes 102 varies depending on the location.

  Further, as shown in FIG. 13, the plurality of through holes 102 can be arranged in a comb shape. When the through holes 102 are arranged in a comb shape as described above, when the interval between the comb teeth portions of the through holes 102 is wide, the dummy through holes 104 are provided between the comb teeth as shown in FIG. You can also. Thereby, it can be set as the structure which provided the dummy through-hole 104 around the through-hole group 112. FIG.

  FIG. 14 is a diagram schematically illustrating a part of the configuration of the entire circuit in which a plurality of through-hole groups 112 are formed. Thus, in the dummy through hole 104, the through hole 102 is formed along the outer peripheral portion of the through hole group 112. As a result, even if the etching rate varies in the outer peripheral portion of the plurality of through holes, such variation occurs in the dummy through hole 104. Therefore, the etching rate of the plurality of through holes contributing to the electrical operation of the semiconductor device is increased. Variations can be reduced.

  In the above embodiment, the through hole has been described as an example, but the same can be applied to the wiring groove. By forming dummy wiring grooves and through holes around the outer peripheral portion and the isolated wiring grooves, variation in etching rate due to the arrangement state of the plurality of wiring grooves can be reduced. In addition, a dummy wiring groove may be formed around the plurality of through holes.

It is a figure which shows the structure of the semiconductor device in embodiment of this invention. It is a top view which shows the arrangement pattern of a dummy through hole. It is a top view which shows the other example of the arrangement pattern of a dummy through hole. It is a top view which shows the other example of the arrangement pattern of a dummy through hole. It is a figure which shows the structure of the semiconductor device in embodiment of this invention. It is a figure which shows the arrangement pattern of the through hole in an Example. It is a figure which shows the etching rate at the time of forming the through hole of the arrangement pattern shown in FIG. It is a figure which shows the phenomenon which arises when using a SiOC film | membrane as an interlayer insulation film and forming a through hole. It is a figure which shows an etching rate when forming a through hole using fluorocarbon type | system | group etching gas. It is a figure which shows the etching rate at the time of changing the kind of interlayer insulation film, and etching gas. It is a top view which shows the other example of the arrangement pattern of a dummy through hole. It is a top view which shows the other example of the arrangement pattern of a dummy through hole. It is a top view which shows the other example of the arrangement pattern of a dummy through hole. It is a figure which shows typically a part of structure of the whole circuit in which the several through-hole group was formed. It is a top view which shows the other example of the arrangement pattern of a dummy through hole.

Explanation of symbols

102 through-holes, 104 dummy through-holes, 110 interlayer insulating film, 112 through-hole group, 114 isolated through-holes.

Claims (8)

An insulating film;
A plurality of concave patterns formed in the insulating film;
A plurality of dummy concave patterns formed on the insulating film and disposed around the plurality of concave patterns;
A semiconductor device comprising: The plurality of concave patterns are formed in a block shape,
The semiconductor device according to claim 1, wherein the dummy concave pattern is formed along an outermost region of the plurality of concave patterns.   The semiconductor device according to claim 1, wherein the dummy concave pattern is formed shallower than a depth of the plurality of concave patterns.   The semiconductor device according to claim 1, wherein an aspect ratio of the dummy concave pattern is lower than an aspect ratio of the plurality of concave patterns. An insulating film;
A plurality of concave patterns formed in the insulating film;
Including
Of the plurality of concave patterns, a semiconductor is formed such that an opening width of a concave pattern not surrounded by another concave pattern is different from an opening width of a concave pattern surrounded by another concave pattern apparatus. Forming an insulating film;
Forming a plurality of concave patterns and a plurality of dummy concave patterns on the insulating film;
Including
In the step of forming the concave pattern, the plurality of dummy concave patterns are arranged around the plurality of concave patterns.   The step of forming the concave pattern includes forming the plurality of concave patterns in a block shape and forming the plurality of dummy concave patterns along an outermost region of the plurality of concave patterns. 6. A method for manufacturing a semiconductor device according to 6. A method for manufacturing a semiconductor device, comprising:
Forming an insulating film;
Forming a plurality of concave patterns in the insulating film;
Including
In the step of forming the plurality of concave patterns, the opening width of the concave pattern not surrounded by the other concave patterns among the plurality of concave patterns is different from the opening width of the concave pattern surrounded by the other concave patterns. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device.

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