JP2005074958A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor wherein the number of accesses to an external memory at a low access speed is reduced when executing a drawing process with CPU resources, thereby enhancing CPU performance. <P>SOLUTION: One chip is provided with: a CPU for interpreting data from a host device and execute the drawing process for developing the interpreted data; a built-in memory for storing the developed data from the CPU; and a transferring means for transferring the data stored in the built-in memory to the external memory for storing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus and a data processing method for performing drawing using a central processing unit (integrated circuit chip).

  In an electrophotographic printer typified by a laser beam printer, print data (code data, image data, etc.) is received from an external device such as a host computer, and bitmap data based on the received print data. After the expansion is completed, the expanded bitmap data is output to the printer engine as video data.

Since this type of drawing processing has a heavy load, conventionally, a drawing circuit is configured by dedicated hardware independent of a CPU (central processing unit) (see, for example, Patent Document 1).
JP-A-9-11548

  However, when drawing logic is assembled with a dedicated hardware circuit, it is necessary to recreate the hardware every time the version is upgraded, and there is a demerit that a great development cost is required.

  Therefore, it is conceivable to perform a drawing process using a recent CPU whose performance has been significantly improved. Recently, since the performance of the CPU has been improved, even if the drawing process using the CPU is performed, the processing time by the dedicated drawing circuit has become comparable.

  However, since the peripheral memory is low speed even when the CPU speed is increased, the CPU wait time increases when the frequency of access to the memory increases, and the CPU performance cannot be sufficiently exhibited.

  Accordingly, the present invention provides a data processing apparatus and data processing that can reduce the number of accesses to a memory having a slow access speed and improve the performance of the central processing unit when performing drawing processing using the resources of the central processing unit. It aims to provide a method.

  In addition, the present invention provides a data processing apparatus and a data processing method capable of speeding up drawing processing and further improving performance when drawing processing is performed using resources of a central processing unit. For other purposes.

  In order to achieve the above object, a data processing apparatus of the present invention interprets processing data, performs first processing for expanding the interpreted data, and stores first drawing data expanded by the calculating device. And a transfer means for performing a transfer process to store the drawing data in a second memory different from the internal memory when the drawing data is accumulated in a predetermined unit in the first memory. Are provided on a single integrated circuit chip, wherein the second memory exists outside the integrated circuit chip.

  In addition, a plurality of the first memories are provided in the integrated circuit chip, and the drawing data developed in band units by the computing means is stored in the first memory in the band units. .

  In addition, when drawing data is stored in the first memory for a predetermined unit, the drawing means has compression means for compressing the drawing data, and the transfer means stores the data compressed by the compression means in the second memory. It is characterized by transferring.

  And a decompression unit that decompresses the compressed data stored in the second memory, and the transfer unit forwards the drawing data decompressed by the decompression unit to a video output interface connected to the integrated circuit chip. It is characterized by that.

  A data processing method according to the present invention is a data processing method executed by a single integrated circuit chip, which interprets input data and develops it into drawing data, and is developed in the development step. A storage step of storing the drawing data; and a transfer step of transferring the data to a storage unit provided outside the integrated circuit chip when the drawing data is stored for a predetermined unit in the storage step. .

  Further, when the drawing data is stored for a predetermined unit in the storing step, it further includes a compression step for compressing the data, and in the transfer step, the data compressed in the compression step is stored outside the integrated circuit chip. It transfers to the said memory | storage part provided in (3), It is characterized by the above-mentioned.

  Further, the method further includes a decompression step of acquiring the compressed data provided outside the integrated circuit chip and performing decompression processing on the data, and in the transfer step, the drawing data decompressed in the decompression step is used as the integrated circuit. It transfers to the video output interface connected to the chip.

  According to the present invention, when the drawing process is performed using the resources of the calculation means, the number of accesses to the memory outside the integrated circuit chip having a low access speed can be reduced, and the performance of the calculation means can be improved. . Furthermore, since the drawing is performed in the first memory in the same chip as the arithmetic means, the first memory can be accessed quickly, so that the drawing process can be performed at a high speed and the performance can be further improved. Become.

  Embodiments of a data processing apparatus and a data processing method of the present invention will be described with reference to the drawings. The data processing apparatus and data processing method of the present embodiment are applied to a printing apparatus.

[First Embodiment]
<Schematic configuration of printing device>
FIG. 1 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the first embodiment of the present invention.

  This printing apparatus includes a PDL controller unit 1 having a characteristic configuration in which a CPU and a drawing band memory are incorporated in the same chip (an ASIC chip 10 described later), and a printer engine unit 2. The PDL controller unit 1 is a special specification IC chip (hereinafter abbreviated as ASIC chip) 10 that controls all of the PDL controller unit 1 and a memory (external memory) arranged outside the ASIC chip 10. A DRAM 106 and a ROM 108 and a display panel 110 are provided.

  In the ASIC chip 10, reference numeral 101 in the figure denotes a CPU incorporating a primary cache memory 102, reference numeral 103 denotes an I / F circuit that controls an interface with the CPU 101, and reference numeral 104 denotes a bus switch circuit that switches various buses. Reference numeral 105 denotes a DRAM controller that exchanges data with the DRAM 106 that is an external memory, and reference numeral 107 denotes a ROM controller that exchanges data with the ROM 108 that is an external memory. Reference numeral 109 denotes an I / F circuit 109 that controls an interface with the display panel 110, and reference numeral 111 denotes an I / F circuit that exchanges data with an external host computer.

  Reference numeral 112 denotes a RAM controller that controls data exchange when the CPU 101 accesses the drawing RAM 113. Reference numeral 114 denotes a RAM controller that also controls access to the drawing RAM 115. The drawing RAMs 113 and 115 each have 1 It has a size that can store the development data for the band. Reference numeral 116 denotes a DMA controller that transfers development data from the drawing RAMs 113 and 115 to the DRAM 106. Reference numeral 117 denotes a DMA controller that reads the data stored in the DRAM 106 and then transfers the development data to the video I / F circuit 118. is there. The video I / F circuit 118 is an interface circuit for sending the development data to the printer engine 2. The printer engine 2 includes a mechanism for receiving the development data and printing it on paper.

<Operation of First Embodiment>
Next, the operation of the PDL controller unit 1 of the present embodiment shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a schematic diagram showing the operation of the PDL controller unit 1 of this embodiment, and FIG. 3 is a diagram for explaining the operation when the print data is divided into a plurality of bands.

  In FIG. 2, when the PDL controller 1 receives a PDL code from an external host computer via the host I / F 111, the PDL controller 1 temporarily stores it in the DRAM 106. The stored PDL code is read by the CPU 101 via the DRAM controller 105 and the CPU-I / F circuit 103 (T1 in FIG. 2), interpreted, further expanded, and expanded in the first band shown in FIG. Data is stored in the drawing RAM 113 via the CPU-I / F circuit 103 and the RAM controller 112 (T2).

  When storing the development data of the first band in the drawing RAM 113 is completed, the DMA controller 116 reads the development data from the drawing RAM 113 via the RAM controller 112 (T3) and stores it in the DRAM 106 via the RAM controller 105. (T4). At that time, the CPU 101 interprets and further expands the PDL code of the second band (T5), and converts the expanded data of the second band to the drawing RAM 115 via the CPU-I / F circuit 103 and the RAM controller 114. (T6).

  Similarly, when the development data for the second band is stored in the drawing RAM 115, the DMA controller 116 reads the development data from the drawing RAM 115 via the RAM controller 114 (T 7), and stores it in the DRAM 106 via the RAM controller 105. Store (T8). At that time, the CPU 101 interprets and further expands the third-band PDL code, and stores the third-band expanded data in the drawing RAM 113 via the CPU-I / F circuit 103 and the RAM controller 112.

  By repeating the above, drawing data for one page is developed and stored in the DRAM 106.

  The DMA controller 117 is activated when the drawing data for one page has been stored, reads the drawing data stored in the DRAM 106 via the DRAM controller 105 (T9), and transfers it to the video I / F circuit 118 ( T10). The video I / F circuit 118 converts the drawing data into the engine I / F specification and transfers it to the printer engine 2.

  Here, once expanded font data or the like is stored in the primary cache memory 102. When the font data needs to be expanded again, the font data stored in the primary cache memory 102 is called by We are trying to improve performance. The bus switch 104 controls the bus switching so that a plurality of bus masters do not collide.

  As described above, in the present embodiment, when drawing processing is performed using CPU resources, drawing RAMs 113 and 115 for a plurality of bands are built in the same chip as the CPU 101, and drawing data is transferred to the external memory 106. Since the transfer is performed after the drawing process is performed instead of the drawing process, the number of accesses to the external memory 106 can be significantly reduced. Further, since the development data is drawn in the drawing RAMs 113 and 115 in the same chip as the CPU 101, the writing / reading access to the drawing RAMs 113 and 115 can be performed quickly, so that the drawing process can be performed at high speed.

[Second Embodiment]
FIG. 4 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the second embodiment of the present invention.

  In the present embodiment, an example in which three drawing RAMs are arranged on the ASIC chip 10 is shown. Specifically, in the configuration shown in FIG. 1, a drawing RAM 121 is added as a third drawing RAM, and a RAM controller 120 for controlling writing / reading of the drawing RAM 121 is further provided.

  As in the first embodiment, the CPU 101 can perform write / read access to the drawing RAM 121 via the CPU-I / F circuit 103 and the RAM controller 120. The DMA controller 116 can also freely access the drawing RAM 121 via the RAM controller 120.

<Operation of Second Embodiment>
FIG. 5 is a schematic diagram showing the operation of the PDL controller unit 1 of the present embodiment.

  The PDL code once stored in the DRAM 106 is read by the CPU 101 (T11 in FIG. 5), interpreted and expanded as in the first embodiment, and the expanded data of the first band shown in FIG. 3 is drawn. It is stored in the RAM 113 (T12).

  When the development data for the first band has been stored in the drawing RAM 113, the DMA controller 116 reads the development data from the drawing RAM 113 (T13) and stores it in the DRAM 106 (T14). At that time, the CPU 101 interprets the PDL codes (T21, T31) of the second band and the third band, further develops them, and develops the developed data of the second band and the third band via the RAM controllers 114 and 120, respectively. Are stored in the drawing RAMs 115 and 121 (T22, T32).

  When the development data for the second band is stored in the drawing RAM 115, the DMA controller 116 reads the development data from the drawing RAM 115 (T23) and stores it in the DRAM 106 (T24).

  Next, the CPU 101 starts interpretation of the fourth band PDL code (T11), and further expands the expanded data of the third band and the fourth band, respectively, to the CPU-I / F circuit 103, the RAM controller 120, The image data is stored in the drawing RAMs 121 and 113 via 112 (T32, T12).

  When the expansion data of the third band has been stored in the drawing RAM 121, the DMA controller 116 reads the expansion data from the drawing RAM 121 (T33) and stores it in the DRAM 106 (T34).

  By repeating the above, drawing data for one page is developed and stored in the DRAM 106.

  The DMA controller 117 is activated when the drawing data for one page has been stored, reads the drawing data stored in the DRAM 106 via the DRAM controller 105 (T35), and transfers it to the video I / F circuit 118 ( T36). The video I / F circuit 118 converts the transferred drawing data into an I / F specification of the engine and transfers it to the printer engine 2.

  As described above, in this embodiment, since the drawing RAM has three bands, the buffer memory for drawing increases. Therefore, even in a system that takes time to transfer the development data, the CPU 101 reduces the waiting time to the drawing RAM. , Can improve performance.

[Third Embodiment]
FIG. 6 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the third embodiment of the present invention.

  This embodiment has a configuration in which three drawing RAMs are arranged on the ASIC chip 10, but the feature is that the developed data is directly transferred to the video I / F circuit 118 without being stored in the DRAM 106 which is an external memory. is there. Therefore, as the configuration, there is only one DMA controller arranged in the configuration of the second embodiment.

<Operation of Third Embodiment>
FIG. 7 is a schematic diagram showing the operation of the PDL controller unit 1 of the present embodiment.

  When receiving the PDL code from the external host computer, the PDL controller 1 temporarily stores it in the DRAM 106. The stored PDL code (T41, T51, T61) is interpreted by the CPU 101 and further expanded, and the expanded data of the first band shown in FIG. 3 is drawn via the CPU-I / F circuit 103 and the RAM controller 112. The developed data for the second band is stored in the drawing RAM 115 (T52) via the CPU-I / F circuit 103 and the RAM controller 114 (T52).

  When storing the development data of the first band and the second band in the drawing RAMs 113 and 115, the DMA controller 116 reads the development data of the first band from the drawing RAM 113 via the RAM controller 112 (T43), Transfer to the video I / F circuit 118 (T44). The video I / F circuit 118 converts the expanded data into the I / F specification of the printer engine 2 and transfers it to the printer engine 2. At this time, the developed data of the third band is stored in the drawing RAM 121 via the CPU-I / F circuit 103 and the RAM controller 120 (T62).

  Thereafter, the same operation is repeated, and the developed data of the second band to the N band are read from the drawing RAMs 113, 115, 121 (T43, T53, T63) and transferred to the video I / F circuit 118 (T44). , T54, T64).

  As described above, in this embodiment, when the decompressed data stored in the drawing RAM 113, 115, or 121 is read out via the RAM controller 112, 114, or 120, the DMA controller 116 directly transfers the video I without transferring it to the DRAM 106. Since the data is transferred to the / F circuit 118, the data transfer bottleneck from the RAM controller 105 to the DRAM 106 does not occur as a result of no access to the DRAM 106, and the performance can be improved as compared with the first and second embodiments. it can.

[Fourth Embodiment]
FIG. 8 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the fourth embodiment of the present invention.

  The configuration of the printing apparatus of the present embodiment is such that an encoder 216 and a decoder 217 are provided instead of the DMA controllers 116 and 117 in the configuration of the first embodiment shown in FIG. The encoder 216 has a function of reading and compressing the decompressed data from the drawing RAMs 113 and 115 via the RAM controllers 112 and 114, respectively, and then transferring the compressed data to the external memory 106. The decoder 217 stores the compressed data from the external memory 106. It has a function of transferring to the video I / F circuit 118 after reading and decompressing.

<Operation of Fourth Embodiment>
FIG. 9 is a schematic diagram showing the operation of the PDL controller unit 1 of the present embodiment.

  When the first band development data has been stored in the drawing RAM 113 (S1, S2 in FIG. 9) in the same process as in the first embodiment described above, the encoder 216 draws the development data via the RAM controller 112. The data is read from the RAM 113 (S3), further compressed, and the compressed data is stored in the external memory 106 via the RAM controller 105 (S4). At that time, the CPU 101 interprets the PDL code of the second band, further expands it, and stores the expanded data of the second band in the drawing RAM 115 via the CPU-I / F circuit 103 and the RAM controller 114 ( S5, S6).

  Similarly, when the development data for the second band is stored in the drawing RAM 115, the encoder 216 reads the development data from the drawing RAM 115 via the RAM controller 114 (S7), and further compresses the compressed data. Is stored in the external memory 106 via the RAM controller 105 (S8). At that time, the CPU 101 interprets and further expands the third-band PDL code (S1), and stores the third-band expanded data in the drawing RAM 113 via the CPU-I / F circuit 103 and the RAM controller 112. (S2).

  By repeating the above, drawing data for one page is expanded, further compressed, and stored in the external memory 106.

  As described above, in the present embodiment, when drawing processing is performed using CPU resources, drawing RAMs 113 and 115 and encoders (compression circuits) 216 for a plurality of bands are built in the same chip as the CPU 101, and drawing data is stored. Since the data is transferred to the external memory 106 after the expansion / compression process, the number of accesses to the external memory 106 having a low access speed can be significantly reduced.

[Fifth Embodiment]
FIG. 10 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the fifth embodiment of the present invention.

  The configuration of the printing apparatus of this embodiment is the same as that of the second embodiment in which three drawing RAMs are arranged on the ACIC chip 10 shown in FIG. 216 and a decoder 217 are provided. The encoder 216 and the decoder 217 have the same functions as those described above.

  As in the first embodiment, the CPU 101 can perform writing / reading access to the drawing RAM 121 via the CPU-I / F circuit 103 and the RAM controller 120, and the encoder 216 also uses the RAM controller 120. Thus, the drawing RAM 121 can be freely accessed.

<Operation of Fifth Embodiment>
FIG. 11 is a schematic diagram showing the operation of the PDL controller unit 1 of the present embodiment.

  When the first band development data has been stored in the drawing RAM 113 by the same processing as in the second embodiment described above (S11, S12 in FIG. 11), the encoder 216 reads the development data from the drawing RAM 113 (S13). Further, compression is performed, and the compressed data is stored in the DRAM 106 via the RAM controller 105 (S14). At that time, the CPU 101 interprets the PDL codes (S21, S31) of the second band and the third band, develops them, and develops the developed data of the second band and the third band via the RAM controllers 114 and 120, respectively. Are stored in the drawing RAMs 115 and 121 (S22, S32).

  When the expansion data of the second band is stored in the drawing RAM 115, the encoder 216 reads the expansion data from the drawing RAM 115 (S23), further compresses it, and stores the compressed data in the DRAM 106 (S24).

  Next, the CPU 101 starts to interpret the PDL code (S11) for the fourth band, further expands it, and develops the expanded data for the third band and the fourth band, respectively, to the CPU-I / F circuit 103 and the RAM controller 120. , 112 are stored in the drawing RAMs 121, 113 (S32, S12).

  When the expansion data of the third band is stored in the drawing RAM 121, the encoder 216 reads the expansion data from the drawing RAM 121 (S33), further compresses it, and stores the compressed data in the DRAM 106 (S34).

  By repeating the above, drawing data for one page is expanded, further compressed, and stored in the DRAM 106.

  The decoder 117 is activated when the drawing data for one page has been stored, reads the compressed drawing data stored in the DRAM 106 via the DRAM controller 105 (S35), and further decompresses the data to the video I / F circuit. The data is transferred to 118 (S36). The video I / F circuit 118 converts the decompressed drawing data into the I / F specification of the printer engine 2 and transfers it to the printer engine 2.

  As described above, in this embodiment, since the drawing RAM has three bands, the buffer memory for drawing increases, so even in a system that takes time to compress and transfer drawing data, the drawing waiting time is reduced. Performance degradation can be avoided.

[Sixth Embodiment]
FIG. 12 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to the sixth embodiment of the present invention.

  This embodiment is characterized in that two drawing RAMs and one compressed data storage RAM are arranged on the same chip (ASIC chip 10). In the figure, reference numeral 123 denotes a compressed data storage RAM, and reference numeral 122 denotes a RAM controller that performs writing / reading control on the compressed data storage RAM 123.

  In this embodiment, the encoder 216 has a function of reading the decompressed data from the drawing RAM 113 or 115 and compressing the decompressed data and writing the compressed data into the compressed data storing RAM 123 via the RAM controller 122. The decoder 217 can freely access the compressed data storage RAM 123 via the RAM controller 122. When the compressed data is read from the compressed data storage memory 123, the compressed data is decompressed and the video I / F is read out. It has a function of transferring to the circuit 117.

<Operation of Sixth Embodiment>
FIG. 13 is a schematic diagram showing the operation of the PDL controller unit 1 of the present embodiment.

  When the first band development data has been stored in the drawing RAM 113 by the same processing as in each of the embodiments described above (S41, S42), the encoder 216 reads the development data from the drawing RAM 113 via the RAM controller 112 ( In step S43, the data is further compressed, and the compressed data is stored in the compressed data storage RAM 123 via the RAM controller 122 (S44). At that time, the CPU 101 interprets the PDL code (S51) of the second band, develops it, and develops the developed data of the second band to the drawing RAM 115 via the CPU-I / F circuit 103 and the RAM controller 114. Store (S52).

  When the development data of the second band is stored in the drawing RAM 115, the encoder 216 reads the development data from the drawing RAM 115 via the RAM controller 114 (S53), further compresses the compressed data, and stores the compressed data in the RAM controller 122. And stored in the compressed data storage RAM 123 (S54).

  When the compressed data is stored in the compressed data storage RAM 123 to some extent, the decoder 217 is activated, reads the compressed data stored in the compressed data storage RAM 123 via the DRAM controller 122 (S55), and further decompresses it. Then, the data is transferred to the video I / F circuit 118 (S56). The video I / F circuit 118 converts the decompressed drawing data into the I / F specification of the printer engine 2 and transfers it to the printer engine 2.

  As described above, in this embodiment, in addition to the two drawing RAMs 113 and 115, one compressed data storage RAM 123 is arranged, so that the encoder 216 and the decoder 217 can access not the external memory 106 but the internal high speed. Since the memory 123 can be accessed, compression / decompression can be accelerated. Further, the number of accesses to the external memory 106 is remarkably reduced, and the occurrence of a data transfer neck from the RAM controller 105 to the external memory 106 can be suppressed.

1 is a block diagram showing an electrical configuration of a printing apparatus equipped with a data processing apparatus according to a first embodiment of the present invention. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 1st this embodiment. It is a figure explaining operation | movement at the time of dividing print data into several bands. It is a block diagram which shows the electric constitution of the printing apparatus by which the data processing apparatus which concerns on 2nd Embodiment of this invention is mounted. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 2nd Embodiment. It is a block diagram which shows the electric constitution of the printing apparatus by which the data processing apparatus which concerns on 3rd Embodiment of this invention is mounted. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 3rd Embodiment. It is a block diagram which shows the electric constitution of the printing apparatus by which the data processor which concerns on 4th Embodiment of this invention is mounted. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 4th Embodiment. It is a block diagram which shows the electric constitution of the printing apparatus by which the data processing apparatus which concerns on 5th Embodiment of this invention is mounted. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 5th Embodiment. It is a block diagram which shows the electric constitution of the printing apparatus by which the data processing apparatus which concerns on 6th Embodiment of this invention is mounted. It is a schematic diagram which shows operation | movement of the PDL controller part 1 of 6th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 PDL controller part 2 Printer engine part 10 ASIC chip 101 in PDL controller CPU
102 Primary cache memory 103 CPU-I / F
104 Bus switch circuit 105 DRAM controller 106 DRAM
107 ROM controller 108 ROM
109 Panel I / F
110 Panel 111 Host I / F
112, 114, 120, 122 RAM controller 113, 115, 121 Rendering RAM
116, 117 DMA controller 118 Video I / F circuit 123 RAM for storing compressed data
216 Encoder 217 Decoder

Claims (7)

An arithmetic unit that interprets the processing data and performs processing for expanding the interpreted data, a first memory that stores the drawing data expanded by the arithmetic unit, and the drawing data stored in the first memory A data processing device provided with a transfer means for performing a transfer process for storing the drawing data in a second memory different from the internal memory when the unit data is stored in one integrated circuit chip. ,
The data processing apparatus according to claim 1, wherein the second memory exists outside the integrated circuit chip.   A plurality of the first memories are provided in the integrated circuit chip, and the drawing data developed in band units by the arithmetic means is stored in the first memories in the band units. The data processing apparatus according to 1.   When drawing data is accumulated in a predetermined unit in the first memory, the drawing means has compression means for compressing the drawing data, and the transfer means transfers the data compressed by the compression means to the second memory. The data processing apparatus according to claim 1.   Expansion means for expanding compressed data stored in the second memory, and the transfer means transfers drawing data expanded by the expansion means to a video output interface connected to the integrated circuit chip. 4. The data processing apparatus according to claim 3, wherein A data processing method performed on a single integrated circuit chip comprising:
An unfolding process that interprets input data and unfolds it into drawing data;
A storage step of storing the drawing data expanded in the expansion step;
When the drawing data is stored for a predetermined unit in the storage step, a transfer step of transferring the data to a storage unit provided outside the integrated circuit chip;
Data processing method to execute.   When the drawing data is stored for a predetermined unit in the storing step, the drawing step further includes a compression step for compressing the data, and the transfer step provides the data compressed in the compression step outside the integrated circuit chip. The data processing method according to claim 5, wherein the data is transferred to the storage unit.   The method further includes a decompression step of acquiring the compressed data provided outside the integrated circuit chip and subjecting the data to decompression processing. In the transfer step, the drawing data decompressed in the decompression step is stored in the integrated circuit chip. 7. The data processing method according to claim 6, wherein the data is transferred to a connected video output interface.

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