JP2005073342A - Packaging structure of semiconductor device - Google Patents

Packaging structure of semiconductor device Download PDF

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JP2005073342A
JP2005073342A JP2003297833A JP2003297833A JP2005073342A JP 2005073342 A JP2005073342 A JP 2005073342A JP 2003297833 A JP2003297833 A JP 2003297833A JP 2003297833 A JP2003297833 A JP 2003297833A JP 2005073342 A JP2005073342 A JP 2005073342A
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electrode plate
insulating
semiconductor
holding member
semiconductor element
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JP4075734B2 (en
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Hiroshi Ishiyama
弘 石山
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Denso Corp
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Denso Corp
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Priority to JP2003297833A priority Critical patent/JP4075734B2/en
Application filed by Denso Corp filed Critical Denso Corp
Priority to US10/554,998 priority patent/US7508668B2/en
Priority to EP10004702A priority patent/EP2216892B1/en
Priority to PCT/JP2004/011970 priority patent/WO2005020276A2/en
Priority to EP10004700A priority patent/EP2216890B1/en
Priority to EP10004701A priority patent/EP2216891B1/en
Priority to EP04771931A priority patent/EP1657806B1/en
Publication of JP2005073342A publication Critical patent/JP2005073342A/en
Priority to US12/073,871 priority patent/US7724523B2/en
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Publication of JP4075734B2 publication Critical patent/JP4075734B2/en
Priority to US12/457,245 priority patent/US7826226B2/en
Priority to US12/457,246 priority patent/US8027161B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide the packaging structure of a semiconductor device in which releasing of noise generated at a semiconductor element is effectively suppressed without externally attaching a bypass capacitor. <P>SOLUTION: The semiconductor device comprises a power semiconductor element, first and second electrode plates jointed to one and the other surfaces of the semiconductor element, a connection terminal for a control circuit that controls the semiconductor element, a semiconductor module 30 comprising an insulating resin mold for sealing the semiconductor element and the first and second electrode plates, and conductive first and second holding members 55A and 55B for holding from both sides the semiconductor module through first and second insulating members 50A and 50B that are to be derivatives. The first and/or the second electrode plate, the first and/or the second holding member, and the first and/or the second insulating member constitute noise suppressing bypass capacitors 57A and 57B which prevent the noise generated at the semiconductor element from being released to a bus bar. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体装置の実装構造、特にインバータ装置として使用される半導体装置におけるノイズの抑制に関する。   The present invention relates to a semiconductor device mounting structure, and more particularly to noise suppression in a semiconductor device used as an inverter device.

直流電源の直流をインバータ装置(半導体装置)で交流に変換し、交流機を駆動することがある。例えば電気自動車及びハイブリッド自動車では、図19に示すように、バッテリ500の直流をインバータ装置510で交流に変換し、交流発電機505を駆動するようになっている。インバータ装置510は複数の半導体モジュールを含む。   The direct current of the direct current power source may be converted into alternating current by an inverter device (semiconductor device) to drive the alternating current machine. For example, in an electric vehicle and a hybrid vehicle, as shown in FIG. 19, the direct current of the battery 500 is converted into alternating current by the inverter device 510, and the alternating current generator 505 is driven. Inverter device 510 includes a plurality of semiconductor modules.

良く知られているように、各半導体モジュールは内部の半導体素子(スイッチ素子)511と、その両側の一対の電極と、外部の制御回路に接続する信号端子とを有する。制御回路から信号端子を介して入力される制御信号により半導体素子がスイッチングされ、擬似的な交流を発生する。   As is well known, each semiconductor module has an internal semiconductor element (switch element) 511, a pair of electrodes on both sides thereof, and a signal terminal connected to an external control circuit. The semiconductor element is switched by a control signal input from the control circuit via a signal terminal, and a pseudo alternating current is generated.

半導体モジュールの作動時、その通電部に高周波のノイズが発生し、直流電力線514、515及び交流電力線516から放出される。これを防止するために、直流電力線514,515とアースとの間、及び交流電力線516とアースとの間にリード線526を介して高周波コンデンサ521,522及び523を接続し、ノイズ成分をバイパスするようになっている。   During the operation of the semiconductor module, high-frequency noise is generated in the energization portion and is emitted from the DC power lines 514 and 515 and the AC power line 516. In order to prevent this, the high frequency capacitors 521, 522 and 523 are connected via the lead wire 526 between the DC power lines 514 and 515 and the ground, and between the AC power line 516 and the ground, thereby bypassing the noise component. It is like that.

一方、図20に示す従来の自励式整流回路(特許文献1参照)は、商用電源530から供給される交流を所望の直流電圧に変換する自励式整流回路部532及び535を含む。整流回路部535を構成する整流素子536のスイッチ動作に起因して発生するノイズが商用電源530に流入し、悪影響を及ぼす。   On the other hand, the conventional self-excited rectifier circuit shown in FIG. 20 (see Patent Document 1) includes self-excited rectifier circuits 532 and 535 that convert alternating current supplied from the commercial power supply 530 into a desired direct-current voltage. Noise generated due to the switching operation of the rectifying element 536 constituting the rectifying circuit portion 535 flows into the commercial power source 530 and has an adverse effect.

これを防止するため、自励式整流回路部532と535との間にノイズ抑制回路540を配置している。ノイズ抑制回路540は、各相線541に配置されたノイズ抑制リアクトル542、各相線541間に配置されたコンデンサ544、及び一つの相線とアースとの間に配置されたコンデンサ546を含む。ノイズ抑制リアクトル542及びコンデンサ544がノーマルモードノイズの放出を抑制し、コンデンサ546がコモンモードノイズの放出を抑制するようになっている。
特開平07−308070号
In order to prevent this, a noise suppression circuit 540 is disposed between the self-excited rectifier circuit portions 532 and 535. The noise suppression circuit 540 includes a noise suppression reactor 542 disposed on each phase line 541, a capacitor 544 disposed between each phase line 541, and a capacitor 546 disposed between one phase line and ground. The noise suppression reactor 542 and the capacitor 544 suppress the emission of normal mode noise, and the capacitor 546 suppresses the emission of common mode noise.
JP 07-308070 A

電気自動車等のインバータ装置では、以下のような問題がある。電力線514から516に高周波コンデンサ521から523を接続しているリード線526は抵抗成分及びインダクタンス成分が大きい。バイパス経路のインピーダンスを下げて十分なノイズ抑制効果を得るためには高周波コンデンサ521から523の容量を大きくする必要がある。そうすると、高周波コンデンサを経由した高周波電流が漏電電流となり、インバータ装置の誤作動要因となるおそれがある。   Inverter devices such as electric vehicles have the following problems. The lead wire 526 connecting the high frequency capacitors 521 to 523 to the power lines 514 to 516 has a large resistance component and inductance component. In order to reduce the impedance of the bypass path and obtain a sufficient noise suppression effect, it is necessary to increase the capacitance of the high frequency capacitors 521 to 523. As a result, the high-frequency current passing through the high-frequency capacitor becomes a leakage current, which may cause a malfunction of the inverter device.

また、ノイズ発生源である半導体モジュールとノイズをバイパスする高周波コンデンサ521から523とが離れているので、その間の電力線514から516からのある程度のノイズ放出は避けられない。   Further, since the semiconductor module that is a noise generation source and the high frequency capacitors 521 to 523 that bypass the noise are separated from each other, a certain amount of noise emission from the power lines 514 to 516 cannot be avoided.

一方、上記自励式整流回路は、各相線541へのリアクトル542の配置、及び各相線541間のコンデンサ544等を示すのみで、コンデンサ544,645の具体的な搭載方法は示していない。いずれにしても、コンデンサ544,546を設ければその分コスト、スペースが増加する。また、コンデンサ521から523を相線541に接続するリード線には抵抗成分等が存在する。更に、コンデンサ544,546が整流回路部535から離れており、両者間の相線541からノイズが放出され易い。   On the other hand, the self-excited rectifier circuit only shows the arrangement of the reactor 542 on each phase line 541 and the capacitor 544 between the phase lines 541, but does not show a specific mounting method of the capacitors 544 and 645. In any case, if capacitors 544 and 546 are provided, the cost and space increase accordingly. In addition, a resistance component or the like exists in the lead wire that connects the capacitors 521 to 523 to the phase wire 541. Further, the capacitors 544 and 546 are separated from the rectifier circuit portion 535, and noise is easily emitted from the phase line 541 between them.

本発明は上記事情に鑑みてなされたもので、半導体素子で発生するノイズの放出を、特別のバイパスコンデンサを外付けすることなく、しかも効果的に抑制できる半導体装置の実装構造を提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a semiconductor device mounting structure capable of effectively suppressing the emission of noise generated in a semiconductor element without externally attaching a special bypass capacitor. Objective.

本発明は、半導体モジュールの半導体素子と半導体モジュールを両側から保持する保持部材との間、又は半導体素子と半導体モジュールを収納するケースとの間に、半導体モジュールの一部、保持部材の一部又は別の仲介部材を介在させて誘電体として、バイパスコンデンサを形成することを特徴とする。   The present invention provides a part of a semiconductor module, a part of a holding member, or a part between a semiconductor element of a semiconductor module and a holding member that holds the semiconductor module from both sides, or between a semiconductor element and a case that houses the semiconductor module. A bypass capacitor is formed as a dielectric by interposing another mediating member.

(1)本願の第1発明による半導体装置の実装構造は、請求項 に記載したように、電力用半導体素子と、半導体素子の一面及び他面にそれぞれ接合された第1の電極板及び第2の電極板と、半導体素子を制御する制御回路との接続端子と、半導体素子並びに第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと;誘導体となる第1絶縁部材及び第2絶縁部材を介して半導体モジュールを両側から保持する導電性の第1保持部材及び第2保持部材と;から成る。  (1) The mounting structure of the semiconductor device according to the first invention of the present application includes, as described in the claims, a power semiconductor element, a first electrode plate and a second electrode joined to one surface and the other surface of the semiconductor element, respectively. A semiconductor module including a connection terminal between the electrode plate and a control circuit for controlling the semiconductor element, and an insulating resin mold for sealing the semiconductor element and the first electrode plate and the second electrode plate; And a conductive first holding member and a second holding member for holding the semiconductor module from both sides via the first insulating member and the second insulating member.

半導体モジュールの作動時に発生するノイズは、第1電極板及び/又は第2の電極板と、第1保持部材及び/又は第2保持部材と、電極板と保持部材との間に位置する第1絶縁部材及び/又は第2絶縁部材とで構成されるノイズ抑制用バイパスコンデンサにより吸収され、電力線等への放出が防止される。   Noise generated during the operation of the semiconductor module is the first electrode plate and / or the second electrode plate, the first holding member and / or the second holding member, and the first electrode located between the electrode plate and the holding member. Absorption by a noise suppressing bypass capacitor constituted by the insulating member and / or the second insulating member is prevented, and emission to a power line or the like is prevented.

請求項2の実装構造は、請求項1において、第1電極板及び第2電極板の一部が露出し、第1絶縁部材及び第2絶縁部材は第1電極板及び第2電極板の露出部分と第1保持部材及び第2保持部材との間に介在された絶縁性の板である。   The mounting structure of claim 2 is the mounting structure according to claim 1, wherein a part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are exposed of the first electrode plate and the second electrode plate. It is the insulating board interposed between the part and the 1st holding member and the 2nd holding member.

請求項3の実装装置は、請求項1において、第1電極板及び第2電極板の一部が露出し、第1絶縁部材及び第2絶縁部材は樹脂モールドと一体化され第1電極板及び第2電極板の露出部分を覆う絶縁性の被膜である。請求項4の実装装置は、請求項1において、第1電極板及び第2電極板の一部が露出し、第1絶縁部材及び第2絶縁部材は第1保持部材及び第2保持部材に露出部分に対向して一体化された絶縁性の被膜である。   A mounting device according to a third aspect is the mounting device according to the first aspect, wherein a part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are integrated with the resin mold, It is an insulating film that covers the exposed portion of the second electrode plate. According to a fourth aspect of the present invention, there is provided the mounting apparatus according to the first aspect, wherein a part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are exposed to the first holding member and the second holding member. It is an insulating film integrated so as to face the part.

請求項5の実装装置は、請求項2,3又は4において、第1保持部材及び第2保持部材は接地されている。請求項6の実装装置は、請求項2,3又は4において、第1保持部材及び第2保持部材は内部に導電性の冷却媒体が流通され、冷却媒体が接地されている実装構造。   According to a fifth aspect of the present invention, in the mounting device according to the second, third, or fourth aspect, the first holding member and the second holding member are grounded. The mounting apparatus according to claim 6 is the mounting structure according to claim 2, 3 or 4, wherein the first holding member and the second holding member have a conductive cooling medium circulated therein and the cooling medium is grounded.

(2)本願の第2発明による半導体装置の実装構造は、請求項7に記載したように、電力用半導体素子と、半導体素子の一面及び他面にそれぞれ接合された第1電極板及び第2電極板と、半導体素子を制御する制御回路との接続端子と、半導体素子並びに第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと;導電性の第1内部部材及び第2内部部材が挿入され、半導体モジュールを両側から保持すると共に、誘導体となる絶縁性の第1保持部材及び第2保持部材と;から成る。  (2) The semiconductor device mounting structure according to the second invention of the present application is as described in claim 7, wherein the power semiconductor element, the first electrode plate and the second electrode respectively joined to one side and the other side of the semiconductor element are provided. A semiconductor module comprising: an electrode plate; a connection terminal for a control circuit that controls the semiconductor element; and an insulating resin mold that seals the semiconductor element and the first electrode plate and the second electrode plate; The first internal member and the second internal member are inserted to hold the semiconductor module from both sides, and include an insulating first holding member and second holding member that are derivatives.

半導体モジュールの作動時に発生するノイズは、第1電極板及び/又は第2電極板と、第1内部部材及び/又は第2内部部材と、電極板と内部部材との間に位置する第1保持部材及び/又は第2保持部材の壁部とで構成されるノイズ抑制用バイパスコンデンサにより吸収され、電力線等への放出が防止される。   The noise generated during the operation of the semiconductor module is a first holding located between the first electrode plate and / or the second electrode plate, the first internal member and / or the second internal member, and the electrode plate and the internal member. It is absorbed by a noise suppressing bypass capacitor constituted by the member and / or the wall portion of the second holding member, and emission to a power line or the like is prevented.

請求項8の実装装置は、請求項7において、第1内部部材及び第2内部部材は接地されている。請求項9の実装装置は、請求項7において、第1内部部材及び第2内部部材は導電性の冷却媒体が流通され、冷却媒体が接地されている。   The mounting device of claim 8 is the mounting device according to claim 7, wherein the first internal member and the second internal member are grounded. According to a ninth aspect of the present invention, in the mounting device according to the seventh aspect, the first internal member and the second internal member are circulated through a conductive cooling medium, and the cooling medium is grounded.

(3)本願の第3発明による半導体装置の実装構造は、請求項10に記載したように、電力用半導体素子と、半導体素子の一面及び他面にそれぞれ接合された第1電極板及び第2電極板と、半導体素子を制御する制御回路との接続端子と、半導体素子並びに第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと;導電性の冷却媒体を収納し、冷却媒体内に複数の半導体モジュールが近接配置された金属製ケースと;から成る。  (3) According to a third aspect of the present invention, there is provided a mounting structure for a semiconductor device according to a tenth aspect of the present invention, wherein a power semiconductor element, a first electrode plate and a second electrode joined to one side and the other side of the semiconductor element, respectively. A semiconductor module comprising: an electrode plate; a connection terminal for a control circuit for controlling the semiconductor element; and an insulating resin mold for sealing the semiconductor element and the first electrode plate and the second electrode plate; and conductive cooling And a metal case in which a plurality of semiconductor modules are arranged close to each other in a cooling medium.

半導体モジュールの作動時に発生するノイズは、第1電極板及び/又は第2電極板と、冷却媒体と、電極板と冷却媒体との間に位置する樹脂モールドの第1モールド部分及び/又は第2モールド部分とで構成されるノイズ抑制用バイパスコンデンサにより吸収され、電力線等への放出が防止される。   Noise generated during the operation of the semiconductor module is caused by the first and / or second electrode plate, the cooling medium, and the first mold portion and / or the second mold of the resin mold located between the electrode plate and the cooling medium. It is absorbed by a noise suppressing bypass capacitor composed of a mold part and is prevented from being emitted to a power line or the like.

請求項11の実装構造は、請求項10において、冷却媒体は接地されている。   The mounting structure of claim 11 is the mounting structure of claim 10, wherein the cooling medium is grounded.

(1)第1発明にかかる半導体装置の実装構造によれば、電力用半導体素子で発生するノイズの放出が、電極板と保持部材との間に位置する絶縁部材を誘電体とするノイズ抑制用バイパスコンデンサにより抑制される。その結果、ノイズ放出を抑制するために専用のバイパスコンデンサが不要となると共にこれを外付けする手間、時間が不要となり、コストが低減する。  (1) According to the mounting structure of the semiconductor device according to the first aspect of the present invention, noise emission generated in the power semiconductor element is for noise suppression using an insulating member located between the electrode plate and the holding member as a dielectric. Suppressed by bypass capacitor. As a result, a dedicated bypass capacitor is not required to suppress noise emission, and the labor and time for externally attaching the capacitor are not required, thereby reducing the cost.

また、バイパスコンデンサが半導体素子の近傍に、しかも半導体素子毎に配置されているので、放出ノイズの抑制効果が確実でしかも効果的である。更に、保持部材が導電性であるので、その接地が容易である。   In addition, since the bypass capacitor is disposed in the vicinity of the semiconductor element and for each semiconductor element, the effect of suppressing the emission noise is reliable and effective. Further, since the holding member is conductive, the grounding is easy.

請求項2の実装構造によれば、半導体モジュールと導電性の保持部材との間に介在させた絶縁性の板が誘電体となる。よって、汎用の半導体モジュール及び保持管をそのまま使用でき、コストの上昇を最低限に抑えることができる。   According to the mounting structure of the second aspect, the insulating plate interposed between the semiconductor module and the conductive holding member becomes the dielectric. Therefore, a general-purpose semiconductor module and holding tube can be used as they are, and an increase in cost can be minimized.

請求項3の実装構造によれば、半導体モジュールの樹脂モールドと一体化した絶縁性の被膜が誘電体となる。また、請求項4の実装構造によれば、保持管と一体化した絶縁性の被膜が誘電体となる。よって、何れも汎用の半導体モジュール及び保持管を少し改良するのみで、容易にバイパスコンデンサを形成できる。   According to the mounting structure of claim 3, the insulating film integrated with the resin mold of the semiconductor module becomes the dielectric. According to the mounting structure of claim 4, the insulating film integrated with the holding tube becomes the dielectric. Therefore, in any case, the bypass capacitor can be easily formed by slightly improving the general-purpose semiconductor module and the holding tube.

請求項5の実装構造によれば、保持部材が接地されているので、バイパスコンデンサによるノイズの抑制がより確実である。請求項6の実装構造によれば、本来半導体素子の冷却手段である冷却媒体を接地手段として利用でき、ノイズの抑制がより確実になる。   According to the mounting structure of the fifth aspect, since the holding member is grounded, noise suppression by the bypass capacitor is more reliable. According to the mounting structure of the sixth aspect, the cooling medium which is originally a cooling means for the semiconductor element can be used as the grounding means, and noise can be more reliably suppressed.

(2)第2発明にかかる半導体装置の実装構造によれば、電力用半導体素子で発生するノイズの放出が、電極板と保持部材との間に位置する保持部材の壁部により形成されるノイズ抑制用バイパスコンデンサにより抑制される。その結果、ノイズ放出を抑制するために専用のバイパスコンデンサが不要となると共にこれを外付けする手間、時間が不要となり、コストが低減する。  (2) According to the mounting structure of the semiconductor device according to the second aspect of the invention, noise generated in the power semiconductor element is generated by the wall of the holding member located between the electrode plate and the holding member. Suppressed by a suppression bypass capacitor. As a result, a dedicated bypass capacitor is not required to suppress noise emission, and the labor and time for externally attaching the capacitor are not required, thereby reducing the cost.

また、バイパスコンデンサが半導体素子の近傍に、しかも半導体素子毎に配置されているので、放出ノイズの抑制効果が確実でしかも効果的である。更に、保持部材が絶縁性であるので、材料の選択の幅が広がり、材質によっては重量が軽くなる。   In addition, since the bypass capacitor is disposed in the vicinity of the semiconductor element and for each semiconductor element, the effect of suppressing the emission noise is reliable and effective. Furthermore, since the holding member is insulative, the selection range of the material is widened, and the weight is reduced depending on the material.

請求項8の実装構造によれば、保持部材が接地されているので、バイパスコンデンサによるノイズの抑制がより確実である。請求項9の実装構造によれば、本来半導体素子の冷却手段である冷却媒体を接地手段として利用でき、ノイズの抑制がより確実になる。   According to the mounting structure of the eighth aspect, since the holding member is grounded, noise suppression by the bypass capacitor is more reliable. According to the mounting structure of the ninth aspect, the cooling medium that is originally a cooling means for the semiconductor element can be used as the grounding means, and noise can be more reliably suppressed.

(3)第3発明にかかる半導体装置の実装構造によれば、電力用半導体素子で発生するノイズの放出が、電極板と冷却媒体との間に位置する樹脂モールドのモールド部分を誘電体とするノイズ抑制用バイパスコンデンサにより抑制される。その結果、ノイズ放出を抑制するために専用のバイパスコンデンサが不要となると共にこれを外付けする手間、時間が不要となり、コストが低減する。  (3) According to the mounting structure of the semiconductor device according to the third aspect of the present invention, the noise emission generated in the power semiconductor element causes the mold part of the resin mold located between the electrode plate and the cooling medium to be a dielectric. Suppressed by a noise suppression bypass capacitor. As a result, a dedicated bypass capacitor is not required to suppress noise emission, and the labor and time for externally attaching the capacitor are not required, thereby reducing the cost.

また、バイパスコンデンサが半導体素子の近傍に、しかも半導体素子毎に配置されているので、放出ノイズの抑制効果が確実でしかも効果的である。更に、冷却媒体を収納したケースが半導体モジュールの位置決め手段を兼ねるので、保持部材が不要となり、部品点数の減少、組立て工程の簡略化が可能となる。   In addition, since the bypass capacitor is disposed in the vicinity of the semiconductor element and for each semiconductor element, the effect of suppressing the emission noise is reliable and effective. Further, since the case containing the cooling medium also serves as a positioning means for the semiconductor module, no holding member is required, and the number of parts can be reduced and the assembly process can be simplified.

請求項11の実装構造によれば、バイパスコンデンサによる放出ノイズの抑制効果がより確実になる。   According to the mounting structure of the eleventh aspect, the effect of suppressing the noise emitted by the bypass capacitor is further ensured.

本発明の半導体装置の実装構造は、ノイズ抑制用バイパスコンデンサの形成の仕方、特に何が誘電体(絶縁体)となるかに応じて、以下の三つのタイプに分類できる。
a.第1タイプでは、半導体モジュールと、これを表裏両側から保持又は挟持する保持部材との間に介在させた絶縁性の板や膜が誘電体となり、種々の態様が含まれる。
The mounting structure of the semiconductor device according to the present invention can be classified into the following three types depending on how the bypass capacitor for noise suppression is formed, in particular, what is a dielectric (insulator).
a. In the first type, an insulating plate or film interposed between a semiconductor module and a holding member that holds or sandwiches the semiconductor module from both front and back sides serves as a dielectric, and includes various modes.

第1態様は、半導体モジュールの電極板は一方極板を形成すべく、半導体モジュールの樹脂モールドからその一部が露出している。保持部材は他方極板を形成すべく導電材から成る。   In the first aspect, a part of the electrode plate of the semiconductor module is exposed from the resin mold of the semiconductor module so as to form one electrode plate. The holding member is made of a conductive material to form the other electrode plate.

半導体モジュールの表面側の第1電極板及び裏面側の第2電極板の両方にバイパスコンデンサが接続されていることが望ましい。但し、そのようになっていることは不可欠ではなく、第1又は第2電極板のみにバイパスコンデンサを接続しても良い。そのためには、一方の電極板とこれに対向する保持部材との間のみに絶縁性の板等を介在させればよい。これは、第1タイプの第2から第4態様や、次述する第2タイプ及び第3タイプでも同様である。   It is desirable that a bypass capacitor is connected to both the first electrode plate on the front surface side and the second electrode plate on the back surface side of the semiconductor module. However, such a configuration is not indispensable, and a bypass capacitor may be connected only to the first or second electrode plate. For this purpose, an insulating plate or the like may be interposed only between one electrode plate and the holding member facing the electrode plate. The same applies to the second to fourth aspects of the first type and the second and third types described below.

第2態様は、半導体モジュールの電極板を覆う樹脂モールドの一部(モールド部分)が誘電体となる。第3態様は、半導体モジュールの半導体モジュールの露出した電極板の一部を、樹脂モジュールと一体化された絶縁性の被膜が覆い、誘電体となっている。第4態様は、保持部材と一体化され、半導体モジュールの露出した電極板の一部と対向する絶縁性の被膜が誘電体となる。   In the second aspect, a part of the resin mold (mold part) covering the electrode plate of the semiconductor module is a dielectric. In the third aspect, a part of the exposed electrode plate of the semiconductor module of the semiconductor module is covered with an insulating film integrated with the resin module to form a dielectric. In the fourth aspect, an insulating film that is integrated with the holding member and faces a part of the exposed electrode plate of the semiconductor module is a dielectric.

なお、何れの態様でも、保持部材はその内部を冷却媒体が流通することが望ましい。冷却媒体は半導体モジュールでの温度上昇を抑えるのみならず、導電性の場合、保持部材を車体に接地する上で有効である。
b.第2タイプでは、半導体モジュールを表裏両側から保持又は挟持する保持部材が誘電体及び他方極板となっている。そのために、保持部材は絶縁材からなり、その内部に導電性の内部部材が挿入されている。なお、半導体モジュールの電極板はその一部が露出している。また、保持部材の内部に冷却媒体を流通させることができる。
c.第3タイプは、半導体モジュールを表裏両側から保持等する保持部材は含まない。一方極板及び誘電体が半導体モジュールに形成され、他方極板は金属製ケースに収納された導電性の冷却媒体である。半導体モジュールの電極板は樹脂モールドの一部(モールド部)により覆われている。複数の半導体モジュールはケースにより所定状態に位置決めされる。
In any aspect, it is desirable that the cooling medium circulates inside the holding member. The cooling medium not only suppresses the temperature rise in the semiconductor module, but if it is conductive, it is effective for grounding the holding member to the vehicle body.
b. In the second type, the holding member for holding or sandwiching the semiconductor module from both the front and back sides is a dielectric and the other electrode plate. For this purpose, the holding member is made of an insulating material, and a conductive internal member is inserted therein. A part of the electrode plate of the semiconductor module is exposed. Further, the cooling medium can be circulated inside the holding member.
c. The third type does not include a holding member that holds the semiconductor module from both the front and back sides. One electrode plate and a dielectric are formed in the semiconductor module, and the other electrode plate is a conductive cooling medium housed in a metal case. The electrode plate of the semiconductor module is covered with a part of the resin mold (mold part). The plurality of semiconductor modules are positioned in a predetermined state by the case.

以下、本発明の実施例を添付図面を参照しつつ説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

<第1実施例>
(構成)
図1に示すハイブリッド自動車の駆動システムは、バッテリ10、発電電動機(MG)20及びインバータ装置60を含む。バッテリ10の正極端子及び負極端子から延びた直流ブスバー11及び12の間に、平滑コンデンサ13と、インバータ装置60を構成する三相交流(U相、V相及びW相)用半導体対とが配置されている。第1U相及び第2U相半導体素子31,32間からU相線16がMG20に延びている。 第1V相及び第2V相半導体素子31,32間からV相線17が、第1W及び第2W相半導体素子31,32間からW相線18が、それぞれMG20に延びている。
<First embodiment>
(Constitution)
The hybrid vehicle drive system shown in FIG. 1 includes a battery 10, a generator motor (MG) 20, and an inverter device 60. Between the DC bus bars 11 and 12 extending from the positive electrode terminal and the negative electrode terminal of the battery 10, the smoothing capacitor 13 and the semiconductor pair for three-phase AC (U phase, V phase, and W phase) constituting the inverter device 60 are arranged. Has been. A U-phase line 16 extends to the MG 20 from between the first U-phase and second U-phase semiconductor elements 31 and 32. A V-phase line 17 extends between the first V-phase and second V-phase semiconductor elements 31 and 32, and a W-phase line 18 extends between the first W and second W-phase semiconductor elements 31 and 32 to the MG 20.

図2から図4に示すように、インバータ装置60は保持管55と、複数の半導体モジュール30とを、絶縁材50を介して高さ方向で交互に積み重ねて成る。図5から図7に示すように、各半導体モジュール30は第1半導体素子(IGBT)31及び第2半導体素子(フライホイールダイオード)32と、はんだ33a、33bを介してこれらの表面側に接合された第1電極板35と、はんだ(不図示)を介してこれらの基板側(裏面側)に接合された第2電極板36と、を含む。   As shown in FIG. 2 to FIG. 4, the inverter device 60 is formed by alternately stacking holding tubes 55 and a plurality of semiconductor modules 30 in the height direction via insulating materials 50. As shown in FIG. 5 to FIG. 7, each semiconductor module 30 is joined to the first semiconductor element (IGBT) 31 and the second semiconductor element (flywheel diode) 32 via the solders 33 a and 33 b on the surface side thereof. The first electrode plate 35 and the second electrode plate 36 joined to these substrate sides (back side) via solder (not shown).

第1電極板35及び第2電極板36にそれぞれ第1駆動電極端子38及び第2駆動電極端子39が一体化されている。第1半導体素子31には、制御電極端子41がボンディングワイヤ42等の信号線により接合されている。制御電極端子41は第1半導体素子31をオンオフするためのゲート端子(G)及びエミッタ端子(Ke)、第1半導体素子31の表面に形成され、その温度を検出する温度ダイオードの出力端子(K,A)、及び第1半導体素子31を流れる電流を検出する電流検出端子(Se)を含む。   A first drive electrode terminal 38 and a second drive electrode terminal 39 are integrated with the first electrode plate 35 and the second electrode plate 36, respectively. A control electrode terminal 41 is joined to the first semiconductor element 31 by a signal line such as a bonding wire 42. The control electrode terminal 41 is formed on the surface of the first semiconductor element 31 with a gate terminal (G) and an emitter terminal (Ke) for turning on and off the first semiconductor element 31, and an output terminal (K of the temperature diode for detecting the temperature thereof. , A), and a current detection terminal (Se) for detecting a current flowing through the first semiconductor element 31.

第1半導体素子31及び第2半導体素子32、第1電極板35及び第2電極板36、第1駆動電極端子38及び第2駆動電極端子39、並びに制御端子41等がモールド樹脂45により封止されている。モールド樹脂45は第1電極板35と第2電極板36の間に充填され、両電極板35,36間の絶縁を確保するとともに、接続端子41を固着し、第1電極板35、第2電極板36及び接続端子41間の絶縁を確保している。第1電極板35及び第2電極板36の裏面は露出している。半導体モジュール30は扁平な矩形状を持っている。   The first semiconductor element 31 and the second semiconductor element 32, the first electrode plate 35 and the second electrode plate 36, the first drive electrode terminal 38 and the second drive electrode terminal 39, the control terminal 41 and the like are sealed with the mold resin 45. Has been. The mold resin 45 is filled between the first electrode plate 35 and the second electrode plate 36 to secure insulation between the two electrode plates 35, 36, and to fix the connection terminal 41, so that the first electrode plate 35, the second electrode plate 35, Insulation between the electrode plate 36 and the connection terminal 41 is ensured. The back surfaces of the first electrode plate 35 and the second electrode plate 36 are exposed. The semiconductor module 30 has a flat rectangular shape.

図2から図4に戻って、絶縁材50は例えば窒化アルミニウムや窒化珪素の板やフィルムから成り、半導体モジュール30よりも少し大きい矩形状を持つ。保持管(挟持管)55はアルミニウムの押出し成形法等で成形され、フィン56bで区画され長手方向にのびる空隙部56aを備えている。半導体モジュール30の電極板35,36の幅よりも少し大きい幅と、複数の半導体モジュール30を載置できる長さとを持つ。空隙部56bは長さ方向貫通しており、その内部を導電性の冷却媒体が流通するようになっている。   Returning to FIG. 2, the insulating material 50 is made of, for example, a plate or film of aluminum nitride or silicon nitride, and has a rectangular shape slightly larger than the semiconductor module 30. The holding tube (clamping tube) 55 is formed by an aluminum extrusion molding method or the like, and includes a gap 56a that is partitioned by fins 56b and extends in the longitudinal direction. It has a width that is slightly larger than the width of the electrode plates 35 and 36 of the semiconductor module 30 and a length on which a plurality of semiconductor modules 30 can be placed. The gap 56b penetrates in the length direction, and a conductive cooling medium circulates through the inside.

ここで、並置された複数の半導体モジュール30と、その表面側の上方(第1)保持管55Aと、その裏面側の下方(第2)保持管55Bとの組合体について考える。上方保持管55Aが第1絶縁板50Aを介して第1電極板35に密着し、下方保持管55Bが第2絶縁板50Bを介して第2電極板36に密着している。   Here, consider a combination of a plurality of semiconductor modules 30 arranged side by side, an upper (first) holding tube 55A on the front side, and a lower (second) holding tube 55B on the back side. The upper holding tube 55A is in close contact with the first electrode plate 35 through the first insulating plate 50A, and the lower holding tube 55B is in close contact with the second electrode plate 36 through the second insulating plate 50B.

第1駆動電極端子38及び第2駆動電極端子39が上方保持管55A及び下方保持管55Bの一側方に突出し、それぞれ前記正の直流ブスバー11及び負の直流ブスバー12、及びMG20に接続される交流ブスバー16から18に接続されている。また、制御電極端子41が他側方から突出し、制御回路48に接続されている。保持管50A,50Bはハイブリッド自動車の車体の一部に接続されている。   The first drive electrode terminal 38 and the second drive electrode terminal 39 protrude to one side of the upper holding tube 55A and the lower holding tube 55B, and are connected to the positive DC bus bar 11, the negative DC bus bar 12, and the MG 20, respectively. AC bus bars 16 to 18 are connected. The control electrode terminal 41 protrudes from the other side and is connected to the control circuit 48. Holding pipes 50A and 50B are connected to a part of the body of the hybrid vehicle.

その結果、導電材である第1電極板35と第1保持管55Aとの間に、非導電材である第1絶縁板50Aが存在し、これら三者により第1バイパスコンデンサ57Aが形成される。同様に、第2電極板36と第2保持管55Bと、両者間に存在する第2絶縁板50Bとで第2バイパスコンデンサ57Bが形成される。   As a result, the first insulating plate 50A, which is a non-conductive material, exists between the first electrode plate 35, which is a conductive material, and the first holding tube 55A, and the first bypass capacitor 57A is formed by these three members. . Similarly, a second bypass capacitor 57B is formed by the second electrode plate 36, the second holding tube 55B, and the second insulating plate 50B existing therebetween.

隣接する上方保持管55A及び下方保持管55Bの両端同士間に蛇腹部材61が介在されている。その両端が気密性を確保した状態で上方保持管55A及び下方保持管55Bにロー付け、接着等により接着されている。上端の蛇腹部材61にパイプ62から供給される冷却媒体は保持管55の空隙部56を流れる。こうしてパイプ62、配管ポンプ及びラジエータ等(不図示)により冷却媒体の循環経路が形成されている。   A bellows member 61 is interposed between both ends of the adjacent upper holding tube 55A and lower holding tube 55B. Both ends thereof are brazed to the upper holding tube 55A and the lower holding tube 55B in a state where airtightness is ensured, and are bonded by bonding or the like. The cooling medium supplied from the pipe 62 to the upper bellows member 61 flows through the gap 56 of the holding pipe 55. Thus, a circulation path for the cooling medium is formed by the pipe 62, the piping pump, the radiator, and the like (not shown).

複数の保持管55及び複数の半導体モジュール30の積み重ね体は金属ケース(不図示)に収容され、この金属ケースは電気自動車の車体に固定、導通している。結局、保持管55は車体に接地されていることになる。   A stack of the plurality of holding tubes 55 and the plurality of semiconductor modules 30 is accommodated in a metal case (not shown), and the metal case is fixed and electrically connected to the body of the electric vehicle. Eventually, the holding tube 55 is grounded to the vehicle body.

(作用効果)
例えば、アイドルストップ後の発進時等に、バッテリ10の直流をインバータ装置60で交流に変換しMG20を駆動する。一方、エンジンによる走行時に、MG20を駆動して発電した交流を直流に変換し、バッテリ10に充電する。この作用自体は周知であるので、詳しい説明は割愛する。
(Function and effect)
For example, when starting after an idle stop, the direct current of the battery 10 is converted into an alternating current by the inverter device 60 and the MG 20 is driven. On the other hand, during traveling by the engine, the alternating current generated by driving the MG 20 is converted into direct current, and the battery 10 is charged. Since this operation itself is well known, a detailed description is omitted.

第1実施例によれば、ノイズの抑制に関し以下の効果が得られる。まず、第1半導体素子31及び第2半導体素子32で発生するノイズのブスバー11,12及び16等への放出が、特別又は専用のバイパスコンデンサを搭載することなく抑制される。電極板35,36が一方極板となり、保持管55A、55Bが他方極板となり、絶縁板50A、50Bが誘電体となり、これらによりバイパスコンデンサ57A、57Bが形成されるからである。   According to the first embodiment, the following effects regarding noise suppression can be obtained. First, the emission of noise generated in the first semiconductor element 31 and the second semiconductor element 32 to the bus bars 11, 12, 16 and the like is suppressed without mounting a special or dedicated bypass capacitor. This is because the electrode plates 35 and 36 are one electrode plates, the holding tubes 55A and 55B are the other electrode plates, and the insulating plates 50A and 50B are dielectrics, thereby forming the bypass capacitors 57A and 57B.

絶縁板50A、50Bは本来半導体素子31,32と保持管55A、55Bとの電気的絶縁のために介在させるものであるが、その性質(絶縁性)及び配置位置から誘電体としても機能する。その結果、専用のバイパスコンデンサをリード線で接続する手間、時間が不要となるのみならず、スペース的に有利である。   The insulating plates 50A and 50B are originally interposed for electrical insulation between the semiconductor elements 31 and 32 and the holding tubes 55A and 55B, but also function as dielectrics due to their properties (insulating properties) and arrangement positions. As a result, not only the labor and time required to connect the dedicated bypass capacitor with the lead wires is unnecessary, but also space is advantageous.

第2に、放出ノイズの抑制が確実である。第1及び半導体素子31及び32のそれぞれに個別にコンデンサ57A、57Bが接続され、しかもバイパスコンデンサ57A、57Bがノイズの発生源である第1及び第2半導体素子31及び32のすぐ近くに位置していることによる。   Second, emission noise is surely suppressed. Capacitors 57A and 57B are individually connected to the first and second semiconductor elements 31 and 32, respectively, and the bypass capacitors 57A and 57B are located in the immediate vicinity of the first and second semiconductor elements 31 and 32 which are noise sources. It depends on.

第3に、2つの理由により放出ノイズの抑制効果が高い。まず、第1保持管55A及び第2保持管55Bは、その内部を流通する導電性のLLC、ポンプ及びラジエータ等を介して車両のボディに接続されている。これにより、半導体素子31,32のノイズをボディにバイパスする経路のインピーダンスが低下する。しかも空隙部56aの内周面に内部に形成したフィン56bが保持管56とLLCとの電気的結合を向上させるからである。   Thirdly, the effect of suppressing emission noise is high for two reasons. First, the first holding pipe 55A and the second holding pipe 55B are connected to the vehicle body via conductive LLC, a pump, a radiator, and the like that flow through the inside. As a result, the impedance of the path for bypassing the noise of the semiconductor elements 31 and 32 to the body is reduced. Moreover, the fins 56b formed inside the inner peripheral surface of the gap 56a improve the electrical coupling between the holding tube 56 and the LLC.

また、第1及び第2半導体素子32及び32の冷却に関し優れた冷却効果が得られる。その表面側に配置された第1電極板35と、その裏面側に配置された第2電極板36とを介して、それぞれ内部を冷却媒体が流通する第1保持管55A及び第2保持管55Bに直接密着している、即ち両面冷却方式を採用しているからである。   Further, an excellent cooling effect can be obtained regarding the cooling of the first and second semiconductor elements 32 and 32. The first holding tube 55A and the second holding tube 55B through which the cooling medium flows are respectively passed through the first electrode plate 35 disposed on the front surface side and the second electrode plate 36 disposed on the back surface side thereof. This is because a double-sided cooling system is employed.

<第2実施例>
図8から図11に第2実施例を示す。第2実施例では上記第1実施例の第1,第2絶縁板50A、50Bの代わりに、半導体モジュールの樹脂モールド110の一部が誘電体を構成している。
<Second embodiment>
8 to 11 show a second embodiment. In the second embodiment, a part of the resin mold 110 of the semiconductor module constitutes a dielectric instead of the first and second insulating plates 50A and 50B of the first embodiment.

詳述すると、第1電極板35の表面及び第2電極板36の裏面は露出しておらず、それぞれ第1モールド部分112及び第2モールド部分113により覆われている。その結果、第1及び第2半導体素子31及び32と、第1及び第2保持管55A及び55Bと、これらの間に位置する第1及び第2モールド部分112及び113とで第1及び第2バイパスコンデンサ115A及び115Bが形成されている。   More specifically, the front surface of the first electrode plate 35 and the back surface of the second electrode plate 36 are not exposed and are covered with the first mold portion 112 and the second mold portion 113, respectively. As a result, the first and second semiconductor elements 31 and 32, the first and second holding pipes 55A and 55B, and the first and second mold parts 112 and 113 positioned between the first and second holding pipes 55A and 55B. Bypass capacitors 115A and 115B are formed.

第2実施例によれば、上記第1実施例と同様の効果が得られる。加えて、半導体装置の構成がコンパクトになる。第1及び第2モールド部分112及び113が、第1及び第2半導体素子31及び32と第1及び第2保持管55A及び55Bとの間の絶縁材としての機能と、バイパスコンデンサの誘電体としての機能を兼ねていることによる。また、第1実施例における第1,第2絶縁板50A、50Bは不要となる。   According to the second embodiment, the same effect as in the first embodiment can be obtained. In addition, the configuration of the semiconductor device becomes compact. The first and second mold parts 112 and 113 function as an insulating material between the first and second semiconductor elements 31 and 32 and the first and second holding tubes 55A and 55B, and serve as a dielectric of the bypass capacitor. Because it also serves as a function. Further, the first and second insulating plates 50A and 50B in the first embodiment are not necessary.

<第3実施例>
図12に示す第3実施例では、第1実施例の絶縁板50A、50Bの代わりに、第1及び第2モールド部分151及び152に、第1及び第2絶縁被膜153及び154を密着形成し、第1及び第2電極板35及び36の露出部分を覆っている。第1及び第2絶縁被膜153及び154は例えばアルミナの溶射膜や、DLC(ダイヤモンドダイクカーボン)の被膜から成る。その結果、第1及び第2半導体素子31及び32と、第1及び第2保持管55A及び55Bと、両者間に位置する第1及び第2絶縁被膜153及び154とでバイパスコンデンサ155A及び155Bが構成される。
<Third embodiment>
In the third embodiment shown in FIG. 12, first and second insulating coatings 153 and 154 are formed in close contact with the first and second mold portions 151 and 152 in place of the insulating plates 50A and 50B of the first embodiment. The exposed portions of the first and second electrode plates 35 and 36 are covered. The first and second insulating coatings 153 and 154 are made of, for example, an alumina sprayed coating or a DLC (Diamond Dike Carbon) coating. As a result, the bypass capacitors 155A and 155B are formed by the first and second semiconductor elements 31 and 32, the first and second holding tubes 55A and 55B, and the first and second insulating coatings 153 and 154 located therebetween. Composed.

第3実施例においても、上記第1実施例と同様の効果が得られる。加えて、第1及び第2絶縁被膜153及び154が第1及び第2半導体素子31及び32のすぐ近くに位置しているので、バイパスコンデンサ155A、155Bの容量を大きくできる。   In the third embodiment, the same effect as in the first embodiment can be obtained. In addition, since the first and second insulating coatings 153 and 154 are located in the immediate vicinity of the first and second semiconductor elements 31 and 32, the capacities of the bypass capacitors 155A and 155B can be increased.

しかも、第1及び第2絶縁被膜153及び154の膜厚を調整すれば、容量を変更することができる。よく知られているように、コンデンサの容量は絶縁被膜153,154の厚さに反比例する。よって、容量を大きくしたいときは絶縁被膜153,154の厚さを薄く、小さくしたいときは厚くすれば良い。なお、容量は電極板35,36の表面積に比例するので、絶縁被膜153,154の膜厚の調整と併行して又はこれとは別に、電極板35,36の表面積を調整することもできる。   In addition, the capacitance can be changed by adjusting the film thicknesses of the first and second insulating coatings 153 and 154. As is well known, the capacitance of the capacitor is inversely proportional to the thickness of the insulating coatings 153 and 154. Therefore, the thickness of the insulating coatings 153 and 154 may be reduced when it is desired to increase the capacity, and may be increased when it is desired to decrease the capacity. Since the capacitance is proportional to the surface area of the electrode plates 35 and 36, the surface area of the electrode plates 35 and 36 can be adjusted in parallel with or separately from the adjustment of the film thickness of the insulating coatings 153 and 154.

なお、半導体モジュール30の第1及び第2電極板35および36は露出させ、第1及び第2絶縁被膜153及び154を第1及び第2保持管55A及び55Bに形成しても良い。   The first and second electrode plates 35 and 36 of the semiconductor module 30 may be exposed, and the first and second insulating coatings 153 and 154 may be formed on the first and second holding tubes 55A and 55B.

<第4実施例>
図13から図15に示す第4実施例では、上記金属製の保持管55の代わりに、樹脂やセラミックス等の絶縁材から成る保持管210が使用されている。絶縁性の保持管210の中空部に導電性の内管215が挿入され、その空隙部216を冷却媒体が流通するようになっている。なお、半導体モジュール30の第1及び第2電極板35及び36は露出している。よって、第1及び第2電極板31及び32と、第1及び第2内管215A及び215Bと、両者の間に位置する保持管210A及び210Bの壁部212A及び212Bとでバイパスコンデンサ220A及び220Bが構成されている。
<Fourth embodiment>
In the fourth embodiment shown in FIGS. 13 to 15, a holding tube 210 made of an insulating material such as resin or ceramics is used instead of the metal holding tube 55. A conductive inner tube 215 is inserted into the hollow portion of the insulating holding tube 210, and a cooling medium flows through the gap 216. Note that the first and second electrode plates 35 and 36 of the semiconductor module 30 are exposed. Therefore, the first and second electrode plates 31 and 32, the first and second inner pipes 215A and 215B, and the wall portions 212A and 212B of the holding pipes 210A and 210B positioned between them, bypass capacitors 220A and 220B. Is configured.

第4実施例によれば、第1実施例と同様の効果に加えて、本来冷却媒体を流通させるための保持管210の絶縁性の壁部212が誘電体となるので、半導体モジュール30に誘電体を形成すること等が不要となる。また、保持管210に導電性が要求されないので、材料の選択の幅が広がる。   According to the fourth embodiment, in addition to the same effects as in the first embodiment, the insulating wall 212 of the holding tube 210 for originally circulating the cooling medium serves as a dielectric, so that the semiconductor module 30 has a dielectric. It is not necessary to form a body. In addition, since the holding tube 210 is not required to have conductivity, the range of selection of materials is widened.

<第5実施例>
図16から図18に第5実施例を示す。第5実施例では、半導体モジュール30の第1及び第2駆動電極端子38及び39と、制御端子41とが同じ側面から突出している。第1電極板35の表面及び第2電極板36の裏面(何れも不図示)は第1,第2モールド部分251,252で覆われている。
<Fifth embodiment>
A fifth embodiment is shown in FIGS. In the fifth embodiment, the first and second drive electrode terminals 38 and 39 of the semiconductor module 30 and the control terminal 41 protrude from the same side surface. The front surface of the first electrode plate 35 and the back surface (both not shown) of the second electrode plate 36 are covered with first and second mold portions 251 and 252.

金属製ケース260は上端側に複数の開口262を持ち、その内部には導電性の冷却媒体265が充填されている。各半導体モジュール30の下端をケース260の冷却媒体265に浸し上端を開口262から上方に突出させ、シール部材263でシールしている。第1及び第2半導体素子32及び32と、冷却媒体265と、両者間に位置するモールド部分251,252とで、第1及び第2バイパスコンデンサ270A及び270Bが形成されている。   The metal case 260 has a plurality of openings 262 on the upper end side, and the inside thereof is filled with a conductive cooling medium 265. The lower end of each semiconductor module 30 is immersed in the cooling medium 265 of the case 260, the upper end protrudes upward from the opening 262, and is sealed with a seal member 263. First and second bypass capacitors 270A and 270B are formed by the first and second semiconductor elements 32 and 32, the cooling medium 265, and the mold portions 251 and 252 positioned therebetween.

第5実施例によれば、第1及び第2半導体素子31及び32毎に、しかもその近傍にバイパスコンデンサ270A及び270Bが形成され、ノイズを効果的に抑制する。加えて、冷却媒体265を収納した金属製ケース260が、複数の半導体モジュール30を所定状態に位置決めしている。各半導体モジュール30をケース260の開口262から挿入するのみで所定状態にセットでき、インバータ装置を製作するための時間が短くできる。   According to the fifth embodiment, the bypass capacitors 270A and 270B are formed in the vicinity of each of the first and second semiconductor elements 31 and 32 to effectively suppress noise. In addition, a metal case 260 containing the cooling medium 265 positions the plurality of semiconductor modules 30 in a predetermined state. Each semiconductor module 30 can be set in a predetermined state simply by being inserted from the opening 262 of the case 260, and the time for manufacturing the inverter device can be shortened.

本発明が適用される電気自動車のシステム説明図である。1 is a system explanatory diagram of an electric vehicle to which the present invention is applied. 本発明の第1実施例を示す正面断面図である。It is front sectional drawing which shows 1st Example of this invention. 図1の3−3断面図である。FIG. 3 is a 3-3 cross-sectional view of FIG. 1. 図1の4−4断面図である。FIG. 4 is a sectional view taken along the line 4-4 in FIG. 1. 第1実施例の半導体モジュールの斜視図である。It is a perspective view of the semiconductor module of 1st Example. 同じく分解斜視図である。It is an exploded perspective view similarly. (a)は図5の7−7断面図、(b)はその要部拡大図である。(A) is 7-7 sectional drawing of FIG. 5, (b) is the principal part enlarged view. 本発明の第2実施例を示す正面断面図である。It is front sectional drawing which shows 2nd Example of this invention. 図8の9−9断面図である。It is 9-9 sectional drawing of FIG. 図8の10−10断面図である。It is 10-10 sectional drawing of FIG. 図7(a)に相当する断面図である。FIG. 8 is a cross-sectional view corresponding to FIG. 本発明の第3実施例を示す、図7(a)に相当する断面図である。It is sectional drawing equivalent to Fig.7 (a) which shows 3rd Example of this invention. 本発明の第3実施例を示す正面断面図である。It is front sectional drawing which shows 3rd Example of this invention. 図13の14−14断面図である。It is 14-14 sectional drawing of FIG. (a)は図13の13−13断面図、(b)は図15(a)の要部拡大図である。(A) is 13-13 sectional drawing of FIG. 13, (b) is a principal part enlarged view of Fig.15 (a). 本発明の第4実施例を示す正面図(一部断面)である。It is a front view (partial cross section) which shows 4th Example of this invention. 同じく平面図である。It is also a plan view. 第4実施例の半導体モジュールを示す正面図である。It is a front view which shows the semiconductor module of 4th Example. 第1従来例の回路説明図である。It is circuit explanatory drawing of a 1st prior art example. 第2従来例の回路説明図である。It is circuit explanatory drawing of a 2nd prior art example.

符号の説明Explanation of symbols

10:バッテリ 20:発電電動機
11、12,16から18:ブスバー
30:半導体モジュール 31、32:半導体素子
35:第1電極板 36:第2電極板
45:樹脂モールド 50,50A、50B:絶縁性の板
55,55A、55B:保持管
57,57A、57B:バイパスコンデンサ
60:インバータ装置
10: battery 20: generator motor 11, 12, 16 to 18: busbar 30: semiconductor module 31, 32: semiconductor element 35: first electrode plate 36: second electrode plate 45: resin mold 50, 50A, 50B: insulation Plate 55, 55A, 55B: holding tube 57, 57A, 57B: bypass capacitor 60: inverter device

Claims (11)

電力用半導体素子と、該半導体素子の一面及び他面にそれぞれ接合された第1の電極板及び第2の電極板と、該半導体素子を制御する制御回路との接続端子と、該半導体素子並びに該第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと、
誘導体となる第1絶縁部材及び第2絶縁部材を介して前記半導体モジュールを両側から保持する導電性の第1保持部材及び第2保持部材と、から成り、
前記第1電極板及び/又は第2の電極板と、前記第1保持部材及び/又は第2保持部材と、前記第1絶縁部材及び/又は第2絶縁部材とによりノイズ抑制用バイパスコンデンサが形成されていることを特徴とする半導体装置の実装構造。
A power semiconductor element, a connection terminal of a first electrode plate and a second electrode plate respectively bonded to one surface and the other surface of the semiconductor element, and a control circuit for controlling the semiconductor element; the semiconductor element; An insulating resin mold for sealing the first electrode plate and the second electrode plate; and a semiconductor module,
A conductive first holding member and a second holding member for holding the semiconductor module from both sides via a first insulating member and a second insulating member to be a derivative;
A noise suppression bypass capacitor is formed by the first electrode plate and / or the second electrode plate, the first holding member and / or the second holding member, and the first insulating member and / or the second insulating member. A mounting structure of a semiconductor device, wherein
前記第1電極板及び第2電極板の一部が露出し、前記第1絶縁部材及び第2絶縁部材は該第1電極板及び第2電極板の露出部分と前記第1保持部材及び第2保持部材との間に介在された絶縁性の板である請求項1に記載の半導体装置の実装構造。   A part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are exposed portions of the first electrode plate and the second electrode plate, the first holding member and the second electrode. The semiconductor device mounting structure according to claim 1, wherein the mounting structure is an insulating plate interposed between the holding member and the holding member. 前記第1電極板及び第2電極板の一部が露出し、前記第1絶縁部材及び第2絶縁部材は前記樹脂モールドと一体化され該第1電極板及び第2電極板の露出部分を覆う絶縁性の被膜である請求項1に記載の半導体装置の実装構造。   A part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are integrated with the resin mold to cover the exposed portions of the first electrode plate and the second electrode plate. 2. The semiconductor device mounting structure according to claim 1, wherein the semiconductor device mounting structure is an insulating film. 前記第1電極板及び第2電極板の一部が露出し、前記第1絶縁部材及び第2絶縁部材は前記第1保持部材及び第2保持部材に該露出部分に対向して一体化された絶縁性の被膜である請求項1に記載の半導体装置の実装構造。   A part of the first electrode plate and the second electrode plate is exposed, and the first insulating member and the second insulating member are integrated with the first holding member and the second holding member so as to face the exposed portion. 2. The semiconductor device mounting structure according to claim 1, wherein the semiconductor device mounting structure is an insulating film. 前記第1保持部材及び第2保持部材は接地されている請求項2,3又は4に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 2, wherein the first holding member and the second holding member are grounded. 前記第1保持部材及び第2保持部材は内部に導電性の冷却媒体が流通され、該冷却媒体が接地されている請求項2,3又は4に記載の半導体装置の実装構造。   5. The semiconductor device mounting structure according to claim 2, wherein the first holding member and the second holding member have a conductive cooling medium flowing therein and are grounded. 電力用半導体素子と、該半導体素子の一面及び他面にそれぞれ接合された第1電極板及び第2電極板と、該半導体素子を制御する制御回路との接続端子と、該半導体素子並びに該第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと、
導電性の第1内部部材及び第2内部部材が挿入され、前記半導体モジュールを両側から保持すると共に、誘導体となる絶縁性の第1保持部材及び第2保持部材と、から成り
前記第1電極板及び/又は前記第2の電極板と、前記第1内部部材及び/又は第2内部部材と、前記第1保持部材及び/又は第2保持部材の壁部とによりノイズ抑制用バイパスコンデンサが形成されていることを特徴とする半導体装置の実装装置。
A power semiconductor element; a connection terminal of a first electrode plate and a second electrode plate respectively bonded to one surface and the other surface of the semiconductor element; a control circuit for controlling the semiconductor element; the semiconductor element; An insulating resin mold that seals the first electrode plate and the second electrode plate; and a semiconductor module,
A conductive first internal member and a second internal member are inserted to hold the semiconductor module from both sides, and include an insulating first holding member and a second holding member which are derivatives. The first electrode plate And / or the second electrode plate, the first internal member and / or the second internal member, and the wall portion of the first holding member and / or the second holding member form a noise suppressing bypass capacitor. An apparatus for mounting a semiconductor device, comprising:
前記第1内部部材及び第2内部部材は接地されている請求項7に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 7, wherein the first internal member and the second internal member are grounded. 前記第1内部部材及び第2内部部材は導電性の冷却媒体が流通され、該冷却媒体が接地されている請求項7に記載の半導体装置の実装構造。   8. The semiconductor device mounting structure according to claim 7, wherein a conductive cooling medium is circulated through the first internal member and the second internal member, and the cooling medium is grounded. 電力用半導体素子と、該半導体素子の一面及び他面にそれぞれ接合された第1電極板及び第2電極板と、該半導体素子を制御する制御回路との接続端子と、該半導体素子並びに該第1電極板及び第2電極板を封止する絶縁性の樹脂モールドと、を含む半導体モジュールと、
導電性の冷却媒体を収納し、該冷却媒体内に複数の前記半導体モジュールが近接配置された金属製ケースと、から成り、
前記第1電極板及び/又は第2電極板と、前記冷却媒体と、前記樹脂モールドの第1モールド部分及び/又は第2モールド部分とにより、ノイズ抑制用バイパスコンデンサが形成されていることを特徴とする半導体装置の実装構造。
A power semiconductor element; a connection terminal of a first electrode plate and a second electrode plate respectively bonded to one surface and the other surface of the semiconductor element; a control circuit for controlling the semiconductor element; the semiconductor element; An insulating resin mold that seals the first electrode plate and the second electrode plate; and a semiconductor module,
A conductive case containing a conductive cooling medium, and a plurality of the semiconductor modules disposed in proximity in the cooling medium; and a metal case,
A noise-suppressing bypass capacitor is formed by the first electrode plate and / or the second electrode plate, the cooling medium, and the first mold portion and / or the second mold portion of the resin mold. A mounting structure of a semiconductor device.
前記冷却媒体は接地されている請求項10に記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 10, wherein the cooling medium is grounded.
JP2003297833A 2003-08-21 2003-08-21 Mounting structure of semiconductor device Expired - Lifetime JP4075734B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP2003297833A JP4075734B2 (en) 2003-08-21 2003-08-21 Mounting structure of semiconductor device
EP10004702A EP2216892B1 (en) 2003-08-21 2004-08-20 Mounting structure of a semiconductor device
PCT/JP2004/011970 WO2005020276A2 (en) 2003-08-21 2004-08-20 Power converter and semiconductor device mounting structure
EP10004700A EP2216890B1 (en) 2003-08-21 2004-08-20 Mounting structure of a semiconductor device
EP10004701A EP2216891B1 (en) 2003-08-21 2004-08-20 Mounting structure ofa semiconductor device
EP04771931A EP1657806B1 (en) 2003-08-21 2004-08-20 Power converter and semiconductor device mounting structure
US10/554,998 US7508668B2 (en) 2003-08-21 2004-08-20 Electric power converter and mounting structure of semiconductor device
US12/073,871 US7724523B2 (en) 2003-08-21 2008-03-11 Electric power converter and mounting structure of semiconductor device
US12/457,245 US7826226B2 (en) 2003-08-21 2009-06-04 Electric power converter and mounting structure of semiconductor device
US12/457,246 US8027161B2 (en) 2003-08-21 2009-06-04 Electronic power converter and mounting structure of semiconductor device

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JP2007311441A (en) * 2006-05-17 2007-11-29 Hitachi Ltd Power semiconductor module
JP2008136333A (en) * 2006-10-30 2008-06-12 Denso Corp Power converter
JP2009268165A (en) * 2008-04-22 2009-11-12 Toyota Motor Corp Inverter module
KR101695492B1 (en) 2009-04-16 2017-01-11 세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지 Device for reducing the interference emission in a power electronic system
KR20100114837A (en) * 2009-04-16 2010-10-26 세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지 Device for reducing the interference emission in a power electronic system
JP2010251750A (en) * 2009-04-16 2010-11-04 Semikron Elektronik Gmbh & Co Kg Device for reducing interference emission in power electronic system
US20130176761A1 (en) * 2010-09-30 2013-07-11 Hitachi Automotive Systems, Ltd. Power Conversion Device
JP2013034304A (en) * 2011-08-02 2013-02-14 Toyota Motor Corp Electric power conversion apparatus
JP2013150488A (en) * 2012-01-23 2013-08-01 Calsonic Kansei Corp Power semiconductor module
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JP2014107341A (en) * 2012-11-26 2014-06-09 Toyota Motor Corp Semiconductor module
WO2014132397A1 (en) 2013-02-28 2014-09-04 新電元工業株式会社 Module, module assembly, and module manufacturing method
US9386698B2 (en) 2013-02-28 2016-07-05 Shindengen Electric Manufacturing Co., Ltd. Module, module combined body and module production method
JP2015115597A (en) * 2013-12-12 2015-06-22 隆達電子股▲ふん▼有限公司 Package material and package structure of light-emitting diode including the same
US10076068B2 (en) 2014-01-09 2018-09-11 Nippon Soken, Inc. Electric power convertor
WO2015111211A1 (en) * 2014-01-27 2015-07-30 株式会社日立製作所 Power module and manufacturing method therefor
US10080313B2 (en) 2014-01-27 2018-09-18 Hitachi, Ltd. Power module and method for manufacturing the same
JP2015167428A (en) * 2014-03-03 2015-09-24 株式会社日本自動車部品総合研究所 Power conversion device
JP2017162988A (en) * 2016-03-09 2017-09-14 株式会社豊田中央研究所 Insulation substrate and electric power conversion system including the same
JP2019075436A (en) * 2017-10-13 2019-05-16 京セラ株式会社 Semiconductor device and semiconductor device manufacturing method

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