JP2005072939A - Pll modem and digital signal transceiver using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small sized PLL modem realized by using a single PLL loop circuit commonly at the time of transmission and at the time of reception. <P>SOLUTION: In a single PLL loop circuit 10, a low-pass filter 7 is set to a lower cutoff frequency, a charge pump 4 is set to a lower charging-discharging current, and the phase comparison frequency is set to be lower according to control data from a PLL loop control terminal at the time for modulation than those at the time for demodulation, this making it commonly usable as a modulator or demodulator and hence realizing a small sized PLL modem. Thus, the one PLL loop circuit is commonly used for the modulation and the demodulation to reduce the number of peripheral components of the PLL modem, thereby realizing a low cost device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PLL modulator / demodulator and a digital signal transmitter / receiver using the same, and more particularly to a digital signal transmitter / receiver that uses a single PLL circuit for both modulation and demodulation.

  The conventional digital signal transmitter / receiver has the following configuration. That is, in FIG. 5, the reception system mainly includes an antenna switch 72 to which the antenna 71 is connected to a common terminal, a reception filter 73 to which one terminal of the antenna switch 72 is connected, and the reception filter 73. A high frequency amplifier 74 to which the output is connected, a reception mixer 76 to which the output of the high frequency amplifier 74 is connected to one input, an intermediate frequency filter 77 to which the output of the reception mixer 76 is connected, and the intermediate frequency An intermediate frequency amplifier 78 to which the output of the filter 77 is connected, a PLL demodulator 79 to which the output of the intermediate frequency amplifier 78 is connected, and an output terminal 80 to which the output of the PLL demodulator 79 is connected. It was.

  On the other hand, the transmission system mainly includes a PLL modulator 82 connected to the input terminal 81, a switch 84 in which the output of the PLL modulator 82 is connected to the other terminal, and an output from the common terminal of the switch 84. The PLL oscillator 75 is connected, and the power amplifier 85 is connected between the output of the PLL oscillator 75 and the other terminal of the antenna switch 72.

  The output of the reference oscillator 83 is connected to one terminal of the switch 84 and to the other input of the PLL modulator 82. The output of the PLL oscillator 75 is also connected to the other input of the receiving mixer 76.

  The operation of the digital signal transceiver configured as described above will be described below. First, the receiving system will be described. A high-frequency received signal received by the antenna 71 is input to the common terminal of the antenna switch 72 and is input to the reception filter 73 via one terminal of the antenna switch 72.

  A desired signal is selected by the reception filter 73. This desired signal is amplified by the high frequency amplifier 74 and then mixed with the output signal of the PLL oscillator 75 by the receiving mixer 76 to be output as an intermediate frequency.

  Further, the signal having the intermediate frequency is amplified by the intermediate frequency amplifier 78 after unnecessary signals other than the desired signal are removed by the intermediate frequency filter 77. The amplified signal is demodulated by the PLL demodulator 79, and a demodulated digital signal is output from the output terminal 80. At this time, the switch 84 is switched so that the output of the reference oscillator 83 is input to the PLL oscillator 75 as indicated by a solid line.

  Next, the transmission system will be described. The digital signal input to the input terminal 81 is digitally modulated by the PLL modulator 82 to generate a transmission signal. The transmission signal is input to the PLL oscillator 75 via the switch 84, and is output from the PLL oscillator 75 as a high-frequency transmission signal.

  Further, the high-frequency transmission signal is amplified by the power amplifier 85 and then transmitted from the antenna 71 via the antenna switch 72. At this time, as indicated by a dotted line, the switch 84 is switched so that the output of the PLL modulator 82 is directly input to the PLL oscillator 75 unlike the reception.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
Japanese Patent Laid-Open No. 06-104790

  However, in the PLL demodulator and the PLL modulator used in such a conventional digital signal transmitter / receiver, the PLL demodulator 79 used at the time of reception and the PLL modulator 82 used at the time of transmission are provided separately, and the problem is that the size is increased. was there.

  The present invention solves this problem, and an object of the present invention is to provide a small PLL modulator / demodulator by using one PLL loop circuit in common during reception and transmission.

  In order to achieve this object, the PLL modem according to the present invention has the following configuration. That is, at the time of demodulation, a received signal that has been digitally modulated is input to the first input terminal, no signal is input to the second input terminal, and a demodulated digital signal is output from the first output terminal. At the time of modulation, a reference oscillator signal is input to the first input terminal, a digital signal is input to the second input terminal, and a digitally modulated transmission is transmitted from the second output terminal. The signal is output, and the modulation frequency is set lower than the demodulation time by the control data from the PLL loop control terminal, the cut-off frequency of the low-pass filter is set lower, and the charge / discharge current of the charge pump is set lower. By setting the phase comparison frequency low, one PLL loop circuit can be shared for demodulation or modulation. Thereby, a small PLL modulator / demodulator can be provided.

  According to the first aspect of the present invention, there is provided a first input terminal, a reference frequency divider to which a signal inputted to the first input terminal is supplied, and an output of the reference frequency divider is one of them. A phase comparator supplied to the input, a charge pump supplied with the output of the phase comparator, a low pass filter supplied with the output of the charge pump, and an output of the low pass filter supplied to one input A voltage controlled oscillator; a comparison frequency divider connected between the output of the voltage controlled oscillator and the other input of the phase comparator; a first output terminal connected to the output of the low pass filter; A second input terminal connected to the other input of the voltage controlled oscillator; a second output terminal connected to the output of the voltage controlled oscillator; the reference frequency divider; the phase comparator; the charge pump; The low-pass fill A PLL loop circuit comprising the voltage controlled oscillator and the comparison frequency divider, a PLL loop control unit for controlling the PLL loop circuit, and a PLL loop control terminal for controlling the PLL loop control unit, A digitally modulated received signal is input to the first input terminal, the second input terminal is connected to the ground, and a digital signal obtained by demodulating the received signal is output from the first output terminal. A demodulator is formed, and a signal of a reference oscillator is input to the first input terminal, a digital signal is input to the second input terminal, and digital modulation is performed from the second output terminal. The transmitted signal is output to form a modulator, and the modulator is controlled by the control data from the PLL loop control terminal so that the modulator Set low cutoff frequency, the charging and discharging current of the charge pump is set small, a PLL modem to set lower the phase comparison frequency.

  Thereby, since one PLL loop circuit can be shared as a modulator or a demodulator, a small PLL modulator / demodulator can be realized. In addition, by sharing one PLL loop circuit in this way, the number of parts can be reduced, so that the price can be reduced.

  That is, at the time of demodulation, by setting the cutoff frequency of the low-pass filter high, the maximum frequency of the digitally modulated received signal input to the PLL modulator / demodulator can be increased, that is, the modulation occupied band of the digitally modulated received signal The width can be widened. Further, since the charge gain / discharge current of the charge pump is set to be large, the loop gain of the PLL loop circuit is increased, so that the followability to the frequency shift of the digitally modulated received signal is improved. Further, by increasing the comparison frequency supplied to one input of the phase comparator, the phase noise of the oscillation signal of the voltage controlled oscillator can be reduced.

  In this way, the PLL modulator / demodulator at the time of demodulation was faithfully demodulated even when a digitally modulated received signal having a high frequency shift and a broadband modulation occupation bandwidth was input to the PLL modulator / demodulator. A digital signal can be output.

  On the other hand, at the time of modulation, the cutoff frequency of the low-pass filter is set low, so that components and noise components that have been frequency modulated by the digital signal are removed. Therefore, only the oscillation component of the voltage controlled oscillator is mainly supplied to and controlled by the input of the voltage controlled oscillator.

  Moreover, since the loop gain of the PLL loop circuit is reduced by setting the charge / discharge current of the charge pump to be small, the PLL loop response can be set late. As a result, the PLL loop circuit does not follow the frequency-modulated component and noise component of the digital signal, but follows the oscillation frequency of the voltage controlled oscillator.

  Furthermore, by lowering the comparison frequency supplied to one input of the phase comparator, the minimum step frequency that can be corrected for deviations in the oscillation frequency of the voltage controlled oscillator can be reduced, so that the oscillation frequency of the voltage controlled oscillator is accurate. Controlled.

  Thus, the PLL modulator / demodulator at the time of modulation has a high-accuracy oscillation frequency and a small noise component even when a digital signal having a high-speed frequency shift and a wide modulation occupation bandwidth is input. The digitally modulated transmission signal can be output.

  According to a second aspect of the present invention, there is provided a digital signal transmitter / receiver having a reception system, a transmission system, and the PLL modulator / demodulator according to the first aspect. A receiving mixer in which the output of the PLL oscillator is supplied to one input and the output of the PLL oscillator is supplied to the other input, and a PLL in which the output of the receiving mixer is supplied to the first input terminal via the first switch A modem, a receiving output terminal to which a digital signal output from the first output terminal of the PLL modulator / demodulator is supplied, and a reference to which a signal is supplied to the input of the PLL oscillator via a second switch An oscillator and a third switch having a second input terminal of the PLL modulator / demodulator connected to the common terminal and connected to the ground are provided. In the transmission system, an input is provided to the modulation input terminal. The digital signal is input to the second input terminal of the PLL modulator / demodulator via the third switch, and the output of the reference oscillator is input to the first input terminal via the first switch. The PLL modulator / demodulator supplied, the PLL oscillator to which a digitally modulated transmission signal from the second output terminal of the PLL modulator / demodulator is supplied via the second switch, and the output of the PLL oscillator A high-frequency output terminal to which a certain high-frequency transmission signal is supplied, and a digital signal transceiver capable of receiving and transmitting by switching each of the first, second, and third switches. Since the PLL loop circuit can be shared as a modulator at the time of transmission and as a demodulator at the time of reception, a miniaturized digital signal transceiver can be realized.

  In addition, by sharing one PLL loop circuit in this way, the number of parts can be reduced, so that the price can be reduced as a digital signal transceiver.

  According to a third aspect of the present invention, in the case of switching from the reception system to the transmission system, after switching the first switch, the PLL modulator / demodulator is switched from demodulation to modulation. It is a signal transceiver, and after switching the first switch from the reception state to the transmission state, the PLL modulator / demodulator is switched from demodulation to modulation.

  As a result, in the switching period from the reception state to the transmission state, the signal of the reference oscillator is first supplied to the phase comparator via the reference frequency divider. After the reference oscillator signal is supplied, the PLL modulator / demodulator is switched from demodulation to modulation, and the voltage controlled oscillator of the PLL loop circuit controls the oscillation frequency.

  At this time, since the signal of the reference oscillator is already supplied to one input of the phase comparator, the PLL loop response time of the PLL modem can be shortened. That is, since the interval between the transmission data and the reception data can be shortened, the amount of transmission / reception data in a certain time can be increased.

  According to the fourth aspect of the present invention, when switching from the reception system to the transmission system, the first switch is switched first, then the PLL modulator / demodulator is switched from demodulation to modulation, and the PLL modulator / demodulator is demodulated. 3. The digital signal transceiver according to claim 2, wherein the second switch is switched after switching from modulation to modulation, and the PLL modulator / demodulator is modulated from demodulation after switching the first switch from the reception state to the transmission state. Is switched to.

  As a result, in the switching period from the reception state to the transmission state, the signal of the reference oscillator is first supplied to the phase comparator via the reference frequency divider. Further, after the reference oscillator signal is supplied, the PLL modulator / demodulator is switched from the demodulated state to the modulated state, and the oscillation frequency of the voltage controlled oscillator is controlled by the PLL loop circuit. At this time, since the signal of the reference oscillator is already supplied to one input of the phase comparator, the PLL loop response time of the PLL modem can be shortened.

  Further, after that, the third switch is switched from the reception state to the transmission state. For this reason, the transmission signal that has already become the predetermined signal is supplied to the input of the PLL oscillator, so that the stabilization time of the PLL oscillator is shortened.

  As described above, since the interval between the transmission data and the reception data can be further shortened, the amount of transmission / reception data in a certain time can be further increased.

  As described above, according to the present invention, in one PLL loop circuit, the cutoff frequency of the low-pass filter is set lower than the time of demodulation by the control data from the PLL loop control terminal, and the charge pump is charged. By setting the discharge current small and setting the phase comparison frequency low, it can be shared as a modulator or demodulator. Therefore, a small PLL modulator / demodulator can be realized.

  In addition, by sharing modulation and demodulation with one PLL loop circuit in this way, the number of parts around the PLL modulator / demodulator can be reduced, so that the price can be reduced.

(Embodiment 1)
FIG. 1 is a block diagram of a PLL modulator / demodulator 1 according to Embodiment 1 of the present invention. In FIG. 1, a PLL modulator / demodulator 1 is configured as follows. That is, the demodulation input terminal 1 a is connected to the reference frequency divider 2. The output of the reference frequency divider 2 is connected to one input of the phase comparator 3. The output of the phase comparator 3 is connected to the input of the charge pump 4. The output of the charge pump 4 is connected to the common terminal of the switch 5. One terminal of the switch 5 is connected to the low-pass filter 6, and the other terminal of the switch 5 is connected to the low-pass filter 7. The outputs of the low-pass filters 6 and 7 are connected to the demodulation output terminal 1 b and to one input 8 a of the voltage controlled oscillator 8.

  A comparison frequency divider 9 is connected between the output of the voltage controlled oscillator 8 and the other input of the phase comparator 3. These reference frequency divider 2, phase comparator 3, charge pump 4, switch 5, low-pass filter 6 or 7, voltage controlled oscillator 8 and comparison frequency divider 9 constitute a PLL loop circuit 10. Further, a transmission input terminal 1 c is connected to the other input 8 b of the voltage controlled oscillator 8. A modulation output terminal 1 d is connected to the output of the voltage controlled oscillator 8.

  Further, a PLL loop control unit 11 is configured to control the PLL loop circuit 10. A PLL loop control terminal 1 e is connected to the input of the PLL loop control unit 11. By inputting control data to the PLL loop control terminal 1e, the PLL modem 1 can be set at the time of demodulation and modulation.

  The operation of the PLL modulator / demodulator 1 at the time of reception and at the time of transmission when the PLL modulator / demodulator 1 of the present invention configured as described above is used in a digital signal transceiver will be described.

  When the digital signal transceiver is receiving, the PLL modem 1 operates as a demodulator. Here, the digitally modulated received signal is input to the demodulation input terminal 1 a of the PLL modem 1. This digitally modulated reception signal has a frequency band and a frequency shift speed corresponding to the digital modulation signal.

  Therefore, it is important for the PLL modulator / demodulator 1 to set the wide band and the high speed as the PLL loop circuit 10 according to the frequency band and frequency shift speed of the digitally modulated received signal.

  When the digital signal transceiver is transmitting, the PLL modulator / demodulator 1 operates as a modulator. Here, a digital signal is supplied to the other input of the voltage controlled oscillator 8 via the transmission input terminal 1 c and is digitally modulated by the voltage controlled oscillator 8. At this time, the PLL loop circuit 10 phase-locks the oscillation frequency f (vco) of the modulated voltage controlled oscillator 8 and sets the PLL loop gain so that the digitally modulated signal is not phase-locked.

  Therefore, it is important for the PLL modulator / demodulator 1 to set narrow bandwidth and low speed as the PLL loop circuit 10 in accordance with the frequency band and frequency shift speed of the digitally modulated transmission signal.

  In order to realize this, the PLL loop circuit 10 at the time of demodulation and modulation is a low-pass having different frequency division ratios of the reference frequency divider 2 and the comparative frequency divider 9, charge / discharge current of the charge pump 4, and cut-off frequency. Switching between the filters 6 and 7 is necessary.

  Hereinafter, the demodulation of the PLL modem 1 will be specifically described. In this PLL modulator / demodulator 1, the frequency f (IF) of the received signal input to the demodulation input terminal 1 a is frequency-divided by 1 / R by the reference frequency divider 2 and then input to one of the phase comparators 3. To be supplied. In this phase comparator 3, the signal supplied to one input of the phase comparator 3 and the signal supplied to the other input are phase-compared, and the signal of the phase difference is output and input to the charge pump 4. Is done. In the charge pump 4, injection and suction are performed on the output current that is the output of the charge pump 4 in accordance with the input phase difference signal.

  The output of the charge pump 4 is connected to the common terminal of the switch 5. At this time, the switch 5 is set so that one terminal connected to the low-pass filter 6 having a high cutoff frequency is connected to the common terminal. For this reason, the output of the charge pump 4 is input to the low-pass filter 6 having a high cutoff frequency. The low-pass filter 6 removes unnecessary noise components other than the frequency band of the received signal.

  Further, the output from the low-pass filter 6 is supplied as a frequency control voltage to one input 8 a of the voltage controlled oscillator 8. That is, the oscillation frequency of the voltage controlled oscillator 8 is controlled by the output from the low pass filter 6. The oscillation frequency f (vco) from the output 8 c of the voltage controlled oscillator 8 is frequency-divided to 1 / N by the comparison frequency divider 9 and then input to the other terminal of the phase comparator 3.

  Thus, in the phase comparator 3, the frequency f (IF) / R from the reference frequency divider 2 and the frequency f (vco) / N from the comparison frequency divider 9 are phase-compared, and the signal of the phase difference is compared. Becomes an output and is input to the charge pump 4. Further, the frequency of the voltage controlled oscillator 8 is controlled by the PLL loop via the switch 5 and the low pass filter 6.

  As a result, the PLL loop control is performed so that the phase of the frequency f (IF) / R from the reference frequency divider 2 and the frequency f (vco) / N from the comparison frequency divider 9 coincide. As a result, a voltage shift corresponding to the frequency shift of the digitally modulated received signal occurs at the input 8a of the voltage controlled oscillator 8. Therefore, this voltage deviation can be used as a demodulated signal and is output from the demodulation output terminal 1b.

  Next, a specific description will be given of the time when the PLL modem 1 is modulated. First, how the voltage controlled oscillator 8 is modulated with a digital signal will be described. A digital signal is input to the transmission input terminal 1 c of the PLL modem 1. This digital signal is supplied to the input 8b of the voltage controlled oscillator 8 as a control voltage. As a result, a digitally modulated transmission signal is output from the output of the voltage controlled oscillator 8.

  Next, how the oscillation frequency f (vco) of the voltage controlled oscillator 8 is PLL loop controlled will be described. At one input of the phase comparator 3, the output of a reference oscillator using an oscillator such as a crystal oscillator or a SAW oscillator is supplied to the input of the reference frequency divider 2 via the demodulation input terminal 1a.

  The output of the reference frequency divider 2 is supplied to one input of the phase comparator 3. At the time of reception, the phase comparator 3, the charge pump 4, the switch 5, the PLL loop circuit 10 including the low-pass filter 7 having a low cutoff frequency selected by the switch 5, the voltage controlled oscillator 8, and the comparison frequency divider 9 In the same manner as described above, the oscillation frequency of the voltage controlled oscillator 8 is controlled to be a predetermined frequency.

  At this time, from the time of demodulation to the time of modulation, the frequency division number R of the reference frequency divider 2 and the frequency division number N of the comparison frequency divider 9 are set large, the charge pump current of the charge pump 4 is set small, and the switch 5, the low-pass filter 7 having a lower cutoff frequency is selected.

  That is, first, the value of the frequency division number R of the reference frequency divider 2 is increased, and the frequency supplied to one input of the phase comparator 3 is decreased. As a result, the cut-off frequency that can be responded as the PLL loop circuit 10 can be lowered, and it is possible to follow the oscillation frequency of the voltage controlled oscillator 8 without following the digital signal that is a high-speed modulation component.

  At this time, if the frequency from the reference frequency divider 2 supplied to one input of the phase comparator 3 is lowered, the frequency from the comparison frequency divider 9 can also be lowered. That is, even if the oscillation frequency of the voltage controlled oscillator 8 is deviated, the minimum step frequency that can be corrected can be reduced, so that the accuracy of the oscillation frequency of the voltage controlled oscillator 8 can be increased.

  Second, the charge / discharge current value of the charge pump 4 is reduced. As a result, the PLL loop gain of the PLL loop circuit 10 can be set low, and can follow the oscillation frequency of the voltage controlled oscillator 8 without following the digital signal which is a high-speed frequency. As described above, the charge / discharge current of the charge pump 4 can be set so as to obtain an optimum PLL loop gain.

  Thirdly, the low-pass filter 7 whose cutoff frequency is set low by the switch 5 is selected. As a result, an unnecessary noise component in the signal modulated with the digital signal is removed, thereby ensuring a more accurate digital modulation signal.

  As described above, the PLL loop circuit 10 can be set to have a wide-band and high-speed PLL loop characteristic at the time of demodulation, and can be set to have a narrow-band and low-speed PLL loop characteristic at the time of modulation.

  FIG. 2 shows the PLL loop response characteristics of the PLL modem 1 according to Embodiment 1 of the present invention. The horizontal axis represents the frequency 21, and the vertical axis represents the PLL loop gain 22. In other words, it represents the PLL loop gain for each frequency, and the PLL loop gain at a high frequency is limited by setting the frequency division ratio of the reference frequency divider, the charge / discharge current of the charge pump, and the cutoff frequency of the low-pass filter. It shows how it works.

  In FIG. 2, the PLL loop response characteristic at the time of reception is indicated by 23, and the modulation occupied bandwidth of the digital signal is 24. The modulation occupied bandwidth 24 of the digital signal is represented by a high frequency 25 and a low frequency 26. Further, the cutoff frequency 27 of the PLL loop response characteristic 23 at the time of demodulation is set to −3 dB with respect to the flat portion 28 of the PLL loop response characteristic 23. At this time, the cutoff frequency 27 of the PLL loop response characteristic 23 at the time of reception is faithfully demodulated from the digitally modulated received signal by setting it higher than the frequency 25 having a high modulation occupied bandwidth 24 of the digital signal. Can output digital signals.

  The PLL loop response characteristic at the time of transmission is indicated by 29. The cutoff frequency 30 of the PLL loop response characteristic 29 at the time of transmission is set to −3 dB with respect to the flat portion 31 of the PLL loop response characteristic 29. At this time, the cut-off frequency 30 of the PLL loop response characteristic 29 at the time of transmission is set to be lower than the frequency 26 having a low modulation occupation bandwidth 24 of the digital signal, so that the oscillation frequency f (vco) of the voltage controlled oscillator is set. Can follow the modulation component, but can faithfully modulate a given digital signal, and can reduce unnecessary noise components in the modulation frequency component of the PLL loop circuit 10. Therefore, it is possible to output a digital modulation signal with good C / N and high frequency accuracy.

(Embodiment 2)
FIG. 3 is a block diagram of a digital signal transceiver using the PLL modulator / demodulator 1 according to Embodiment 2 of the present invention. In FIG. 3, the digital signal transceiver is formed of a reception system 41, a transmission system 42, and a PLL modulator / demodulator 1. Here, the PLL modulator / demodulator 1 shown in FIG. 3 is the same as that shown in FIG.

  First, the receiving system 41 will be described. The antenna 43 is connected to the common terminal 44 a of the antenna switch 44. A reception filter 45 is connected to one terminal 44 b of the antenna switch 44. The output of the reception filter 45 is connected to the input of the high frequency amplifier 46. The output of the high frequency amplifier 46 is connected to one input of a receiving mixer 48 via a high frequency input terminal 47, and the output of the PLL oscillator 49 is connected to the other input.

  Further, the output of the receiving mixer 48 is connected to the intermediate frequency filter 50. The output of the intermediate frequency filter 50 is connected to the intermediate frequency amplifier 51. The output of the intermediate frequency amplifier 51 is connected to one terminal 52 a of the switch 52, and the output of the reference oscillator 53 is connected to the other terminal 52 c of the switch 52.

  The common terminal 52 b of the switch 52 is connected to the demodulation input terminal 1 a of the PLL modem 1. The demodulation output terminal 1 b of the PLL modulator / demodulator 1 is connected to the reception output terminal 54. At this time, the transmission input terminal 1c of the PLL modem 1 is connected to the common terminal 56a of the switch 56, and one terminal 56b is connected to the ground. The output of the reference oscillator 53 is connected to one terminal 57 a of the switch 57 and is connected to the input of the PLL oscillator 49 via the common terminal 57 b of the switch 57.

  Next, the transmission system 42 will be described. The transmission input terminal 55 is connected to the other terminal 56 c of the switch 56, and is connected to the transmission input terminal 1 c of the PLL modem 1 via the common terminal 56 a of the switch 56. The output of the reference oscillator 53 is connected to the other terminal 52 c of the switch 52 and is connected to the demodulation input terminal 1 a of the PLL modulator / demodulator 1 through the common terminal 52 b of the switch 52.

  Further, the modulation output terminal 1 d of the PLL modulator / demodulator 1 is connected to the other terminal 57 c of the switch 57 and to the input of the PLL oscillator 49 via the common terminal 57 b of the switch 57. The output of the PLL oscillator 49 is connected to the input of the power amplifier 59 via the high frequency output terminal 58.

  The output of the power amplifier 59 is connected to the other terminal 44 c of the switch 44 and also connected to the antenna 43 via the common terminal 44 a of the switch 44. The PLL loop control input terminal 60 to which control data is input is connected to the PLL control terminal 1 e of the PLL modem 1.

  At this time, when the control data from the PLL loop control input terminal 60 is input to the PLL modulator / demodulator 1, the switching control of each of the switches 44, 52, 56, 57 becomes possible. However, the respective connections to the switches 44, 52, 56 and 57 by the PLL modulator / demodulator 1 are not shown. In the switches 44, 52, 56, and 57, the solid line represents the connection at the time of reception, and the dotted line represents the connection at the time of transmission.

  The operation of the digital signal transceiver configured as described above will be described below. First, the receiving system 41 will be described. First, the switch 44 switches so that the common terminal 44a is connected to one terminal 44b. Then, the high-frequency reception signal received by the antenna 43 is input to the reception filter 45 via one terminal 44b of the antenna switch 44, and a desired signal is selected. This desired signal is amplified by the high frequency amplifier 46 and then mixed with the output of the PLL oscillator 49 via the high frequency input terminal 47 in the reception mixer 48 to be output from the reception mixer 48 as an intermediate frequency. At this time, the switch 57 is set so that the output of the reference oscillator 53 is input to the PLL oscillator 49, whereby the oscillation frequency of the PLL oscillator 49 is determined.

  Further, the intermediate frequency signal output from the receiving mixer 48 is further selected by the intermediate frequency filter 50 and a nearby noise signal is removed, and is amplified by the intermediate frequency amplifier 51. At this time, the switch 52 is set so that the output of the intermediate frequency amplifier 51 is connected to the demodulation input terminal 1 a of the PLL modem 1.

  Therefore, the desired signal output from the intermediate frequency amplifier 51 is supplied to the demodulation input terminal 1 a of the PLL modulator / demodulator 1 via the switch 52, so that the desired signal is demodulated by the PLL modulator / demodulator 1. Therefore, the demodulated digital signal from the demodulation output terminal 1 b of the PLL modulator / demodulator 1 is output from the reception output terminal 54.

  At this time, the switch 57 is set so that the output of the reference oscillator 53 is input to the PLL oscillator 49. The switch 56 is set so that the common terminal 56a is connected to one terminal 56b. Therefore, the transmission input terminal 1 c of the PLL modem 1 is connected to the ground via the switch 56. As a result, the PLL modem 1 operates as a demodulator.

  Next, the transmission system 42 will be described. In the transmission system 42, the digital signal input to the transmission input terminal 55 is supplied to the other terminal 56 c of the switch 56. At this time, the switch 56 is set so that the other terminal 56c is connected to the common terminal 56a. Therefore, the digital signal input to the transmission input terminal 55 is supplied to the transmission input terminal 1 c of the PLL modulator / demodulator 1 via the switch 56.

  On the other hand, the output of the reference oscillator 53 is supplied to the other terminal 52 c of the switch 52. At this time, the switch 52 is selected so that the other terminal 52c and the common terminal 52b are connected. Therefore, the output of the reference oscillator 53 is supplied to the demodulation input terminal 1 a of the PLL modem 1 via the switch 52. Thereby, the PLL modem 1 operates as a modulator.

  That is, the digital signal input to the transmission input terminal 55 becomes a transmission signal digitally modulated by the PLL modulator / demodulator 1, and this transmission signal is supplied to the other input terminal 57 c of the switch 57. At this time, the switch 57 is selected so that the other input terminal 57c and the common terminal 57b are connected. Therefore, the digitally modulated transmission signal from the modulation output terminal 1 d of the PLL modulator / demodulator 1 is supplied to the input of the PLL oscillator 49 via the switch 57.

  Further, the high-frequency transmission signal that is the output of the PLL oscillator 49 is amplified by the power amplifier 59 via the transmission output terminal 58. Thereafter, the signal is input to the other terminal 44 c of the antenna switch 44. At this time, the other terminal 44c of the antenna switch 44 and the common terminal 44a are selected to be connected. Therefore, the high-frequency transmission signal that is the output of the power amplifier 59 is transmitted from the antenna 43 via the antenna switch 44.

  At this time, the settings at the time of demodulation or modulation by the antenna switch 44, switch 52, switch 56, switch 57, and the PLL modulator / demodulator 1 are such that the control data input to the PLL loop control input terminal 60 is the PLL modulator / demodulator 1. Switching control is possible at the time of reception and at the time of transmission. However, the connection to the antenna switch 44, the switch 52, the switch 56, and the switch 57 by the PLL loop control unit 11 is not illustrated.

  Furthermore, the frequency relationship from the input to the output in the digital signal transceiver according to the present invention will be described as a representative example with reference to FIGS.

  First, in a reception state, a high-frequency reception signal of 915 MHz is input to the reception mixer 48 via the antenna 43 and then converted to a signal of 10.7 MHz, which is an intermediate frequency. This 10.7 MHz signal is input from the demodulation input terminal 1a of the PLL modulator / demodulator 1 and then converted into a 1.07 MHz signal divided by 1/10 by the reference frequency divider 2 to obtain a phase comparator. 3 is input.

  Here, the oscillation frequency of the voltage controlled oscillator 8 is controlled to 38.52 MHz by the PLL loop circuit 10. This 38.52 MHz signal is divided by 1/36 by the comparison frequency divider 9 to become a 1.07 MHz signal. This 1.07 MHz signal is supplied to the other input of the phase comparator 3.

  At this time, the charge pump current is 6 mA. The cutoff frequency of the low-pass filter 6 is about 70 kHz, and a digital signal up to 19.2 kbps is demodulated.

  Next, the transmission state will be described. The frequency 16.8 MHz of the reference oscillator 53 is input from the demodulation input terminal 1 a of the PLL modem 1 via the switch 52. The frequency 16.8 MHz of the reference oscillator 53 is frequency-divided by 1/560 by the reference frequency divider 2 to become a 30 kHz signal, and is further supplied to one input of the phase comparator 3.

  Here, the oscillation frequency of the voltage controlled oscillator 8 is controlled to 38.52 MHz by the PLL loop circuit 10. This 38.52 MHz is divided by 1/1284 by the comparison frequency divider 9 to become a 30 kHz signal, and is further input to the other terminal of the phase comparator 3.

  At this time, the charge pump current is 1.5 mA. The cut-off frequency of the low-pass filter 7 is about 400 Hz, and a digital modulation signal up to 1 kbps is realized.

  FIG. 4 is a timing chart at the time of PLL loop control in the digital signal transceiver according to the second embodiment of the present invention. In FIG. 4, reference numeral 61 denotes transmission / reception data including reception data 61a and 61c received by the antenna 43 and transmission data 61b. Here, for example, 5 msec is provided as the switching period 62 between the reception data 61a and the transmission data 61b.

  Corresponding to the transmission / reception data 61, switching data of the antenna switch 44 is represented by 63. For example, when data 0 indicated by 63a and 63c is input to the PLL loop control input terminal 60 during reception, the common terminal 44a of the antenna switch 44 is connected to one terminal 44b, and during transmission, the PLL loop control input terminal When data 1 indicated by 63b is input to 60, the common terminal 44a is connected to the other terminal 44c.

  At this time, the rising time 62a of the data 63b of the antenna switch 44 is substantially matched with the rising time of the transmission data 61b. Further, the fall time 62b of the data 63b of the antenna switch 44 is substantially coincident with the fall time of the transmission data 61b. This is because power consumption in the power amplifier 59 is reduced by minimizing the energization time of the power amplifier 59.

  Further, the switching data of the switch 52 is represented by 64. For example, when data 0 indicated by 64a and 64c is input to the PLL loop control input terminal 60 during reception, the common terminal 52b of the switch 52 is connected to one terminal 52a, and during transmission, the PLL loop control input terminal 60 is input. The data 1 indicated by 64b is input to the common terminal 52b, and the common terminal 52b is connected to the other terminal 52c.

  At this time, the rise time of the data 64b of the switch 52 is substantially matched with the fall time 62c of the received data 61a. As a result, simultaneously with the end of the reception data 61a, the output of the reference oscillator 53 is supplied to one input of the phase comparator 3.

  The switching data of the PLL modulator / demodulator 1 is denoted by 65. For example, when receiving, data 0 indicated by 65a and 65c is input to the PLL loop control input terminal 60, and when transmitting, data 1 indicated by 65b is input to the PLL loop control input terminal 60 and transmitted. It becomes.

  At this time, the rising time 62d of the data 65b of the PLL modem 1 is delayed by about 0.2 msec from the rising time 62c of the digital data 64b of the switch 52.

  Further, the switching data of the switch 57 is represented by 66. For example, data 0 indicated by 66a and 66c is input to the PLL loop control input terminal 60 at the time of reception, and the common terminal 57b of the switch 57 is connected to one terminal 57a to enter a reception state, and at the time of transmission, the PLL loop control input terminal The digital data 1 indicated by 66b is input to 60, and the common terminal 57b is connected to the other terminal 57c to enter the transmission state.

  At this time, the rising time 62e of the data 66b of the PLL modem 1 is delayed by about 0.2 msec from the rising time 62d of the data 65b of the PLL modem 1.

  As described above, in the switching period 62 from the reception data 61a to the transmission data 61b, the signal of the reference oscillator 53 is first supplied to the phase comparator 3 via the reference frequency divider 2. Thereafter, the PLL modulator / demodulator 1 is switched from demodulation to modulation, and the oscillation frequency of the voltage controlled oscillator 8 of the PLL loop circuit 10 is controlled.

  At this time, the signal of the reference oscillator 53 is already supplied to one input of the phase comparator 3, and the reference signal to be compared is determined. For this reason, the PLL loop response time of the PLL modem 1 can be further shortened.

  Thereafter, the switch 57 is switched from the reception state to the transmission state. Therefore, a transmission signal having a predetermined frequency is supplied to the input of the PLL oscillator 49. For this reason, the time until the PLL oscillator 49 is stabilized is shortened.

  That is, since the switching period 62, which is the interval between transmission data and reception data, can be shortened, the amount of transmission / reception data within a certain time can be increased.

  In the PLL modulator / demodulator according to the present invention, a single PLL loop circuit can be shared as a modulator at the time of transmission and as a demodulator at the time of reception by the control data from the PLL loop control terminal. Since it can be realized, it is useful for miniaturization and rational design of digital signal transceivers.

Block diagram of a PLL modem in Embodiment 1 of the present invention Same as above, PLL loop response characteristics in PLL modulator / demodulator Block diagram of a digital transceiver using a PLL modulator / demodulator in Embodiment 2 of the present invention Same as above, timing chart for PLL loop control in digital signal transceiver Block diagram of a conventional digital signal transceiver

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 PLL modem 1a Demodulation input terminal 1b Demodulation output terminal 1c Modulation input terminal 1d Modulation output terminal 1e PLL control terminal 2 Reference frequency divider 3 Phase comparator 4 Charge pump 5 Switch 6 Low pass filter 7 Low pass filter 8 Voltage Control oscillator 9 Comparison frequency divider 10 PLL loop circuit 11 PLL control unit

Claims (4)

A first input terminal; a reference frequency divider to which a signal input to the first input terminal is supplied; a phase comparator to which an output of the reference frequency divider is supplied to one input; A charge pump to which the output of the comparator is supplied, a low-pass filter to which the output of the charge pump is supplied, a voltage-controlled oscillator to which the output of the low-pass filter is supplied to one input, and an output of the voltage-controlled oscillator A comparison frequency divider connected to the other input of the phase comparator; a first output terminal connected to the output of the low pass filter; and a first output terminal connected to the other input of the voltage controlled oscillator. 2 input terminals, a second output terminal connected to the output of the voltage controlled oscillator, the reference frequency divider, the phase comparator, the charge pump, the low pass filter, the voltage controlled oscillator, and the comparison A PLL loop circuit including a frequency divider, a PLL loop control unit for controlling the PLL loop circuit, and a PLL loop control terminal for controlling the PLL loop control unit, and digital modulation at the first input terminal The received signal is input, the second input terminal is connected to the ground, the digital signal obtained by demodulating the received signal is output from the first output terminal to form a demodulator, A reference oscillator signal is input to the first input terminal, a digital signal is input to the second input terminal, and a digitally modulated transmission signal is output from the second output terminal for modulation. And the modulator sets the cut-off frequency of the low-pass filter to be lower than that at the time of demodulation by the control data from the PLL loop control terminal. Set to a small charge and discharge current of the charge pump, PLL modem to set lower the phase comparison frequency. In the digital signal transceiver having the reception system, the transmission system, and the PLL modulator / demodulator according to claim 1, in the reception system, a high-frequency reception signal is supplied to one input via a high-frequency input terminal, and the PLL oscillator A receiving mixer whose output is supplied to the other input, a PLL modulator / demodulator whose output is supplied to the first input terminal via the first switch, and a first PLL of this PLL modulator / demodulator A receiving output terminal to which a digital signal output from the output terminal is supplied, a reference oscillator to which a signal is supplied to the input of the PLL oscillator via a second switch, and a second input of the PLL modulator / demodulator A third switch connected to the common terminal and connected to the ground, and in the transmission system, the digital signal input to the modulation input terminal is the third switch. A PLL modulator / demodulator that is input to a second input terminal of the PLL modulator / demodulator via a switch and an output of the reference oscillator is supplied to the first input terminal via the first switch; The PLL oscillator to which the digitally modulated transmission signal from the second output terminal of the PLL modulator / demodulator is supplied via the second switch, and the high-frequency transmission signal that is the output of the PLL oscillator are supplied. A digital signal transceiver comprising a high-frequency output terminal and enabling reception and transmission by switching each of the first, second and third switches. 3. The digital signal transceiver according to claim 2, wherein in switching from the reception system to the transmission system, the PLL modulator / demodulator is switched from demodulation to modulation after switching the first switch. When switching from the reception system to the transmission system, the first switch is switched first, then the PLL modulator / demodulator is switched from demodulation to modulation, and then the second switch is switched after switching the PLL modulator / demodulator from demodulation to modulation. The digital signal transceiver according to claim 2.

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