JP2005072893A - Radio communication reception circuit and dc offset voltage correction method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately correct the output DC offset voltage of a gain control amplifier and to prevent the generation of the output DC offset voltage even in the case of changing a gain after correcting the output DC offset voltage in a radio communication reception circuit. <P>SOLUTION: A DC offset correction circuit 110 (111) comprises a chopper type comparator 113 for judging the size relation of the differential output DC voltage of the gain control amplifier 106 (108), a DC offset correction control circuit 114 for outputting offset correction control data corresponding to the size relation of the differential output DC voltage of the gain control amplifier, and a DC control circuit 115 for controlling the offset of the differential input DC voltage of the gain control amplifier corresponding to the offset correction control data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a direct conversion wireless communication receiving circuit.

  There is an increasing demand for miniaturization and cost reduction for wireless communication devices, and there is a direct conversion method as a method that can reduce the number of parts. However, the direct conversion method also has drawbacks, and one of the major drawbacks is a DC offset voltage.

  The timing at which the DC offset voltage can be corrected differs depending on the communication method. FIG. 8 shows the relationship between reception slots and transmission slots in a TDMA (Time Division Multiple Access) system such as GSM (Global System for Mobile communication) in Europe and PDC (Personal Digital Cellular) in Japan. Indicates. In GSM and PDC, since reception and transmission are performed alternately in time, the DC offset voltage can be corrected immediately before the reception slot is input.

  Therefore, in GSM and PDC, the DC offset voltage can be corrected after the gain of the gain control amplifier is determined. Therefore, if the DC offset voltage is corrected every time a reception slot is input, the DC offset voltage can be reduced. It is possible not to change the gain after correction.

  However, W-CDMA (Wide-band Code-Division Multiple Access) system performs continuous reception. FIG. 9 shows the relationship between reception slots and transmission slots in the W-CDMA system. As shown in FIG. 9, the timing at which the DC offset voltage can be corrected by the W-CDMA system is only the period from when the receiving circuit is activated to the active state until the receiving slot is input. In the reception state, there is no timing for correcting the DC offset voltage.

  Therefore, in a communication system that performs continuous reception such as the W-CDMA system, it is necessary to correct the DC offset voltage before the reception slot is input after the reception circuit is activated.

  Therefore, unlike the TDMA system such as GSM and PDC, the gain changes even after correcting the DC offset voltage in the W-CDMA system.

  Also in a conventional direct conversion type receiving circuit, the DC offset voltage is corrected (for example, see Patent Document 1). The configuration diagram is shown in FIG.

  In FIG. 6, the conventional receiving circuit includes a gain control amplifier, an analog / digital converter ADC 607, a control circuit 608, and digital / analog converters DACs 609 and 610. The gain control amplifier includes transistors 601 and 602 connected to each other's emitters, resistors 603 and 604 connected between the collectors of these transistors and the power supply Vdd, and emitters of the differential pair of transistors 601 and 602, respectively. The transistor 605 is connected, and a resistor 606 is connected between the emitter of the transistor 605 and the ground. Note that reference numerals 611 and 612 denote input terminals of the gain control amplifier, and reference numerals 613 and 614 denote output terminals of the gain control amplifier.

  Next, the operation of the conventional receiving circuit configured as described above will be described.

  The gain control amplifier controls the gain by controlling the current flowing through the transistor 605. Further, the ADC 607 compares the DC voltage at the output terminals 613 and 614 of the gain control amplifier, and the control circuit 608 controls the DACs 609 and 610, and flows current from the DACs 609 and 610 into the resistors 603 and 604. Correction of the DC offset voltage at the output terminals 613 and 614 is performed.

  With the above configuration and operation, the output DC offset voltage of the gain control amplifier can be corrected. However, if the gain is changed after correcting the output DC offset voltage, the output DC offset voltage of the gain control amplifier is generated again. become. This will be described below.

  When the DC offset voltage is generated at the output terminals 613 and 614 of the gain control amplifier due to the resistance value of the resistor 603 varying to R1 and the resistance value of the resistor 604 varying to R2, first, the current Idac is caused to flow from the DACs 609 and 610. Next, the output DC offset voltage of the gain control amplifier is corrected, and then the DC offset voltage of the gain control amplifier when the gain is changed will be considered. Note that Ig is a current that flows in the transistor 605 that is a current source of the gain control amplifier.

  If the voltages at the input terminals 611 and 612 of the gain control amplifier are the same, the currents flowing through the resistors 603 and 604 are the same. If the current flowing through these resistors is Ir, the current Ir is expressed as ).

Ir = Ig / 2 (Formula 1)
If the respective voltages of the output terminals 613 and 614 of the gain control amplifier are Vout3 and Vout4 and the power supply voltage is Vdd, the output voltages Vout3 and Vout4 are expressed by the following (Expression 2) and (Expression 3), respectively. .

Vout3 = Vdd−R1 · Ir
= Vdd-R1 · Ig / 2 (Formula 2)
Vout4 = Vdd−R2 · Ir
= Vdd-R2 · Ig / 2 (Formula 3)
If the DC offset voltage of the output of the gain control amplifier is Vdc, the DC offset voltage Vdc is expressed by the following (Expression 4) from the above (Expression 1), (Expression 2), and (Expression 3).

Vdc = Vout3-Vout4
= (R2-R1) · Ig / 2 (Formula 4)
Therefore, the DC offset voltage Vdc represented by the above (formula 4) is generated in the gain control amplifier output.

  Next, the DC offset voltage of the gain control amplifier output is corrected by flowing current from the DACs 609 and 610 to the gain control amplifier output. When the current Idac is fed from the DAC 610 to the output terminal 613 of the gain control amplifier and the same current Idac is pulled from the output terminal 614 of the gain control amplifier to the DAC 609, the output pressures Vout3 and Vout4 of the gain control amplifier are as follows. (Expression 5) and (Expression 6).

Vout3 = Vdd−R1 · (Ig / 2−Idac) (Formula 5)
Vout4 = Vdd−R2 · (Ig / 2 + Idac) (Formula 6)
Therefore, in order to correct the output DC offset voltage by Idac, Vout3 expressed by (Expression 5) is equal to Vout4 expressed by (Expression 6). That is, the following (Expression 7) is established. There is a need to.

Vdd-R1. (Ig / 2-Idac)
= Vdd-R2 · (Ig / 2 + Idac) (Formula 7)
Accordingly, Idac satisfying (Expression 7) is obtained by the following (Expression 8).

Idac = (R1−R2) · Ig / [2 · (R1 + R2)] (Equation 8)
From the above, when the resistance values of the resistors 603 and 604 vary in R1 and R2, respectively, the output DC offset voltage of the gain control amplifier can be corrected by flowing the current Idac represented by (Equation 8) from the DAC. it can.

  If the gain at this time is G0, the gain G0 is expressed by the following (Equation 9).

G0 = (R1 + R2) · Ig · q / 4kT (Formula 9)
Here, q is a charge amount of electrons, k is a Boltzmann constant, and T is an absolute temperature.

  Next, after correcting the output DC offset voltage of the gain control amplifier, the output DC offset voltage when the gain is changed is obtained.

  In this case, Idac, which is the current of the DAC, remains as (Equation 8), and a case is considered in which the current of the transistor 605 serving as the current source of the gain control amplifier is changed from Ig to Ig · α. If the gain when the current of the transistor 605 is Ig · α is Ga, Ga is expressed by the following (formula 10).

Ga = (R1 + R2) · α · Ig · q / 4kT (Formula 10)
From (Expression 9) and (Expression 10), α becomes (Expression 11) below.

α = Ga / G0 (Formula 11)
The output voltages Vout3 and Vout4 at the output terminals 613 and 614 of the gain control amplifier when the gain is changed from G0 to Ga are expressed by the following (Expression 12) and (Expression 13), respectively.

Vout3 = Vdd−R1 · (α · Ig / 2−Idac) (Expression 12)
Vout4 = Vdd−R2 · (α · Ig / 2 + Idac) (Formula 13)
The output DC offset voltage Vdc of the gain control amplifier at this time is expressed by the following (Equation 14).

Vdc = Vout3-Vout4
= (R2−R1) · α · Ig / 2 + Idac · (R1 + R2)
... (Formula 14)
Substituting (Expression 8) representing Idac into (Expression 14) above, Vdc is expressed as (Expression 15) below.

Vdc = (R2-R1) · (α-1) · Ig / 2 (Equation 15)
Substituting (Expression 11) representing α into (Expression 15), Vdc becomes as shown in (Expression 16) below.

Vdc = (R2-R1). (Ga / G0-1) .Ig / 2 (Formula 16)
The above (Equation 16) shows the output DC offset voltage of the gain control amplifier when the gain is changed from G0 to Ga after correcting the output DC offset voltage of the gain control amplifier.

Here, the relationship between Vdc and Ga in the above (formula 16) is shown in FIG. As shown in FIG. 7, in the conventional example, when the gain is changed after correcting the output DC offset voltage of the gain control amplifier, the output DC offset voltage is generated again, and its value changes in proportion to the gain.
JP 2001-211098 A

  As described above, conventionally, when the gain is changed after correcting the DC offset voltage, the DC offset voltage is generated again, which is a problem in a communication system such as W-CDMA system that performs continuous reception.

  The present invention has been made in view of such a problem, and an object of the present invention is to correct the output DC offset voltage of the gain control amplifier with high accuracy, and to change the gain after correcting the output DC offset voltage. However, it is an object of the present invention to provide an excellent wireless communication receiving circuit and a DC offset voltage correction method that do not generate an output DC offset voltage.

  In order to achieve the above object, a wireless communication receiving circuit according to the present invention receives a preamplifier for amplifying a received RF signal, an RF signal from the preamplifier and a local signal generated locally, and converts the RF signal into a baseband signal. A mixer for conversion, a differential input / output gain control amplifier that variably controls the gain to amplify the baseband signal, a low-pass filter that removes high-frequency components from the output signal from the gain control amplifier, and a gain control amplifier And a DC offset correction circuit for correcting an output DC offset voltage of the gain control amplifier, wherein the DC offset correction circuit is a differential output DC voltage of the gain control amplifier. A chopper comparator that determines the magnitude relationship between the A DC offset correction control circuit that controls the par comparator to output offset correction control data corresponding to the magnitude relationship of the differential output DC voltage of the gain control amplifier, and a difference between the gain control amplifier according to the offset correction control data And a DC control circuit for controlling the offset of the dynamic input DC voltage.

  In the wireless communication receiving circuit according to the present invention, the chopper comparator compares the first control signal from the DC offset correction control circuit with a first one that conducts / cuts off one of the differential output DC voltages of the gain control amplifier. In response to a second control signal having a phase opposite to that of the first control signal from the switch and the DC offset correction control circuit, the second of the differential output DC voltage of the gain control amplifier is turned on / off. The DC offset is obtained by inverting and amplifying the voltage of the switch, the capacitor to which the differential output DC voltage of the gain control amplifier is supplied to the first terminal via the first and second switches, and the voltage of the second terminal of the capacitor. A third inverter connected between the inverting amplifier output to the correction control circuit and the input / output terminals of the inverting amplifier and controlled to open and close according to the first control signal. It is preferable and a pitch.

  According to the above configuration, the output DC offset voltage of the gain control amplifier can be corrected with high accuracy.

  The wireless communication receiving circuit according to the present invention further includes an antenna that receives an RF radio wave, and a switch that switches a path from the antenna to the preamplifier.

  According to this configuration, in a communication system that performs continuous reception such as the W-CDMA system, reception can be performed stably.

  In the radio communication receiving circuit according to the present invention, the DC control circuit includes a digital / analog converter that converts the offset correction control data from the DC offset correction control circuit into an analog voltage, and a reference voltage for the digital / analog converter. A reference voltage generation circuit that generates the voltage, a voltage-current conversion circuit that converts a differential voltage between the voltage from the digital / analog converter and the reference voltage into a differential current, one input terminal of the gain control amplifier, and a voltage-current A first resistor having one output terminal of the differential current from the conversion circuit connected to one end, the other input terminal of the gain control amplifier, and the other output terminal of the differential current from the voltage-current conversion circuit It is preferable to provide a second resistor connected to one end.

  According to this configuration, it is possible to realize a function of correcting the output DC offset voltage of the gain control amplifier by flowing a differential current into the first resistor and the second resistor and generating an offset voltage at the input of the gain control amplifier. . Thereby, even if the gain is changed after correcting the DC offset voltage, the DC offset voltage is not generated again.

  In the wireless communication receiver circuit according to the present invention, the gain control amplifier includes a differential input / output type operational amplifier, an input resistor connected to the differential input terminal of the operational amplifier, and a differential input terminal of the operational amplifier. It is preferable to include a plurality of feedback resistors connected between the differential output terminals and a plurality of switches that switch connection states of the plurality of feedback resistors in order to perform gain control.

  According to this configuration, the linearity of the gain control amplifier can be improved, and further, even if the gain is changed after correcting the output DC offset voltage, the DC offset voltage is not regenerated.

  Alternatively, in the wireless communication receiving circuit according to the present invention, the gain control amplifier includes a first operational amplifier that functions as a normal amplifier, a second operational amplifier that functions as a normal amplifier, and an inversion of the first operational amplifier. A plurality of first feedback resistors connected between the input terminal and the output terminal, a plurality of second feedback resistors connected between the inverting input terminal and the output terminal of the second operational amplifier, and a gain A first switch that switches connection states of the plurality of first feedback resistors to perform control; and a second switch that switches connection states of the plurality of second feedback resistors to perform gain control. preferable.

  According to this configuration, the input impedance of the gain control amplifier can be increased, and even if the gain is changed after correcting the output DC offset voltage, the output DC offset voltage is not regenerated.

  In order to achieve the above object, a DC offset voltage correction method according to the present invention is a DC offset voltage correction method for a gain control amplifier output in a wireless communication receiver circuit according to the present invention, and includes: (a) a DC offset correction control circuit; The step of controlling the chopper type comparator by (b) the step of (b) determining the magnitude relation of the differential output DC voltage of the gain control amplifier by the chopper type comparator, and (c) the DC when the chopper type comparator is in the comparison operation state. The step of reading the output voltage from the chopper comparator by the offset correction control circuit, and (d) the gain control amplifier by the DC control circuit according to the offset correction control data at the timing when the chopper comparator moves from the comparison operation state to the reset state. A step of changing the output DC offset, characterized by comprising a step of correcting the (e) by the steps (a) through (d) are repeated a plurality of times, the output DC offset of the gain control amplifier.

  According to this method, the output DC offset voltage of the gain control amplifier can be corrected with high accuracy.

  According to the present invention, it is possible to correct the output DC offset voltage of the gain control amplifier with high accuracy, and even if the gain is changed after correcting the output DC offset voltage, an excellent wireless communication that does not generate the output DC offset voltage. A communication receiving circuit and a wireless communication receiving method can be realized.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration example of a wireless communication receiving circuit according to the first embodiment of the present invention. In FIG. 1, the radio communication receiving circuit of this embodiment includes an antenna 101 for receiving RF radio waves, a switch 102, an LNA (Low Noise Amplifier) 103 as a preamplifier for amplifying an RF signal, a mixer 104, and a gain control. It comprises amplifiers 106 and 108, low-pass filters 107 and 109, and DC offset correction circuits 110 and 111.

  The mixer 104 receives the RF signal from the LNA 103 and the locally generated local signal from the local signal input terminal 105, and converts the RF signal into a baseband signal. The gain control amplifier 106 amplifies the baseband signal from the mixer 104 by variably controlling the gain. The low pass filter 107 removes a high frequency component in the output signal of the gain control amplifier 106. The gain control amplifier 108 amplifies the baseband signal from the low-pass filter 107 by variably controlling the gain. The low-pass filter 109 removes high frequency components in the output signal of the gain control amplifier 108.

  The DC offset correction circuit 110 is connected between the input / output terminals of the gain control amplifier 106 and corrects the output DC offset voltage of the gain control amplifier 106. The DC offset correction circuit 111 is connected between the input and output terminals of the gain control amplifier 108 and corrects the output DC offset voltage of the gain control amplifier 108. Although the internal configuration of the DC offset correction circuit 111 is not illustrated in FIG. 1, it is the same as the internal configuration of the DC offset correction circuit 110, and therefore the configuration and operation of the DC offset correction circuit 110 will be described below. To do.

  The DC offset correction circuit 110 includes a chopper comparator 113, a DC offset correction control circuit 114, and a DC control circuit 115.

  The chopper comparator 113 includes a first switch constituted by a first n-type MOS transistor 116, a first p-type MOS transistor 117, and a first inverter 118, a second n-type MOS transistor 119, 2 p-type MOS transistor 120 and a second switch constituted by a second inverter 121, a third n-type MOS transistor 123, a third p-type MOS transistor 124, and a third inverter 125. The third switch, an inverting amplifier composed of the fourth n-type MOS transistor 126 and the fourth p-type MOS transistor 127, a fifth n-type MOS transistor 128, and a capacitor 122. .

  In FIG. 1, i and j represent the first terminal and the second terminal of the capacitor 122, respectively. The second terminal j is composed of a fourth n-type MOS transistor 126 and a fourth p-type MOS transistor 127. It is also the input terminal of the inverting amplifier.

  Next, the operation of the DC offset correction circuit 110 configured as described above will be described with reference to FIG. FIG. 2 is a timing chart of each signal in the DC offset correction circuit 110 of FIG.

  2, a, b, and c are control signals for the chopper comparator 113 (a is a first control signal, b is a second control signal), and d is an output signal of the chopper comparator 113 (also abbreviated as a comparator output signal). E, f are output signals of opposite polarities to the gain control amplifier 106, and ef is an output DC offset voltage of the gain control amplifier 106.

  Whether or not to perform output DC offset correction is controlled by the control signal c from the DC offset correction control circuit 114, and the fifth n-type MOS transistor 128 is turned off during the period in which the control signal c is logic logic low. DC offset correction is performed. When the control signal c is logic logic high, the fifth n-type MOS transistor 128 is turned on, the second terminal of the capacitor 122 is fixed to logic logic low, and the output DC offset is not corrected.

  When the control signal c becomes logic logic low and the DC offset correction starts at time t1 in FIG. 2, both the first control signal a and the second control signal b are logic logic low, and the time t2 , The first control signal a becomes logic logic high.

  From time t2 to t3, the first control signal a is logic high and the second control signal b is logic low. During this period, the first n-type MOS transistor 116 and the first p-type MOS transistor 117 and the first switch constituted by the first inverter 118, and the third switch constituted by the third n-type MOS transistor 123, the third p-type MOS transistor 124, and the third inverter 125. Is short-circuited, and the second switch constituted by the second n-type MOS transistor 119, the second p-type MOS transistor 120, and the second inverter 121 is in an open state.

  At this time, since the input terminal and the output terminal of the inverting amplifier constituted by the fourth n-type MOS transistor 126 and the fourth p-type MOS transistor 127 are short-circuited, if the power supply voltage of the inverting amplifier is Vdd, the inverting amplifier The voltage at the input terminal j of the amplifier and the signal d at the output terminal are settled at a voltage of Vdd / 2, and the chopper comparator 113 is reset.

  Further, since the output signal f of the gain control amplifier 106 is supplied to the first terminal i of the capacitor 122 and the second terminal j becomes Vdd / 2, Vdd / 2 and the gain control amplifier 106 are supplied to the capacitor 122. Charge corresponding to the difference between the output signal f and the DC voltage is charged.

  Next, at time t3, the first control signal a becomes logic low, the second control signal b becomes logic high, and the states of the first control signal a and the second control signal b continue until time t5. In the period from t3 to t5, the first switch and the third switch are in an open state, and the second switch is in a short state.

  At this time, the input terminal and the output terminal of the inverting amplifier are opened, and the charge amount of the capacitor 122 does not change from the charge amount stored between time t2 and t3.

  Further, since the output signal e of the gain control amplifier 106 is supplied to the first terminal i of the capacitor 122, if the DC voltage of the output signal e of the gain control amplifier 106 is larger than the DC voltage of the output signal f, the capacitor The second terminal j changes so that the voltage amount of the DC offset between the output signal e and the output signal f becomes larger than Vdd / 2, and the change amount is inverted and amplified by the inverting amplifier, and the output signal of the inverting amplifier is output. d becomes logic low.

  If the DC voltage of the output signal e of the gain control amplifier 106 is smaller than the DC voltage of the output signal f, the second terminal j of the capacitor is Vdd / 2 by the voltage amount of the DC offset between the output signal e and the output signal f. The amount of change is inverted and amplified by the inverting amplifier, and the output signal d of the inverting amplifier becomes logic high.

  Therefore, the period from time t3 to t5 is a period in which the chopper comparator 113 compares the DC voltages of the output signals e and f of the gain control amplifier 106 in the period from time t2 to t5, and determines which is greater. If the output signal e of the gain control amplifier 106 is larger than the output signal f, the comparator output signal d becomes logic low, and if the output signal f is larger than the output signal e, the comparator output signal d becomes logic high.

  The DC offset correction control circuit determines which of the output signal e and the output signal f of the gain control amplifier 106 is greater by reading the comparator output signal d into the DC offset correction control circuit 114 at time t4 within the period from time t3 to t5. 114, the DC offset correction control circuit 114 controls the DC control circuit 115 at the timing of time t5, and controls the input DC voltage of the gain control amplifier 106 in a direction in which the output DC offset of the gain control amplifier 106 decreases. .

  In this control, the timing for reading the comparator output signal d into the DC offset correction control circuit 114 is shifted from the rising edge and falling edge of the first control signal a and the second control signal b, whereby the first control signal a Thus, the erroneous determination of the comparator caused by the second control signal b jumping into the comparator output d can be prevented.

  Note that the timing for reading the comparator output signal d into the DC offset correction control circuit 114 may be any time as long as it is a period between times t3 and t5.

  After the time t5, the control in the period from the time t2 to the time t5 is repeatedly performed until the output signal e of the gain control amplifier 106 and the DC offset voltage (ef) of the output signal f are corrected and disappear. repeat.

  In the present embodiment, the control from time t2 to time t5 is repeated five times, but may be repeated any number of times.

  As described above, according to the present embodiment, erroneous determination of the chopper type comparator 113 due to jumping of the control signal of the chopper type comparator 113 can be avoided, and correction of the output DC offset voltage of the gain control amplifier 106 can be performed with high accuracy. Can be done.

  FIG. 3 is a circuit diagram showing an internal configuration example of the DC control circuit 115 in the DC offset correction circuit 110 of FIG. 1 and a general configuration of the same gain control amplifier as the conventional example described with reference to FIG.

  In FIG. 3, the DC control circuit 115 includes a voltage output type DAC 303, a DAC reference voltage generation circuit 304, a voltage-current conversion circuit 305, a first resistor 301, and a second resistor 302.

  The first resistor 301 is connected between the output terminal 317 of the mixer 104 and the input terminal 313 of the gain control amplifier 106, and the second resistor 302 is an input of the output terminal 316 of the mixer 104 and the gain control amplifier 106. It is connected between the terminal 312.

  The DC control circuit 115 outputs the output voltage of the voltage output type DAC 303 to which the offset correction control data (g) from the DC offset correction control circuit 114 (FIG. 1) is input, and the reference voltage generated by the DAC reference voltage generation circuit 304. Is converted into a current by the voltage-current conversion circuit 305, and the converted current is fed into the first resistor 301 and the second resistor 302, whereby the offset voltage is applied to the input terminals 312 and 313 of the gain control amplifier 106. And a function of correcting the output DC offset voltage of the gain control amplifier 106.

  Next, correction of the output DC offset voltage of the gain control amplifier 106 when the gain is changed after the output DC offset voltage of the gain control amplifier 106 is corrected by the DC control circuit 115 shown in FIG. 3 will be described.

  The gain control amplifier 106 is the same gain control amplifier as in the conventional example. That is, the gain control amplifier 106 includes transistors 306 and 307 connected to each other's emitters, resistors 308 and 309 connected between the collectors of these transistors and the power supply, and emitters of the transistors 306 and 307 of the differential pair. And a resistor 311 connected between the emitter of the transistor 310 and the ground, 312 and 313 are input terminals of the gain control amplifier 106, and 314 and 315 are output terminals of the gain control amplifier 106. Yes, the gain is controlled by controlling the current flowing through the transistor 310.

  As in the conventional example, it is assumed that the resistance value of the resistor 308 varies to R1, the resistance value of the resistor 309 varies to R2, and a DC offset occurs at the output terminals 314 and 315 of the gain control amplifier 106. A case where the gain is changed after correcting the output DC offset voltage of the gain control amplifier 106 by flowing the current Im from the conversion circuit 305 will be described.

  Let Ig3 be the current flowing through the transistor 310, which is the current source of the gain control amplifier 106. If the voltages at the input terminals 312 and 313 of the gain control amplifier 106 are the same, the currents flowing through the resistors 308 and 309 are the same, and the voltages at the output terminals 314 and 315 of the gain control amplifier 106 are Vout31 and Vout32, respectively. Assuming that the power supply voltage is Vdd, the DC voltages Vout31 and Vout32 of the gain control amplifier output are different as represented by the following (Equation 17) and (Equation 18), respectively, and a DC offset voltage is generated.

Vout31 = Vdd−R1 · Ig3 / 2 (Expression 17)
Vout32 = Vdd−R2 · Ig3 / 2 (Expression 18)
Next, the voltage-current conversion circuit 305 flows the current Im into the resistor 301 connected to the input terminal 313 of the gain control amplifier 106, and Im through the resistor 302 connected to the input terminal 312 of the gain control amplifier 106. , The output DC offset of the gain control amplifier 106 is corrected. Assuming that the base currents of the differential pair transistors 306 and 307 are small and can be ignored, the values of the resistors 301 and 302 are Rm, the voltages of the input terminals 312 and 313 of the gain control amplifier 106 are V33 and V34, respectively. Nodes 316 and 317 are nodes to which the preceding circuit of the gain control amplifier 106 (108) is connected. If the voltage V35 is the same, V33 and V34 are expressed by the following (Equation 19) and (Equation 20), respectively. expressed.

V33 = V35−Rm · Im (Equation 19)
V34 = V35 + Rm · Im (Expression 20)
Next, assuming that the current flowing through the resistor 308 is I31 and the current flowing through the resistor 309 is I32, I31 and I32 are expressed as follows using Ig3, V33, V34 and the above (formula 19) and (formula 20), respectively. It can be written as (Equation 21) and (Equation 22).

I31 = Ig3 / {1 + exp [4q · Rm · Im / kT]} (Formula 21)
I32 = Ig3 · exp [4q · Rm · Im / kT]
/ {1 + exp [4q · Rm · Im / kT]} (Formula 22)
Therefore, the output DC voltage of the gain control amplifier 106 after correcting the output DC offset voltage of the gain control amplifier 106 by flowing Im current from the voltage-current conversion circuit 305 in a state where the DC offset is generated. Vout31 and Vout32 are represented by the following (Equation 23) and (Equation 24), respectively.

Vout31 = Vdd−R1 · I31 (Equation 23)
Vout32 = Vdd−R2 · I32 (Equation 24)
After correcting the output DC offset voltage of the gain control amplifier 106, the output DC voltages Vout31 and Vout32 become equal, and the following (Expression 25) is established from the above (Expression 23) and (Expression 24).

R1 · I31 = R2 · I32 (Formula 25)
From the above (Expression 21), (Expression 22), and (Expression 25), the following (Expression 26) is established.

exp [4q · Rm · Im / kT] = R1 / R2 (Equation 26)
Therefore, after correcting the output DC offset voltage of the gain control amplifier 106, the current Im becomes a value satisfying the above (Equation 26). At this time, the voltages Vout31 and Vout32 of the output terminals 314 and 315 of the gain control amplifier 106 are as follows according to (Expression 21), (Expression 22), (Expression 23), (Expression 24), and (Expression 26), respectively. (Expression 27) and (Expression 28).

Vout31 = Vdd−Ig3 · R1 · R2 / (R1 + R2) (Expression 27)
Vout32 = Vdd−Ig3 · R1 · R2 / (R1 + R2) (Equation 28)
From the above, the DC offset voltage of the DC voltage at the output terminals 314 and 315 of the gain control amplifier 106 is corrected as represented by (Equation 27) and (Equation 28).

  Next, consider a case where the gain is changed after correcting the DC offset voltage at the output terminals 314 and 315 of the gain control amplifier 106. Changing the gain changes the current Ig3 flowing through the transistor 310. However, from the above (Equation 27) and (Equation 28), even if Ig3 is changed, Vout31 and Vout32 are equal, so the DC offset No voltage is generated.

  As described above, according to the present embodiment, it is possible to realize an excellent wireless communication receiving circuit in which no DC offset voltage is generated even if the gain is changed after correcting the DC offset voltage.

(Second Embodiment)
The second embodiment of the present invention is different from the first embodiment in the configuration of the gain control amplifier. FIG. 4 is a circuit diagram showing an example of the internal configuration of the gain control amplifier 106 in the second embodiment of the present invention and the same internal configuration of the DC control circuit 115 as that of the first embodiment. Hereinafter, only the gain control amplifier 106 will be described, but the same applies to the gain control amplifier 108.

  4, the gain control amplifier 106 includes input resistors 401 and 402, feedback resistors 403, 404, 406, and 407, switches 405 and 408, and a differential input / output operational amplifier 409. The gain control amplifier 106 according to the present embodiment is configured as a differential input / output inverting amplifier, and gain control is performed by switching the connection of a feedback resistor with a switch.

  The conventional gain control amplifier shown in FIGS. 3 and 6 is a circuit using a transistor differential circuit, but the distortion characteristic can be improved by the configuration of the gain control amplifier of this embodiment. Furthermore, the gain control is performed by switching the connection of the feedback resistors 403, 404, 405, and 406 with the switches 408 and 409. Thereby, even if the gain is changed after correcting the output DC offset voltage of the gain control amplifier, no DC offset is generated in the output of the gain control amplifier.

  In this embodiment, the case where the gain is controlled by switching in two stages is illustrated and described. However, when the gain is switched in multiple stages, the gain is controlled by connecting a plurality of sets of resistors and switches to the feedback path. Even in this case, even if the gain is changed after correcting the output DC offset voltage of the gain control amplifier, no DC offset occurs in the output of the gain control amplifier.

  As described above, according to the present embodiment, the distortion characteristic of the gain control amplifier is improved, and even if the gain is changed after the DC offset voltage is corrected, the DC offset voltage is not generated, and excellent wireless communication reception is achieved. A circuit can be realized.

(Third embodiment)
The third embodiment of the present invention is different from the first and second embodiments in the configuration of the gain control amplifier. FIG. 5 is a circuit diagram showing an example of the internal configuration of the gain control amplifier 106 according to the third embodiment of the present invention and the same internal configuration of the DC control circuit 115 as that of the first embodiment. Hereinafter, only the gain control amplifier 106 will be described, but the same applies to the gain control amplifier 108.

  In FIG. 5, the gain control amplifier 106 includes a resistor 501, first feedback resistors 502 and 503, a resistor 505, second feedback resistors 506 and 507, a first switch 504, and a second switch 508. And a first operational amplifier 509 and a second operational amplifier 510. The gain control amplifier 106 of the present embodiment is configured as two sets of forward rotation amplifiers, and the gain control is performed by connecting the first feedback resistors 502 and 503 of the first operational amplifier 509 with the first switch 504, The connection of the second feedback resistors 506 and 507 of the second operational amplifier 510 is switched by the second switch 508.

  In the conventional example, since the input impedance of the gain control amplifier is finite, when the output impedance of the previous circuit of the gain control amplifier is large, there is a possibility that the characteristics may be changed by connecting the previous circuit. However, according to the present embodiment, since the input impedance of the gain control amplifier 106 is large, it is possible to prevent a change in circuit characteristics due to the connection of the previous stage circuit.

  Further, the gain control is performed by switching the connection of the first feedback resistors 502 and 503 and the second feedback resistors 506 and 507 with the first switch 504 and the second switch 508, respectively. Thus, even if the gain is changed after correcting the output DC offset voltage of the gain control amplifier 106, no DC offset is generated in the output of the gain control amplifier 106.

  As described above, according to this embodiment, it is possible to avoid a change in the characteristics of the previous circuit of the gain control amplifier, and even if the gain is changed after correcting the DC offset voltage, no DC offset voltage is generated. An excellent wireless communication receiving circuit can be realized.

  The wireless communication receiving circuit according to the present invention can correct the output DC offset voltage of the gain control amplifier with high accuracy, and even if the gain is changed after correcting the output DC offset voltage, the output DC offset voltage is not generated. It is useful for communication systems that perform continuous reception such as W-CDMA.

1 is a circuit diagram showing a configuration example of a wireless communication receiving circuit according to a first embodiment of the present invention; Timing chart of each signal in DC offset correction circuit 110 (111) of FIG. 1 is a circuit diagram showing an internal configuration example of the DC control circuit 115 in the DC offset correction circuit 110 (111) of FIG. 1 and a general configuration of the same gain control amplifier as the conventional example described with reference to FIG. The circuit diagram which shows the internal structure example of the gain control amplifier 106 (108) in the 2nd Embodiment of this invention, and the internal structure of the DC control circuit 115 same as 1st Embodiment The circuit diagram which shows the internal structural example of the gain control amplifier 106 (108) in the 3rd Embodiment of this invention, and the internal structure of the DC control circuit 115 same as 1st Embodiment Circuit diagram showing a configuration example of a gain control amplifier and its output DC offset correction circuit in a conventional wireless communication receiving circuit The figure which shows the relationship between the output DC offset voltage Vdc and gain Ga of the gain control amplifier in the circuit shown in FIG. The figure which shows the relationship between the reception slot and transmission slot in TDMA systems, such as PDC and GSM The figure which shows the relationship between the transmission slot and reception slot in W-CDMA system which performs continuous reception

Explanation of symbols

101 antenna 102 switch 103 LNA (preamplifier)
104 mixer 105 local signal input terminal 106, 108 gain control amplifier 107, 109 low pass filter 110, 111 DC offset correction circuit 113 chopper type comparator 114 DC offset correction control circuit 115 DC control circuit 116 first n-type MOS transistor 117 First p-type MOS transistor 118 First inverter 119 Second n-type MOS transistor 120 Second p-type MOS transistor 121 Second inverter 122 Capacitor 123 Third n-type MOS transistor 124 Third p-type MOS Transistor 125 Third inverter 126 Fourth n-type MOS transistor 127 Fourth p-type MOS transistor 128 Fifth n-type MOS transistor 301 First resistor 302 Second Resistance 303 voltage output type DAC of
304 DAC reference voltage generation circuit 305 Voltage-current conversion circuit 306, 307, 310 Bipolar transistors 308, 309, 311 Resistance 312, 313 Gain control amplifier input terminal 314, 315 Gain control amplifier output terminal 401, 402 Input resistance 403, 404, 406, 407 Feedback resistor 405, 408 Switch 409 Differential input / output operational amplifier 501, 505 Resistor 502, 503 First feedback resistor 506, 507 Second feedback resistor 504 First switch 508 Second switch 509 First operational amplifier 510 Second operational amplifier 601 602 605 Bipolar transistor 603 604 606 Resistor 607 ADC
608 Control circuit 609, 610 DAC
611, 612 Gain control amplifier input terminal 613, 614 Gain control amplifier output terminal

Claims (7)

A preamplifier that amplifies the received RF signal, a mixer that receives the RF signal from the preamplifier and a locally generated local signal and converts the RF signal into a baseband signal, and amplifies the baseband signal by variably controlling the gain A differential input / output type gain control amplifier, a low-pass filter for removing high frequency components in an output signal from the gain control amplifier, and an input / output terminal of the gain control amplifier. A wireless communication receiving circuit having a DC offset correction circuit for correcting an output DC offset voltage,
The DC offset correction circuit includes:
A chopper comparator that determines the magnitude relationship of the differential output DC voltage of the gain control amplifier;
A DC offset correction control circuit that controls the chopper comparator and outputs offset correction control data corresponding to the magnitude relationship of the differential output DC voltage of the gain control amplifier;
A radio communication receiving circuit comprising: a DC control circuit that controls an offset of a differential input DC voltage of the gain control amplifier according to the offset correction control data.   The wireless communication receiving circuit according to claim 1, further comprising: an antenna that receives an RF radio wave; and a switch that switches a path from the antenna to the preamplifier. The chopper type comparator is
A first switch for conducting / cutting off one of the differential output DC voltages of the gain control amplifier in response to a first control signal from the DC offset correction control circuit;
In response to a second control signal having a phase opposite to that of the first control signal from the DC offset correction control circuit, the second differential output DC voltage of the gain control amplifier is turned on / off. A switch,
A capacitor through which the differential output DC voltage of the gain control amplifier is supplied to the first terminal via the first and second switches;
An inverting amplifier that inverts and amplifies the voltage at the second terminal of the capacitor and outputs the amplified voltage to the DC offset correction control circuit;
3. The wireless communication receiving circuit according to claim 1, further comprising: a third switch connected between the input and output terminals of the inverting amplifier and controlled to open and close in accordance with the first control signal. The DC control circuit includes:
A digital / analog converter for converting the offset correction control data from the DC offset correction control circuit into an analog voltage;
A reference voltage generating circuit for generating a reference voltage for the digital / analog converter;
A voltage-current conversion circuit for converting a differential voltage between the voltage from the digital / analog converter and the reference voltage into a differential current;
A first resistor having one input terminal of the gain control amplifier and one output terminal of a differential current from the voltage-current conversion circuit connected to one end;
4. The device according to claim 1, further comprising: a second resistor having one end connected to the other input terminal of the gain control amplifier and the other output terminal of the differential current from the voltage-current conversion circuit. The wireless communication receiving circuit according to the item. The gain control amplifier is
A differential input / output operational amplifier;
An input resistor connected to the differential input terminal of the operational amplifier;
A plurality of feedback resistors connected between a differential input terminal and a differential output terminal of the operational amplifier;
5. The wireless communication receiving circuit according to claim 1, further comprising: a plurality of switches that switch connection states of the plurality of feedback resistors in order to perform gain control. The gain control amplifier is
A first operational amplifier that functions as a forward amplifier;
A second operational amplifier that functions as a forward amplifier;
A plurality of first feedback resistors connected between an inverting input terminal and an output terminal of the first operational amplifier;
A plurality of second feedback resistors connected between an inverting input terminal and an output terminal of the second operational amplifier;
A first switch for switching a connection state of the plurality of first feedback resistors to perform gain control;
5. The wireless communication receiving circuit according to claim 1, further comprising a second switch that switches a connection state of the plurality of second feedback resistors in order to perform gain control. A method for correcting a DC offset voltage of a gain control amplifier output in a wireless communication receiver circuit according to any one of claims 1 to 6,
(A) controlling the chopper comparator by the DC offset correction control circuit;
(B) determining the magnitude relationship of the differential output DC voltage of the gain control amplifier by the chopper comparator;
(C) reading the output voltage from the chopper type comparator by the DC offset correction control circuit when the chopper type comparator is in a comparison operation state;
(D) changing the output DC offset of the gain control amplifier by the DC control circuit according to the offset correction control data at a timing when the chopper type comparator shifts from the comparison operation state to the reset state;
(E) correcting the output DC offset of the gain control amplifier by repeating the steps (a) to (d) a plurality of times, and a DC offset voltage correcting method.

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