JP2005072379A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of making an Rf of a pin diode not more than 5 Ω in a low current region. <P>SOLUTION: The method for manufacturing a semiconductor device comprises the steps of forming a first insulating film 3 on an n-type high concentration substrate 1 after growing an I-layer 2 having a relatively low impurity concentration on the main surface of the substrate 1, and exposing the I-layer 2 in a peripheral portion by removing an unnecessary portion of the film 3. Subsequently, a phosphorus is introduced into the I-layer 2 to form a phosphorus processing layer 4 having a relatively high impurity concentration to the exposed I-layer 2, which surrounds the I-layer 2 with the layer 4 and the substrate 1, increasing a carrier concentration per unit volume in the I-layer 2 by decreasing the volume of the I-layer 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having an antenna switch pin (Positive Intrinsic Negative) diode, such as a digital cellular phone and a wireless LAN.

  A pin diode used for switching or attenuation of a high-frequency signal has a structure in which an intrinsic semiconductor region containing no impurities is sandwiched between a p-type semiconductor region and an n-type semiconductor region of the diode. Actually, since it is impossible to form an intrinsic semiconductor region, a p-type or n-type semiconductor region (hereinafter referred to as an I layer) having a very high specific resistance is used instead of the intrinsic semiconductor region (Non-patent Document 1). reference).

  When the pin diode is DC-biased in the forward direction, holes are injected from the p-type semiconductor region and electrons are injected from the n-type semiconductor region into the I layer, so that a current flows and a low impedance state is obtained. On the other hand, if the pin diode is DC biased in the reverse direction, the current is cut off and a high impedance state is obtained. Using such a difference between forward bias and reverse bias, a switch or a phase shifter made of a pin diode is made.

When a forward bias is applied to the pin diode, as described above, the impedance becomes a low impedance state, and the high frequency operating resistance (hereinafter referred to as Rf) of the entire pin diode is lowered. If the thickness and concentration of the I layer are the same, Rf is the injection amount of carriers (holes injected from the p-type semiconductor region and electrons injected from the n-type semiconductor region) into the I layer, that is, the order. Depending on the directional bias current, for example, when the forward bias current is small, injected carriers are dispersed and the carrier concentration per unit volume is lowered, so that Rf becomes large.
March 20, 1999, published by Nikkan Kogyo Shimbun, Inc., “Semiconductor Glossary of Terms”, p23-p124

FIG. 13 shows a cross-sectional view of a main part of a pin diode PD ₀ used as an antenna switch for transmission / reception switching of a digital cellular phone or the like studied by the present inventors.

The pin diode PD ₀ is configured by a pin junction including the n-type high concentration substrate 21, the I layer 22 and the p-type diffusion layer 23. A power source 25 is connected to the p-type diffusion layer 23 via the surface electrode 24, and the pin junction is forward-biased by a positive potential applied to the p-type diffusion layer 23 so that a current flows.

By the way, in a mobile phone, a pin diode having a low current and a low resistance is required at the time of forward bias in order to reduce power consumption during standby. For example, when the forward bias current is 500 μA, Rf is desired to be 5Ω or less. However, as a result of investigation by the present inventors, when the forward bias current is 500 μA, the Rf of the pin diode PD ₀ is about 7Ω, and there is a problem that desired power consumption cannot be obtained.

  In order to solve the above problem, it is necessary to increase the conductivity of the I layer and reduce Rf by improving the carrier concentration per unit volume in the I layer. Specifically, measures such as increasing the forward bias current, thinning the I layer, or narrowing the lateral width of the semiconductor chip forming the pin diode can be taken. However, each of them increases power consumption, deteriorates harmonic distortion, or malfunctions when handling a semiconductor chip, so these are not fundamental improvements for improving the carrier concentration per unit volume in the I layer. .

  An object of the present invention is to provide a technique capable of reducing Rf in a low current region to 5Ω or less in a pin diode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention includes a step of growing an I layer on a main surface of an n-type high concentration substrate, and after forming a first insulating film on the n-type high concentration substrate, removing unnecessary portions of the first insulating film, A step of exposing the peripheral portion of the I layer, a step of introducing phosphorus into the I layer to form a phosphorus treatment layer on the exposed I layer, and a second insulating film on the n-type high concentration substrate, Removing unnecessary portions of the first and second insulating films to expose the central I layer; and introducing p-type impurities into the I layer to form a p-type diffusion layer in the exposed I layer. The phosphorus concentration of the phosphorus treatment layer is higher than the p-type impurity concentration of the I layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By forming a high-concentration phosphorus treatment layer around the pin junction and reducing the volume of the I layer, the carrier concentration per unit volume in the I layer increases, and Rf is 5Ω in the low current region during forward bias. It can be as follows.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a circuit diagram showing an example of an antenna switching circuit using a pin diode according to the first embodiment of the present invention. In the figure, D ₁ and D ₂ are pin diodes, C ₁ , C ₂ , C ₃ and C ₄ are capacitors, and Z ₁ and Z ₂ are microstrip lines (distributed constant circuit).

The pin diodes D ₁ and D ₂ exhibit a high resistance value when a forward current is not flowing, and a low resistance value when a forward current is flowing, for a high-frequency signal of about 300 MHz to 3 GHz. It functions as a switch that performs antenna switching with reception. The pin diodes D ₁ and D ₂ have excellent high-frequency characteristics compared to general switching diodes. Therefore, the internal resistance value according to the forward current change in addition to the switching of the high-frequency signal of the antenna switching circuit. It can also be used for gain control using the fact that

Next, a method for manufacturing a pin diode PD ₁ is the first embodiment of the present invention in the order of steps according to Figures 2-5. In each figure, it is a fragmentary cross-sectional view of a semiconductor substrate along line A-A 'of (a) a main part plan view of the semiconductor substrate showing the pin diode PD ₁ is, (b) is (a). Thousands of pin diodes PD ₁ are simultaneously formed on a single semiconductor wafer (a thin semiconductor plate having a substantially circular plane). Here, a single pin diode PD ₁ is exemplified.

First, as shown in FIG. 2, an epitaxial layer is grown on an n-type (first conductivity type) high-concentration substrate (a substrate called a semiconductor wafer at this stage) 1 to thereby form an I layer ( _first layer) of the pin diode PD 1. Semiconductor layer) 2 is formed. The impurity concentration of the n-type high-concentration substrate 1 is, for example, about 10 ¹⁹ to 10 ²¹ cm ⁻³ , the impurity concentration of the I layer 2 is, for example, about 10 ¹² to 10 ¹³ cm ⁻³ , and the thickness of the I layer 2 is For example, it is about 10 μm. Subsequently, after the first insulating film 3 is formed on the n-type high concentration substrate 1, a part of the first insulating film 3 is etched using a resist pattern formed by a photolithography technique as a mask, so that a peripheral portion ( The surface of the I layer 2 of the p-type (second conductivity type) diffusion layer, which will be described later, is exposed.

Next, as shown in FIG. 3, phosphorus treatment is performed, phosphorus is introduced from the exposed surface of the I layer 2 to the I layer 2 and reaches the n-type high concentration substrate 1 (second semiconductor layer). 4 is formed. The impurity concentration of the phosphorus treatment layer 4 is set higher than the impurity concentration of the I layer 2 and is, for example, about 10 ¹⁷ to 10 ²⁰ cm ⁻³ . By forming the phosphorus treatment layer 4, the I layer 2 is surrounded by the n-type high concentration substrate 1 and the phosphorus treatment layer 4 having a high impurity concentration, and the volume thereof can be reduced.

  Next, as shown in FIG. 4, after the second insulating film 5 is formed on the n-type high-concentration substrate 1, the first insulating film 3 and the second insulating film are formed using a resist pattern formed by photolithography as a mask. By etching a part of the film 5, a hole 6 is formed in the central part to expose the surface of the I layer 2.

  Next, a doping material such as PBF is applied to the exposed surface of the I layer 2. Subsequently, by annealing the n-type high concentration substrate 1 in an atmosphere of about 900 ° C., boron is doped into the I layer 2 from the hole 6 to form a p-type diffusion layer (third semiconductor layer) 7. Here, the p-type diffusion layer 7 is formed so as not to be connected to the phosphorus treatment layer 4. Subsequently, a heat treatment at about 1000 ° C. is performed on the n-type high concentration substrate 1 in a nitrogen atmosphere to form a pin junction composed of the p-type diffusion layer 7, the I layer 2 and the n-type high concentration substrate 1.

  Next, as shown in FIG. 5, an alloy film made of aluminum and silicon is deposited on the n-type high concentration substrate 1 by using, for example, a sputtering method. Subsequently, using the resist pattern formed by photolithography as a mask, the alloy film is etched to form a surface electrode 8 (shown by hatching in FIG. 5A) connected to the p-type diffusion layer 7. Form.

  Next, a silicon nitride film is deposited on the n-type high concentration substrate 1. Subsequently, a silicon oxide film is deposited on the silicon nitride film to form a surface protective film 9 made of a laminated film of a silicon nitride film and a silicon oxide film. Furthermore, the surface of the surface electrode 8 is exposed by etching the surface protective film 9 using a resist pattern formed by photolithography as a mask.

  Next, a protective tape (not shown) made of plastic for protecting the main surface is pasted on the main surface of the n-type high concentration substrate 1 on which the surface electrode 8 and the surface protective film 9 are formed. After that, the back surface of the n-type high concentration substrate 1 is ground by grinding, and the n-type high concentration substrate 1 is thinned according to the package form. In addition, after grinding the back surface of the n-type high concentration substrate 1, the back surface of the n-type high concentration substrate 1 may be further light-etched.

Next, after peeling off the above-mentioned protective tape and washing the n-type high concentration substrate 1, a multilayer film (thin film) made of gold / antimony / gold is deposited on the back surface of the n-type high concentration substrate 1. Subsequently, by forming the back electrode 10 by etching the multilayer film, the pin diode PD _{1 of the} first embodiment is substantially completed. Thereafter, the semiconductor wafer on which the pin diode PD ₁ is formed is cut to divide the pin diode PD ₁ into unit elements (semiconductor chips). Then the individual pin diode PD ₁ is sealed by the sealing resin, packaging.

FIG. 6 is a graph showing the relationship between the high frequency operating resistance Rf of the pin diode and the forward bias current If. In the figure, the solid line indicates the characteristics of the pin diode PD _{1 according to} the present invention, and the dotted line indicates the characteristics of the pin diode PD ₀ (see FIG. 13) investigated by the present inventors.

Rf of the pin diodes PD ₁ and PD ₀ depends on the forward bias current, and increases as the forward bias current decreases. However, the forward bias current is below 1mA low-current region, Rf of pin diode PD ₁ is smaller than Rf of pin diode PD _0. For example, when the forward bias current is 500 μA, the Rf of the pin diode PD ₀ is about 7Ω, but the Rf of the pin diode PD ₁ is about 3Ω, which can satisfy the target of 5Ω or less. This is because the volume of the I layer 2 of the pin diode PD ₁ becomes smaller than the volume of the I layer 22 of the pin diode PD ₀ by forming the phosphorous treatment layer 4 in the I layer 2. In this case, it is considered that the I layer 2 of the pin diode PD ₁ is filled with carriers, the carrier concentration per unit volume in the I layer 2 is increased, and an Rf of 5Ω or less can be obtained in the low current region.

In the pin diode PD ₁ , the phosphorus treatment layer 4 reaches the n-type high concentration substrate 1, but does not necessarily reach the n-type high concentration substrate 1, and the phosphorus treatment layer 4 does not diffuse carriers. It only has to have a depth that can be prevented. For example, the phosphorus treatment layer 4 may be formed deeper than the p-type diffusion layer 4.

FIG. 7 shows a cross-sectional view of the main part of a pin diode PD ₂ in which the phosphorus treatment layer, which is a modification of the first embodiment of the present invention, does not reach the n-type high concentration substrate.

pin diode PD ₂ in I layer 2 is relatively thick and has a thickness of, for example, about 15 to 25 [mu] m. On the other hand, in the phosphorus treatment in which phosphorus is introduced into the I layer 2 using a diffusion source, there is a limit to the depth of phosphorus introduction, and the depth is, for example, about 10 μm. For this reason, the phosphorus treatment layer 4 does not reach the n-type high concentration substrate 1. However, since the phosphorous treatment layer 4 is formed deeper than the p-type diffusion layer 4, carrier diffusion can be prevented.

  As described above, according to the first embodiment, the volume of the I layer 2 can be reduced by forming the high concentration phosphorous treatment layer 4 in the peripheral portion of the pin junction. The carrier concentration per volume is increased, and an Rf of 5Ω or less can be obtained in a low current region where the forward bias current is about 500 μA.

(Embodiment 2)
A method for manufacturing the pin diode PD _{3 according to} the second embodiment of the present invention will be described in the order of steps according to FIGS. In each figure, (a) is a plan view of the main part of the semiconductor substrate showing the pin diode PD ₃ , and (b) is a cross-sectional view of the main part of the semiconductor substrate along the line AA ′ in (a). Similarly to the first embodiment, one pin diode PD ₃ formed on the semiconductor wafer is illustrated.

  First, as shown in FIG. 8, an epitaxial layer is grown on an n-type high concentration substrate 1 to form an I layer 2 of a pin diode. Subsequently, after forming the third insulating film 11 on the n-type high concentration substrate 1, a part of the third insulating film 11 is etched using a resist pattern formed by a photolithography technique as a mask. Subsequently, after removing the resist pattern, a part of the I layer 2 is etched using the third insulating film 11 as a mask to form a trench groove 12. The trench groove 12 has a planar ring shape in the n-type high concentration substrate 1. By introducing impurities from the bottom of the trench groove 12 in a later step, a phosphorus treatment layer is formed in the I layer 2 under the trench groove 12. The trench is so formed that this phosphorus treatment layer reaches the n-type high concentration substrate 1. The depth of the groove 12 is determined. For example, when the thickness of the I layer 2 is about 25 μm and the depth of the phosphorus treatment layer is about 10 μm, the depth of the trench groove 12 is about 15 μm.

  Next, as shown in FIG. 9, after removing the third insulating film 11, a first insulating film 13 is formed on the n-type high concentration substrate 1. Subsequently, using the resist pattern formed by the photolithography technique as a mask, a part of the first insulating film 13 is etched to expose the surface of the outer I layer 2 from the bottom of the trench groove 12.

Next, as shown in FIG. 10, phosphorus treatment is performed, phosphorus is introduced into the I layer 2 from the exposed surface of the I layer 2, and reaches the n-type high concentration substrate 1 (second semiconductor layer). 14 is formed. The impurity concentration of the phosphorus treatment layer 14 is set higher than the impurity concentration of the I layer 2 and is, for example, about 10 ¹⁷ to 10 ²⁰ cm ⁻³ . Although the thickness of the I layer 2 is thicker than about 10 μm, which is the depth of introduction of phosphorus, by forming the trench groove 12 and introducing phosphorus from the bottom thereof, the phosphorus treatment layer 14 is formed on the n-type high concentration substrate 1. Can be reached. Therefore, even when the thickness of the I layer 2 is larger than 10 μm, the I layer 2 is surrounded by the n-type high concentration substrate 1 and the phosphorus treatment layer 14 having a high impurity concentration, and the volume can be reduced. As a result, the carrier concentration per unit volume in the I layer 2 increases, and a low Rf can be obtained in a low current region during forward bias.

  Next, as shown in FIG. 11, after the second insulating film 15 is formed on the n-type high concentration substrate 1, the first insulating film 13 and the second insulating film are formed using a resist pattern formed by a photolithography technique as a mask. By etching a part of the film 15, a hole 16 is formed in the central part to expose the surface of the I layer 2. Subsequently, as in the first embodiment, a p-type diffusion layer (third semiconductor layer) 17 is formed on the exposed surface of the I layer 2, and the p-type diffusion layer 17, the I layer 2 and the n-type high concentration substrate 1 are formed. A pin junction is formed.

Thereafter, as shown in FIG. 12, as in the first embodiment, a front electrode 18 connected to the p-type diffusion layer 17 is formed, and a back electrode (not shown) is formed on the back surface of the n-type high concentration substrate 1. Thus, the pin diode PD _{3 of the} second embodiment is formed.

  As described above, according to the second embodiment, even when the thickness of the I layer 2 is thicker than the depth of introduction of phosphorus, the trench groove 12 is formed in the I layer 2 in the peripheral portion, and phosphorus from the bottom is formed. By introducing the high-concentration phosphorus treatment layer 14 reaching the n-type high-concentration substrate 1 in the peripheral portion of the pin junction, the volume of the I layer 2 can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the present invention is applied to a pin diode has been described. However, the present invention can also be applied to a capacity limitation of a diode such as a varicap.

It is a circuit diagram which shows an example of the antenna switching circuit which uses the pin diode which is Embodiment 1 of this invention. (A) And (b) is the principal part top view and principal part sectional drawing of a semiconductor substrate which respectively show the manufacturing method of the pin diode which is Embodiment 1 of this invention. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 2, respectively. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 3, respectively. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 4, respectively. It is a graph which shows the relationship between the high frequency operating resistance Rf of a pin diode, and the forward direction bias current If. It is principal part sectional drawing of the semiconductor substrate which shows the modification of the pin diode which is Embodiment 1 of this invention. (A) And (b) is the principal part top view and principal part sectional drawing of a semiconductor substrate which respectively show the manufacturing method of the pin diode which is Embodiment 2 of this invention. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 8, respectively. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 9, respectively. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 10, respectively. (A) And (b) is the principal part top view and principal part sectional drawing in the manufacturing process of the pin diode which follow FIG. 11, respectively. It is principal part sectional drawing of the semiconductor substrate which shows the pin diode examined by the present inventors.

Explanation of symbols

1 n-type high concentration substrate (substrate)
2 I layer (first semiconductor layer)
3 First insulating film 4 Phosphorus treatment layer (second semiconductor layer)
5 Second insulating film 6 Hole 7 P-type diffusion layer (third semiconductor layer)
8 Surface electrode 9 Surface protective film 10 Back electrode 11 Third insulating film 12 Trench groove 13 First insulating film 14 Phosphorus treatment layer (second semiconductor layer)
15 Second insulating film 16 Hole 17 p-type diffusion layer (third semiconductor layer)
18 Surface electrode 21 n-type high concentration substrate 22 I layer 23 p-type diffusion layer 24 Surface electrode 25 Electrode PD ₀ pin diode PD ₁ pin diode PD ₂ pin diode PD ₃ pin diode D ₁ pin diode D ₂ pin diode C ₁ capacitance C ₂ capacity C ₃ capacity C ₄ capacity Z ₁ microstrip line Z ₂ microstrip line

Claims (5)

(A) growing a first semiconductor layer on the main surface of the first conductivity type substrate;
(B) after forming a first insulating film on the substrate, removing unnecessary portions of the first insulating film to expose the first semiconductor layer in the peripheral portion;
(C) introducing a first conductivity type impurity into the first semiconductor layer to form a second semiconductor layer on the exposed first semiconductor layer;
(D) after forming a second insulating film on the substrate, removing unnecessary portions of the first and second insulating films to expose the first semiconductor layer in a central portion;
(E) introducing a second conductivity type impurity opposite to the first conductivity type into the first semiconductor layer to form a third semiconductor layer in the exposed first semiconductor layer;
A method of manufacturing a semiconductor device, wherein impurity concentrations of the substrate and the second semiconductor layer are higher than impurity concentrations of the first semiconductor layer. (A) growing a first semiconductor layer on the main surface of the first conductivity type substrate;
(B) after forming a first insulating film on the substrate, removing unnecessary portions of the first insulating film to expose the first semiconductor layer in the peripheral portion;
(C) introducing a first conductivity type impurity into the first semiconductor layer to form a second semiconductor layer on the exposed first semiconductor layer;
(D) after forming a second insulating film on the substrate, removing unnecessary portions of the first and second insulating films to expose the first semiconductor layer in a central portion;
(E) introducing a second conductivity type impurity opposite to the first conductivity type into the first semiconductor layer to form a third semiconductor layer in the exposed first semiconductor layer;
A method of manufacturing a semiconductor device, wherein the impurity concentration of the first semiconductor layer is about 10 ¹² to 10 ¹³ cm ⁻³ , and the impurity concentration of the second semiconductor layer is about 10 ¹⁷ to 10 ²⁰ cm ⁻³ . (A) growing a first semiconductor layer on the main surface of the first conductivity type substrate;
(B) after forming a first insulating film on the substrate, removing unnecessary portions of the first insulating film to expose the first semiconductor layer in the peripheral portion;
(C) introducing a first conductivity type impurity into the first semiconductor layer to form a second semiconductor layer on the exposed first semiconductor layer;
(D) after forming a second insulating film on the substrate, removing unnecessary portions of the first and second insulating films to expose the first semiconductor layer in a central portion;
(E) introducing a second conductivity type impurity opposite to the first conductivity type into the first semiconductor layer to form a third semiconductor layer in the exposed first semiconductor layer;
An impurity concentration of the substrate and the second semiconductor layer is higher than an impurity concentration of the first semiconductor layer, and the second semiconductor layer reaches the substrate. (A) growing a first semiconductor layer on a main surface of a first conductivity type substrate;
(B) after forming a first insulating film on the substrate, removing an unnecessary portion of the first insulating film to expose the first semiconductor layer in a peripheral portion;
(C) introducing an impurity of the first conductivity type into the first semiconductor layer to form a second semiconductor layer in the exposed first semiconductor layer;
(D) after forming a second insulating film on the substrate, removing unnecessary portions of the first and second insulating films to expose the first semiconductor layer in a central portion;
(E) introducing a second conductivity type impurity opposite to the first conductivity type into the first semiconductor layer to form a third semiconductor layer in the exposed first semiconductor layer;
An impurity concentration of the substrate and the second semiconductor layer is higher than an impurity concentration of the first semiconductor layer, and the second semiconductor layer is formed deeper than the third semiconductor layer. Method. (A) growing a first semiconductor layer on the main surface of the first conductivity type substrate;
(B) removing unnecessary portions of the first semiconductor layer to form a planar ring-shaped trench groove;
(C) after forming a first insulating film on the substrate, removing unnecessary portions of the first insulating film to expose the first semiconductor layer in the peripheral portion from the bottom of the trench groove;
(D) introducing a first conductivity type impurity into the first semiconductor layer to form a second semiconductor layer reaching the substrate in the exposed first semiconductor layer;
(E) after forming a second insulating film on the substrate, removing unnecessary portions of the first and second insulating films to expose the first semiconductor layer in a central portion;
(F) introducing a second conductivity type impurity opposite to the first conductivity type into the first semiconductor layer to form a third semiconductor layer in the exposed first semiconductor layer;
A method of manufacturing a semiconductor device, wherein impurity concentrations of the substrate and the second semiconductor layer are higher than impurity concentrations of the first semiconductor layer.

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