JP2005071067A - Voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage generation circuit capable of making the gain of an error amplifier greater than usual, while keeping the error amplifier from consuming more current. <P>SOLUTION: When the error amplifier 5 has a slight decrease in gate voltage Vg, the value of the gate voltage Vg after the decrease is higher than the operating threshold voltage Vth of an inverter circuit 21. The error amplifier 5 thus controls the gate voltage Vg of a P-channel MOSFET 4 by means of only a differential amplification circuit 11. If an internal source voltage Vdd2 drops greatly with a sudden increase in the operating current of an internal circuit 3, the error amplifier 5 greatly lowers the gate voltage Vg. In this case, the value of the gate voltage Vg after the lowering is lower than the operating threshold voltage Vth of the inverter circuit 21. Hence, the error amplifier 5 controls the gate voltage Vg of the P-channel MOSFET 4 by means of two steps of differential amplification circuits 10, 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage generation circuit used in a semiconductor integrated circuit.

  The voltage generation circuit drops a power supply voltage (referred to as “external power supply voltage” in this specification) supplied from an external power supply to a predetermined reference voltage, thereby supplying a power supply voltage (this specification (Referred to as “internal power supply voltage”).

  A conventional voltage generation circuit includes an error amplifier configured using a single-stage differential amplifier circuit and a P-channel MOSFET. The error amplifier has a first input terminal to which a reference voltage is input, a second input terminal connected to the power supply input terminal of the internal circuit, and an output terminal connected to the gate electrode of the P-channel MOSFET. ing. The source electrode of the P-channel MOSFET is connected to an external power supply, and the drain electrode is connected to the power input terminal.

  The error amplifier compares the internal power supply voltage with the reference voltage, generates a voltage corresponding to the difference between the two voltages, and applies it as a gate voltage to the gate electrode of the P-channel MOSFET. Thus, the current flowing from the source electrode to the drain electrode of the P-channel MOSFET is increased or decreased according to the difference between the internal power supply voltage and the reference voltage, and as a result, the internal power supply voltage is controlled to be equal to the reference voltage.

  The technology relating to the voltage generation circuit is disclosed in the following Patent Documents 1 and 2.

JP 2000-75941 A JP 2000-148263 A

  However, in the conventional voltage generation circuit, the error amplifier has a small gain because the error amplifier is configured using a single-stage differential amplifier circuit.

  Accordingly, since the response speed of the error amplifier with respect to the change of the internal power supply voltage is slow, the time that the value of the internal power supply voltage deviates from the value of the reference voltage becomes long when the operating current of the internal circuit changes rapidly. There is. Further, since the lower limit value of the voltage that can be output from the error amplifier is relatively high, the gate voltage of the P-channel MOSFET cannot be lowered sufficiently. Therefore, there is a problem that the maximum value of the current supplied from the external power source to the internal circuit via the P-channel MOSFET is small.

  When an error amplifier is configured using a plurality of stages of differential amplifier circuits, the gain of the error amplifier increases. However, since the differential amplifier circuit constantly consumes current, if an error amplifier is configured by simply cascading a plurality of differential amplifier circuits, current consumption in the error amplifier increases. . In particular, when the operating current of the internal circuit is small, the error amplifier occupies most of the total current consumption in the semiconductor integrated circuit.

  The present invention has been made to solve such a problem, and an object of the present invention is to obtain a voltage generation circuit capable of increasing the gain of the error amplifier compared to the conventional one while suppressing an increase in current consumption in the error amplifier. .

  A voltage generation circuit according to the present invention is a voltage generation circuit that generates an internal power supply voltage to be supplied to an internal circuit by dropping an external power supply voltage supplied from an external power supply to a predetermined reference voltage. A control voltage is generated by amplifying an error between a reference voltage and an internal power supply voltage, a transistor having an electrode, a first electrode connected to an external power supply, and a second electrode connected to an internal circuit. An error amplifier that applies a voltage to the control electrode, and a control circuit that controls the gain and current consumption of the error amplifier according to the value of the control voltage are provided.

  According to the present invention, it is possible to increase the gain of the error amplifier while suppressing an increase in current consumption in the error amplifier.

  FIG. 1 is a circuit diagram schematically showing the configuration of a voltage generation circuit 1 according to an embodiment of the present invention in a state where it is connected to an external power supply 2 and an internal circuit 3. The voltage generation circuit 1 generates an internal power supply voltage Vdd2 to be supplied to the internal circuit 3 by dropping the external power supply voltage Vdd1 supplied from the external power supply 2 to a voltage equal to a predetermined reference voltage Vref.

  The voltage generation circuit 1 includes a P-channel MOSFET 4 (also referred to as “driver transistor”), an error amplifier 5 with variable gain and current consumption, and a control circuit 6. P-channel MOSFET 4 has a gate electrode, a source electrode connected to external power supply 2, and a drain electrode connected to internal circuit 2. Error amplifier 5 has an inverting input terminal to which reference voltage Vref is input, a non-inverting input terminal to which internal power supply voltage Vdd2 is input, and an output terminal connected to the gate electrode of P-channel MOSFET 4. The error amplifier 5 amplifies an error between the reference voltage Vref and the internal power supply voltage Vdd2 to generate a control voltage (gate voltage Vg), and applies the gate voltage Vg to the gate electrode of the P-channel MOSFET 4. The control circuit 6 controls the gain and current consumption of the error amplifier 5 according to the value of the gate voltage Vg.

  Next, the operation of the voltage generation circuit 1 shown in FIG. 1 will be described. Error amplifier 5 controls gate voltage Vg of P-channel MOSFET 4 such that reference voltage Vref and internal power supply voltage Vdd2 are equal. For example, when the operating state of the internal circuit 3 changes and the operating current increases, the internal power supply voltage Vdd2 starts to decrease. Then, error amplifier 5 reduces gate voltage Vg in response to the decrease in internal power supply voltage Vdd2. The lower the internal power supply voltage Vdd2, that is, the greater the error between the internal power supply voltage Vdd2 and the reference voltage Vref, the lower the gate voltage Vg. When the gate voltage Vg decreases, the current flowing from the source electrode to the drain electrode of the P-channel MOSFET 4 increases, so that the internal power supply voltage Vdd2 increases. The error amplifier 5 maintains the state where the gate voltage Vg is lowered until the internal power supply voltage Vdd2 becomes equal to the reference voltage Vref.

  On the other hand, when the operating current of internal circuit 3 decreases, internal power supply voltage Vdd2 starts to increase. Then, error amplifier 5 raises gate voltage Vg in response to the rise in internal power supply voltage Vdd2. When the gate voltage Vg increases, the current flowing from the source electrode to the drain electrode of the P-channel MOSFET 4 decreases, so that the internal power supply voltage Vdd2 decreases. The error amplifier 5 maintains the state where the gate voltage Vg is increased until the internal power supply voltage Vdd2 becomes equal to the reference voltage Vref.

  By repeating the above operation, the voltage generation circuit 1 generates the internal power supply voltage Vdd2 equal to the reference voltage Vref regardless of the operation state of the internal circuit 3.

  FIG. 2 is a circuit diagram specifically showing the configuration of the error amplifier 5 and the control circuit 6 shown in FIG. 1 while being connected to the external power supply 2 and the internal circuit 3. The error amplifier 5 has two stages of differential amplifier circuits 10 and 11 connected in cascade. The differential amplifier circuit 10 includes an input terminal 12 to which a reference voltage Vref is input, an input terminal 13 to which an internal power supply voltage Vdd2 is input, a drive control terminal 14 for controlling driving of the differential amplifier circuit 10, An output terminal pair 15 including output terminals 15a and 15b is provided.

  The differential amplifier circuit 11 has input terminal pairs 16 and 17, drive control terminal pairs 18 and 19, and an output terminal 20. Input terminal pair 16 includes an input terminal 16a to which reference voltage Vref is input and an input terminal 16b to which internal power supply voltage Vdd2 is input. The input terminal pair 17 includes input terminals 17a and 17b connected to the output terminals 15a and 15b of the differential amplifier circuit 10, respectively. The drive control terminal pair 18 includes drive control terminals 18 a and 18 b for controlling driving of the differential amplifier circuit 11 with respect to the input terminal pair 16. The drive control terminal pair 19 includes drive control terminals 19 a and 19 b for controlling the drive of the differential amplifier circuit 11 with respect to the input terminal pair 17. The output terminal 20 is connected to the gate electrode of the P-channel MOSFET 4.

  The input terminals 12 and 16a correspond to the inverting input terminal shown in FIG. 1, and the input terminals 13 and 16b correspond to the non-inverting input terminal shown in FIG.

  The control circuit 6 includes inverter circuits 21 and 22 connected in cascade. The inverter circuit 21 has an input terminal commonly connected to the output terminal 20 of the differential amplifier circuit 11 and the gate electrode of the P-channel MOSFET 4, and an output terminal connected to the drive control terminal pair 19 of the differential amplifier circuit 11. Have. The inverter circuit 22 has an input terminal connected to the output terminal of the inverter circuit 21, and an output terminal connected to the drive control terminal 14 of the differential amplifier circuit 10 and the drive control terminal pair 18 of the differential amplifier circuit 11. doing. The control circuit 6 drives both the differential amplifier circuits 10 and 11 or drives only the differential amplifier circuit 11 depending on the level relationship between the gate voltage Vg and the operation threshold voltage Vth of the inverter circuit 21. (Details will be described later).

  FIG. 3 is a circuit diagram specifically showing the configuration of the differential amplifier circuits 10 and 11 and the inverter circuits 21 and 22 shown in FIG. 2 in a state where they are connected to the external power supply 2 and the internal circuit 3.

  First, the configuration of the differential amplifier circuit 10 will be described. The differential amplifier circuit 10 includes N-channel MOSFETs MN211 to MN214 and a P-channel MOSFET MP211. The gate electrode of the P-channel MOSFET MP211 is connected to the output terminal of the inverter circuit 22, the source electrode is connected to the external power supply 2, and the drain electrode is connected to the drain electrodes of the N-channel MOSFETs MN211 and MN212.

  A reference voltage Vref is input to the gate electrode of the N-channel MOSFET MN211. The gate electrode of the N-channel MOSFET MN212 is connected to the drain electrode of the P-channel MOSFET 4 and the internal power supply voltage Vdd2 is input to the gate electrode of the N-channel MOSFET MN212. The source electrode of the N-channel MOSFET MN211 is connected to the drain electrode of the N-channel MOSFET MN213, and the source electrode of the N-channel MOSFET MN212 is connected to the drain electrode of the N-channel MOSFET MN214. The gate electrodes of the N channel MOSFETs MN213 and MN214 are connected to the drain electrode of the N channel MOSFET MN214. The source electrodes of the N-channel MOSFETs MN213 and MN214 are connected to a common ground.

  The gate electrode of the N-channel MOSFET MN211 corresponds to the input terminal 12 shown in FIG. 2, the gate electrode of the N-channel MOSFET MN212 corresponds to the input terminal 13 shown in FIG. 2, and the gate electrode of the P-channel MOSFET MP211 shown in FIG. It corresponds to the drive control terminal 14. Further, the drain electrode of the N-channel MOSFET MN213 corresponds to the output terminal 15a shown in FIG. 2, and the drain electrode of the N-channel MOSFET MN214 corresponds to the output terminal 15b shown in FIG.

  Next, the configuration of the differential amplifier circuit 11 will be described. The differential amplifier circuit 11 includes N-channel MOSFETs MN201 to MN209 and P-channel MOSFETs MP201 and MP202. Each source electrode of the P-channel MOSFETs MP201 and MP202 is connected to the external power source 2. The drain electrode of the P-channel MOSFET MP201 is connected to the gate electrode of the P-channel MOSFET 4 and the drain electrodes of the N-channel MOSFETs MN201 and MN203. The drain electrode of the P-channel MOSFET MP202 is connected to the drain electrodes of the N-channel MOSFETs MN202 and MN204. Each gate electrode of the P-channel MOSFETs MP201 and MP202 is connected to the drain electrode of the P-channel MOSFET MP202.

  The gate electrode of the N-channel MOSFET MN203 is connected to the drain electrode of the N-channel MOSFET MN213 that the differential amplifier circuit 10 has. The source electrode of the N channel MOSFET MN203 is connected to the drain electrode of the N channel MOSFET MN207. The gate electrode of the N-channel MOSFET MN207 is connected to the output terminal of the inverter circuit 21. The source electrode of the N-channel MOSFET MN207 is connected to the drain electrode of the N-channel MOSFET MN209.

  A reference voltage Vref is input to the gate electrode of the N-channel MOSFET MN201. The source electrode of the N channel MOSFET MN201 is connected to the drain electrode of the N channel MOSFET MN205. The gate electrode of the N-channel MOSFET MN205 is connected to the output terminal of the inverter circuit 22. The source electrode of the N channel MOSFET MN205 is connected to the drain electrode of the N channel MOSFET MN209.

  The gate electrode of the N-channel MOSFET MN202 is connected to the drain electrode of the P-channel MOSFET 4 and the internal power supply voltage Vdd2 is input to the gate electrode of the N-channel MOSFET MN202. The source electrode of the N channel MOSFET MN202 is connected to the drain electrode of the N channel MOSFET MN206. The gate electrode of the N-channel MOSFET MN206 is connected to the output terminal of the inverter circuit 22. The source electrode of the N-channel MOSFET MN206 is connected to the drain electrode of the N-channel MOSFET MN209.

  The gate electrode of the N-channel MOSFET MN204 is connected to the drain electrode of the N-channel MOSFET MN214 included in the differential amplifier circuit 10. The source electrode of the N channel MOSFET MN204 is connected to the drain electrode of the N channel MOSFET MN208. The gate electrode of the N-channel MOSFET MN208 is connected to the output terminal of the inverter circuit 21. The source electrode of the N-channel MOSFET MN208 is connected to the drain electrode of the N-channel MOSFET MN209.

  The gate electrode of the N-channel MOSFET MN209 is connected to the external power supply 2, and the source electrode is connected to a common ground.

  The gate electrode of the N-channel MOSFET MN201 corresponds to the input terminal 16a shown in FIG. 2, the gate electrode of the N-channel MOSFET MN202 corresponds to the input terminal 16b shown in FIG. 2, and the gate electrode of the N-channel MOSFET MN203 shown in FIG. It corresponds to the input terminal 17a, and the gate electrode of the N-channel MOSFET MN204 corresponds to the input terminal 17b shown in FIG. Further, the gate electrode of the N-channel MOSFET MN205 corresponds to the drive control terminal 18a shown in FIG. 2, the gate electrode of the N-channel MOSFET MN206 corresponds to the drive control terminal 18b shown in FIG. 2, and the gate electrode of the N-channel MOSFET MN207 is shown in FIG. 2 corresponds to the drive control terminal 19a shown in FIG. 2, and the gate electrode of the N-channel MOSFET MN208 corresponds to the drive control terminal 19b shown in FIG. Further, the drain electrode of the P-channel MOSFET MP201 corresponds to the output terminal 20 shown in FIG.

  Next, the configuration of the inverter circuits 21 and 22 will be described. The inverter circuit 21 has a P-channel MOSFET MP221 and an N-channel MOSFET MN221. A source electrode of the P-channel MOSFET MP 221 is connected to the external power supply 2. The drain electrode of the P-channel MOSFET MP221 is connected to the drain electrode of the N-channel MOSFET MN221. The source electrode of the N-channel MOSFET MN221 is connected to a common ground. The gate electrodes of the P-channel MOSFET MP221 and the N-channel MOSFET MN221 are commonly connected to the drain electrode of the P-channel MOSFET MP201 included in the differential amplifier circuit 11 and the gate electrode of the P-channel MOSFET4.

  The inverter circuit 22 has a P-channel MOSFET MP222 and an N-channel MOSFET MN222. A source electrode of the P-channel MOSFET MP222 is connected to the external power supply 2. The drain electrode of the P-channel MOSFET MP222 is connected to the drain electrode of the N-channel MOSFET MN222. The source electrode of the N-channel MOSFET MN222 is connected to a common ground. The gate electrodes of the P-channel MOSFET MP222 and the N-channel MOSFET MN222 are connected to the drain electrodes of the P-channel MOSFET MP221 and the N-channel MOSFET MN221 that the inverter circuit 21 has.

  Each gate electrode of the P-channel MOSFET MP221 and the N-channel MOSFET MN221 corresponds to the input terminal of the inverter circuit 21 shown in FIG. 2, and each drain electrode of the P-channel MOSFET MP221 and the N-channel MOSFET MN221 corresponds to the inverter circuit 21 shown in FIG. The gate electrodes of the P-channel MOSFET MP222 and the N-channel MOSFET MN222 correspond to the output terminals, and correspond to the input terminals of the inverter circuit 22 shown in FIG. 2, and the drain electrodes of the P-channel MOSFET MP222 and the N-channel MOSFET MN222 are shown in FIG. This corresponds to the output terminal of the inverter circuit 22 shown.

  When the output voltage V1 of the inverter circuit 21 is at a high level and the output voltage V2 of the inverter circuit 22 is at a low level, the P-channel MOSFET MP211 is turned on, so that the differential amplifier circuit 10 is driven. Further, since the N-channel MOSFETs MN205 and MN206 are turned off, the differential amplifier circuit 11 is not driven with respect to the input terminal pair 16 shown in FIG. 2 (N-channel MOSFETs MN201 and MN202 shown in FIG. 3). Further, since the N-channel MOSFETs MN207 and MN208 are turned on, the differential amplifier circuit 11 is driven with respect to the input terminal pair 17 shown in FIG. 2 (N-channel MOSFETs MN203 and MN204 shown in FIG. 3).

  On the other hand, when the output voltage V1 of the inverter circuit 21 is low level and the output voltage V2 of the inverter circuit 22 is high level, the P-channel MOSFET MP211 is turned off, so that the differential amplifier circuit 10 is not driven. Further, since the N-channel MOSFETs MN205 and MN206 are turned on, the differential amplifier circuit 11 is driven with respect to the input terminal pair 16 shown in FIG. 2 (N-channel MOSFETs MN201 and MN202 shown in FIG. 3). Further, since the N-channel MOSFETs MN207 and MN208 are turned off, the differential amplifier circuit 11 is not driven with respect to the input terminal pair 17 shown in FIG. 2 (N-channel MOSFETs MN203 and MN204 shown in FIG. 3).

  Hereinafter, the operation of the voltage generation circuit 1 shown in FIG. 3 will be described. As described above, when the operating current of the internal circuit 3 increases and the internal power supply voltage Vdd2 decreases, the error amplifier 5 decreases the gate voltage Vg according to the error between the internal power supply voltage Vdd2 and the reference voltage Vref.

  First, it is assumed that the error amplifier 5 slightly reduces the gate voltage Vg due to the internal power supply voltage Vdd2 being slightly lower than the reference voltage Vref. In this case, the lowered gate voltage Vg is higher than the operation threshold voltage Vth of the inverter circuit 21. Accordingly, since the output voltage V1 of the inverter circuit 21 is low level and the output voltage V2 of the inverter circuit 22 is high level, the differential amplifier circuit 10 is not driven as described above, and differential amplification is performed with respect to the N-channel MOSFETs MN201 and MN202. The circuit 11 is driven, and the differential amplifier circuit 11 is not driven with respect to the N-channel MOSFETs MN203 and MN204. Therefore, the error amplifier 5 is based on the reference voltage Vref input to the gate electrode of the N-channel MOSFET MN201 and the internal power supply voltage Vdd2 input to the gate electrode of the N-channel MOSFET MN202. The gate voltage Vg of the P-channel MOSFET 4 is controlled so that the voltage Vref and the internal power supply voltage Vdd2 are equal.

  In this case, since the differential amplifier circuit 10 is not driven, the current consumed in the error amplifier 5 is only the current that flows as the differential amplifier circuit 11 is driven.

  From this state, it is assumed that the internal power supply voltage Vdd2 has greatly decreased due to a sudden increase in the operating current of the internal circuit 3. Then, the error amplifier 5 greatly reduces the gate voltage Vg according to the error between the internal power supply voltage Vdd2 and the reference voltage Vref. In this case, the value of the lowered gate voltage Vg is lower than the operation threshold voltage Vth of the inverter circuit 21. Therefore, since the output voltage V1 of the inverter circuit 21 is high level and the output voltage V2 of the inverter circuit 22 is low level, the differential amplifier circuit 10 is driven as described above, and the differential amplifier circuit is related to the N-channel MOSFETs MN201 and MN202. 11 is not driven, and the differential amplifier circuit 11 is driven with respect to the N-channel MOSFETs MN203 and MN204. Therefore, the error amplifier 5 includes two stages of differential circuits connected in cascade based on the reference voltage Vref input to the gate electrode of the N-channel MOSFET MN211 and the internal power supply voltage Vdd2 input to the gate electrode of the N-channel MOSFET MN212. The amplifier circuits 10 and 11 control the gate voltage Vg of the P-channel MOSFET 4 so that the reference voltage Vref and the internal power supply voltage Vdd2 are equal.

  In this case, the output of the differential amplifier circuit 10 at the preceding stage is input to the differential amplifier circuit 11 at the subsequent stage. Therefore, the gain of the error amplifier 5 is higher than when only the one-stage differential amplifier circuit 11 is driven.

  Further, the current consumed in the error amplifier 5 is the sum of the currents that flow as the differential amplifier circuits 10 and 11 are driven. However, the differential amplifier circuits 10 and 11 are both driven only when the operating current of the internal circuit 3 is large to some extent. Therefore, compared with the operating current of the internal circuit 3, the increase in the current consumption in the error amplifier 5 is negligible, so that the current consumption of the entire semiconductor integrated circuit is hardly affected.

  As described above, according to the voltage generation circuit 1 according to the embodiment of the present invention, when the operating current of the internal circuit 3 is large, the differential amplifier circuits 10 and 11 are both driven, so that the error amplifier 5 Since the gain is increased, the responsiveness to changes in the operating state of the internal circuit 3 can be improved, and the current supply capability to the internal circuit 3 can be improved. Since the differential amplifier circuit 10 is not driven when the operating current of the internal circuit 3 is small, the current consumption in the error amplifier 5 is compared with the case where the two-stage differential amplifier circuits 10 and 11 are always driven. The amount can be suppressed.

1 is a circuit diagram schematically showing a configuration of a voltage generation circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram specifically illustrating configurations of an error amplifier and a control circuit illustrated in FIG. 1. FIG. 3 is a circuit diagram specifically illustrating configurations of a differential amplifier circuit and an inverter circuit illustrated in FIG. 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage generator circuit, 2 External power supply, 3 Internal circuit, 4 P channel MOSFET, 5 Error amplifier, 6 Control circuit, 10, 11 Differential amplifier circuit, 12, 13, 16a, 16b, 17a, 17b Input terminal, 16, 17 Input terminal pair, 14, 18a, 18b, 19a, 19b Drive control terminal, 18, 19 Drive control terminal pair, 15a, 15b, 20 Output terminal, 15 Output terminal pair, 21, 22 Inverter circuit.

Claims (3)

A voltage generation circuit that generates an internal power supply voltage to be supplied to an internal circuit by dropping an external power supply voltage supplied from an external power supply to a predetermined reference voltage,
A transistor having a control electrode, a first electrode connected to the external power source, and a second electrode connected to the internal circuit;
An error amplifier that amplifies an error between the reference voltage and the internal power supply voltage to generate a control voltage and applies the control voltage to the control electrode;
And a control circuit that controls a gain and current consumption of the error amplifier according to the value of the control voltage. The error amplifier has first and second differential amplifier circuits connected in cascade,
The control circuit controls whether to drive both the first and second differential amplifier circuits or only the second differential amplifier circuit according to a value of the control voltage. Item 2. The voltage generation circuit according to Item 1. The first differential amplifier circuit includes:
One input terminal to which the reference voltage is input;
The other input terminal to which the internal power supply voltage is input;
A drive control terminal for controlling driving of the first differential amplifier circuit;
An output terminal pair,
The second differential amplifier circuit includes:
A first input terminal pair including one input terminal to which the reference voltage is input and the other input terminal to which the internal power supply voltage is input;
A second input terminal pair connected to the output terminal pair;
A first drive control terminal pair for controlling driving of the second differential amplifier circuit with respect to the first input terminal pair;
A second drive control terminal pair for controlling driving of the second differential amplifier circuit with respect to the second input terminal pair;
An output terminal connected to the control electrode;
Depending on the output of the control circuit,
The first differential amplifier circuit is driven, the second differential amplifier circuit is not driven with respect to the first input terminal pair, and the second differential amplifier circuit with respect to the second input terminal pair is A first state to be driven;
The first differential amplifier circuit is not driven, the second differential amplifier circuit is driven with respect to the first input terminal pair, and the second differential amplifier circuit with respect to the second input terminal pair is The voltage generation circuit according to claim 2, wherein the voltage generation circuit is switched to a second state that is not driven.

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