JP2005065364A - Semiconductor integrated circuit and magnetic disk memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit technology which can shorten the developing period of an LSI for controlling an information device, such as a hard disc unit, etc. <P>SOLUTION: The semiconductor integrated circuit and a magnetic disk memory include a plurality (111-117) sets (channels) of PWM modulating circuits (PWM1-PWM7) and output driver circuits (DRV1-DRV7) driven by PWM control pulses generated from the PWM modulating circuits, programmable arithmetic circuits (173, 176) which are constituted to be arbitrarily combined and which can execute an arbitrary process by an externally loaded program, a programmable sequence control circuit (175) for generating a control signal for operating the arithmetic circuit and the channel in an arbitrary order by the externally loaded program, and ports (171, 172) for loading the program. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a semiconductor integrated circuit for controlling a plurality of drivers capable of PWM (pulse width modulation) control driving, such as a three-phase brushless motor for rotational driving, a direct current motor that functions as an actuator, and a DC-DC converter that generates a direct current power source. The present invention relates to a technique that is effective when applied to a circuit, for example, a technique that is effective when used in a drive control device of an information device such as a hard disk (hard disk drive) device.
[0002]
[Prior art]
In general, a three-phase brushless motor called a spindle motor is used for rotating a magnetic disk in a hard disk device. The magnetic disk is rotated at high speed by the spindle motor, and the surface of the rotating magnetic disk is read / written. Information is written or read while moving the magnetic head in the radial direction of the magnetic disk by an actuator such as a voice coil motor.
[0003]
Conventionally, since a spindle motor and an actuator are driven differently, drive control is performed by control circuits designed with different specifications. On the other hand, in the field of small information devices typified by hard disk devices, there is a high demand for lower prices. Therefore, hard disk devices include drive control of spindle motors and actuators and power supply circuits that generate DC power supply voltages necessary for these controls. It has been integrated on a single semiconductor chip to reduce the cost.
As an invention in which the drive control circuit for the spindle motor and the drive control circuit for the voice coil motor are made into one chip, there is one disclosed in Patent Document 1, for example.
[0004]
[Patent Document 1]
JP 2001-275387 A
[0005]
[Problems to be solved by the invention]
The drive control system of a conventional hard disk device is generally composed of an analog control circuit and an output stage (driver), and the output stage can be of various types such as a class AB power amplifier, a full bridge circuit, a high side driver, and a low side driver. It has a form.
[0006]
In addition, the specifications for drive control of spindle motors and voice coil motors differ for each manufacturer and for each device in hard disk devices, and the LSI manufacturer for control changes the LSI specifications every time the device manufacturer changes the model. Forced to change. Therefore, in the control LSI in which the drive control circuit for the spindle motor and the drive control circuit for the voice coil motor are integrated on a single chip as described above, the period for developing the LSI corresponding to the new specification becomes long and the short period However, there is a problem that a very large number of manpower is required to complete the development, resulting in an increase in cost.
[0007]
Such a problem occurs not only in the hard disk device but also in information devices such as a DVD (digital video disk) device having a similar hardware configuration and a printer having a plurality of actuators, OA devices, robots, automobiles, and the like.
[0008]
An object of the present invention is to provide a semiconductor integrated circuit technology capable of shortening the development period of a control LSI for an information device such as a hard disk device.
Another object of the present invention is to provide a highly flexible control LSI that can quickly cope with changes in specifications in information equipment such as a hard disk device.
Another object of the present invention is to provide a highly versatile control LSI capable of handling information devices of the same type but having different specifications.
[0009]
Still another object of the present invention is to provide a highly versatile control capable of dealing with devices having a plurality of motors and actuators such as information devices, OA devices, robots, automobiles and the like having different functions such as hard disk devices, DVD devices, and printers. It is to provide an LSI for use.
The above and other objects and features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, a plurality of (preferably seven or more) sets of PWM modulation circuits and output driver circuits driven by PWM control pulses generated by the PWM modulation circuits (hereinafter referred to as channels) are provided and arbitrarily combined. Programmable arithmetic circuit capable of executing arbitrary arithmetic processing by an externally loaded program and a control signal for generating the control signal for operating the arithmetic circuit and the channel in an arbitrary procedure by an externally loaded program A sequence control circuit and a port for loading the program are provided.
[0011]
According to the above means, a driving circuit for a three-phase brushless motor is realized by using three of the plurality of channels, and an actuator driving circuit is realized by using two channels. A drive circuit for a DC-DC converter can be realized by using a channel, and further, the drive circuit can be appropriately operated according to a control target by a programmable sequence control circuit. Therefore, it is possible to provide a highly versatile control LSI capable of supporting information devices having different functions such as a printer.
[0012]
In addition, it is possible to deal with devices having different specifications by changing the contents of the calculation in the calculation circuit. In addition, each channel is equipped with a PWM modulation circuit, so compared to the control by a general-purpose control device such as a DSP, torque ripple is small when the control target is a motor, and high-speed response control is possible when an actuator is used. Thus, in the case of a switching regulator, the power supply can be stabilized, and the performance of the system using the control LSI of the present invention is comparable to that of a system using a control LSI designed for exclusive use in the past. be able to.
[0013]
Further, in the control LSI of the present invention, preferably, logic can be changed such as custom logic or FPGA (Field Programmable Logic Array) so that each LSI can have a specific function. Built-in logic circuit. Accordingly, it is possible to provide a control LSI that has high versatility and flexibility and can enhance performance or function according to the device to be used.
[0014]
According to a second aspect of the present application, a first element formation region and a second element formation region that are electrically isolated from each other by an isolation band made of an insulator are provided on one surface of a semiconductor substrate. A buried insulating layer is formed in the element formation region, and the second element formation region is formed so that at least one side thereof extends to the edge of the semiconductor substrate, and embedded in the second element formation region. A transistor element in which a larger current flows than the transistor element formed in the first element formation region without forming an insulating layer is formed.
[0015]
According to such means, even when a large current flows through the transistor element formed in the second element formation region without the buried insulating layer and heat is generated, the heat is quickly transmitted to the substrate side and dissipated. Therefore, it is possible to avoid a change in the characteristics of the output transistor due to an extremely high temperature.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration of an embodiment of a control LSI according to the present invention. As shown by reference numerals 111 to 117, the control LSI of this embodiment is a combination of PWM modulation circuits PWM1 to PWM7 and output driver circuits DRV1 to DRV7 driven by PWM control pulses generated by the PWM modulation circuit. 7 channels are provided.
Further, three current sensing resistors Rs1 to Rs3 for detecting a current flowing in an external device connected to the external terminal, and current sensing amplifiers 121, 123, 125 for amplifying a potential difference between both terminals of these resistors. Is provided.
[0017]
Further, three voltage sensing amplifiers 122, 124, 126 that are connected to external terminals and amplify the potential difference between the terminals are also provided. The number of current sense amplifiers and voltage sense amplifiers may be increased as necessary.
A common AD conversion circuit 130 is provided for the amplifiers 121 to 126, and the AD conversion circuit 130 is connected to any one of the amplifiers by switches SW1 to SW6 provided between the output terminals of the amplifiers. Are input, the analog outputs of a plurality of amplifiers are converted into digital signals in a time division manner and output onto the internal bus 140.
[0018]
The control LSI of this embodiment is provided with output control circuits 151, 152, and 153 for controlling the 7-channel PWM modulation circuits PWM1 to PWM7 to drive the output driver circuits DRV1 to DRV7. . These output control circuits 151, 152, and 153 are not the entire control circuit but a dedicated circuit or counter such as a coordinate conversion circuit that constitutes a control circuit integrated with a register or DSP (digital signal processor) as described later. Etc.
[0019]
In this embodiment, the output control circuits 151, 152, and 153 can be connected to the 7-channel PWM modulation circuits PWM1 to PWM7 via the channel selector 160, and any of the 7-channel PWM modulation circuits PWM1 to PWM7 is connected. Is also configured to be controllable. When the output control circuits 151, 152, and 153 are prepared as circuits for controlling the DC-DC converter, no dedicated circuit is required, and a buffer or simply supplying a signal on the internal bus 140 to the PWM modulation circuits PWM1 to PWM7. A circuit functioning as a path can be obtained.
[0020]
Further, in the control LSI of the present embodiment, a serial input / output interface 171 for exchanging signals with an external device such as a microprocessor in a serial manner, and a parallel input / output interface 172 for exchanging signals in a parallel manner are also used. From a DSP unit 173 having the same configuration as a known DSP comprising an addition / subtraction circuit, a multiplication / division circuit and a microprogram control unit, a RAM (random access memory) for storing a control program loaded from the outside, and the like 174, a sequencer 175 for sequentially generating control signals inside the chip in accordance with a program stored in the memory 174, registers REG0 to REG15, REG. A to REG. A register group 176 consisting of F is provided.
[0021]
The sequencer 175 can be composed of a program counter that generates an address for sequentially reading instructions of a program stored in the memory 174, a decoder that decodes the read instruction code, and the like. As the memory 174, a flash memory that can be written and erased or a nonvolatile memory such as an EEPROM may be used instead of the RAM. When a non-volatile memory is used, in addition to the sequence control program, data for adjusting variations in the circuits in the chip, such as a DC-DC converter, can be stored in the same memory.
[0022]
Further, the control LSI of this embodiment includes an oscillation circuit 181 for generating a clock signal φc necessary for internal operation of the chip, a reference voltage generation circuit 182 for generating a reference voltage Vref, a reference voltage Vref and a power source. A comparator 183 that determines whether the power supply voltage has risen by comparing with the voltage Vcc, a power-on reset circuit 184 that generates a reset signal RS based on the output of the comparator 183, and the like are provided.
[0023]
In the control LSI having the above-described configuration, a control system (see FIG. 2) such as a hard disk device and a DVD device each having one three-phase brushless motor, one voice coil motor, and one DC-DC converter is configured. Of course, a control system such as a printer that does not have a three-phase brushless motor but instead has two actuators such as stepping motors and DC motors, and a robot that has two three-phase brushless motors (see FIG. 3). Since it can also be used when configuring the LSI, it is an LSI with extremely high versatility.
[0024]
In the control system of FIG. 2, one end of each of the U-phase, V-phase, and W-phase coils of the three-phase brushless motor (spindle motor) M1 is connected to the output terminals of the channels 111 to 113, and the output terminals of the channels 114 and 116 are connected. The terminals of the coil of the voice coil motor VCM are connected to each other, and one end of the voltage conversion coil L of the DC-DC converter is connected to the output terminal of the channel 117. The output control circuit 151 functions as a spindle motor output control circuit, the output control circuit 152 functions as a voice coil motor output control circuit, and the output control circuit 153 functions as a DC-DC converter output control circuit. The In this system, the amplifier 122 and the channel 115 are unused.
[0025]
In the control system of FIG. 3, one end of each of the U-phase, V-phase, and W-phase coils of the first three-phase brushless motor M1 is connected to the output terminals of the channels 111 to 113, and the output terminals of the channels 114 to 116 are connected to the first output terminals. One end of each of the U-phase, V-phase, and W-phase coils of the second three-phase brushless motor M2 is connected, and one end of the voltage conversion coil L of the DC-DC converter is connected to the output terminal of the channel 117. The output control circuits 151 and 152 both function as a spindle motor output control circuit, and the output control circuit 153 is configured to function as a DC-DC converter output control circuit. In this system, the amplifiers 122 and 124 are unused.
[0026]
FIG. 4 shows a general configuration example of a PWM-controlled drive control circuit for a sensorless three-phase brushless motor, and FIG. 5 shows a case where the drive control circuit of FIG. 4 is realized by the hardware components of FIG. FIG. 6 shows an example of a configuration in which each function of the control unit of the three-phase brushless motor in the system of FIG. 2 or 3 is assigned to each circuit of the hardware of FIG.
[0027]
As shown in FIG. 4, the drive control circuit of the PWM control method of the sensorless three-phase brushless motor is based on the current Isens detected by the current sensing resistors Rs1 or Rs2 and Rs3 and the amplifier 121 or 123,125. A three-phase coil current reproduction circuit 231 that reproduces the currents iuc, ivc, and iwc of the three-phase coils U, V, and W in real time, and a coordinate conversion of the reproduced currents iuc, ivc, and iwc into two-phase DC currents id and iq The uvw / dq conversion circuit 232, the subtracter 233 for taking the difference between the converted current id, iq and the current command value Id, Iq, and the output so that the current id, iq and the current command value Id, Iq are equal. A voltage control circuit 234 that adjusts the voltages Vd and Vq, and dq that generates the three-phase AC voltages Vu, Vv, and Vw by performing inverse coordinate transformation of the voltages Vd and Vq. The uvw conversion circuit 235, the axis error calculation circuit 236 that calculates the axis error Δθ from the voltages Vd, Vq, id, iq, and the rotation speed signal ω, and the difference between the calculated axis error Δθ and the predetermined value “0”. Subtractor 237, a phase control circuit 238 for generating the rotation speed signal ω, and an integration circuit 238 for integrating the rotation speed signal ω. The phase control circuit 238 and the integration circuit 239 have an axis error Δθ of “ PLL (phase locked loop) control is performed so as to be “0”. The circuit shown in FIG. 4 is generally called a vector control unit.
[0028]
In order to drive the motor with an appropriate torque, this vector control unit generates a three-phase sine wave voltage value based on the reproduction currents iuc, ivc, iwc from the current reproduction unit 231 and the current command values Id, Iq from the external controller. The amplitude and phase of Vu, Vv, and Vw are controlled, and such a vector control unit has the same configuration as a known vector control unit, and therefore detailed description thereof is omitted. The rotational speed signal ω detected by the phase control circuit 238 is also supplied to a controller (not shown), and the controller sends a current command value so that the rotational speed signal ω becomes constant according to the detected rotational speed. come.
[0029]
In FIG. 5 showing a configuration method when the drive control circuit of FIG. 4 is realized by the hardware components of FIG. 1, the same circuits as those shown in FIG. 1 and FIG. It is attached. Reference numeral M denotes a three-phase brushless motor. In FIG. 5, the channel selector between the dq / uvw conversion circuit 235 and the PWM modulation circuits PWM1 to PWM7 is not shown. The output (detection current Isens) of the amplifier 121 (123) connected to both terminals of the current sensing resistor Rs1 (Rs2) is converted into a digital signal by the AD conversion circuit 130 and input to the three-phase coil current reproduction circuit 231. From this, it can be seen that the control unit 230 is a digital circuit.
[0030]
As apparent from comparison between FIG. 5 and FIG. 4, in FIG. 5, among the circuits constituting the control unit 230 of FIG. 4, the three-phase coil current reproduction circuit 231, the uvw / dq conversion circuit 232, and dq Only the / uvw conversion circuit 235, the axis error calculation circuit 236, and the subtractor 237 are shown, the voltage control circuit 234, the phase control circuit 238, and the integration circuit 238 are not shown. Instead, the filters FLT1, FLT2, and FLT3 And a counter CNT is shown.
[0031]
This is because in the digital circuit, the functions of the current control circuit 234, the phase control circuit 238, and the integration circuit 238 can be realized by filter calculation processing and counter processing. The function of the axis error calculation circuit 236 can also be realized by calculation processing, but it may be provided as a dedicated circuit. In FIG. 4, there are two subtractors 233 and 237, while FIG. 5 shows three subtractors 233a, 233b, and 237. In FIG. 4, 233 subtractors originally composed of two subtractors are shown. Is shown as one for convenience of illustration, and there is no difference between FIG. 4 and FIG.
[0032]
FIG. 6 shows an example of a configuration in which each function of the control unit of the three-phase brushless motor in the system of FIG. 2 or FIG. 3 is assigned to each circuit of the hardware of FIG. The same circuit as the circuit is denoted by the same reference numeral. In FIG. 6, the control unit of the three-phase brushless motor includes an output control circuit 151 (or 152), a DSP 173, a sequencer 174, and a register group 176.
[0033]
As apparent from comparison between FIG. 6 and FIG. 4, in FIG. 6, the unit UNIT1 having the function of the three-phase coil current reproduction circuit 231 among the circuits constituting the control unit 230 of FIG. Only the unit UNIT2 having the functions of the conversion circuit 232 and the dq / uvw conversion circuit 235 is shown, the axis error calculation circuit 236, the subtractor 237, the current control circuit 234, the phase control circuit 238, and the integration circuit 239 are shown. Instead, a counter CNT is shown. This is because, as described above, in the digital circuit, the functions of the current control circuit 234, the axis error calculation circuit 236, the phase control circuit 238, and the integration circuit 239 can be realized by filter calculation processing and counter processing.
[0034]
6 and FIG. 5, among the circuits constituting the control unit 230 in FIG. 5, the filters FLT1, FLT2, and FLT3 and the subtracters 233a, 233b, and 237 are shown in FIG. It has not been. In the digital circuit, the functions of the filters FLT1, FLT2, and FLT3 can be realized by filter arithmetic processing using a DSP and a register, and the functions of the subtractors 233a, 233b, and 237 are, for example, arithmetic units incorporated in the DSP. This is because it can be realized.
[0035]
On the other hand, the functions of the three-phase coil current reproduction circuit 231 and the functions of the uvw / dq conversion circuit 232 and the dq / uvw conversion circuit 235 are intended to increase the speed of digital arithmetic processing. The unit UNIT1 having the function 231 and the unit UNIT2 having the functions of the uvw / dq conversion circuit 232 and the dq / uvw conversion circuit 235 are provided in the output control circuit 151 as hardware dedicated to the three-phase brushless motor. As for the counter, its function can be realized by using an arithmetic unit in the DSP, but if it is so, a sufficient speed cannot be obtained. Therefore, in this embodiment, the counter circuit CNT is also provided in the output control circuit 151 as hardware dedicated to the three-phase brushless motor.
[0036]
The unit UNIT 1 having the function of the three-phase coil current reproduction circuit 231, the unit UNIT 2 having the functions of the uvw / dq conversion circuit 232 and the dq / uvw conversion circuit 235, and the counter circuit CNT are not limited to the output control circuit 151. By providing the output control circuit 152 as well, a system for driving and controlling two three-phase brushless motors as shown in FIG. 3 can be configured relatively easily. However, the unit UNIT1, the unit UNIT2, the counter circuit CNT, Even if only the output control circuit 151 is provided, when the high rotation speed is not required, that is, when the high-speed PWM carrier and the high-speed current sampling are not required, the output control circuit 151 is provided with two three-phase brushless motors. Can be used in a time-sharing manner. Such time division control is possible by switching the channel selector 160 as appropriate.
[0037]
Furthermore, in this embodiment, the unit UNIT1 having the function of the three-phase coil current reproduction circuit 231 differs depending on the system manufacturer that is the user, and is defined by the control technology based on the know-how that each user has accumulated independently. Therefore, it is mounted on the chip as an FPGA or a custom logic circuit. Programming to the FPGA (for example, writing connection information between elements or circuits) can be performed by the user who has received the control LSI, but the manufacturer obtains information such as circuit design data from the user. You may make it perform in the manufacturing process (for example, test process etc.) of LSI.
[0038]
As shown in FIG. 6, the DSP 273 used in this embodiment includes an arithmetic register 731 such as an accumulator and an ALU (arithmetic operation) that can perform complex operations such as addition / subtraction / multiplication / division, product-sum operation, and trigonometric function operation. Logical unit) 732, a microprogram memory 733 composed of a RAM or nonvolatile memory for storing an operation control microprogram, and a decoder for sequentially reading out the microinstructions from the memory to generate and control control signals for the ALU 732 and the operation register 731 And a microsequencer 734 including the above. As a dedicated sequencer for realizing the filter transfer function requested by the user, the microsequencer controls the DSP unit independently of the program of the sequencer 175, so that high-speed filter calculation is possible. For example, PWM control at 100 kHz or higher, which is difficult to achieve with microprocessor control, or high-precision high-speed rotation control is possible. Since the configuration of the other DSP unit 731 is the same as that of a known DSP, detailed description is omitted.
[0039]
In the control LSI of this embodiment, the microprogram memory 733 is composed of a RAM or a nonvolatile memory, and the microprogram can be loaded from the serial port 171 or the parallel port 172. By rewriting the microprogram, for example, the transfer function of the filters FLT1 to FLT3 shown in FIG. 5 can be changed to realize a first-order filter or a second-order or third-order filter. Therefore, the control circuit which can perform optimal control according to the three-phase brushless motor to be used with high flexibility of the system can be constructed.
[0040]
In the control LSI of this embodiment, the memory 174 for storing the sequence control program is also composed of a RAM or a non-volatile memory so that the program can be loaded from the serial port 171 or the parallel port 172. ing. Therefore, by rewriting this sequence control program, for example, the switching control signal of the channel selector 160 or the like is changed to change one 3-phase brushless motor, one actuator, and one as shown in FIG. A control circuit for driving and controlling a DC-DC converter, or a control circuit for driving and controlling two three-phase brushless motors and one DC-DC converter as shown in FIG. it can.
[0041]
In addition, the arithmetic control program and the sequence control program can be decoded by the sequencer 175 or 734 with a dedicated compiler after designing the basic architecture using system development support software (development tool) such as MATLAB. It can be created efficiently by converting to language. The created program can be written by the user from the serial port 171 or the parallel port 172 to the microprogram memory 733 or the memory 174 in the chip, but may be written by the manufacturer. In addition, it is possible to use the port properly such that the parallel port 172 is used when the manufacturer loads the program into the memory, and the serial port is used when the user changes the program.
[0042]
FIG. 7 shows a configuration example of a control circuit that performs PWM drive control of a voice coil motor VCM as an example of an actuator. In FIG. 7, the same circuits as those shown in FIG.
As shown in FIG. 7, the control unit of the voice coil motor VCM includes an amplifier 123 (121) that amplifies the voltage across the terminals of the sense resistor Rs2 (Rs1) that detects the current flowing through the drivers DRV4 and DRV5. An AD converter circuit 130 that converts the output of the amplifier into a digital signal, a subtractor SUB that takes the difference between the current command value Ivcm from an external controller and the output of the AD converter circuit 130, the output of the filter FLT4, and the output of the filter FLT4 The inverter INV and the PWM modulation circuits PWM4 and PWM5 can be used.
[0043]
Here, the subtracter SUB can be realized by the ALU 732 in the DSP 173, or the filter FLT 4 can be realized by the DSP 173 and any register in the register group 176. The inverter INV can also be realized by using the DSP 173, but if the speed is slow, the area occupied by the inverter circuit is very small. Therefore, the inverter INV is provided in the output control circuit 152 (or 151 and 152) as a dedicated circuit for actuator drive control. It is good to keep it. Thus, by rewriting the sequence control program in the memory 174 and the calculation control program in the DSP 173, the DSP 173, the register group 176, and the channels 114 and 115 (or 116) are used to drive the voice coil motor VCM. Can be built. Further, the subtractor SUB and the filter FLT5 may be further provided as a dedicated circuit in the output control circuit 152 (or 151 and 152).
[0044]
In the embodiment of FIG. 7, the current is detected and the drive control signal is generated, but the voltage between both terminals of the coil of the voice coil motor VCM is detected to generate the drive control signal and to control the speed. Is also possible. In that case, the voltage between both terminals of the coil detected using the amplifier 124 may be converted into a digital signal and fed back to the control circuit.
[0045]
FIG. 8 shows a configuration example of a control circuit that performs PWM drive control of the DC-DC converter. In FIG. 8, the same circuits as those shown in FIG.
As shown in FIG. 8, the control unit of the DC-DC converter includes an amplifier 126 that detects the output voltage Vout, an AD conversion circuit 130 that converts the output of the amplifier into a digital signal, and an external controller. Voltage command value Vo1 ^* And a subtractor SUB that takes the difference between the output of the AD conversion circuit 130, a filter FLT5, and a PWM modulation circuit PWM7. Further, the amplifier 125, the current sense resistor Rs3, and the AD converter circuit 130 may constitute a current feedback minor loop to improve the response of the DC-DC converter.
[0046]
Here, the subtracter SUB can be realized by the ALU 732 in the DSP 173, or the filter FLT5 can be realized by the DSP 173 and any register in the register group 176. Therefore, by rewriting the sequence control program in the memory 174 and the calculation control program in the DSP 173, a drive control circuit for the DC-DC converter can be constructed using the DSP 173, the register group 176, and the channel 117.
[0047]
As can be seen from the above description, it is not necessary to provide any dedicated circuit in the output control circuit 153 of FIG. 1 in order to be able to configure the DC-DC converter control unit as shown in FIG. However, the output control circuit 153 may be provided with the subtracter SUB and the filter FLT5 as dedicated circuits. As a result, the processing speed can be increased compared to the case where the drive control circuit is configured using the DSP 173 and the register group 176.
[0048]
In FIG. 9, as the filters FLT1 to FLT5 constituting the control unit as shown in FIG. 5, FIG. 7, and FIG.
H (z) = k · [{1 + b1 · (z) ^-1 } / {1-a1 · (z) ^-1 }]
A configuration example of a filter in the case of using a first-order IIR filter represented by
[0049]
From FIG. 9, it can be seen that in order to realize the IIR filter, it is only necessary to create a DSP operation program using the DSP 173 and the register group 176 so as to execute the operation in the following procedure.
(1) OUTA ′ (N) * a1 + IN (N) → OUTA (N)
(2) OUTA ′ (N) * b1 + OUTA (N) → OUTC (N)
(3) OUTC (N) * k → OUT (N)
(4) OUTA (N) → OUTA '(N)
Further, the operation result OUTA (N) of (1) is stored in the register REG0, the operation result OUTC (N) of (2) is stored in the register REG2, the operation result OUT (N) of (3) is stored in the register REG3, (4 The sequence control program may be created so that the operation result OUTA ′ (N) of () is stored in the register REG1.
[0050]
FIG. 10 shows a specific circuit example of the PWM modulation circuits PWM1 to PWM7 constituting the channels 111 to 117 shown in FIG. The PWM modulation circuits PWM1 to PWM7 of this embodiment are constituted by digital circuits. Specifically, the up / down counter CNT1, the digital comparator CMP1 that compares the count value of the counter CNT1 with a predetermined comparison value A, and the digital comparator CMP2 that compares the count value of the counter CNT1 with a predetermined comparison value B And a logic circuit LG that receives the outputs of the comparators CMP1 and CMP2. The logic circuit LG can be configured using, for example, an RS type flip-flop that toggles according to the outputs of the comparators CMP1 and CMP2. Two counters may be provided for each of the comparators CMP1 and CMP2 instead of one counter.
[0051]
A PWM modulation circuit used in a conventional PWM control circuit of a spindle motor is an analog PWM modulation circuit including a triangular wave generation circuit having a predetermined period and amplitude, an analog comparator for comparing the generated triangular wave and a control voltage, and the like. It is often composed of. Such an analog PWM modulation circuit can be used as the PWM modulation circuits PWM1 to PWM7 constituting the channels 111 to 117 shown in FIG. 1. However, when an analog circuit is used, the period is changed or the amplitude is changed. The triangular wave generating circuit that can be changed has a complicated circuit configuration, and the analog comparator is also required to have high accuracy. In addition, an accurate triangular wave oscillator is required to ensure the linearity of PWM modulation. Therefore, the entire circuit can be simplified by using the digital PWM modulation circuit having the configuration as shown in FIG.
[0052]
In the digital PWM modulation circuit of FIG. 10, the same result as changing the period of the triangular wave generated by the triangular wave generation circuit of the analog PWM modulation circuit by changing the frequency of the clock CLK for operating the up / down counter CNT1. Is obtained. Further, by changing the comparison value A (or B) input to the digital comparators CMP1 and CMP2, the same result as that obtained by changing the amplitude of the triangular wave generated by the triangular wave generating circuit of the analog PWM modulation circuit is obtained. By changing the value B (or A), the pulse width of the output control pulse Ppwm can be changed.
[0053]
11A and 11B show specific circuit examples of the drivers DRV1 to DRV7 constituting the channels 111 to 117 shown in FIG. Of these, the driver shown in FIG. 11A is a driver suitable for performing synchronous rectification control, and is an output transistor Q1, Q2 composed of two serial N-channel MOSFETs, and the gate terminals of these transistors Q1, Q2. And a differential amplifier AMP1 for controlling The input of the differential amplifier AMP1 receives a drive pulse Ppwm whose pulse width is controlled from the previous PWM modulation circuit, and the output transistors Q1 and Q2 are complementarily turned on and off. The output transistors Q1 and Q2 are high breakdown voltage, high output MOSFETs called so-called power MOSs that can flow a relatively large current through a coil connected to an external terminal. A bipolar transistor can be used instead of a MOSFET. good.
[0054]
The driver shown in FIG. 11B includes an output transistor Q1 formed of an N-channel MOSFET, a Schottky diode D1 connected in the reverse direction to the source terminal of Q1, and a differential amplifier AMP1 that controls the gate terminal of the output transistor Q1. It is composed.
[0055]
FIG. 12 shows a chart summarizing each component of the control LSI according to the present invention and a method for realizing the component.
As can be seen from FIG. 12, the control LSI according to the present invention includes dedicated hardware, programmable hardware, a programmable sequencer (control device), and user design logic according to the purpose of the circuit. There are four categories. In this way, by changing the properties of the components according to the purpose, it is possible to provide a control LSI that can realize a circuit having high versatility and a function corresponding to the target system at a low price. It becomes. In this embodiment, the DSP belongs to both programmable hardware and a programmable sequencer.
[0056]
FIG. 13 shows a control LSI according to the present invention comprising a disk rotation spindle motor, an arm moving voice coil motor, and a power source DC-DC converter in a hard disk type magnetic storage device (hereinafter simply referred to as a hard disk device). The example of a structure of the whole system at the time of using for the control apparatus which controls drive is shown. Note that the control circuit 100 in FIG. 13 functionally shows a hard disk control device, and the circuit blocks as shown do not exist as independent circuits.
[0057]
As shown in FIG. 13, the hard disk device of this embodiment has a magnetic disk 300, a spindle motor 310 that drives the magnetic disk 300 to rotate at high speed, and a read / write of information with respect to storage tracks on the magnetic disk 300. An arm 320 having a magnetic head HD at the tip for writing, a voice coil motor 340 for moving the magnetic head HD on the magnetic disk 300 via the arm, and an arm 320 disposed outside the magnetic disk 300 when the disk rotation is stopped. , A drive control circuit 100 for controlling the drive of the spindle motor 310 and the voice coil motor 340, and controlling the overall operation of the hard disk device, and a current command value for the spindle motor 310 and a current command value for the voice coil motor 340. Having such as a controller 200 to power.
[0058]
The controller 200 is composed of a microcomputer (CPU) or the like, and the drive current command value output from the controller 200 is sent to the motor drive circuit 100. There are drive current command values relating to the control of the spindle motor 310 (Id, Iq) and those relating to the control of the voice coil motor 340 (Ivcm), and the spindle motor 310 and the voice coil motor 340 are separately driven and controlled. The From the controller 200 to the motor drive circuit 100, a voltage command value Vo1 for a regulator composed of a DC-DC converter. ^* Is also sent. Although not shown in FIG. 13, the arm 320 is separately provided with a signal processing IC for driving the magnetic head HD to perform writing on the magnetic disk 300 and detecting position information based on a read signal.
[0059]
The drive control circuit 100 includes a spindle motor driver 400, a voice coil motor driver 500 that moves the magnetic head in the radial direction of the disk, and an input / output port 700, and operates according to a control signal supplied from the controller 200. The voice coil motor 340 and the spindle motor 310 are controlled so that the magnetic head seeks to a desired track and the relative speed of the magnetic head is constant. Further, the drive control circuit 100 includes a regulator 600 formed of a DC-DC converter and a power supply monitor circuit 800. The regulator 600 steps down the power supply voltage Vcc2 for IC such as 5V, such as 3.3V. The internal power supply voltages Vreg1 to Vreg3 are generated. The generated power supply voltages Vreg1 to Vreg3 are also supplied to the controller 200. The power supply monitor circuit 800 monitors Vreg1 to Vreg3 and generates a power-on detection signal P-ON indicating the rising of the internal voltage, or outputs a reset signal RS to the controller 200. The power switch PSW that supplies the power supply voltage Vcc1 to the control LSI 100 is turned on and off by the power-on detection signal P-ON.
[0060]
The controller 200 is composed of a microcomputer or the like, and takes in read data transmitted from the signal processing circuit of the head and performs error correction processing, or performs error correction coding processing on write data from the host computer and outputs a signal. Or output to the processing circuit. The signal processing circuit performs signal processing such as modulation / demodulation processing suitable for magnetic recording and waveform shaping in consideration of magnetic recording characteristics, or reads the position information of the magnetic head HD in response to a signal from the read / write IC. It has a function to do.
[0061]
The controller 200 is connected to a host computer such as a microcomputer of the personal computer body. The controller 200 controls each part of the system according to the operation mode, and calculates the sector position and the like based on address information supplied from the host computer. A cache memory for a buffer that temporarily stores read data read from the magnetic disk at high speed may be provided.
[0062]
Next, the second invention of the present application will be described.
In the control LSI of the embodiment, the output transistors Q1 and Q2 constituting the output driver circuits DRV1 to DRV7 are constituted by high withstand voltage and high output MOSFETs, and the high withstand voltage and high output MOSFETs constitute other circuits. It is formed on one semiconductor chip together with the element to be operated.
[0063]
Conventionally, in an LSI in which such a high withstand voltage and high output MOSFET is formed on one semiconductor chip together with elements constituting other circuits, as shown in FIG. 23, it is formed by an insulating film such as silicon oxide. An island-like semiconductor region 12 surrounded by the isolation band 11 and the buried insulating layer 14 is provided on the semiconductor substrate 10, a high-voltage, high-power MOSFET is provided in the island-like region 12, and another region 13 is provided in the outer region 13. In many cases, an element constituting a circuit is formed. 23A is a plan view of the semiconductor chip, and FIG. 23B is a cross-sectional view showing a cross-sectional structure taken along the line BB ′ in FIG.
[0064]
Since a very large current flows through a transistor such as an output transistor of an output driver circuit that drives a motor, a large amount of heat is generated there. However, since an insulating film used in silicon oxide or other semiconductor devices has low thermal conductivity, an island-shaped semiconductor region surrounded by the isolation band 11 and the embedded insulating layer 14 formed of the insulating film as described above. In the semiconductor integrated circuit in which an output transistor having a high withstand voltage and a high output is formed on 12, there is a problem that the heat generated in the output transistor is not sufficiently dissipated and the characteristics may be deteriorated. The second invention provides a technique for solving such a problem.
[0065]
FIG. 14 shows a first embodiment of a substrate structure of a semiconductor integrated circuit to which the present invention is applied. FIG. 14 shows two adjacent chips 20a and 20b on the semiconductor wafer, and a control LSI as shown in FIG. 1 is formed on each chip. In FIG. 14A, the alternate long and short dash line corresponds to a scribe line for cutting each chip from the wafer. FIG. 14B is a cross-sectional view showing a cross-sectional structure cut along the line BB ′ in FIG.
[0066]
In the embodiment of FIG. 14, an output transistor formation region 12 is provided across the two chips at the boundary between two adjacent chips 20a and 20b. An element forming region 13 separated by a wall-shaped isolation band 11 made of an insulating film is provided outside the output transistor forming region 12, and circuit elements other than the output transistor are formed in the element forming region 13. A buried insulating layer 14 is formed below the element formation region 13, and the element formation region 13 is completely insulated from the substrate 10. The separation band 11 can be formed by, for example, a so-called trench isolation technique in which a groove is cut on the surface of a chip and an insulating material is filled inside the groove.
[0067]
On the other hand, an insulating layer is not provided below the output transistor formation region 12 and is in contact with the substrate 10. Therefore, even if a relatively large current flows through the output transistor in the formation region 12 and the temperature rises, it is avoided that the heat is transferred to the substrate 10 and becomes extremely high temperature, thereby suppressing the change in the characteristics of the output transistor. can do. In addition, in this embodiment, since the output transistor formation region 12 is formed across two chips, it can be used effectively up to the edge of the chip, and is provided inside the chip as shown in FIG. The area of the element formation region 13 is not reduced compared to the case where the device is formed. That is, the chip size can be reduced as compared with the prior art.
[0068]
FIG. 15 shows a second embodiment of the structure of the substrate of the semiconductor integrated circuit to which the present invention is applied. The cross-sectional structure is the same as FIG.
In the second embodiment, an output transistor formation region 12 is provided across two chips at the boundary between two adjacent chips 20a and 20b, and a wall shape is provided outside the output transistor formation region 12. The separation band 11 is formed in a pentagon. A buried insulating layer is not provided below the output transistor formation region 11 surrounded by the isolation band 11 made of an insulating film, and a buried insulating layer 14 is provided below the element formation region 13 outside the isolation band 11. Is formed, and the element formation region 13 is completely insulated from the substrate 10.
[0069]
In this embodiment, although not particularly limited, an output transistor is formed in the rectangular region 12 a inside the output transistor forming region 12, and circuit elements other than the output transistor are formed in the element forming region 13. In this embodiment, the same effect as that of the first embodiment can be obtained, and since the shape of the separation band 11 is a polygon, the distortion generated at each corner due to the thermal stress in the process and the stress of the package is alleviated. There is an advantage that. A polygon such as a hexagon or an octagon may be used instead of the pentagon.
[0070]
Further, as shown in FIG. 16, the shape of the separation band 11 may be circular. In this case, distortion due to stress can be minimized. Further, FIGS. 14 to 16 show the case where the output transistor formation region 12 is formed so as to extend over two chips, but as shown in FIG. 17, each of the chips 20a, 20b, 20c, 20d. An output transistor formation region 12 surrounded by a separation band 11 may be provided so as to straddle between chips adjacent to each corner.
[0071]
FIG. 18 shows another embodiment of a substrate structure of a semiconductor integrated circuit to which the present invention is applied. In this embodiment, an output transistor formation region 12a in which output transistors Q1 and Q2 are separated by an isolation band 11 ′ made of an insulating film for each of output driver circuits DRV1 to DRV7 of the channels 111 to 117 of the control LSI of FIG. It is made to form in ~ 12g. An isolation band 11 is provided so as to surround the entire output transistor formation regions 12a to 12g, and the outside is an element formation region 13 of another circuit. As in this embodiment, since the output transistor formation regions 12a to 12g are separated for each channel by the separation band 11 ', there is an advantage that latch-up is less likely to occur.
[0072]
Similarly to the above embodiment, the buried insulating layer 14 is formed corresponding to the element forming region 13, and the buried insulating layer is not formed in the region inside the isolation band 11. Further, the inner region of the separation band 11 having no embedded insulating layer is provided across adjacent chips. The one-dot chain line shown in FIG. 18 can be regarded as a scribe line indicating the boundary of each chip. Since a buried insulating layer is not formed in the inner region of the separation band 11, the output transistor formed in the inner region of the separation band 11 does not generate heat even if a relatively large current flows, as in the previous embodiment. It is avoided that the output transistor reaches an extremely high temperature due to the transmission to the substrate 10, and the deterioration of the characteristics of the output transistor can be suppressed.
[0073]
Since the buried insulating layer is not formed in the region inside the separation band 11, the lower end of the separation band 11 ′ is not in contact with the buried insulating layer unlike the separation band 11, as shown in FIG. The transistor formation regions 12a to 12g are not electrically separated from each other through the substrate 10, but can be latched up to the extent that there is no practical problem by appropriately setting the distance D between the regions 12a to 12g. The strength can be sufficiently increased.
[0074]
Next, a method for manufacturing a wafer capable of forming a semiconductor integrated circuit having the structure as in the above embodiment will be described.
FIG. 19 shows the procedure of the first manufacturing method of the wafer forming the semiconductor integrated circuit of the above embodiment in the order of steps.
First, in the first step (A), a region AR2 other than the portion AR1 which becomes the output transistor formation region 12 on the surface of the bare wafer WF1 such as single crystal silicon is selectively etched. Next, the entire surface is oxidized in the step (B), and the entire surface is polished in the step (C) until the silicon in the AR1 part is exposed, and the surface of the wafer WF1 is further cleaned by sputter etching or the like. As another method, an appropriate mask MSK (nitride film or the like) is formed on the surface of AR1, and selective oxidation is performed to form an oxide film SiO on the surface of region AR2. ₂ In the next step (C), the mask MSK is removed, the entire surface of the AR1 portion is polished with respect to the entire surface of the wafer WF1, and the surface of the wafer WF1 is further cleaned by sputtering etching or the like. In this way, a step is formed on the silicon and the whole surface is oxidized and flattened, or a partially oxidized region is formed using a mask and then flattened.
[0075]
Thereafter, in step (D), a wafer WF2 whose surface is separately cleaned by sputter etching or the like is brought, and the two wafers are bonded and processed at a high temperature so that the cleaned surfaces face each other. Connect firmly. Then, in the last step (E), the rear surface of the wafer WF2 bonded later is polished to a desired thickness and completed.
[0076]
FIG. 20 shows the procedure of the second manufacturing method of the wafer forming the semiconductor integrated circuit of the above embodiment in the order of steps.
First, in the first step (A), an oxide film SiO is formed on the entire surface of the bare wafer WF1. ₂ Form. In the second step (B), the oxide film SiO of the part AR1 which becomes the output transistor formation region 12 of the wafer WF1. ₂ Selectively etch. In the next step (C), a polysilicon layer P-Si is formed on the entire surface of the wafer WF1. As another method, an epitaxial growth technique can be used to grow a good crystal having the same crystal orientation as that of the substrate in the AR1 portion, and polysilicon can be grown in AR2 on the oxide film.
In the fourth step (D), the entire surface of the wafer WF1 is polished to remove polysilicon on the oxide film in the region AR2 other than the output transistor formation region (AR1), and the surface of the wafer WF1 is further cleaned by sputter etching or the like. .
[0077]
Thereafter, the process is the same as steps (D) and (E) in FIG. 19. First, in step (E), a wafer WF2 whose surface is separately cleaned by sputter etching or the like is brought and the cleaned surfaces face each other. In this way, the two wafers are bonded and processed at a high temperature to bond them more firmly. In the final step (F), the rear surface of the wafer WF2 bonded later is polished to a desired thickness and completed.
[0078]
FIG. 21 shows the procedure of the third manufacturing method of the wafer forming the semiconductor integrated circuit of the above embodiment in the order of steps.
In this embodiment, first, the oxide film SiO is formed on the surface of the region AR2 other than the portion AR1 which becomes the output transistor formation region 12 of the bare wafer WF1 by the same procedure as the steps (A) to (C) of FIG. ₂ (A). Next, another wafer WF2 is prepared and hydrogen ions are implanted from the surface to form an ion implantation layer HIL, and the surfaces of the wafers WF1 and WF2 are cleaned by sputtering etching or the like (B).
[0079]
The ion-implanted wafer WF2 has a characteristic that the bonding strength of the ion-implanted layer HIL is lowered. Therefore, the two wafers are bonded and processed at a high temperature so that the cleaned surfaces of the wafers WF1 and WF2 whose surfaces are cleaned by sputter etching or the like face each other (C). Then, the wafer WF2 is peeled off along the ion implantation layer HIL, and the peeled wafer WF2 is polished to a desired thickness to complete (D).
[0080]
Note that the oxide film SiO is formed on the surface of the region AR2 other than the portion AR1 to be the output transistor formation region 12 of the bare wafer WF1 in the same procedure as the steps (A) to (D) in FIG. ₂ Alternatively, a desired wafer may be obtained by applying the steps (B) to (D) shown in FIG.
[0081]
Further, as shown in FIG. 22A, oxygen ions are implanted into a region AR2 other than the region AR1 to be the output transistor formation region 12 of the bare wafer WF1 from a surface to a deep region with a high concentration and high energy, and then a high temperature heat treatment is performed. Then, the buried insulating layer 14 may be selectively formed as shown in FIG.
[0082]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Not too long. For example, in the control LSI of the above embodiment, an example was described in which an on-chip power MOSFET was used as an output transistor of an output driver circuit that supplies current to the coils of a three-phase motor, actuator, or switching regulator. The output transistor may be constituted by a power IC formed on a semiconductor chip separate from other circuits. In that case, it is desirable that the control LSI and the power IC are mounted on an insulating substrate such as ceramic and mounted in one package to constitute a so-called module.
[0083]
Further, in the above description, the case where the invention made by the present inventor is applied to a control LSI of a hard disk storage device, which is a field of use that is the background of the invention, has been described. The present invention can be widely used for control LSIs such as information devices and OA devices having actuators such as brushless motors such as a motor for rotating a polygon mirror and an axial fan motor, voice coil motors, stepping motors and solenoids.
[0084]
The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, it is possible to shorten the development period of a control LSI for an information device such as a hard disk device. Further, according to the present invention, it is possible to realize a highly flexible control LSI that can quickly cope with a change in specifications in an information device such as a hard disk device.
Furthermore, according to the present invention, even the same type of information equipment can be used with different specifications, and information equipment with different functions such as a hard disk device, a DVD device, a printer, an OA device, a robot, A highly versatile control LSI that can be widely applied to devices having a plurality of motors and actuators such as automobiles can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a control LSI according to the present invention.
FIG. 2 is a circuit configuration diagram showing a configuration example of a system in which the control LSI of the embodiment is used as a control LSI of an apparatus having one each of a three-phase brushless motor, a voice coil motor, and a DC-DC converter.
FIG. 3 is a circuit configuration diagram showing a configuration example of a system in which the control LSI according to the embodiment is used as a control LSI of an apparatus having two three-phase brushless motors and a DC-DC converter.
FIG. 4 is a block diagram showing a general configuration example of a PWM control method drive control circuit for a sensorless three-phase brushless motor.
5 is a block diagram showing a configuration method when the drive control circuit of FIG. 4 is realized by the hardware components of FIG. 1;
6 is a block diagram showing an example of a configuration in a case where the functions of the control unit of the three-phase brushless motor in the system of FIG. 2 or FIG. 3 are assigned to the hardware circuits of FIG. 1;
FIG. 7 is a block diagram illustrating a configuration example of a control circuit that performs PWM drive control of a voice coil motor VCM as an example of an actuator.
FIG. 8 is a block diagram illustrating a configuration example of a control circuit that performs PWM drive control of a DC-DC converter.
FIG. 9 is an explanatory diagram showing a configuration example of a filter constituting the control unit as shown in FIG. 5, FIG. 7, and FIG.
FIG. 10 is a block diagram illustrating a configuration example of a PWM modulation circuit.
FIGS. 11A and 11B are circuit diagrams illustrating configuration examples of output driver circuits, respectively.
FIG. 12 is a chart summarizing each component of the control LSI according to the present invention and a method for realizing the component.
FIG. 13 shows a case where the control LSI according to the present invention is used in a control device for driving and controlling a disk rotating spindle motor, an arm moving voice coil motor, and a power source DC-DC converter in a hard disk type magnetic storage device. It is a block diagram which shows the example of a structure of the whole system.
14A is a plan view showing a first embodiment of a substrate of a semiconductor integrated circuit to which the present invention is applied, and FIG. 14B is a sectional view thereof.
FIG. 15 is a plan view showing a second embodiment of the substrate of the semiconductor integrated circuit to which the present invention is applied;
FIG. 16 is a plan view showing a third embodiment of the substrate of the semiconductor integrated circuit to which the present invention is applied;
FIG. 17 is a plan view of a wafer showing a fourth embodiment of a substrate of a semiconductor integrated circuit to which the present invention is applied;
FIG. 18 is a wafer plan view showing a fifth embodiment of a substrate of a semiconductor integrated circuit to which the present invention is applied;
FIG. 19 is an explanatory cross-sectional view showing the steps of the first manufacturing method of the wafer for forming the semiconductor integrated circuit of the example in the order of steps.
FIG. 20 is a cross-sectional explanatory view showing the steps of the second manufacturing method of the wafer for forming the semiconductor integrated circuit of the example in order of processes.
FIG. 21 is an explanatory cross-sectional view showing the steps of the third manufacturing method of the wafer for forming the semiconductor integrated circuit of the example in order of steps.
22 is an explanatory cross-sectional view showing the steps of the fourth manufacturing method of the wafer for forming the semiconductor integrated circuit of the example in order of processes. FIG.
23A is a plan view showing a configuration example of a substrate of a semiconductor integrated circuit having a conventional high breakdown voltage, high output transistor, and FIG. 23B is a cross-sectional view thereof.
[Explanation of symbols]
100 Semiconductor integrated circuit for control (control LSI)
111-117 channels (PWM modulation circuit & output driver circuit)
110 Output driver circuit
121, 123, 125 Current detection amplifier
122, 124, 126 Voltage detection amplifier
130 AD converter circuit
140 Bus
151-153 Output control circuit
160 Channel selector
171 Serial port
172 parallel port
173 DPS (Programmable arithmetic circuit)
175 Sequence control unit
176 Registers
300 magnetic disk
310 spindle motor
320 arms
340 Voice coil motor
PWM1 to PWM7 PWM modulation circuit
DRV1 to DRV7 output driver circuit
Rs1 to Rs3 Current sensing resistors

Claims (23)

A plurality of sets of PWM modulation circuits and output driver circuits driven by PWM control pulses generated by the PWM modulation circuits; a programmable arithmetic circuit capable of executing arbitrary arithmetic processing by a program loaded from the outside; A programmable sequence control circuit for generating a control signal for operating the arithmetic circuit and the channel in an arbitrary procedure by an externally loaded program, a port for reading the program, and a memory for storing the read program A control semiconductor integrated circuit. The control semiconductor according to claim 1, further comprising: a bus connected to the arithmetic circuit and the sequence control circuit; and a plurality of registers connected to the bus and capable of holding an arithmetic result in the arithmetic circuit. Integrated circuit. 3. The control semiconductor integrated circuit according to claim 1, wherein the memory is a writable nonvolatile memory. 4. The control semiconductor integrated circuit according to claim 1, further comprising a plurality of current detection means for detecting a current flowing in the output driver circuit or a load means driven by the output driver circuit. 5. The control semiconductor integrated circuit according to claim 4, further comprising an AD conversion circuit that converts a current value detected by the current detection means into a digital value. 6. The control semiconductor integrated circuit according to claim 5, further comprising switching means for converting the current values detected by the plurality of current detection means into digital values in a time division manner by the AD conversion circuit. 7. The control semiconductor integrated circuit according to claim 1, further comprising an output control circuit including a dedicated circuit for driving and controlling a predetermined load means. The output control circuit includes a plurality of output control circuits, and one of the output control circuits includes a dedicated circuit constituting a part of a control circuit for PWM driving control of a three-phase brushless motor. A control semiconductor integrated circuit. The dedicated circuit includes a current reproduction circuit that reproduces a current flowing through each coil of the three-phase brushless motor based on the current detected by the current detection unit, and a coordinate conversion that converts a signal of orthogonal coordinates and a signal of polar coordinates. 9. The control semiconductor integrated circuit according to claim 8, wherein the control semiconductor integrated circuit is a circuit. 10. The control semiconductor integrated circuit according to claim 9, wherein the current reproduction circuit is configured by a variable logic circuit or a custom logic circuit capable of configuring an arbitrary logic. 11. The control semiconductor integrated circuit according to claim 7, further comprising selection means for connecting the output control circuit to a set of an arbitrary PWM modulation circuit and output driver circuit. 11. The control semiconductor integrated circuit according to claim 10, wherein the selection means is controlled by a signal from the sequence control circuit. 13. The control semiconductor integrated circuit according to claim 1, wherein the arithmetic circuit is a digital signal processor. 14. The control semiconductor integrated circuit according to claim 1, wherein the output driver circuit includes a power transistor that causes a drive current to flow to a load unit connected to an external terminal. 15. The semiconductor integrated circuit for control according to claim 1, a spindle motor that rotationally drives a magnetic storage disk, and a magnetic head that reads / writes information from / to a storage track on the magnetic storage disk; And a voice coil motor for moving the magnetic head on the magnetic storage disk, and the spindle motor and the voice coil motor are configured to be driven and controlled by the control semiconductor integrated circuit. A magnetic disk storage device. 16. The magnetic disk storage device according to claim 15, further comprising a voltage conversion coil, wherein the coil is configured to generate a DC voltage when a switching current is passed by the control semiconductor integrated circuit. apparatus. One surface of the semiconductor substrate has a first element formation region and a second element formation region which are electrically separated from each other by an isolation band made of an insulator, and the first element formation region has a buried insulating layer The second element formation region is formed so that at least one side thereof extends to the edge of the semiconductor substrate, and no buried insulating layer is formed in the second element formation region. A semiconductor integrated circuit, characterized in that a transistor element is formed in which a larger current flows than a transistor element formed in the element forming region. The separation band for electrically separating the first element formation region and the second element formation region is formed to form a polygon or a part of a circle on one surface of the semiconductor substrate. The semiconductor integrated circuit according to claim 17, characterized in that: 19. The semiconductor integrated circuit according to claim 17, wherein the first element formation region is surrounded by the isolation band. 20. The semiconductor integrated circuit according to claim 19, wherein a lower end of the separation band is in contact with the buried insulating layer. 21. A second isolation band is formed in the second element forming region so as to surround a transistor element formed in the second element forming region. The semiconductor integrated circuit as described. The semiconductor integrated circuit according to claim 21, wherein a lower end of the second separation band is not in contact with the buried insulating layer. 23. The semiconductor integrated circuit according to claim 17, wherein a plurality of the second element formation regions are formed on one semiconductor substrate.

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