JP2005065135A - Driver circuit and method for initiating gain control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an overshoot from occurring in an output when initiating a built-in gain control circuit, without increasing power consumption. <P>SOLUTION: After an internal control voltage 200 which controls a gain of a gain control circuit 10 reaches a setting value, a bias voltage 202 which operates the gain control circuit 10, reaches a setting value, and a time until returning the bias voltage 202 which becomes the setting value, to an initial value is set shorter relatively to a time for allowing the bias voltage 202 reaching the setting value from its initial value. Therefore, the gain control circuit 10 can be turned into an active state by the bias voltage 202 after its gain is set by the internal control voltage 200, thereby eliminating the occurrence of the overshoot caused by a change of the gain from an output 400 of the gain control circuit 10. Further, the gain control circuit 10 is turned on and off as needed, so that power consumption does not increase. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a driver circuit for a transmission power amplifier such as a radio transmitter, and more particularly to a method for starting a gain control circuit that prevents overshoot from occurring when a gain control circuit constituting the driver circuit is started.

  FIG. 7 is a block diagram showing a configuration example of a conventional driver circuit. The driver circuit generates a reference voltage generation circuit 52 that generates a reference voltage based on an on / off signal 100 input from the outside, a reference voltage output from the reference voltage generation circuit 52, and an external control voltage 102 input from the outside. An internal control voltage generation circuit 54 that generates an internal control voltage 200 based on the reference voltage, a bias voltage generation circuit 56 that generates a bias voltage 202 based on a reference voltage output from the reference voltage generation circuit 52, and an input signal 300 input from the outside And a gain control circuit 60 that amplifies the output of the fixed gain circuit 58 with variable gain (see, for example, Patent Document 1).

  Next, the operation of the conventional driver circuit will be described with reference to the operation waveform diagram of FIG. When a signal 100 for turning on the gain control circuit 60 from the outside is input at time T0 as shown in FIG. 8A, the reference voltage generated by the reference voltage generation circuit 52 is as shown in FIG. 8B. Since the predetermined reference voltage is reached at time T1, the internal control voltage generation circuit 54 starts the operation of generating the internal control voltage 200 as shown in FIG. 8C, and the bias voltage generation circuit 56 operates as shown in FIG. The operation for generating the bias voltage 202 is started as shown in FIG. When the ON signal 100 is input, an external control voltage 102 that sets the gain of the gain control circuit 60 is input to the internal control voltage generation circuit 54.

  Here, the internal control voltage 200 generated when the internal control voltage generation circuit 54 is started is high, and then falls to the set voltage specified by the external control voltage 102. For this reason, the internal control voltage 200 generated by the internal control voltage generation circuit 54 falls at the gradient P, and reaches the set value at the time T3.

During this time, the bias voltage 202 generated from the bias voltage generation circuit 56 rises at the gradient Q and reaches the set value at time T2. For this reason, the fixed gain circuit 58 and the gain control circuit 60 become operable at the time T2, and the gain control circuit 60 is started before the internal control voltage 200 reaches the set value. As a result, the gain control circuit 60 initially operates at a gain higher than the gain specified by the external control voltage 102. Thereafter, when the internal control voltage 200 reaches a predetermined value at time T3, the gain control circuit 60 specifies the gain. As shown in FIG. 8E, overshoot due to a change in gain during operation occurs at the output (OUTPUT) 400 of the gain control circuit 60 between times T2 and T3.
JP 2001-196872 A (page 3-4, FIG. 1)

  As described above, in the driver circuit including the conventional gain control circuit 60, overshoot occurs when the gain control circuit 60 is started, and this becomes an unnecessary radio wave level radiation that becomes noise. On the other hand, for example, in the W-CDMA mobile phone, the overshoot as the ON / OFF characteristic of Transmit in 3GPP (3rd Generation Partnership Project) is standardized to ± 0.5 dB, and unnecessary radio wave level radiation is generated. Suppressed. In order to satisfy this standard, it is necessary to take measures such as turning on only the gain control circuit 60 in advance on the terminal set side. However, this has a problem that power consumption increases.

  The present invention has been devised in view of the above circumstances, and an object of the present invention is to prevent overshoot from occurring at the output of a built-in gain control circuit without increasing power consumption. It is an object of the present invention to provide a driver circuit and a method for starting up a gain control circuit.

  In order to achieve the above object, the present invention makes a gain control circuit that amplifies an input signal with a set gain, control voltage generation means for generating a control voltage for setting the gain, and makes the gain control circuit operable. A bias voltage generating means for generating a bias voltage, and a bias voltage generated by the bias voltage generating means reaches a set value after the control voltage generated by the control voltage generating means reaches a set value. And setting means for setting the time for the bias voltage to reach a set value from an initial value and the time for the control voltage to reach a set value different from each other.

  The present invention also provides a gain control circuit for amplifying an input signal with a set gain, control voltage generating means for generating a control voltage for setting the gain, and a bias voltage for operating the gain control circuit. The bias voltage generating means that sets the bias voltage generated by the bias voltage generating means to be different from the time until the bias voltage reaching the set value from the initial value returns to the initial value. And setting means.

  A method for starting a gain control circuit for amplifying an input signal with variable gain, wherein a rise time of a control voltage for setting a gain of the gain control circuit is shorter than a rise time of a bias voltage for operating the gain control circuit. In addition, the falling time of the bias voltage is shorter than the rising time.

  As described above, the driver circuit of the present invention is configured so that the bias voltage generated by the bias voltage generating means reaches the set value after the control voltage generated by the control voltage generating means reaches the set value. After the gain of the gain control circuit is set with the control voltage, the gain control circuit starts operation by inputting the bias voltage of the set value, so that the gain may change after the gain control circuit operates. Thus, it is possible to eliminate the occurrence of overshoot due to a change in gain at the output of the gain control circuit. In addition, the gain until the bias voltage that has reached the set value returns to the initial value is set shorter than the time from the initial value of the bias voltage generated by the bias voltage generating means to the set value. Even when the time from when the control circuit is turned off to when it is short, the bias voltage rises from a sufficiently lowered level, so that it takes a long time to reach the set value. As a result, since the bias voltage reaches the set value after the control voltage reaches the set value, the gain does not change after the gain control circuit operates, and an overshoot occurs in the output. Can be eliminated.

As described above in detail, according to the present invention, after the internal control voltage for controlling the gain of the gain control circuit reaches the set value, the bias voltage for operating the gain control circuit reaches the set value. Thus, since the gain control circuit operates after the gain of the gain control circuit is set, it is possible to eliminate the occurrence of overshoot due to a change in gain during operation from the output of the gain control circuit.
Furthermore, the time from the turn-off to the turn-on of the driver circuit is set by shortening the time until the bias voltage that has reached the set value returns to the initial value with respect to the time from the initial value of the bias voltage to the set value. Even if is short, the bias voltage rises from a sufficiently lowered level, so it takes a long time to reach the set value. It is possible to eliminate the occurrence of overshoot due to a change in gain during operation from the output of the gain control circuit, and in any case, it is possible to prevent overshoot from occurring in the output of the gain control circuit.
Accordingly, terminal design measures such as a W-CDMA mobile phone that always operates the gain control circuit are not necessary, and the gain control circuit only needs to be operated when necessary, without increasing power consumption. The above effects can be obtained.

  After the internal control voltage that controls the gain of the gain control circuit reaches the set value, the purpose is to prevent overshoot from occurring at the output of the gain control circuit built in the driver circuit without increasing the power consumption. The bias voltage for operating the gain control circuit reaches the set value, and the bias voltage that has become the set value is longer than the time until the bias voltage reaches the set value from the initial value until the bias voltage returns to the initial value. This was achieved by setting the time to be shorter.

  FIG. 1 is a block diagram showing the configuration of the driver circuit according to the first embodiment of the present invention. The driver circuit 80 includes a reference voltage generation circuit 2 that generates a reference voltage based on an on / off signal 100 input from the outside, a reference voltage output from the reference voltage generation circuit 2, and an external control voltage input from the outside An internal control voltage generation circuit 4 that generates an internal control voltage 200 based on 102, and a bias voltage 202 that operates the fixed gain circuit 8 and the gain control circuit 10 based on the reference voltage output from the reference voltage generation circuit 2 are generated. And a gain control circuit 10 that amplifies the output of the fixed gain circuit 8 with a variable gain. The However, the claimed gain control circuit corresponds to the gain control circuit 10, the control voltage generation means corresponds to the internal control voltage generation circuit 4, and the bias voltage generation means corresponds to the bias voltage generation circuit 6.

  FIG. 2 is a circuit diagram showing a configuration of the bias voltage generation circuit 6 shown in FIG. The bias voltage generation circuit 6 includes a pair of P-type MOS transistors (hereinafter simply referred to as transistors) in which a resistor S1 and a resistor R2 that form a voltage dividing circuit that divides a reference voltage input from an input terminal 18 and a source S are connected in common. TR1, TR2, N-type MOS transistor (hereinafter simply referred to as transistor) TR3 connected to the drain D of the transistor TR1, and the drain D of the transistor TR2 and the drain D and the gate G are connected in common. , An N-type MOS transistor (hereinafter simply referred to as a transistor) TR4 that forms a current mirror circuit with the transistor TR3, a current source 12 that connects between the sources S of the transistors TR1 and TR2 and the power supply voltage VDD, and the transistors TR1 and TR3. Gate G is connected to the connection point, An N-type MOS transistor (hereinafter simply referred to as a transistor) TR5 in which the rain D is connected to the power supply voltage VDD via the current source 14 and the source S is connected to VSS (for example, ground potential), and the drain D of the transistor TR5 An N-type MOS transistor (hereinafter simply referred to as a transistor) TR6 in which the gate G is connected to the connection point of the current source 14, the drain D is connected to the power supply voltage VDD, and the source S is connected to VSS via the resistor R3. Have.

Further, the gate G of the transistor TR1 is connected to the connection point of the resistors R1 and R2 forming the voltage dividing circuit, the gate G of the transistor TR2 is connected to the source S of the transistor TR6, and the sources S of the transistors TR3 and TR4. Is connected to VSS. Further, a phase compensation capacitor C is connected between the drain D and the gate G of the transistor TR5. Further, the reference voltage is input from the input terminal 18 connected to the other end of the resistor R1 forming the voltage dividing circuit, the power supply voltage VDD is input from the input terminal 16, and the ground voltage VSS is input from the input terminal 20. still,
In this embodiment, the capacity of the phase compensation capacitor C is made larger than that of the conventional one. However, the setting means in the claims corresponds to the phase compensation capacitor C, the voltage dividing circuit corresponds to the resistors R1 and R2, the first transistor corresponds to the transistor TR6, and the predetermined voltage generation circuit corresponds to the transistors TR1 to TR1. The second transistor corresponds to TR4 and the current source 12, and the second transistor corresponds to the transistor TR5.

  Next, the operation of the present embodiment will be described with reference to the operation waveform diagram of FIG. When a signal 100 for turning on the gain control circuit 10 from the outside is input at time T0 in FIG. 3A, the reference voltage generated by the reference voltage generation circuit 2 is at time T1 as shown in FIG. 3B. A predetermined reference voltage is reached, and this reference voltage is input from the input terminal 18 of FIG. 2, and the bias voltage generation circuit 6 starts the operation of generating the bias voltage 202 as shown in FIG. At the same time that the bias voltage generation circuit 6 starts the operation of generating the bias voltage 202, the internal control voltage generation circuit 4 starts the operation of generating the internal control voltage 200 as shown in FIG. At this time, the external control voltage 102 for setting the gain of the gain control circuit 10 is input to the internal control voltage generation circuit 4.

  Immediately before the reference voltage is input to the bias voltage generation circuit 6, the current sources 12 and 14 are not operating, the transistors TR1 to TR6 are off, and the bias voltage 202, which is the source voltage of the transistor TR6, is also an initial value. It is low.

  When the reference voltage is input from the input terminal 18 at time T1, the reference voltage is divided by the resistors R1 and R2 and applied to the gate G of the transistor TR1, and a current flows through the transistors TR1 and TR3. A current flows through the transistor TR4. Further, since the current sources 12 and 14 also start to operate together with the input of the reference voltage, the source voltage of the transistor TR6, that is, the bias voltage 202 also starts to rise from time T1.

  The transistor TR3 and the transistor TR4 form a current mirror, and the same current as the current flowing through the transistor TR3 (TR3 and TR4 have the same size) flows through the transistor TR4. The gate voltage of the transistor TR2 (source voltage of the transistor TR6) is determined so as to flow through TR4. In this case, the gate voltage is a divided voltage by the resistors R1 and R2.

  Therefore, a current must flow through the transistors TR6 and TR5 so that the gate voltage of the transistor TR2 becomes a divided voltage, and the voltage at the connection point between the transistors TR1 and TR3 is determined so as to be like this. A voltage is applied to the gate G of the transistor TR5.

  At this time, since the phase compensation capacitor C is connected between the drain D and the gate G of the transistor TR5, a charging current for charging the phase compensation capacitor C flows from the connection point between the transistors TR1 and TR3. At the time when the capacitor C is charged and the gate voltage of the transistor TR5 reaches a predetermined value, that is, at time T3, the source voltage of the transistor TR6, that is, the bias voltage 202 also becomes a set value.

  Therefore, the bias voltage 202 rises from the time T1 to the time T3 with a gradient as shown in FIG. This time point is a time point T3 shown in FIG. 3D (for example, 5 μs after time T0). In this embodiment, since the capacitance of the phase compensation capacitor C is increased, the charging time of the phase compensation capacitor C is long, and accordingly, the time until the gate voltage of the transistor TR5 reaches a predetermined value becomes long. For this reason, the rising gradient of the bias voltage 202 from time T1 to time T3 decreases, and the time until the set value is reached increases. In order to lengthen the charging time of the phase compensation capacitor C, the phase compensation capacitor C may have the same capacity as the conventional one and the charging current may be reduced. However, in this example, the capacity is increased.

  In addition to the operation of the bias voltage generation circuit 6, the internal control voltage generation circuit 4 operates to generate the internal control voltage 200 from time T1 in FIG. 3C. The internal control voltage 200 decreases from the initial value. Then, the set value is reached and stabilized at time T2. Since the descending gradient of the internal control voltage 200 is the same as before, the bias voltage 202 reaches the set value after the internal control voltage 200 reaches the set value and stabilizes. Therefore, the bias voltage 202 reaches the set value and the gain control circuit 10 starts to operate from time T3. At this time, the internal control voltage 200 has already reached the set value and is stable, so that the gain control circuit 10 The gain is a value corresponding to the set value of the internal control voltage 200 from the beginning, and no overshoot occurs in the output (Output) 400 of the gain control circuit 10 as shown in FIG.

  According to the present embodiment, when the driver circuit 80 is switched from OFF to ON, the rising slope of the bias voltage 202 generated from the bias voltage generation circuit 6 is reduced, thereby reducing the internal control voltage generated from the internal control voltage generation circuit 4. Since the gain voltage does not change during the operation of the gain control circuit 10 by operating the gain control circuit 10 when the bias voltage 202 reaches the set value after the control voltage 200 reaches the set value and stabilizes, the gain control is performed. It is possible to prevent an overshoot from occurring in the output 400 of the circuit 10, and it is possible to eliminate unnecessary radio wave level radiation due to the overshoot. In the present embodiment, since the gain control circuit 10 is operated only when the driver circuit 80 is operated, the above effect can be obtained without increasing the power consumption.

  4A and 4B are a plan view and a cross-sectional view showing the configuration of the phase compensation capacitor included in the bias voltage generation circuit according to the second embodiment of the present invention. However, since the configuration of this example is the same as that of the first embodiment described above, the description of the configuration operation of each unit having the same configuration is omitted, and the characteristic part of the operation is described below. .

  In the first embodiment described above, the capacitance of the phase compensation capacitor C of the bias voltage generation circuit 6 is increased to reduce the rising gradient of the bias voltage 202 when the driver circuit 80 is turned on. Even when the circuit 80 is turned off (time T4 in FIG. 3), the discharge time from the phase compensation capacitor C becomes longer, the descending gradient of the bias voltage 202 becomes smaller, and the driver does not decrease the bias voltage 202 so much. When the circuit 80 is turned on (time T6 in FIG. 3), the bias voltage 202 reaches the set value before the time when the internal control voltage 200 generated from the internal control voltage generation circuit 4 reaches the set value (time T9 in FIG. 3). 3 (time T8 in FIG. 3), an overshoot occurs in the output 400 of the gain control amplifier 10 as shown in FIG. 3E (FIG. 3). Time T8 from T9), it could not be completely eliminated overshoot generated in the output 400 of the gain control amplifier 10.

  Therefore, in this embodiment, in order to prevent overshoot from occurring in the output 400 of the gain control amplifier 10 even in the above case, the phase compensation capacitor C connected to the transistor TR5 of the bias voltage generation circuit 6 is used. And the gate G of the transistor TR5 have a predetermined relationship, which will be described later, so that the rising gradient of the bias voltage 202 generated by the operation of the bias voltage generation circuit 6 is reduced, and the bias voltage generation circuit 6 It is different from the first embodiment in that the occurrence of the overshoot is completely eliminated by increasing the descending gradient when the bias voltage 202 is lowered and the bias voltage 202 is lowered. Other configurations and operations are the same as the first embodiment. This is the same as the embodiment.

  The phase compensation capacitor C shown in FIG. 4 connects between the gate G and the drain D of the transistor TR5. FIG. 4 (A) is a plan view thereof, and FIG. 4 (B) is its P-P sectional view. Show. In FIG. 4A, the phase compensation capacitor C includes a plate-like wide Al electrode 32 and an Al electrode 34 disposed in a notch portion of the electrode 32 so as to be electrically separated from the Al electrode 32. And have.

  In FIG. 4B, the phase compensation capacitor C is formed on the inner side of the N-type epitaxial layer 38 formed on the P-type substrate 36 and from the surface of the N-type epitaxial layer 38. An emitter diffusion region 40, an oxide film 42 stacked on the surface of the emitter diffusion region 40 and the epitaxial layer 38, and an Al electrode 32 and an Al electrode 34 disposed on the oxide film 42, are formed. A capacitance is formed between the region 40 and the Al electrode 32. In addition, the gate side end of the transistor TR 5 in the emitter diffusion region 40 is connected to the Al electrode 34 by the Al conductor portion 44. Although not shown, the gate G of the transistor TR5 is formed on the left side of the P-type substrate 36 in FIG. However, the semiconductor layer in the claims corresponds to the N type epitaxial layer 38, the emitter diffusion region corresponds to the emitter diffusion region 40, the conductive member as the first electrode corresponds to the Al electrode 32, and the second The electrode corresponds to the Al electrode 34, and the conductive path corresponds to the Al conductor portion 44.

  FIG. 5A is a circuit diagram showing an equivalent circuit of the phase compensation capacitor C shown in FIG. A circuit in which a capacitor C1 to the substrate is connected between the terminal 46 and the ground potential and an actual capacitor C2 is connected between the terminal 46 and the terminal 48 is obtained. The terminal 46 corresponds to the Al electrode 34, and the terminal 48 corresponds to the Al electrode 32. The terminal 46 is connected to the gate G of the transistor TR5, and the terminal 48 is connected to the drain D of the transistor TR5.

  The equivalent circuit is such that the Al electrode 34 is drawn from the gate side end of the transistor TR5 in the emitter diffusion region 40 through the Al conductor 44 in FIG. Conversely, when the Al electrode 34 is drawn out from the end of the emitter diffusion region 40 opposite to the transistor TR5 via the Al conductor portion, the equivalent circuit is as shown in FIG. ) Will be different.

  Next, the operation of the present embodiment will be described with reference to the operation waveform diagram of FIG. As shown in FIG. 6A, even when the signal 100 for turning on / off the driver circuit 80 is turned on at time T0, the current sources 12 and 14 operate immediately before the reference voltage is input to the bias voltage generating circuit 6. The transistors TR1 to TR6 are off, and the bias voltage 202, which is the source voltage of the transistor TR6, is also low at the initial value.

  As shown in FIG. 6B, when the reference voltage rises at time T1 and this reference voltage is input from the input terminal 18 to the bias voltage generation circuit 6 at time T1, the reference voltage is divided by the resistors R1 and R2. And applied to the gate G of the transistor TR1, the transistors TR1 to TR4 operate, and the current sources 12 and 14 start to operate together with the input of the reference voltage. Therefore, as shown in FIG. The source voltage, that is, the bias voltage 202 also starts to rise from the initial value. At the same time, as shown in FIG. 6C, the internal control voltage 200 generated from the internal control voltage generation circuit 4 also starts to decrease from the initial value.

  The transistor TR3 and the transistor TR4 form a current mirror, and the same current as the current flowing through the transistor TR3 (TR3 and TR4 have the same size) flows through the transistor TR4. The gate voltage of the transistor TR2 (source voltage of the transistor TR6) is determined so as to flow through TR4. In this case, the gate voltage is a divided voltage by the resistors R1 and R2.

  Therefore, the gate voltage is supplied from the connection point of the transistors TR1 and TR3 to the gate G of the transistor TR5 so that the gate voltage of the transistor TR2 becomes a divided voltage. At this time, the phase compensation capacitor C is charged. When the charging current flows and the capacitor C is charged, the gate voltage of the transistor TR5 becomes a predetermined value, and the source voltage of the transistor TR6, that is, the bias voltage 202 is also set as shown in FIG. 6D at time T3. Value. At this time, as shown in FIG. 6C, the internal control voltage 200 generated from the internal control voltage generation circuit 4 is already set at the time T2, so as shown in FIG. The variable gain circuit 10 operates at a stable gain specified by the external control voltage 102, and its output 400 becomes high level.

  The operation for charging the phase compensation capacitor C will be described with reference to the equivalent circuit of FIG. 5A. The capacitors C1 and C2 must be charged, and the current for charging the capacitor C2 is reduced. The time until the charging is completed becomes longer, and the time until the gate voltage of the transistor TR5 reaches a predetermined value becomes longer. Therefore, as shown in FIG. 6D, the time until the bias voltage 202 reaches the set value is long, and when the bias voltage 202 reaches the set value, the internal control voltage 200 output from the internal control voltage generation circuit 4 has already been reached. Since the set value has been reached at time T2, no overshoot occurs in the output 400 of the gain control circuit 10, as shown in FIG.

  Next, as shown in FIG. 6A, when the signal 100 for turning on / off the driver circuit 80 is turned off at time T4 and then turned on immediately at time T6, the reference is made at time T5 in FIG. 6B. When the voltage reaches the initial value, as shown in FIGS. 6C and 6D, the internal control voltage 200 starts to increase from the set value, and the bias voltage 202 starts to decrease from the set value. In this case, when the gate voltage of the transistor TR5 disappears, that is, when the phase compensation capacitor C is discharged at time T7, the source voltage of the transistor TR6, that is, the bias voltage 202 also returns to the initial value.

  The discharging operation of the phase compensation capacitor C will be described with reference to the equivalent circuit of FIG. 5A. Since the capacitors C1 and C2 are discharged in a state of being connected in series, the discharge current is large and the phase compensation capacitor C2 is discharged. The discharge time is shorter than the charge time. Therefore, when the driver circuit 80 is turned off, the descending gradient at which the bias voltage 202 returns to the initial value increases, and the bias voltage 202 returns from the set value to the initial value in a short time. Accordingly, when the on / off signal 100 in FIG. 6A is turned on again at time T6 and the internal control voltage 200 starts decreasing at the time T8 and the bias voltage 202 starts increasing simultaneously, the bias voltage 202 is sufficient. It is descending and it takes a long time to reach the set value because it starts to rise from the initial value. Therefore, since the internal control voltage 200 has already reached the set value at time T9 when the bias voltage 202 has reached the set value, the output of the gain control circuit 10 at time T9 as shown in FIG. 6 (E). No overshoot occurs at 400.

  When the electrode is drawn from the end of the phase compensation capacitor C in the direction opposite to the gate G of the transistor TR5 in the emitter diffusion region 40, the equivalent circuit is as shown in FIG. Since the discharge time becomes longer, an operation reverse to the above occurs and the occurrence of overshoot cannot be prevented.

  According to the present embodiment, the rise of the bias voltage 202 is slowed when the driver circuit 80 is turned on, and the fall of the bias voltage 202 is made sharp when the driver circuit 80 is turned off. In particular, it is possible to prevent an overshoot from occurring in the output 400 of the voltage control circuit 10 even when the OFF and ON periods of the driver circuit 80 are short. Even if it is used in the front stage of the transmission power amplifier circuit of a mobile phone, the Transmit ON / OFF characteristic standard in 3GPP (3rd Generation Partnership Project) can be cleared. In addition, since the above effect can be obtained without an increase in power consumption, the battery life of the mobile phone can be extended.

  In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can implement also with another various form in a concrete structure, a function, an effect | action, and an effect. In the above embodiment, the rise time and the fall time of the bias voltage 202 of the bias voltage generation circuit 6 are different, but the fall time of the internal control voltage 200 of the internal control voltage generation circuit 4 is compared with the rise time. By shortening, adjustment may be performed such that the internal control voltage 200 reaches the set value before the bias voltage 202 reaches the set value, or both the bias voltage 202 and the internal control voltage 200 rise. The same effect can be obtained by adjusting the fall time.

  The bias voltage generation circuit of the above embodiment is assumed to be composed of a MOS transistor. However, even if it is composed of a bipolar transistor, the same effect can be obtained with the same structure as that of the above embodiment.

  Furthermore, the present embodiment is premised on use as a driver circuit in front of a transmission power amplifier for a mobile phone. However, if the device does not want to generate an overshoot when the driver circuit is on, the present embodiment The same effect can be obtained by using the driver circuit in the form as a triber stage of various devices.

It is the block diagram which showed the structure of the driver circuit based on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram showing a configuration of a bias voltage generation circuit 6 shown in FIG. 1. FIG. 4 is an operation waveform diagram illustrating an operation of the driver circuit according to the first embodiment. It is the top view and sectional drawing which showed the structure of the capacitor for phase compensation contained in the bias voltage generation circuit which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing an equivalent circuit of the capacitor C shown in FIG. 4. FIG. 10 is an operation waveform diagram illustrating an operation of the driver circuit according to the second embodiment. It is the block diagram which showed the structural example of the conventional driver circuit. It is an operation | movement waveform diagram which showed operation | movement of the conventional driver circuit.

Explanation of symbols

2 ... Reference voltage generation circuit, 4 ... Internal control voltage generation circuit, 6 ... Bias voltage generation circuit, 8 ... Fixed gain circuit, 10 ... Gain control circuit, 12, 14 ... Current source, 16, 18 , 20... Input terminal, 32, 34... Al electrode, 36... P-type substrate, 38... N-type epitaxial layer, 40. , 80... Driver circuit, C... Phase compensation capacitor, C1 .. capacitance to substrate, C2... Actual capacitance, R1 to R3... Resistor, TR1 to TR6.

Claims (10)

A gain control circuit for amplifying an input signal with a set gain;
Control voltage generating means for generating a control voltage for setting the gain;
A bias voltage generating means for generating a bias voltage for operating the gain control circuit; and a bias voltage generated by the bias voltage generating means after the control voltage generated by the control voltage generating means reaches a set value. Setting means for setting the time until the bias voltage reaches the set value from the initial value and the time until the control voltage reaches the set value from the initial value so that the bias voltage reaches the set value,
A driver circuit comprising:   2. The driver circuit according to claim 1, wherein the setting means sets a time until the bias voltage reaches a set value from an initial value longer than a time until the control voltage reaches a set value from the initial value. .   The bias voltage generating means includes a voltage dividing circuit that divides a reference voltage inputted from the outside, a first transistor for output that outputs the bias voltage, and an output point of the bias voltage of the first transistor. A predetermined voltage generating circuit that sets a voltage to a predetermined voltage corresponding to the divided voltage divided by the voltage dividing circuit; and a gate voltage supplied from the predetermined voltage generating circuit causes the output point of the first transistor to be a predetermined voltage. A second transistor for controlling the current flowing through the first transistor so that the setting means is a phase compensation capacitor for compensating the phase of the second transistor. The driver circuit according to claim 1. A gain control circuit for amplifying an input signal with a set gain;
Control voltage generating means for generating a control voltage for setting the gain;
A bias voltage generating means for generating a bias voltage for operating the gain control circuit; a time until the bias voltage generated by the bias voltage generating means reaches a set value from an initial value; A setting means for setting different times until the value returns to the initial value,
A driver circuit comprising:   5. The driver according to claim 4, wherein the setting means sets the time until the bias voltage reaches the set value from the initial value longer than the time until the bias voltage that has reached the set value returns to the initial value. circuit.   The said setting means sets the time until the said bias voltage reaches a setting value from an initial value longer than the time until the said control voltage reaches a setting value from an initial value, The Claim 4 or 5 characterized by the above-mentioned. Driver circuit.   The bias voltage generating means includes a voltage dividing circuit that divides a reference voltage inputted from the outside, a first transistor for output that outputs the bias voltage, and an output point of the bias voltage of the first transistor. A predetermined voltage generating circuit that sets a voltage to a predetermined voltage corresponding to the divided voltage divided by the voltage dividing circuit; and a gate voltage supplied from the predetermined voltage generating circuit causes the output point of the first transistor to be a predetermined voltage. A second transistor for controlling the current flowing through the first transistor so that the setting means is a phase compensation capacitor for compensating the phase of the second transistor. The driver circuit according to claim 4. The phase compensation capacitor includes an emitter diffusion region formed from the surface of the semiconductor layer adjacent to the semiconductor layer in which the bias voltage generating means is formed to the inside, and an insulating layer on the surface of the semiconductor layer. A capacitor is formed between the first electrode and the conductive member that is laminated,
An end of the emitter diffusion region having a predetermined positional relationship with respect to a gate side of the second transistor is connected to a second electrode formed on the surface of the insulating layer through a conductive path. The driver circuit according to claim 7.   9. The end of the emitter diffusion region adjacent to the gate side of the second transistor is connected to a second electrode formed on the surface of the insulating layer through a conductive path. Driver circuit. A method of starting a gain control circuit that amplifies an input signal with variable gain,
The rise time of the control voltage for setting the gain of the gain control circuit is made shorter than the rise time of the bias voltage for operating the gain control circuit, and the fall time of the bias voltage is made shorter than the rise time. To start the gain control circuit.

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