JP2005065060A - Semiconductor switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor switching circuit with large withstanding input power, low insert loss, and high isolation. <P>SOLUTION: A first capacitor 108 is connected between a drain and a gate of a first MOSFET 103 included in a first switch element 11, while a second capacitor 109 is connected between a source and a gate of a second MOSFET 104. A third capacitor 115 is connected between a drain and a gate of a third MOSFET 110 included in a second switching element 12, while a fourth capacitor 114 is connected between a source and gate of a fourth MOSFET 111. These capacitors 108, 109, 115 and 116 are set below a parasitic capacity between the gate and the drain or the parasitic capacity between the gate and the source while each MOSFET connected with the capacitor is put in an off state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor switch circuit used for switching a high-frequency signal, and more particularly to a semiconductor switch circuit that is intended to reduce insertion loss and improve isolation characteristics.

  Conventionally, as this type of circuit, for example, a circuit having the configuration shown in FIG. 5 is publicly known. Hereinafter, the conventional circuit will be described with reference to FIG. 1. The semiconductor switch circuit includes first and second field effect transistors 103, 102 connected in series between first and second high frequency terminals 101, 102, respectively. A first switch element 11 having 104 as a main component, and a second switch element 12 having field effect transistors 110 and 111 connected in series between the second high-frequency terminal 102 and the ground as a main component; It is comprised and comprises.

  Then, by applying a control voltage higher than the pinch-off voltage of the first and second field effect transistors 103 and 104 to the first control terminal 105, the drain-source between the first and second field effect transistors 103 and 104 is applied. Is applied to the second control terminal 112 by applying a control voltage lower than the pinch-off voltage of the third and fourth field effect transistors 110 and 111 to the second control terminal 112. , 111 have a high impedance between the drain and the source, the first high frequency terminal 101 and the second high frequency terminal 102 can be turned on (hereinafter referred to as “semiconductor switch circuit is turned on”). .

  Further, by applying a control voltage lower than the pinch-off voltage of the first and second field effect transistors 103 and 104 to the first control terminal 105, the drain and source of the first and second field effect transistors 103 and 104 are connected. Is applied to the second control terminal 112 by applying a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 110 and 111 to the second control terminal 112. , 111 having a low impedance between the drain and source, the first high-frequency terminal 101 and the second high-frequency terminal 102 can be turned off (hereinafter referred to as “semiconductor switch circuit is turned off”). .

  Here, when the semiconductor switch circuit is turned off, a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 110 and 111 is applied to the second control terminal 112 to apply the third voltage. In addition, by turning on the fourth field effect transistors 110 and 111, the high-frequency signal input from the first high-frequency terminal 101 regardless of whether the first and second field-effect transistors 103 and 104 are off. However, the electric power leaked without being interrupted by the first and second field effect transistors 103 and 104 is grounded in a high frequency manner, and high isolation between the first and second high frequency terminals 101 and 102 is ensured.

  When a high-frequency signal having a high peak value is input from the first high-frequency terminal 101 when the semiconductor switch circuit having such a configuration is in an off state, the gate potentials of the first and second field-effect transistors 103 and 104 are input. The gate potential of the field effect transistors 110 and 111 becomes higher than the pinch-off voltage due to the voltage amplitude of the input high-frequency signal. As a result, the first and second field effect transistors 103 and 104 are turned on and turned off. Cannot be maintained. In addition, when a high-frequency signal having a high peak value is input from the first high-frequency terminal 101 when the semiconductor switch circuit having such a configuration is in an on state, the third and fourth field effect transistors 110 and 111 The gate potential becomes higher than the pinch-off voltage due to the voltage amplitude of the input high-frequency signal. As a result, the third and fourth field effect transistors 110 and 111 are turned on, and the off state cannot be maintained. That is, in this conventional circuit, the disadvantage is that the output voltage is compressed by the input of a high-frequency signal having a high peak value in any of the field effect transistors, but the output voltage is compressed by turning on the on state, and the distortion characteristics deteriorate. In other words, there is a drawback that the input power resistance characteristic is low.

For this reason, a semiconductor switch circuit having the configuration shown in FIG. 6 has been proposed in order to improve such input power resistance characteristics.
The semiconductor switch circuit will be described below with reference to FIG. Note that the same components as those shown in FIG. 5 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
The conventional circuit shown in FIG. 6 is the same as the conventional circuit shown in FIG. 5 except that the first capacitor is provided between the gate electrode of the first field effect transistor 103 and the first high-frequency terminal 101. 108 is a second capacitor 109 between the gate electrode of the second field-effect transistor 104 and the second high-frequency terminal 102, and a gate capacitor of the third field-effect transistor 110 is connected to the second high-frequency terminal 102. A third capacitor 115 is provided between them, and a fourth capacitor 116 is provided between the gate electrode of the fourth field effect transistor 111 and the ground, respectively.

The capacitance value of the first capacitor 108 is set to be larger than the parasitic capacitance Cgd1 between the gate and the drain of the first field effect transistor 103 and the parasitic capacitance Cgs1 between the gate and the source. The capacitance value of the capacitor 109 is set larger than the gate-source capacitance Cgs1 and the gate-drain parasitic capacitance Cgd1 of the second field effect transistor 104.
Similarly, the capacitance value of the third capacitor 115 is set to be larger than the parasitic capacitance Cgd2 between the gate and the drain of the third field effect transistor 110 and the parasitic capacitance Cgs2 between the gate and the source. The capacitance value of the capacitor 116 is set larger than the gate-source parasitic capacitance Cgs2 and the gate-drain parasitic capacitance Cgd2 of the fourth field effect transistor 111.

In such a configuration, by adding the first and second capacitors 108 and 109, the voltage applied between the gate and drain (or source) of the first and second field effect transistors 103 and 104 by the input power is distributed. The ratio is changed, and the peak voltage applied between the gate and drain (or source) of the first and second field effect transistors 103 and 104 is suppressed, so that the semiconductor switch circuit is turned off. In this case, the anti-input power characteristic is improved.
Similarly, by adding the third and fourth capacitors 115 and 116, the distribution ratio of the voltage applied between the gate and drain (or source) of the third and fourth field effect transistors 110 and 111 by the input power. And the peak voltage applied between the gate and drain (or source) of the third and fourth field effect transistors 110 and 111 is suppressed, so that the semiconductor switch circuit is turned on. In this case, the input power resistance characteristics are improved.
Such a conventional circuit is known and well-known in, for example, Patent Document 1.

Japanese Patent No. 2770846

However, in the latter conventional circuit, the disadvantage of the low input power characteristic in the former conventional circuit can be solved, but the input power leaks through the newly added capacitor, and the semiconductor switch circuit is turned on. However, there is a problem that the conductive state is deteriorated (insertion loss is increased), and the non-conductive state is deteriorated (isolation is deteriorated) in the off state of the semiconductor switch circuit.
The present invention has been made in view of the above circumstances, and provides a semiconductor switch circuit having good input power resistance characteristics, low insertion loss in an on state, and high isolation characteristics in an off state. .

In order to achieve the object of the present invention, a semiconductor switch circuit according to claim 1 of the present application is provided between first and second high-frequency terminals for inputting and outputting a high-frequency signal, and the first and second high-frequency terminals. In the semiconductor switch circuit comprising the first switch element,
The first switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between the first and second high-frequency terminals, and among the plurality of field effect transistors, A capacitor is connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the first high frequency terminal or the second high frequency terminal,
The capacitance values of all the capacitors are set to be equal to or less than the parasitic capacitance value between the gate and the drain in the off state of each field effect transistor to which the capacitor is connected, or the parasitic capacitance value between the gate and the source. It is.
In addition, a semiconductor switch circuit according to claim 2 of the present application includes first and second high-frequency terminals that input and output a high-frequency signal, a first switch element provided between the first and second high-frequency terminals, In a semiconductor switch circuit comprising a second switch element provided between one of the first high-frequency terminal and the second high-frequency terminal and the ground,
The first switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between the first and second high-frequency terminals, and among the plurality of field effect transistors, Capacitors are respectively connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the first high frequency terminal or the second high frequency terminal,
The second switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between one of the first and second high-frequency terminals and the ground. A capacitor is connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the second high-frequency terminal or ground,
The capacitance values of all the capacitors are set to be equal to or less than the parasitic capacitance value between the gate and the drain in the off state of each field effect transistor to which the capacitor is connected, or the parasitic capacitance value between the gate and the source. It is.

  According to the present invention, the capacitance value of the capacitor connected between the gate and the drain of the field effect transistor that forms the path of the high-frequency signal, and between the gate and the source is determined as the parasitic capacitance between the gate and the drain in the off state of the field effect transistor. Value or less than the parasitic capacitance between the gate and source, the amount of power leaking through the capacitor can be reduced, and the insertion loss when the semiconductor switch circuit is in the ON state can be reduced. There is an effect that it is possible to provide a semiconductor switch circuit with high power durability characteristics without suppressing an increase and without causing deterioration of isolation when the semiconductor switch circuit is in an OFF state.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. Further, the same components as those shown in FIG. 6 are denoted by the same reference numerals.
First, a configuration example of a semiconductor switch circuit according to an embodiment of the present invention will be described with reference to FIG.
The semiconductor switch circuit according to the embodiment of the present invention includes first and second field effect transistors 103 and 104 connected in series between the first and second high-frequency terminals 101 and 102 as the main components. The switch element 11 includes a second switch element 12 including the third and fourth field effect transistors 110 and 111 connected in series between the second high-frequency terminal 102 and the ground. This basic configuration is the same as that of the conventional circuit.

  In the first switch element 11, the source electrode of the first field effect transistor 103 and the drain electrode of the second field effect transistor 104 are connected to each other, while the drain electrode of the first field effect transistor 103 is the first electrode. The source electrode of the second field effect transistor 104 is connected to the second high frequency terminal 102, respectively.

The gate electrode of the first field effect transistor 103 is connected to the first high resistor 106, and the gate electrode of the second field effect transistor 104 is connected to the first high resistor 107 through the first high resistor 107. It is connected to the control terminal 105.
And between the 1st high frequency terminal 101 and the gate electrode of the 1st field effect transistor 103, the 1st capacitor 108 is between the 2nd high frequency terminal 102 and the gate electrode of the 2nd field effect transistor 104. A second capacitor 109 is connected between them.

On the other hand, in the second switch element 12, the source electrode of the third field effect transistor 110 and the drain electrode of the fourth field effect transistor 111 are connected to each other, while the drain electrode of the third field effect transistor 110 is connected. Are connected to the second high-frequency terminal 102 and the source electrode of the fourth field effect transistor 111 is connected to the ground.
Further, the gate electrode of the third field effect transistor 110 is connected via the third high resistor 113, and the gate electrode of the fourth field effect transistor 111 is connected via the fourth high resistor 114. 2 connected to the control terminal 112.

Further, a third capacitor 115 is provided between the second high-frequency terminal 102 and the gate electrode of the third field effect transistor 110, and a fourth capacitor is provided between the ground and the gate electrode of the fourth field effect transistor 111. The capacitors 116 are connected to each other.
The capacitance value of the first capacitor 108 is less than or equal to the parasitic capacitance Cgd1 between the gate and the drain in the off state of the first field effect transistor 103, and the capacitance value of the second capacitor 109 is the second field effect transistor. The gate-source parasitic capacitance Cgs1 is set to be equal to or less than the gate-source parasitic capacitance 104 in the OFF state.
The capacitance value of the third capacitor 115 is equal to or less than the parasitic capacitance Cgd2 between the gate and the drain in the off state of the third field effect transistor 110, and the capacitance value of the fourth capacitor 116 is the fourth field effect transistor. The gate-source parasitic capacitance Cgs2 is set to be equal to or less than the gate-source parasitic capacitance 111 in the off state.

  As described above, in the semiconductor switch circuit according to the embodiment of the present invention, the capacitance values of the first to fourth capacitors 108, 109, 115, and 116 are the field effect transistors 103, 104, 110, 111 is different from the conventional circuit in that the parasitic capacitance value between the gate and the drain in the OFF state or the parasitic capacitance value between the gate and the source is set to be equal to or less than the conventional circuit.

  Since the basic operation in such a configuration is the same as that of the conventional circuit, generally speaking, control higher than the pinch-off voltage of the first and second field effect transistors 103 and 104 at the first control terminal 105 will be described. A voltage is applied to make the impedance between the drain and source of the first and second field effect transistors 103 and 104 low, while the third control terminal 112 has the third and fourth field effect transistors 110 and 111 connected to each other. By applying a control voltage lower than the pinch-off voltage so that the drain and source of the third and fourth field effect transistors 110 and 111 have high impedance, the first high frequency terminal 101 and the second high frequency terminal 102 are connected. Is turned on.

  Further, by applying a control voltage lower than the pinch-off voltage of the first and second field effect transistors 103 and 104 to the first control terminal 105, the drain and source of the first and second field effect transistors 103 and 104 are connected. Is applied to the second control terminal 112 by applying a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 110 and 111 to the second control terminal 112. , 111 has a low impedance between the drain and the source so that the first high frequency terminal 101 and the second high frequency terminal 102 are turned off.

  However, in the semiconductor switch circuit according to the embodiment of the present invention, the capacitance values of the first to fourth capacitors 108, 109, 115, and 116 are set as described above. The rate at which electric power leaks through the first to fourth capacitors 108, 109, 115, and 116 is reduced. At the same time, when the semiconductor switch circuit is on, unlike the conventional circuit, the increase in insertion loss is suppressed by the capacitance setting of the first to fourth capacitors 108, 109, 115, 116 described above, while the semiconductor switch circuit In the off state, an operation having high power durability characteristics can be obtained without causing deterioration of isolation characteristics.

FIG. 2 shows an example of input / output characteristics of the semiconductor switch circuit according to the embodiment of the present invention, together with the same characteristics of the conventional circuit, which will be described below.
In FIG. 2, the horizontal axis represents input power (dBm), and the vertical axis represents output power (dBm). In FIG. 2, a characteristic line represented by a solid line is a characteristic line indicating a change in output power with respect to a change in input power of the semiconductor switch circuit in the embodiment of the present invention, and is a characteristic line represented by a two-dot chain line. These are characteristic lines which show the change of the output power with respect to the input power change of the conventional circuit (see FIG. 5).

  Comparing both characteristics, up to about 30 dBm input power, the output power increases as the input power increases. The characteristics are almost the same, but the input power exceeds 31 dBm. Thus, while the linearity of the output power change with respect to the input power change of the conventional circuit is impaired, the semiconductor switch circuit in the embodiment of the present invention still maintains the linearity of the output power change with respect to the input power change. Thus, a large output power can be obtained as compared with the conventional circuit.

FIG. 3 shows an example of the change characteristic of the insertion loss with respect to the frequency change between the first high-frequency terminal 101 and the second high-frequency terminal 102 when the semiconductor switch circuit according to the embodiment of the present invention is on. This is shown together with the characteristics and will be described below.
In FIG. 3, the horizontal axis represents frequency (GHz) and the vertical axis represents insertion loss (dB). In the figure, a characteristic line represented by a solid line is a characteristic line of the semiconductor switch circuit in the embodiment of the present invention, and a characteristic line represented by a two-dot chain line is a characteristic line of the conventional circuit (see FIG. 6). It is a characteristic line.
According to the figure, it can be confirmed that the insertion loss of the semiconductor switch circuit in the embodiment of the present invention is surely improved as compared with the conventional circuit.

FIG. 4 shows an example of a change characteristic of isolation with respect to a frequency change between the first high-frequency terminal 101 and the second high-frequency terminal 102 when the semiconductor switch circuit according to the embodiment of the present invention is in an OFF state. This is shown together with the characteristics and will be described below.
In FIG. 4, the horizontal axis represents frequency (GHz) and the vertical axis represents isolation (dB). In the figure, a characteristic line represented by a solid line is a characteristic line of the semiconductor switch circuit in the embodiment of the present invention, and a characteristic line represented by a two-dot chain line is a characteristic line of the conventional circuit (see FIG. 6). It is a characteristic line.
According to the figure, it can be confirmed that the isolation of the semiconductor switch circuit in the embodiment of the present invention is surely improved as compared with the conventional circuit.

In the above-described configuration example, each of the first and second switch elements 11 and 12 is configured by connecting two field effect transistors in series, but it is not necessary to be limited to two. Of course, a configuration in which two or more field-effect transistors are connected in series is also possible.
In addition, as the isolation between the first and second high frequency terminals 101 and 102 when the first and second field effect transistors 103 and 104 are in the OFF state, when the isolation is not particularly high, the second The semiconductor switch circuit may be configured with only the first switch element 11 without providing the switch element 12. Of course, even in this case, the capacitance value of the first capacitor 108 is set to be equal to or less than the parasitic capacitance Cgd1 between the gate and the drain in the off state of the first field effect transistor 103. The second field effect transistor 104 is set to be equal to or less than the gate-source parasitic capacitance Cgs1 in the off state.

It is a circuit diagram which shows the example of 1 circuit structure of the semiconductor switch circuit in embodiment of this invention. It is a characteristic diagram which shows the input-output characteristic example of the semiconductor switch circuit in embodiment of this invention, and a conventional circuit. The characteristic diagram which showed the example of a change characteristic of the insertion loss with respect to the frequency change between the 1st high frequency terminal and the 2nd high frequency terminal when the semiconductor switch circuit in an embodiment of the present invention is in the ON state together with the characteristic example of the conventional circuit It is. A characteristic diagram showing an example of a change characteristic of isolation with respect to a frequency change between the first high-frequency terminal and the second high-frequency terminal when the semiconductor switch circuit according to the embodiment of the present invention is in an ON state, together with a characteristic example of a conventional circuit. It is. It is a circuit diagram which shows the circuit structural example of a conventional circuit. It is a circuit diagram which shows the other circuit structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... 1st switch element 12 ... 2nd switch element 101 ... 1st high frequency terminal 102 ... 2nd high frequency terminal 103 ... 1st field effect transistor 104 ... 2nd field effect transistor 108 ... 1st capacitor 109 ... second capacitor 110 ... third field effect transistor 111 ... fourth field effect transistor 115 ... third capacitor 116 ... fourth capacitor

Claims (2)

In a semiconductor switch circuit comprising first and second high frequency terminals for inputting and outputting a high frequency signal, and a first switch element provided between the first and second high frequency terminals,
The first switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between the first and second high-frequency terminals, and among the plurality of field effect transistors, A capacitor is connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the first high frequency terminal or the second high frequency terminal,
The capacitance values of all the capacitors are set to be equal to or less than the parasitic capacitance value between the gate and the drain in the off state of each field effect transistor to which the capacitor is connected, or the parasitic capacitance value between the gate and the source. A semiconductor switch circuit. First and second high-frequency terminals for inputting and outputting a high-frequency signal; a first switch element provided between the first and second high-frequency terminals; and the first high-frequency terminal and the second high-frequency terminal. In a semiconductor switch circuit comprising a second switch element provided between either one and ground,
The first switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between the first and second high-frequency terminals, and among the plurality of field effect transistors, Capacitors are respectively connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the first high frequency terminal or the second high frequency terminal,
The second switch element includes a plurality of field effect transistors in which a drain electrode and a source electrode are connected in series between one of the first and second high-frequency terminals and the ground. A capacitor is connected between the drain electrode or the source electrode and the gate electrode of the field effect transistor in which the drain electrode or the source electrode is connected to the second high-frequency terminal or ground,
The capacitance values of all the capacitors are set to be equal to or less than the parasitic capacitance value between the gate and the drain in the off state of each field effect transistor to which the capacitor is connected, or the parasitic capacitance value between the gate and the source. A semiconductor switch circuit.

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