CN100563106C - Radio-frequency (RF) switch - Google Patents
Radio-frequency (RF) switch Download PDFInfo
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- CN100563106C CN100563106C CNB2005100045198A CN200510004519A CN100563106C CN 100563106 C CN100563106 C CN 100563106C CN B2005100045198 A CNB2005100045198 A CN B2005100045198A CN 200510004519 A CN200510004519 A CN 200510004519A CN 100563106 C CN100563106 C CN 100563106C
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Abstract
A kind of switch that optionally changes radiofrequency signal comprises at least 3 field-effect transistors, and they connect with series system.The width that is arranged on the source electrode of intergrade or drain electrode is narrower than the width of source electrode that is arranged on initial level and final stage or drain electrode.Therefore, just might reduce over the ground parasitic capacitance, and might realize having the switch of high processing power thus in intergrade.
Description
Technical field
Relate generally to of the present invention is used for radio frequency (RF) switch of radio-frequency unit (such as mobile communications device), more particularly, relates to the radio-frequency (RF) switch that has a plurality of field-effect transistors (RF) to be connected in series thereon.
Background technology
In recent years, used the radio-frequency (RF) switch (SPNT: hilted broadsword (pole) N throws (through): N represents port number) with a plurality of ports in mobile telephone unit, above-mentioned mobile telephone unit is by a plurality of CF signal communications.Radio-frequency (RF) switch comprises the field-effect transistor (FET) that is made of various kinds of compound semiconductors.This radio-frequency (RF) switch is required to have low harmonic performance, more particularly, be the first-harmonic that transmits-70dBc or following.For harmonic components being suppressed on the low level, require field-effect transistor to improve the linearity of resistance under conducting state, have fabulous cut-off state power simultaneously.
In order to improve cut-off state power, usually, field-effect transistor is connected in the mode of M level series connection.Fig. 1 represents an example of the field-effect transistor of M level series connection.All be at all field-effect transistors under the situation of cut-off state, radiofrequency signal will be passed through rf signal line.All be at all field-effect transistors under the situation of conducting state, radiofrequency signal will be crossed over the field-effect transistor arrival point.All be under the situation of cut-off state at all field-effect transistors that the M level is connected in series, in theory, each grade only receives the voltage of 1/M.As if the voltage of representing radiofrequency signal with V, the voltage that then is applied to each field-effect transistor is V/M.Yet in fact, each field-effect transistor all is subjected to the influence of this field-effect transistor parasitic capacitance over the ground, and above-mentioned parasitic capacitance is represented as Cp in Fig. 2.With reference to Fig. 2, Cds represents that between the drain electrode of each field-effect transistor and the electric capacity between the source electrode Cg represents between the grid of each field-effect transistor and source electrode or the electric capacity between grid and drain electrode.With reference to Fig. 3 A, the impedance Z cp of parasitic capacitance Cp over the ground is connected to the impedance Z of the field-effect transistor of each grade.Correspondingly, shown in Fig. 3 B, the impedance of each grade is unequal (Z → Z ' (＜Z)).Because the disparity of above-mentioned impedance between at different levels, so voltage V1 is applied to the field-effect transistor (impedance Z) of the most close (or being directly connected to) rf signal line, wherein, the voltage V1 voltage V2 that other are at different levels greater than being applied to (impedance Z ' (＜Z)) (＜V1).So just produce a problem, that is, and the numerical value that processing power (handling power) becomes and calculates less than from following logical formula 1.
(formula 1)
Pmax＝2[M(Vp-Vcont)]
2/Zo
Here, M represents the progression that is connected in series, and Vp represents pinch off (pinch-off) voltage, at this voltage place, field-effect transistor becomes from conducting and ends, and vice versa, Vcont is the control voltage that is applied to the grid of field-effect transistor, and Zo is a system impedance, and Pmax is maximum processing power.
In order to address the above problem, as shown in Figure 4, propositions such as Mitchell B.Shifrin are added capacitor C 1 and C2 to and are gone at different levels, change over the ground parasitic capacitance thus and (see that people such as MitchellB.Shifrin is published in IEEE Transactions on Microwave Theory andTechnique, Vol.37, No.12, December 1989, and pp.2134-2141 is entitled as " Monolithic FET structures for High-Power Control ComponentApplications " literary composition) (hereinafter referred to as document 1).By capacitor C 1 and C2 are followed the field-effect transistor parallel connection, impedance will be assigned to each level equably, and high frequency voltage V is divided into V1, V2 and V3 (V1=V2=V3) equably simultaneously.
With reference to Fig. 5 A and 5B, Japanese Patent Application 7-70245 number (hereinafter referred to as document 2) and Japanese Patent Application 9-8621 number (hereinafter referred to as document 3) disclose capacitor C a in Fig. 5 A and another capacitor C b in Fig. 5 B, added to respectively between source electrode or drain electrode and the grid, and the voltage that is distributed between grid and source electrode is offset wittingly.Fig. 6 A is illustrated under the situation of not adding capacitor C a and Cb, the variation of another voltage difference (V2-V3) between the voltage difference between V1 and the V2 (V1-V2) and V2 and the V3.Fig. 6 B represents, under the situation of having added capacitor C a such shown in Fig. 5 A and 5B and Cb, and the variation of voltage difference (V1-V2) and voltage difference (V2-V3).Here, V1 is a radiofrequency signal voltage, and V2 is the voltage at the tie point place between capacitor C a and grid, and V3 is the voltages at nodes of two field-effect transistors of being connected in series.Symbol Vp among Fig. 6 A and the 6B represents pinch-off voltage.The use of additional capacitor Ca and Cb makes the voltage that is distributed between grid and the source electrode be offset.Even radio-frequency voltage has big amplitude, this voltage also can be biased, thereby makes grid voltage be no more than pinch-off voltage Vp.Therefore, processing power is improved.
Yet, in document 1 routine techniques disclosed and shown in Figure 4, there is a problem, that is, signal leaks by capacitor C 1 and C2.When disconnecting, this leakage current descends insulativity.Cost will increase in the technology that forms electric capacity.In addition, have under the situation of low puncture voltage in capacitor C 1 and C2, the surge resistance such such as ESD may descend.In general, the electric capacity on the MMIC has low puncture voltage.
Also have with document 1 described identical problem in and Fig. 5 A disclosed and the routine techniques shown in the 5B at document 2 with 3.In addition, also have another problem, that is,, require field-effect transistor to have higher puncture voltage with there not being the circuit of capacitor C a and Cb to compare.
Also have, in recent years,, used High Electron Mobility Transistor (HEMT) to come substituted metal semiconductor field effect transistor (MESFET) in order to reduce the insertion loss of switch.In general, when the resistance of conducting state reduces, because highly concentrated channel layer makes puncture voltage be tending towards reducing.Therefore, may use routine techniques disclosed in document 1 to 3, that have various break-down voltage problem to solve the problems referred to above with regard to no longer including.
Summary of the invention
Catalogue of the present invention be exactly to address the above problem and provide a kind of radio-frequency (RF) switch.More particularly, the voltage that is applied to the field-effect transistor that is connected in series under cut-off state will be improved processing power with low cost simultaneously easily by five equilibrium.
According to an aspect of the present invention, preferably, a kind of switch is provided, it comprises at least 3 field-effect transistors that are connected in series, in order to selecting one of them radiofrequency signal, and it is narrower than the width of the source electrode of other field-effect transistors that are arranged on initial level and final stage or drain electrode to be arranged on one of them the source electrode or the width of drain electrode of at least 3 field-effect transistors of intergrade.Therefore just might thus, utilize the field-effect transistor that is in cut-off state that is connected in series, realize the raising of processing power easily with low cost in intergrade reduction parasitic capacitance over the ground.
In above-mentioned configuration, radio-frequency (RF) switch comprises at least 4 field-effect transistors that are connected in series.Each the source electrode or the width of drain electrode of at least 4 field-effect transistors that is arranged on intergrade is narrower than the width of source electrode that is arranged on initial level and final stage or drain electrode.Preferably, except those were arranged on the field-effect transistor of initial level and final stage, the overall width of the grid of other each field-effect transistors was less than the overall width of the grid of each field-effect transistor that is arranged on initial level and final stage.In addition, above-mentioned configuration may further include the electrode wires of extending along the grid of at least 3 field-effect transistors, and, except those were arranged on the field-effect transistor of initial level and final stage, the electrode wires of other each field-effect transistors was shorter than the electrode wires of each field-effect transistor that is arranged on initial level and final stage.
Description of drawings
With reference to all accompanying drawings each preferred embodiment of the present invention is elaborated below, in all accompanying drawings:
Fig. 1 represents an example of the field-effect transistor that the M level is connected in series;
Fig. 2 represents the equivalent electric circuit of a radio-frequency (RF) switch;
Fig. 3 A and 3B represent parasitic capacitance over the ground and the circuit diagram of the defective brought thus;
Fig. 4 is a circuit diagram that can solve in the conventional radio-frequency (RF) switch of the defective shown in Fig. 3 A and the 3B;
Fig. 5 is another circuit diagram that can solve in the conventional radio-frequency (RF) switch of the defective shown in Fig. 3 A and the 3B;
Fig. 6 A and 6B are the oscillograms of the work of expression radio-frequency (RF) switch shown in Figure 5;
Fig. 7 is the plane graph according to the radio-frequency (RF) switch of the first embodiment of the present invention;
Fig. 8 is that explanation compares with prior art, the viewed graph of a relation that applies between power and the insertion loss in the first embodiment of the present invention;
Fig. 9 is the plane graph of radio-frequency (RF) switch according to a second embodiment of the present invention;
Figure 10 is the plane graph of the radio-frequency (RF) switch of a third embodiment in accordance with the invention;
Embodiment
Provide the explanation of various embodiments of the present invention referring now to all accompanying drawings.
(first embodiment)
Fig. 7 A is the plane graph according to the radio-frequency (RF) switch of the first embodiment of the present invention.Radio-frequency (RF) switch among Fig. 7 A comprises the field-effect transistor of 3 grades of series connection.Fig. 7 B represents to have the conventional radio-frequency (RF) switch of the field-effect transistor of 3 grades of series connection.As will illustrating below, the width that is connected to the electrode interconnection (interconnection) of the source electrode of field-effect transistor of a centre (second) level or drain electrode is narrower than the width of another electrode interconnection of the source electrode of the field-effect transistor that is connected to one initial (first) level or a drain electrode and a radio frequency line, perhaps is connected to the width of another electrode interconnection of the source electrode of field-effect transistor of an end (the 3rd) level or a drain electrode and an earth connection.The electrode interconnection that is connected to the source electrode of field-effect transistor is called as source electrode.The electrode interconnection that is connected to the drain electrode of field-effect transistor is called as drain electrode.
3 field- effect transistors 10
1, 10
2With 10
3Be set at 3 independently field-effect transistor formation districts 16
1, 16
2With 16
3Among, the latter provides in a compound semiconductor substrate such as GaAs (GaAs).Compound semiconductor substrate is corresponding to a slice among Fig. 7 (sheet).These field-effect transistors are called as field-effect transistor group 10.Form district 16 at field-effect transistor
1, 16
2With 16
3In each field-effect transistor 10 of being connected in series
1, 10
2With 10
3All comprise a plurality of field-effect transistors that are connected in parallel.Shown in Fig. 7 A, form district 16 at each field-effect transistor
1, 16
2With 16
37 field-effect transistors are all arranged.Field- effect transistor 10
1, 10
2With 10
3All be connected in series between radio frequency line 12 and ground (GND) line 14.Field-effect transistor 10
1Directly be connected to radio frequency line 12.Field-effect transistor 10
3Directly be connected to ground wire 14.Field-effect transistor 10
2Be connected field-effect transistor 10
1With field-effect transistor 10
3Between.
Source/drain electrode interconnection (hereinafter referred to as a S/D electrode interconnection) 20
1, vertically extend to field-effect transistor from radio frequency line 12 and form district 16
1On.S/D electrode interconnection 22
1Be set at field-effect transistor and form district 16
1On.A gate interconnection 18
1Be set at S/D electrode interconnection 20
1With 22
1Between.S/D electrode interconnection 20
1With 22
1Respectively with opposite direction towards gate interconnection 18
1S/D electrode interconnection 22
1Be connected to S/D electrode interconnection 20
2, the latter is parallel to the link electrode interconnection 24 that radio frequency line 12 extends by one
1Be set at and be in partial field-effect transistor formation district 16
2On.S/D electrode interconnection 20
2, link electrode interconnection 24
1And S/D electrode interconnection 22
1Form a continuous interconnection graph, the latter is connected to and is positioned at partial field-effect transistor 10 in the series circuit of 3 field-effect transistors
2Source electrode or drain electrode.Comprise 22
1, 24
1, 20
2This continuous interconnection graph with a Reference numeral 30
1Represent.
S/D electrode interconnection 22
2And S/D electrode interconnection 20
2Be set at field-effect transistor and form district 16
2Gate interconnection 18
2Be set at S/D electrode interconnection 20
2With 22
2Between.S/D electrode interconnection 20
2With 22
2Respectively with opposite direction towards gate interconnection 18
2S/D electrode interconnection 22
2Be connected to S/D electrode interconnection 20
3, the latter is parallel to the link electrode interconnection 24 that radio frequency line 12 extends by one
2Be set at the field-effect transistor that is in the third level and form district 16
3On.S/D electrode interconnection 22
2, link electrode interconnection 24
2And S/D electrode interconnection 20
3Form a continuous interconnection graph, the latter is connected to the partial field-effect transistor 10 at series circuit
2Source electrode or drain electrode.Comprise 22
2, 24
2With 20
3This continuous interconnection graph with a Reference numeral 30
2Represent.
S/D electrode interconnection 22
3And S/D electrode interconnection 20
3Be set at field-effect transistor and form district 16
3S/D electrode interconnection 22
3Extend from ground wire 14.Gate interconnection 18
3Be set at S/D electrode interconnection 20
3With 22
3Between.S/D electrode interconnection 20
3With 22
3Respectively with opposite direction towards gate interconnection 18
3
According to the first embodiment of the present invention, by electrode interconnection being attenuated reduce parasitic capacitance Cp over the ground.Electrode interconnection produces parasitic capacitance Cp over the ground.Shown in the equivalent electric circuit of Fig. 2, parasitic capacitance Cp over the ground brings disparity to each voltage that is applied, corresponding to be positioned at partial drain electrode or source electrode in series circuit.In the disparity of the voltage that is applied, do not relate to the electrode that is connected to radio frequency line 12 or ground wire 14.The first embodiment of the present invention lays stress on this point.S/D electrode interconnection 30
1With 30
2Width be narrower than S/D electrode interconnection 20
1With 22
3Width.S/D electrode interconnection 30
1With 30
2Be connected to partial source electrode or drain electrode.S/D electrode interconnection 20
1Be connected to the field-effect transistor 10 that is positioned at the first order
1Source electrode or drain electrode and radio frequency line 12.S/D electrode interconnection 22
3Be connected to the field-effect transistor 10 that is positioned at the third level
3Source electrode or drain electrode and ground wire 14.
Suppose a condition, that is: (Wc＜Wb), Wc represents S/D electrode interconnection 30 to Wc here less than Wb
1With 30
2Width, Wb represents S/D electrode interconnection 20
1With 22
3Width.It is that 2 μ m and Wb are under the condition of 5 μ m that Fig. 8 is illustrated in Wc, the numerical value of input power of actual measurement (dBm) and insertion loss (dB).Fig. 7 B is the plane graph of the conventional radio-frequency (RF) switch of a comparison, and wherein, all S/D electrode interconnection all have the same widths Wa of 3 μ m.In order to compare, Fig. 8 also shows the field-effect transistor characteristic of the conventional radio-frequency (RF) switch among Fig. 7 B.With reference to Fig. 8, in custom circuit, reduce 0.1dB if insert loss, then the power that is applied is 35dBm.In contrast, the first embodiment of the present invention obtains the improvement of about 2dB, because concerning the applying the power of 37dBm, insert loss and reduce 0.1dB.
As mentioned above, not having expensive building-out condenser and reducing under the condition of surge resistance,, just might realize the improved radio-frequency (RF) switch of high processing power by reducing parasitic capacitance Cp over the ground.
Get back to Fig. 7 B, S/D electrode interconnection 30
1With 30
2All has identical width W c.Can link electrode interconnection 24 for alternatively
1With 24
2Width can be a bit larger tham the width of other S/D electrode interconnection.In other words, the S/D electrode interconnection 30
1With 30
2Can have different width.As long as S/D electrode interconnection 30
1With 30
2All have area, just can reduce parasitic capacitance Cp over the ground less than custom circuit.
The present invention is not limited to 3 grades of series circuits shown in Fig. 7 A, can use the level of arbitrary number.For example, can use 5 grades of series circuits, therein, have width W c in the second S/D electrode interconnection to the fourth stage, first and the level V S/D electrode interconnection that is connected to radio frequency line and ground wire then has width W b (Wc＜Wb).
(second embodiment)
Fig. 9 is the plane graph of radio-frequency (RF) switch according to a second embodiment of the present invention.Below, in a second embodiment, the parts identical with first embodiment all have identical Reference numeral with configuration.According to a second embodiment of the present invention, be set at the field-effect transistor formation district 16 of intergrade (being the second level in the present embodiment)
2Among total grid width of field-effect transistor be set to less than total grid width at the field-effect transistor of initial level and final stage.More particularly, field-effect transistor forms district 16
1With 16
3Central each all comprises 7 field-effect transistors.In contrast, field-effect transistor forms district 16
2Comprise 6 field-effect transistors.Therefore, compare, might reduce S/D electrode interconnection 30 with the circuit shown in Fig. 7 A
1With 30
2The gross area, and reduce over the ground parasitic capacitance thus further.So, not having expensive building-out condenser and reducing under the condition of surge resistance,, just might realize having the radio-frequency (RF) switch of higher processing power by reducing parasitic capacitance Cp over the ground.
Figure 10 is the plane graph of the radio-frequency (RF) switch of a third embodiment in accordance with the invention.Below, in the 3rd embodiment, the parts identical with first embodiment all have identical Reference numeral with configuration.The 3rd embodiment has such setting, and wherein, the field-effect transistor that is set at second (centre) level forms district 16
2Among the size of each field-effect transistor all less than size at each field-effect transistor of the first order and the third level.Therefore, by shortening S/D electrode interconnection 30
1With 30
2Total length, just can reduce parasitic capacitance over the ground further.So, not having expensive building-out condenser and reducing under the condition of surge resistance,, just might realize having the radio-frequency (RF) switch of higher processing power by reducing parasitic capacitance Cp over the ground.The third embodiment of the present invention can combine with second embodiment.
The present invention is not limited to the foregoing description, and, under the prerequisite of not leaving scope of the present invention, can make other various embodiment, change and modification.
The present invention is based on the Japanese patent application submitted on January 16th, 2004 2004-009878 number, its whole disclosures are as a reference by income this paper.
Claims (5)
1. a switch comprises at least 3 field-effect transistors, and all described at least 3 field-effect transistors make radiofrequency signal transmit towards the other end from an end, and makes radiofrequency signal pass through all described at least 3 field-effect transistors from a described end,
Described at least 3 field-effect transistors are connected in series between the node and ground between a described end and the described other end, the field-effect transistor that is arranged on initial level at least in wherein said 3 field-effect transistors is connected to described node, and the field-effect transistor that is arranged on final stage at least in described 3 field-effect transistors is connected to ground, wherein
The drain electrode that is arranged on the field-effect transistor of initial level at least in described 3 field-effect transistors is connected to described node, and the source electrode that is arranged on the field-effect transistor of final stage at least in described 3 field-effect transistors is connected to ground;
The drain electrode that is arranged on the field-effect transistor of intergrade at least in described 3 field-effect transistors is connected to the source electrode of the field-effect transistor that is arranged on initial level at least in described 3 field-effect transistors, and the source electrode that is arranged on the field-effect transistor of intergrade at least in described 3 field-effect transistors is connected to the drain electrode that is arranged on the field-effect transistor of final stage at least in described 3 field-effect transistors;
The width that is arranged on the source electrode of field-effect transistor of intergrade and drain electrode at least in described 3 field-effect transistors is less than the width of the source electrode of the field-effect transistor that is arranged on final stage at least in the width of the drain electrode of the field-effect transistor that is arranged on initial level at least in described 3 field-effect transistors and described 3 field-effect transistors; And
All be under the situation of cut-off state at whole described at least 3 field-effect transistors, described switch makes radiofrequency signal transmit towards the described other end from a described end, and all be under the situation of conducting state at whole described at least 3 field-effect transistors, make radiofrequency signal pass through all described at least 3 field-effect transistor arrival points from a described end.
2. switch according to claim 1, wherein, this radio-frequency (RF) switch comprises at least 4 field-effect transistors that are connected in series.
3. switch according to claim 2, wherein, the width that is arranged on the source electrode of field-effect transistor of intergrade or drain electrode at least in 4 field-effect transistors is less than the source electrode of the field-effect transistor that is arranged on initial level and final stage or the width of drain electrode.
4. switch according to claim 1, wherein, except those were arranged on the field-effect transistor of initial level and final stage, the overall width of the grid of a plurality of field-effect transistors that are connected in parallel in described at least 3 field-effect transistors was less than the overall width of the grid of the field-effect transistor that is arranged on initial level or final stage.
5. switch according to claim 1, the length that is arranged on the source electrode of described field-effect transistor of intergrade and drain electrode at least in described 3 field-effect transistors is less than the source electrode of described other field-effect transistors that are connected to described node or ground and the length of drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100045198A CN100563106C (en) | 2005-01-14 | 2005-01-14 | Radio-frequency (RF) switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100045198A CN100563106C (en) | 2005-01-14 | 2005-01-14 | Radio-frequency (RF) switch |
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| CN1805283A CN1805283A (en) | 2006-07-19 |
| CN100563106C true CN100563106C (en) | 2009-11-25 |
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| CNB2005100045198A Expired - Fee Related CN100563106C (en) | 2005-01-14 | 2005-01-14 | Radio-frequency (RF) switch |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9515645B2 (en) * | 2014-06-03 | 2016-12-06 | Infineon Technologies Ag | System and method for a radio frequency switch |
| US10032775B2 (en) * | 2015-05-29 | 2018-07-24 | Rohde & Schwarz Gmbh & Co. Kg | Switching device for switching radio frequency signals |
| CN106656128A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Voltage homogenization method for radio frequency switch with multiple serially connected transistors and radio frequency switch |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313083A (en) * | 1988-12-16 | 1994-05-17 | Raytheon Company | R.F. switching circuits |
| US5973377A (en) * | 1995-12-28 | 1999-10-26 | Nec Corporation | Semiconductor device having FETs with shared source and drain regions |
| US6563366B1 (en) * | 1997-10-30 | 2003-05-13 | Sony Corporation | High-frequency Circuit |
| CN1452317A (en) * | 2002-04-17 | 2003-10-29 | 三洋电机株式会社 | Semiconductor switch circuit device |
-
2005
- 2005-01-14 CN CNB2005100045198A patent/CN100563106C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313083A (en) * | 1988-12-16 | 1994-05-17 | Raytheon Company | R.F. switching circuits |
| US5973377A (en) * | 1995-12-28 | 1999-10-26 | Nec Corporation | Semiconductor device having FETs with shared source and drain regions |
| US6563366B1 (en) * | 1997-10-30 | 2003-05-13 | Sony Corporation | High-frequency Circuit |
| CN1452317A (en) * | 2002-04-17 | 2003-10-29 | 三洋电机株式会社 | Semiconductor switch circuit device |
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