JP2005063619A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remarkably shorten a write cycle compared with a conventional method, even in a batch write operation mode and to perform evaluation for durability in rewriting in a short period of time without increasing a layout space in a semiconductor storage device. <P>SOLUTION: The semiconductor storage device has a test mode decision circuit 40 in which a first sense amplifier external activating signal SAPE as an external signal for a first sense amplifier activating signal SAP and a word line batch write mode selection signal TEST are inputted in its peripheral circuit part and the first amplifier activating signal SAP is outputted. The test mode decision circuit 40 makes the first sense amplifier signal SAP inactive during the period of data writing in the word line batch write operation mode, and a P channel type MOS transistor Qp4 as the transistor for power supply to the sense amplifier is made to be in an inactive state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device capable of performing a word line batch rewrite operation during rewrite endurance evaluation.

  The word line batch rewrite operation in the semiconductor memory device inevitably increases the power consumption because the number of columns to be rewritten is larger than the operation of rewriting only the memory cell arranged in the region where the word line and the bit line intersect each other. . As a countermeasure against this, there has been proposed a method of limiting the operation area during the rewriting operation (see, for example, Patent Document 1).

  Specifically, the operation of writing data to all of the sense amplifiers connected to one of the plurality of word lines and the data latched by the sense amplifier while sequentially accessing all the word lines are written to the memory cells. The above operations are repeated as a series of operations with data inverted. However, if such a method is adopted, it is necessary to continuously execute two different operation modes, so that two systems of control circuits and mode switching circuits are required, which increases the circuit scale of the semiconductor memory device itself. There is a problem that the control operation is complicated and the evaluation apparatus is restricted.

  On the other hand, since the evaluation of rewriting durability for a semiconductor memory device is only one evaluation item in the development stage of the device, the power consumption of the semiconductor memory device is not a problem as long as the driving capability of the evaluation device is ensured. .

  Hereinafter, in order to solve the above-described problem, a conventional technique employing a word line batch rewrite operation executed in a single operation mode in all rewrite operations will be described with reference to the drawings.

  FIG. 9 shows a circuit block of a conventional semiconductor memory device, which is a ferroelectric memory device using a ferroelectric material for a cell capacitor.

  As shown in FIG. 9, externally designated addresses A0 to Am are input to an address buffer, and an output signal from the address buffer is a row decoder that decodes and selects word lines WL to WLx, respectively, and a sense amplifier block SAB0 to SABy are input to a column decoder for decoding and selecting.

  Operations of the address buffer, the I / O buffer, the row decoder, the column decoder, and the sense amplifier blocks SAB0 to SABy are controlled by control signals from a control circuit to which external signals CE, WE, OE and the like are input. The bit configuration of the unit memory is 8 bits, and each memory cell is a so-called 2T2C type memory cell composed of two transistors and a ferroelectric capacitor.

  Of the n memory cells connected to one word line WL, the first eight are connected to bit line pairs BL0 to BL7 and / BL0 to / BL7, respectively, and a sense amplifier is supplied by a column selection signal CSEL0 from the column decoder. By activating block SAB0, a read operation or a write operation is performed via each data line pair DL0 to DL7 and / DL0 to / DL7.

  FIG. 10 shows the configuration of one sense amplifier block SAB0, and FIG. 11 shows the detailed configuration of the sense amplifier and column selection switch section.

  As shown in FIG. 10 or FIG. 11, memory cells accessed from the outside are selectively connected to the bit line pairs BL0 to BL7 and / BL0 to / BL7 by the word line WL and the plate line CP, and the bit line pair BL0. ... To BL7 and / BL0 to / BL7 are connected to the sense amplifiers SA0 to SA7, respectively. The signal SAP for controlling the operation of each sense amplifier is input in common to the gates of the P-channel MOS transistors Qp4 included in each sense amplifier of the sense amplifier blocks SAB0 to SABy. The N-channel MOS transistor Qn4 included in each sense amplifier is controlled by a start signal SANE, a stop signal SAND, and a column selection signal CSEL0. As a result, the P-channel MOS transistor Qp4 is simultaneously activated in all the columns regardless of the column selection signal CSEL0. On the other hand, only the selected column of N channel type MOS transistor Qn4 is activated.

  An N-channel MOS transistor Qn6, which is a column selection switch for connecting the bit line pairs BL0 to BL7 and / BL0 to / BL7 and the data line pairs DL0 to DL7 and / DL0 to / DL7, respectively, has an activation signal YS and a column selection signal CSEL0. Is selectively activated.

  In a semiconductor memory device, the rewrite endurance of a memory cell has become a more important factor in terms of reliability. In recent years, even in a ferroelectric memory device, the rewrite endurance has been relatively improved, and the evaluation time has been increased. It tends to be longer. On the other hand, in the development and commercialization of a memory core using a new miniaturization process, it is required to evaluate rewrite resistance and perform screening before shipment more efficiently and in a short time. Therefore, as a method for efficiently evaluating a semiconductor memory device, a technique has been developed in which all memory cells connected to one word line are simultaneously selected and data is written to all the memory cells at once. Has been. By repeatedly performing this operation using data whose polarities are reversed from each other, it is possible to evaluate the rewrite resistance in a short time.

  Next, the operation of the column selection switch and the sense amplifier in the case where all the memory cells connected to one word line are collectively written will be described with reference to FIG.

  First, as shown in FIG. 12, when all the column addresses 0 to y are selected, all the column selection signals CSEL0 to CSELy are set to the “H (high)” level in an activated state, and then the activation signal SAP. As a result of the transition to the “L (low)” level, which is an activated state, all the P-channel MOS transistors Qp4 constituting the sense amplifier are activated.

  On the other hand, at all column addresses, the P-channel MOS transistor Qp1 constituting the column selection switch receives the “H” level column selection signals CSEL0 to CSELy at its gate and is in an inactive state. Further, a P-channel MOS transistor Qp2 that receives a signal SANE that has transitioned to the “L” level simultaneously with the signal SAP at its gate, and a P-channel MOS transistor Qp3 that receives a stop signal SAND that is at the “L” level at this time at its gate. Both are activated. As a result, the signals SAN0 to SANy output from the column selection switch become “H” level, the N-channel MOS transistor Qn4 of each sense amplifier is activated, and the bit depends on the data read from the memory cell. The potentials of the lines BL and / BL are amplified.

Next, when the stop signal SAND transits to the “H” level in order to write data, the P-channel MOS transistor Qp3 is deactivated and the N-channel MOS transistor Qn3 is activated. At this time, in all the column addresses, the N channel MOS transistors Qn1 receiving the “H” level column selection signals CSEL0 to CSELy at their gates are also in an activated state, so that the signals SAN0 to SANy are temporarily “L”. At the level, N channel type MOS transistor Qn4 is inactivated. While the N-channel MOS transistor Qn4 for supplying ground power to the sense amplifier is deactivated, the control signals YS and YS0 to YSy of the column selection switch are changed to the “H” level for a predetermined time, so that N Bit line pairs BL0 to BLn and / BL0 to / BLn and data line pairs DL0 to DL7 and / DL0 to / DL7 are connected via channel type MOS transistor Qn6, respectively, and data is rewritten over all columns.
JP 2000-173296 A

  The inventor of the present application has found the following problems as a result of various studies on the word line batch rewrite operation in the conventional semiconductor memory device.

  That is, in the conventional semiconductor memory device, when all the memory cells connected to one word line are collectively written, bit lines BL, / DL connected to one data line DL, / DL are written. The number of BLs is (y + 1) times (y is an integer equal to or greater than 1) compared to the normal write operation. As a result, the total capacity of the bit lines BL and / BL becomes much larger than the capacity of the data lines DL and / DL, so that the column selection switch control signals YS0 to YSy are “H” as in the normal operation. Even if the N-channel MOS transistor Qn4 is in an inactive state during the write period when the level is reached, the bit lines / BL0 to / BLn can be easily rewritten from the “L” level to the “H” level. It is not.

  Furthermore, since the P-channel MOS transistor Qp4 that supplies the power supply potential to the sense amplifier remains active, it is very difficult to rewrite the bit lines BL0 to BLn from the “H” level to the “L” level. It is. Even if bit complementary lines / BL0 to / BLn become equal to or higher than the threshold voltage of P channel type MOS transistor Qp4, P channel type MOS transistor Qp5 connected to the drain of bit lines BL0 to BLn is inactivated. However, the rewrite time is much longer than that in the normal write operation.

  As described above, the conventional batch write type semiconductor memory device requires a very long operation cycle as compared with a normal write operation. As a result, it takes a lot of time to evaluate the rewriting durability, and further, the scale of the delay circuit for executing this evaluation becomes large, resulting in an increase in layout area.

  The present invention solves the above-described conventional problems, and can shorten the write cycle significantly in the batch write operation mode as compared with the conventional one without increasing the layout area, and can evaluate the rewrite endurance in a short time. For the purpose.

  In order to achieve the above object, according to the present invention, a semiconductor memory device includes a power supply included in a sense amplifier in a word line batch write operation mode and in a data write period in which each bit line and each data line are connected. A power supply transistor that supplies a potential or a ground potential is inactivated.

  Specifically, a first semiconductor memory device according to the present invention includes a plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines intersecting with the plurality of word lines, a plurality of bit lines, Each of the sense amplifiers includes a plurality of differential amplification type sense amplifiers connected to each other, and a plurality of bit lines and a plurality of data lines connected via the sense amplifiers. A power supply transistor that is connected, and the power supply transistor is in a word line batch write operation mode for writing to all of the memory cells connected to one of the plurality of word lines; It becomes inactive during a data write period in which each bit line and each data line are connected.

  According to the first semiconductor memory device, the power supply transistor is in the word line batch write operation mode in which writing is performed to all of the memory cells connected to one of the plurality of word lines. Since the data writing period in which the line and each data line are connected is inactivated, the power supply potential or the ground potential is not supplied to each bit line during the data writing period. That is, since each bit line is in a floating state in the sense amplifier during the data write period, it is easy to write data from each connected data line to each bit line. As a result, the rewrite resistance can be evaluated in a short time.

  In the first semiconductor memory device, each sense amplifier preferably performs a sensing operation by activating a power supply transistor included in each sense amplifier after the data write period ends. In this way, it is possible to reliably write the input data to the memory cell connected to each bit line.

  In the first semiconductor memory device, the plurality of bit lines are composed of a plurality of bit line pairs that can take complementary potentials, and each sense amplifier is connected to one of the plurality of bit line pairs. It is preferable that the sense operation is performed by activating the power supply transistor after the polarities of the pair of bit lines are inverted from each other in the data write period. In this way, it is possible to reliably write the input data to the memory cell connected to each bit line.

  A second semiconductor memory device according to the present invention is connected to a plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines crossing the plurality of word lines, and to a plurality of bit lines. Each of the sense amplifiers includes a plurality of differential amplification type sense amplifiers and a plurality of data lines connected to the plurality of bit lines via the sense amplifiers, and each sense amplifier has a power source whose source is connected to a power supply potential or a ground potential A power supply transistor, and the power supply transistor is in a word line batch write operation mode in which writing is performed to all of the memory cells connected to one of the plurality of word lines. It becomes inactive in a data writing period in which each data line is connected and in a period before the data writing period.

  According to the second semiconductor memory device, the power supply transistor is in the word line batch write operation mode in which writing is performed to all of the memory cells connected to one of the plurality of word lines. Inactive during the data write period in which the line and each data line are connected and in the previous period, the power supply potential or the ground potential is not supplied to each bit line in the data write period and in the previous period. That is, since each bit line is in a floating state in the sense amplifier in the data write period and the previous period, it is easier to write data from each connected data line to each bit line. The write cycle in the mode can be greatly shortened compared to the conventional case, and as a result, the evaluation of the rewrite resistance can be performed in a shorter time.

  In the first or second semiconductor memory device, an N-channel transistor can be used as the power supply transistor.

  In the first or second semiconductor memory device, a p-channel transistor can be used as the power supply transistor.

  In these cases, more specifically, the power supply transistor whose source is connected to the power supply potential is a P-channel transistor, and the power supply transistor whose source is connected to the ground potential is an N-channel transistor. It is preferable.

  The first or second semiconductor memory device preferably further includes a mode determination circuit that is shared by a plurality of bit lines and switches between the normal operation mode and the word line batch write operation mode for each sense amplifier. .

  In this case, the mode determination circuit includes an AND gate that receives a first signal representing the word line batch write operation mode at one input terminal, and a normal operation mode and a word line batch write operation mode at one input terminal. A logical sum gate which receives a significant second signal and receives the output of the logical product gate at another input terminal, and the logical product gate receives a delayed signal obtained by delaying the second signal at the other input terminal. It is preferred that

  According to the first or second semiconductor memory device of the present invention, since the write cycle in the word line batch write operation mode can be shortened as compared with the conventional one without increasing the layout area, the rewrite endurance is evaluated in a short time. It becomes possible.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit block of a semiconductor memory device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device 10 includes a plurality of word lines WL0 to WLx (where x is an integer of 1 or more) and a plurality of bit lines BL0, / BL0 to BLn, / BLn (where n is an integer greater than or equal to 1), each of which is connected to, for example, a plurality of 2T2C type memory cells (not shown) arranged in a matrix, and the memory cell array 20 , A sense amplifier 21, an address buffer 22, a row decoder 23, a column decoder 24, a control circuit 25, and an I / O buffer 26.

  The sense amplifier 21 is divided into (y + 1) blocks SAB0 to SAB7 (where y is an integer equal to or greater than 1). For example, the first sense amplifier block SAB0 has eight bit line pairs BL0 and / BL0. To BL7, / BL7.

  The address buffer 22 latches addresses A0 to Am designated from the outside (where m is an integer equal to or greater than 1), and outputs the result to the row decoder 23 and the column decoder 24.

  The row decoder 23 receives the output signal from the address buffer 22 and decodes and selects the word lines WL to WLx. The column decoder 24 receives the output signal from the address buffer 22 and receives each of the sense amplifier blocks SAB0 to SABy. Decode and select.

  The control circuit 25 receives a chip enable signal CE, a write enable signal WE, and an output enable signal OE from the outside, and supplies the address buffer 22, the row decoder 23, the column decoder 24, the control circuit 25, and the I / O buffer 26 with predetermined values, respectively. The control signal is output.

  2 shows details of the sense amplifier block SAB0, the bit line pairs BL0, / BL0 to BL7, / BL7, the data line pairs DL0, / DL0 to DL7, / DL7 and the memory cell 30 respectively connected to the sense amplifier block SAB0. The configuration is shown.

  As shown in FIG. 2, for example, one sense amplifier connected to the bit line pair BL0, / BL0 has an inverter pair composed of a P-channel MOS transistor Qp5 and an N-channel MOS transistor Qn5, respectively. This is a so-called differential amplification type amplifier. Connected to the inverter pair are a P-channel MOS transistor Qp4 for supplying a power supply potential to the inverter pair and an N-channel MOS transistor Qn4 for supplying a ground potential.

  The P-channel MOS transistor Qp4 has a gate to which the first sense amplifier activation signal SAP is input, a source connected to the power supply, and a drain connected to a shared source between the P-channel MOS transistors Qp5. Therefore, the P-channel MOS transistor Qp4 is activated simultaneously in all columns regardless of the column selection signal.

  On the other hand, the N-channel MOS transistor Qn4 receives the second sense amplifier activation signal SAN0 selectively activated by the column selection signal at its gate, the source is grounded, and the drain is between the N-channel MOS transistors Qn5. Connected with a shared source.

  The bit line pairs BL0, / BL0 to BLn, / BLn and the data line pairs DL0, / DL0 to DL7, / DL7 are connected in series with the bit line pairs BL0, / BL0, etc. A common gate shared between the pair is selectively connected by a plurality of N-channel MOS transistors Qn6 receiving a column selection switch activation signal YS0.

  FIG. 3 shows a test mode determination circuit 40, a column selection switch 41, and a sense amplifier block SAB0 according to the first embodiment of the present invention. FIG. 4 shows a configuration example of the test mode determination circuit 40.

  As shown in FIG. 3, the semiconductor memory device according to the first embodiment includes a first sense amplifier external activation signal SAPE that is an external signal of the first sense amplifier activation signal SAP, and a word line batch write mode selection signal. A test mode determination circuit 40 that receives TEST as an input and outputs a first sense amplifier activation signal SAP is provided.

  As shown in FIG. 4, the test mode determination circuit 40 according to the first embodiment includes, as an example, an AND gate 401 that receives a word line batch write mode selection signal TEST at a first input terminal, and an input terminal at one input terminal. The first sense amplifier external activation signal SAPE is received, and the OR gate 402 receives the output of the AND gate 401 at the other input terminal.

  The AND gate 401 receives a first sense amplifier external activation signal SAPE via a first delay circuit 40a composed of a plurality of inverters connected in series to a second input terminal, and a third input terminal receives The first delay signal from the first delay circuit 40a is received, and the second delay signal is received through the second delay circuit 40b including a plurality of inverters connected in series. Here, the first delay time by the first delay circuit 40a is a, and the second delay time by the second delay circuit 40b is b.

  As shown in FIG. 3, the column selection switch 41 receives the column selection switch external activation signal YS at one input terminal, receives the column selection signal CSEL0 at the column address 0 at the other input terminal, and performs an AND operation thereof. AND gate 411 which outputs column selection switch activation signal YS0 in a row, P channel type MOS transistor Qp1 and N channel type MOS transistor Qn1 receiving column selection signal CSEL0 at the gate, and second sense amplifier external activation signal SANE at the gate P-channel MOS transistor Qp2 and N-channel MOS transistor Qn2 receiving the signal, and P-channel MOS transistors Qp3 and Np receiving the sense amplifier stop signal SAND that deactivates the second sense amplifier activation signal SAN0 for a predetermined time at the gates channel And a MOS transistor Qn3 Metropolitan.

  The operation of the column selection switch 41 and the sense amplifier block SAB in the word line batch write mode of the semiconductor memory device configured as described above will be described below with reference to FIG.

  As shown in FIG. 5, first, the word line batch write mode selection signal TEST is fixed to the “H” level at the beginning of the operation cycle. After that, all the column addresses 0 to y are selected, and all the column selection signals CSEL0 to CSELy are all shifted to the “H” level in the activated state. Thereafter, the first sense amplifier external activation signal SAPE and the first When both sense amplifier activation signals SAP transition to the “L” level, the P-channel MOS transistors Qp4 included in the sense amplifier blocks SAB0 to SABy are activated.

  On the other hand, at all column addresses 0 to y, the P-channel MOS transistor Qp1 included in each column selection switch 41 is inactive because each column selection signal CSEL0 to CSELy is at “H” level. Since the second sense amplifier external activation signal SANE is also changed to the “L” level simultaneously with the first sense amplifier external activation signal SAPE signal, and the sense amplifier stop signal SAND is in the “L” level state, P Channel type MOS transistors Qp2 and Qp3 are activated. As a result, the second sense amplifier activation signals SAN0 to SANy are set to the “H” level, the N channel MOS transistors Qn4 are activated, and the sense amplifier blocks SAB0 to SABy are connected to the P channel MOS transistors. The power supply potential is supplied from the transistor Qp4, and the ground potential is supplied from each N-channel MOS transistor Qn4 to each sense amplifier. As a result, the potential reflecting the data read from the memory cell 30 is amplified in each bit line pair BL0, / BL0 to BL7, / BL7.

  Subsequently, the sense amplifier stop signal SAND is changed to “H” level so that data is written to each memory cell 30 connected to the selected one word line WL, and each column selection switch Inactivate the P-channel MOS transistor Qp3 included in 41, while activating the N-channel MOS transistor Qn3. At this time, in all the column addresses 0 to y, the N-channel MOS transistors Qn1 are in the active state with the column selection signals CSEL0 to CSELy being at the “H” level, and thus the second sense amplifier activation signals SAN0 to SAN0. SANy temporarily becomes "L" level, and N-channel MOS transistor Qn4 is deactivated.

  As a feature of the first embodiment, in the test mode determination circuit 40, the first delay circuit 40a is composed of an odd number of inverters after the first sense amplifier external activation signal SAPE transitions to the “L” level. After the elapse of the first delay time a, the first sense amplifier activation signal SAP, which is the output signal, transitions to the “H” level. As a result, the P-channel MOS transistor Qp4 in each sense amplifier block SAB0-SABy is inactivated.

  As described above, in each sense amplifier block SAB0-SABy, the N-channel MOS transistor Qn4 that supplies the ground potential to each sense amplifier and the P-channel MOS transistor Qp4 that supplies the power supply potential are inactive. The bit line pair BL0, / BL0 to BLn, / BLn and the data line pair DL0, / DL0 are set by setting the column selection switch external activation signal YS and the column selection switch activation signals YS0 to YSy to the “H” level for a predetermined time. ... To DL7, / DL7 are connected to each other through an N channel type MOS transistor Qn6 to rewrite data in all columns.

  Here, the second delay time b included in the second delay circuit 40b constituting the test mode determination circuit 40 is a time during which the column selection switch external activation signal YS and the column selection switch activation signals YS0 to YSy are activated. It needs to be set longer. Thereafter, the ground potential is supplied to each sense amplifier by setting the first sense amplifier activation signal SAP to “L” level and the second sense amplifier activation signals SAN0 to SANy to “H” level again for a predetermined period. The N-channel MOS transistor Qn4 and the P-channel MOS transistor Qp4 that supplies the power supply potential are activated to activate each sense amplifier, whereby predetermined data is written to each memory cell 30.

  As described above, according to the first embodiment, when data is written to the bit line pairs BL0, / BL0 to BLn, / BLn for accessing the memory cells 30 connected to one word line WL, the sense amplifier is supplied with power. By deactivating the P-channel MOS transistor Qp4 and the N-channel MOS transistor Qn4 that supply the potential and the ground potential, respectively, the data line pair DL0, / DL0 to DL7, / DL7 and the N-channel MOS transistor Writing to the bit line pairs BL0, / BL0 to BLn, / BLn respectively connected via Qn6 becomes extremely easy. For this reason, in the batch write operation mode, the write cycle can be greatly shortened as compared with the prior art, so that the rewrite endurance can be evaluated in a short time.

  Note that the circuit configuration of the test mode determination circuit 40 is not limited to the configuration illustrated in FIG. 4, and may be another circuit configuration as long as it has an equivalent function.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  The second embodiment shows another mode of operation in the word line batch write mode using a circuit configuration equivalent to that of the semiconductor memory device according to the first embodiment.

  That is, here, until the write period for each of the bit line pairs BL0, / BL0 to BLn, / BLn is completed, the first sense amplifier activation signal SAP is maintained at the “H” level state and is not activated. The configuration.

  FIG. 6 shows operation timings of the column selection switch 41 and the sense amplifier block SAB in the word line batch write mode of the semiconductor memory device according to the second embodiment of the present invention.

  As shown in FIG. 6, first, the word line batch write mode selection signal TEST is set to the “H” level at the beginning of the operation cycle. Thereafter, all the column addresses 0 to y are selected, and all the column selection signals CSEL0 to CSELy transit to the “H” level in the activated state.

  Subsequently, the first sense amplifier external activation signal SAPE transitions to the “L” level. Here, for example, when a test mode determination circuit 42 having a delay circuit 42c composed of an even number of inverters for generating a delay time c as shown in FIG. 7 is used, a first sense amplifier activation signal SAP as an output signal thereof is used. Maintains “H” level. As a result, all the P-channel MOS transistors Qp4 included in the sense amplifier blocks SAB0 to SABy remain inactive.

  On the other hand, at all column addresses 0 to y, the P-channel MOS transistor Qp1 included in each column selection switch 41 is inactive because each column selection signal CSEL0 to CSELy is at “H” level. Since the second sense amplifier external activation signal SANE is also changed to the “L” level simultaneously with the first sense amplifier external activation signal SAPE signal, and the sense amplifier stop signal SAND is in the “L” level state, P Channel type MOS transistors Qp2 and Qp3 are activated. As a result, the second sense amplifier activation signals SAN0 to SANy are set to the “H” level, and the ground potential is supplied to the sense amplifier from each N-channel MOS transistor Qn4. As a result, only the potential of the bit line BL0 on the “L” level side is amplified in the data read from the memory cell 30.

  Subsequently, the sense amplifier stop signal SAND is changed to “H” level so that data is written to each memory cell 30 connected to the selected one word line WL, and each column selection switch Inactivate the P-channel MOS transistor Qp3 included in 41, while activating the N-channel MOS transistor Qn3. At this time, in all the column addresses 0 to y, the N-channel MOS transistors Qn1 are in the active state with the column selection signals CSEL0 to CSELy being at the “H” level, and thus the second sense amplifier activation signals SAN0 to SAN0. SANy temporarily becomes "L" level, and N-channel MOS transistor Qn4 is deactivated. Further, the first sense amplifier activation signal SAP is at “H” level, and all the P-channel MOS transistors Qp4 included in the sense amplifier blocks SAB0 to SABy maintain the inactive state.

  As described above, in each sense amplifier block SAB0-SABy, the N-channel MOS transistor Qn4 that supplies the ground potential to each sense amplifier and the P-channel MOS transistor Qp4 that supplies the power supply potential are inactive. By setting the column selection switch external activation signal YS and the column selection switch activation signals YS0 to YSy to the “H” level for a predetermined time, the bit line pair BL0, / BL0 to BLn, / BLn and the data line pair DL0, / DL0 to DL7, / DL7 are connected to each other through an N-channel MOS transistor Qn6, and data in all columns is rewritten.

  Subsequently, the signal level of the first sense amplifier activation signal SAP is maintained at the “H” level for the delay time c by the test mode determination circuit 42, and then is set to the “L” level for a predetermined time. By setting the activation signals SAN0 to SANy to the “H” level, the N-channel MOS transistor Qn4 that supplies the ground potential to each sense amplifier and the P-channel MOS transistor Qp4 that supplies the power supply potential are activated, and each sense is activated. By starting the amplifier, predetermined data is written in each memory cell 30.

  As described above, according to the second embodiment, when data is written to the bit line pairs BL0, / BL0 to BLn, / BLn that access the memory cells 30 connected to one word line WL, the sense amplifier is used. Writing from the data line pairs DL0, / DL0 to DL7, / DL7 becomes extremely easy by deactivating the P-channel MOS transistor Qp4 and the N-channel MOS transistor Qn4 that supply the power supply potential and the ground potential, respectively. Therefore, in the batch write operation mode, the write cycle can be greatly shortened as compared with the conventional case, so that it is possible to evaluate the rewrite endurance in a short time.

  In addition, the first sense amplifier activation signal SAP is maintained in the “H” level inactive state until the write period for each of the bit line pairs BL0, / BL0 to BLn, / BLn is completed. Since the data on the “H” level side read to the line pairs BL0, / BL0 to BLn, / BLn is not amplified, the data rewrite is further facilitated, and the write cycle is made easier in the batch write operation mode. Therefore, it is possible to evaluate the rewrite resistance in a shorter time.

  Note that the same effect can be obtained even when the second sense amplifier activation signal SAN0 is the only signal that does not activate until the write period for each bit line pair BL0, / BL0 to BLn, / BLn is completed. Needless to say.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  The third embodiment shows still another form of operation in the word line batch write mode using a circuit configuration equivalent to that of the semiconductor memory device according to the first embodiment.

  That is, until the write period for each of the bit line pairs BL0, / BL0 to BLn, / BLn is completed, the first sense amplifier activation signal SAP is set to the “H” level and the second sense amplifier activation signals SAN0 to SAN0. SANy is set to “L” level, and both are not activated.

  FIG. 8 shows operation timings of the column selection switch 41 and the sense amplifier block SAB in the word line batch write mode of the semiconductor memory device according to the third embodiment of the present invention.

  As shown in FIG. 8, first, the word line batch write mode selection signal TEST is set to the “H” level at the beginning of the operation cycle. Thereafter, the sense amplifier stop signal SAND is shifted to the “H” level, all the column addresses 0 to y are subsequently selected, and all the column selection signals CSEL0 to CSELy are all shifted to the “H” level in the activated state. To do. As a result, the column selection signals CSEL0 to CSELy and the sense amplifier are stopped even if the second sense amplifier external activation signal SANE is set to “L” level and the N-channel MOS transistor Qn2 in the column selection switch 41 is deactivated. Since both of the signals SAND are at the “H” level, the P-channel MOS transistors Qp1 and Qp3 are inactive and the N-channel MOS transistors Qn1 and Qn3 are active. Therefore, the second sense amplifier activation signals SAN0 to SANm all become “L” level, and the N-channel MOS transistor Qn4 in the sense amplifier maintains the inactive state.

  Even if the first sense amplifier external activation signal SAPE transitions to the “L” level at the same time as the second sense amplifier external activation signal SANE becomes the “L” level, for example, as shown in FIG. By using the test mode determination circuit 42 having the same configuration as that of the second embodiment, the first sense amplifier activation signal SAP, which is the output signal thereof, maintains the “H” level, so that each of the sense amplifier blocks SAB0 to SABy. All of the P-channel MOS transistors Qp4 included in are kept inactive. Therefore, neither “H” level data nor “L” level data is amplified in the data read from the memory cell 30 activated by the designated word line WL.

  Subsequently, while the N-channel MOS transistor Qn4 and the P-channel MOS transistor Qp4 are inactive, the column selection switch external activation signal YS and the column selection switch activation signals YS0 to YSy are set to “H” for a predetermined time. By setting the level, the bit line pairs BL0, / BL0 to BLn, / BLn and the data line pairs DL0, / DL0 to DL7, / DL7 are respectively connected via the N-channel MOS transistor Qn6, and the data of all columns Is rewritten.

  Subsequently, the first sense amplifier activation signal SAP is set to the “L” level and the second sense amplifier activation signals SAN0 to SANy are set to the “H” level only for a predetermined period, thereby supplying the ground potential to each sense amplifier. The N-channel MOS transistor Qn4 and the P-channel MOS transistor Qp4 that supplies the power supply potential are activated to activate each sense amplifier, whereby predetermined data is written to each memory cell 30.

  As described above, according to the third embodiment, when data is written to the bit line pairs BL0, / BL0 to BLn, / BLn for accessing the memory cells 30 connected to one word line WL, the sense amplifier is used. Writing from the data line pairs DL0, / DL0 to DL7, / DL7 becomes extremely easy by deactivating the P-channel MOS transistor Qp4 and the N-channel MOS transistor Qn4 that supply the power supply potential and the ground potential, respectively. .

  In addition, in the third embodiment, the first sense amplifier activation signal SAP is set to the “H” level until the write period for the bit line pairs BL0, / BL0 to BLn, / BLn is completed, and the second When the sense amplifier activation signals SAN0 to SANy are set to “L” and none of them is activated, the “H” level and “L” level read to each of the bit line pairs BL0, / BL0 to BLn, / BLn are set. Data is not amplified. As a result, data rewriting is further facilitated, so that even in the batch write operation mode, the write cycle can be further shortened compared to the prior art, and the rewrite endurance can be evaluated in a short time.

  Since the semiconductor memory device according to the present invention can shorten the write cycle in the word line batch write operation mode as compared with the conventional one without increasing the layout area, it is possible to evaluate the rewrite durability in a short time. This is useful for a semiconductor memory device capable of performing a word line batch rewrite operation during rewrite endurance evaluation.

1 is a circuit block diagram showing a semiconductor memory device according to first to third embodiments of the present invention. FIG. 4 is a configuration diagram showing a sense amplifier block, a bit line pair, a data line pair, and a memory cell in the semiconductor memory device according to the first to third embodiments of the present invention. FIG. 5 is a configuration diagram showing a test mode determination circuit, a column selection switch, and a sense amplifier block in the semiconductor memory device according to the first to third embodiments of the present invention. FIG. 1 is a detailed configuration diagram illustrating an example of a test mode determination circuit in a semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a timing chart showing operations of the column selection switch and the sense amplifier block in the word line batch write mode of the semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a timing chart showing the operation of the column selection switch and the sense amplifier block in the word line batch write mode of the semiconductor memory device according to the second embodiment of the present invention. FIG. 5 is a detailed configuration diagram showing an example of a test mode determination circuit in a semiconductor memory device according to a second embodiment of the present invention. FIG. 10 is a timing chart illustrating operations of a column selection switch and a sense amplifier block in a word line batch write mode of a semiconductor memory device according to a third embodiment of the present invention. It is a circuit block diagram showing a conventional ferroelectric memory device. It is a block diagram showing a column selection switch and a sense amplifier block in a conventional ferroelectric memory device. It is a block diagram showing a sense amplifier block, a bit line pair, a data line pair and a memory cell in a conventional ferroelectric memory device. FIG. 10 is a timing chart showing operations of a column selection switch and a sense amplifier block in a word line batch write mode of a conventional ferroelectric memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor memory device 20 Memory cell array 21 Sense amplifier SAB Sense amplifier block 22 Address buffer 23 Row decoder 24 Column decoder 25 Control circuit 26 I / O buffer 30 Memory cell 40 Test mode determination circuit 41 Column selection switch 40a First delay circuit 40b Second delay circuit 401 AND gate 402 OR gate 42 Test mode determination circuit 42c Delay circuit Qp4 P-channel MOS transistor (power supply transistor)
Qn4 N-channel MOS transistor (power supply transistor)

Claims (9)

A plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines;
A plurality of differential amplification type sense amplifiers respectively connected to the plurality of bit lines;
The plurality of bit lines and a plurality of data lines connected through the sense amplifiers,
Each of the sense amplifiers includes a power supply transistor having a source connected to a power supply potential or a ground potential,
The power supply transistor is in a word line batch write operation mode for writing to all of the memory cells connected to one of the plurality of word lines, and each bit line and each data A semiconductor memory device, wherein the semiconductor memory device is inactivated in a data writing period in which a line is connected.   2. The sense amplifier according to claim 1, wherein each of the sense amplifiers performs a sensing operation by activating the power supply transistor included in each of the sense amplifiers after the data writing period ends. Semiconductor memory device. The plurality of bit lines are composed of a plurality of bit line pairs that can take a complementary potential.
Each of the sense amplifiers is connected to one of the plurality of bit line pairs, and activates the power supply transistor after the polarities of the pair of bit lines are mutually inverted in the data write period The semiconductor memory device according to claim 1, wherein a sense operation is performed. A plurality of memory cells respectively connected to a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines;
A plurality of differential amplification type sense amplifiers respectively connected to the plurality of bit lines;
The plurality of bit lines and a plurality of data lines connected through the sense amplifiers,
Each of the sense amplifiers includes a power supply transistor having a source connected to a power supply potential or a ground potential,
The power supply transistor is in a word line batch write operation mode for writing to all of the memory cells connected to one of the plurality of word lines, and each bit line and each data A semiconductor memory device which is inactive in a data writing period in which a line is connected and in a period before the data writing period.   5. The semiconductor memory device according to claim 1, wherein the power supply transistor is an N-channel transistor.   5. The semiconductor memory device according to claim 1, wherein the power supply transistor is a P-channel transistor.   2. The power supply transistor whose source is connected to a power supply potential is a P-channel transistor, and the power supply transistor whose source is connected to a ground potential is an N-channel transistor. 5. The semiconductor memory device according to 4.   5. The mode determination circuit according to claim 1, further comprising a mode determination circuit that is shared by the plurality of bit lines and switches between the normal operation mode and the word line batch write operation mode for each of the sense amplifiers. The semiconductor memory device described. The mode determination circuit includes:
An AND gate receiving a first signal representing the word line batch write operation mode at one input terminal;
An OR gate that receives a significant second signal in one input terminal during the normal operation mode and the word line batch write operation mode and receives the output of the AND gate in the other input terminal;
9. The semiconductor memory device according to claim 8, wherein the AND gate receives a delayed signal obtained by delaying the second signal at another input terminal.

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