JP2005063293A - High speed interface power management system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high speed interface power management system capable of efficiently reducing electric power consumption by a combination of a transfer rate and a communication protocol. <P>SOLUTION: The high speed interface power management system includes a clock control state machine 112 carrying out state transition on the basis of a state signal outputted from circuits 105-109 divided by the transfer rate and the communication protocol, and gate circuits 113-118 carrying out supply stoppage of a clock when a control signal outputted from the clock control state machine 112 is received. During high speed idling, clock supply is carried out to only an HSDLL 110 and an elasticity buffer 111. During high speed reception, clock supply is carried out to an HS data reception circuit 106 in addition to those in high speed idling. During high speed transmission, clock supply is carried out to only an HS data/device chirp transmission circuit 105. Clock supply stoppage is carried out in response to transmission/reception/idling during low speed transfer also to save power. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an interface having a plurality of transfer speeds and communication protocols, and more particularly, to a high-speed interface power management apparatus for performing USB 2.0 clock control.

  In recent years, it has a transfer speed of 480 Mbps, which is an extension of USB (Universal Serial Bus) 1.1, which has a transfer speed of 12 Mbps, as an interface standard for connecting personal computers and peripheral devices. USB 2.0 has been used as a standard interface for personal computers.

A conventional high-speed interface power management apparatus will be described below. The conventional high-speed interface power management device has a PLL that is used for high-speed transfer at 480 Mbps and low-speed transfer at 12 Mbps. During high-speed transfer, the PLL is used for high-speed transfer to supply clocks to high-speed circuits, and low-speed transfer In some cases, a low-speed transfer PLL is used to supply a clock to the low-speed circuit, and the clock supply is stopped by switching the PLL to save power (for example, see Patent Document 1).
JP 2002-141911 (page 6, FIG. 1)

  However, in the above conventional method, once the PLL oscillation is stopped, a long time on the order of μs is required until the PLL oscillation is started. For this reason, if clock control is performed in a short time of the ns order according to the communication protocol, the interpacket delay time defined by USB may not be satisfied. The interpacket delay is the time until the USB device mounted on the peripheral device responds to the data sent from the USB host mounted on the personal computer. For this reason, there is a problem in that it is not possible to save power by combining the transfer rate and the communication protocol only by controlling the PLL.

  The present invention takes the following means in order to solve the above problems.

  In order to achieve this object, the high-speed interface power management apparatus of the present invention includes one PLL, each circuit according to the transfer rate and the communication protocol, a detection circuit, and a control circuit for stopping the clock supply.

  With this configuration, the detection circuit detects each state of HS (High Speed) / FS (Full Speed) / chirp and transmission / reception / idle, outputs a signal corresponding to each state, and inputs it to the control circuit Since the clock of the circuit can be immediately stopped according to each state, the maximum power saving can be achieved by using one PLL.

  Expanding at a more specific level, each configuration is as follows.

  The high-speed interface power management device of the first solving means has a different configuration depending on a plurality of transfer speeds and communication protocols, receives a status signal output from the configuration, detects a status, and outputs from the detection circuit And a control circuit for stopping the supply of the input clock to the configuration according to the control signal, and reducing the power consumption by combining the transfer rate and the communication protocol.

  The configuration of the first solution is from an HS (high speed) data circuit / chirp transmission circuit, an HS data reception circuit, an FS (low speed) data transmission circuit, an FS data reception circuit, and a constant clock supply circuit (including a chirp reception circuit). An HSDLL (High Speed Delay Line PLL) that supplies a clock only when the detection circuit is in the HS idle state and the HS data reception state, and an elasticity buffer.

  In the above configuration, the detection circuit includes an FS idle state, an FS transmission state, an FS reception state, an HS idle state, an HS transmission / device chirp state, an HS reception state, and a host chirp state.

  In the above configuration, the detection circuit performs transition at the lowest frequency at which data can be normally received on the receiving side.

  Further, in the above configuration, the detection circuit separates the FS state and the HS / chirp state by using an HS driver that drives differential data of the communication bus and a signal that controls the FS driver, and an HS transmission state and a chirp transmission. The state is also used.

  In the above configuration, the detection circuit uses the output of the squelch differential receiver as a control signal for transition from the HS idle state to the HS reception state.

  In the above configuration, the detection circuit shifts from the HS data transmission / chirp transmission state of the detection circuit configured to perform transition at the lowest frequency at which data can be normally received on the reception side when shifting from the handshake protocol to the HS mode. A signal for controlling the termination resistance of the communication bus and an output signal of the squelch differential receiver are used as signals for transition to the HS idle state through the host chirp state.

  According to the present invention, by providing a circuit divided according to the transfer rate and communication protocol and a control circuit such as a clock control state machine, it is possible to efficiently stop the supply of clocks to the circuit and save power. An excellent high-speed interface power management device can be realized.

  Embodiments of a high-speed interface power management apparatus according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a high-speed interface power management apparatus (USB 2.0) according to an embodiment of the present invention.

  Here, a clock control state machine 112 is used as a detection circuit, and gate circuits 113 to 118 are used here as control circuits. Further, XCVRSELECT is used as a signal for controlling the HS driver 119 and the FS driver 120 for driving D + and D−, and TERMSELECT is used as a signal for controlling the switch 123 of the 45 ohm termination resistor 122 of D + and D−. HS_ENV_OUT is used as the output of the dynamic driver 121. XCVRSELECT is a signal for enabling the HS driver when “0” and for enabling the FS driver when “1”. TERMSELECT is a signal that enables HS termination when “0” and enables FS termination when “1”.

  In FIG. 1, 101 is a 12 MHz crystal oscillator, 102 is a PLL that multiplies a 12 MHz clock by 40 to generate a 480 MHz clock, and 103 is a 1/4 frequency that generates a 120 MHz clock from a 480 MHz clock generated by the PLL 102. The circuit, 104 is a 1/8 frequency dividing circuit that generates a 60 MHz clock from the 480 MHz clock generated by the PLL 102, 105 is an HS data / device chirp transmission circuit that only needs to supply a 120 MHz clock during HS transmission, and 106 is HS data receiving circuit that needs to supply a clock of 120 MHz only when receiving HS, 107 an FS data transmitting circuit that needs to supply a clock of 60 MHz only when transmitting FS, and 108 that only needs to supply a clock of 60 MHz only when receiving FS FS data receiving circuit 109 is a constant clock supply circuit that always needs to supply clocks of 60 MHz and 120 MHz, and 110 is an HSDLL (High Speed Delay Line PLL) that only needs to supply an 8-phase clock generated by the PLL only during HS idle and HS reception. , 111 is an elasticity buffer (ElasticityBuffer) that only needs to supply a clock of 120 MHz when HS idle and HS is received, 112 receives state signals output by the circuits 105 to 109, and changes the state. The clock control state machines 113 to 116 for generating a control signal necessary for stopping the clock supply in the circuit 113 and 116 receive the clock generated from the clock divider circuits 103 and 104 and the signal output from the clock control state machine 112 as inputs. To stop supplying the clock supplied to .about.108 It is a gate circuit.

  The operation of the USB 2.0 power management apparatus, which is the high-speed interface of the present embodiment configured as described above, will be described below.

  First, as shown in the timing chart of FIG. 3, when a USB cable is connected and a voltage VBUS of 5V on the USB bus is supplied, clock oscillation starts at timing T0. When the RESET signal becomes active at timing T1, the transition of the clock control state machine 112 starts.

  FIG. 2 shows functions of the clock control state machine of FIG. 1, and state transition is performed by a rising clock of 60 MHz. The RESET signal is set to “1”, and a transition is made to the FS idle state (STATE [7: 0] = 8′h01). At this time, since all the control signals output from the clock control state machine 112 are in the “0” state, the outputs of the gate circuits 113 to 116 are all fixed to “1”, except for the constant clock supply circuit 109. The clock to circuits 105-108 is stopped.

  Next, USB 2.0 enters a handshake protocol for HS transfer or FS transfer. FIG. 4 is a timing chart when entering HS transfer from the handshake protocol. Since the USB device transmits a chirp to the USB host at timing T0, XCVRSELECT is set to “0”, and TXVALID is set to “1”. This XCVRSELECT is set to “1” at the time of HS transfer and device chirp, and is switched to “0” at the time of FS transfer to switch between the HS driver 119 and the FS driver 120. After the setting, STATE [7: 0] = 8′h08 is changed at the rising timing T1 of the 60 MHz clock CLK60. In FIG. 2, this means that the FS idle state has changed to the HS idle state. At this time, the HS_DLL_EB signal becomes “1”, but the TERMSELECT is “1” and the outputs of the gates 117 and 118 are fixed to “1”. Therefore, the clock to the HS_DLL 110 and the elasticity buffer 111 is stopped. The

  Next, STATE [7: 0] = 8′h20 is changed at timing T2 at the rising edge of CLK60. In FIG. 2, this means that the transition from the HS idle / chirp state to the HS transmission / device chirp state has occurred. At this time, since the USB device transmits a chirp to the USB host, the HS_TX signal becomes “1”, and only the TX_CLK 120 clock passes through the gate 113 to transmit the device chirp to the HS data / device chirp transmission circuit 105. To be supplied.

  At time T3, device chirp ends, and at time T4, host chirp starts.

  It changes to STATE [7: 0] = 8'h40 at the rising timing T5 of the clock CLK60 of 60 MHz. This means that, in FIG. 2, the transition is from the HS transmission / device chirp transmission state to the host chirp 1 state. At this time, since all the control signals output from the clock control state machine 112 are “0”, the clock is supplied only to the constant clock supply circuit 109 for receiving the host chirp.

  D + / D− KJ from the host (K is D +, D− differential is Low, J means High) is detected and the transition to the HS mode is made at timing T6, and the TERMSELECT is “ When it becomes 0 ″, STATE [7: 0] = 8′h80 is changed. This means that in FIG. 2, the host chirp 1 state has transitioned to the host chirp 2 state. Although in the HS mode, since the host chirp is transmitted, the clock is continuously supplied only to the clock supply circuit 109 continuously.

  Since host chirp ends at timing T7, STATE [7: 0] = 8'h08 changes at the rising edge of CLK60 at timing T8. In FIG. 2, this means that the host chirp 2 state has transitioned to the HS idle state. A clock is supplied to the HSDLL 110 and the elasticity buffer 111 in order to make the HS transmission from the host ready.

  FIG. 5 is a timing chart when the FS transfer is entered from the handshake communication protocol. Up to T5, the process is the same as when entering HS transfer.

  Since the host chirp is not sent at the timing T6, the mode shifts to the FS mode, and the XCVRSELECT becomes “1”. Timing STATE [7: 0] changes to 8'h01. In FIG. 2, this means that the host chirp 1 state has changed to the FS idle state.

  FIG. 6 is a timing chart at the start of HS reception. The SYNC pattern starts from timing T0, followed by a USB packet. At the time of reception, the USB device generates a data clock from the SYNC pattern, and uses this clock to receive a USB packet in synchronization with the USB host. After KJ (K is D +, D− differential is Low, J is High) continues for 10 bits, it ends with KK. Originally, the SYNC pattern is a 32-bit pattern in which the continuous data of KJ is 30 bits and 2 bits of KK. The SYNC pattern shown in the timing chart is a waveform when a 5-bit USB-HUB is connected between the USB host and the USB device and a 12-bit SYNC pattern, which is the minimum bit when the 12-bit SYNC pattern is missing, is received. It has become.

  In order for the HS data receiving circuit 106 to recognize the SYNC pattern, it is necessary to correctly receive a total of 6 bits including 4 bits of continuous data of KJ and 2 bits of KK as data. Since the time when the SYNC pattern is received at T0 and the squelch differential receiver 121 reacts is 3 bits, the output signal HS_ENV_OUT of the squelch differential receiver 121 becomes “0” at timing T1, and HS_SERIAL_DATA is output from the HS differential receiver. Is output.

  Since HS_SERIAL_DATA is input to the HS DLL 110 and the time for generating the data clock is 1 bit, the data clock DCLK 480 is generated at timing T2. HS_SERIAL_DATA is synchronized with this clock and output to the elasticity buffer 111. Serial-parallel conversion is performed from 1-bit data to 4-bit data. KJKJ 4-bit serial data is output as parallel data 4 ′ ha at the rising edge of the 120 MHz clock CLK 120 at timing T 3 and input to the HS data receiving circuit 106.

  At the same time, HS_ENV_OUT is “0” at timing T1, so the clock control state machine in FIG. 2 transitions from the HS idle state to the HS reception state at the rising edge of the 60 MHz clock CLK60, and the clock is sent to the HS data reception circuit 106. Will be supplied. At the rising edge of CLK 120 at timing T 5, KJKK 4-bit serial data is output as parallel data 4 ′ h 2 and input to the HS data receiving circuit 106. Further, the 4'ha data changed at timing T3 at the rising edge of CLK120, that is, the first 4 bits of the SYNC pattern is received by the HS data receiving circuit 106, and the 4'h2 data at the rising edge of CLK120 at timing T6, that is, SYNC. Since the remaining 4 bits of the pattern are received by the HS data receiving circuit 106, the circuit normally processes the SYNC pattern.

  As described above, according to the present embodiment, each circuit configuration based on the transfer rate and communication protocol, the clock control state machine, and the gate circuit configuration make it possible to stop the clock supply in a few ns or less, which is optimal. Power consumption can be reduced.

  In addition, the HS DLL and elasticity buffer used when receiving HS data are made independent of the HS data receiving circuit, the clock is made a separate system, and the clock is supplied only in the HS idle state and the HS receiving state. Can immediately respond to the 480 Mbps SYNC pattern, and can reduce power consumption optimally within a range where data can be normally received.

  In addition, the power consumption can be reduced optimally by performing the state machine transition at the minimum frequency of 60 MHz at which the received data can be normally received by the HS data receiving circuit.

  In addition, by combining the HS data transmission state and the chirp transmission state that can be used in common, it is possible to configure a clock control state machine having a minimum circuit scale.

  In addition, the host chirp state is divided into the host chirp 1 state and the host chirp 2 state, TERMSELECT is used for transition from the host chirp 1 state to the host chirp 2 state, and HS_ENV_OUT is used for the transition from the host chirp 2 state to the HS idle state. By using this, it is possible to configure a circuit that enables clock control during host chirp with a minimum circuit scale without detecting the KJKJKJ signal of the host chirp.

  Although the USB has been described as an example, it is needless to say that the present invention can be applied to communication methods other than USB.

  The high-speed interface power management apparatus of the present invention is useful for an interface having a plurality of transfer speeds and communication protocols, particularly when performing USB 2.0 clock control.

The circuit diagram which shows the structure of the clock control circuit of USB2.0 in embodiment of this invention State transition diagram of clock control state machine in the embodiment of the present invention Timing waveform diagram immediately after the USB bus connection in the embodiment of the present invention HS detection handshake timing waveform chart at the time of transition to the HS mode in the embodiment of the present invention HS detection handshake timing waveform diagram at the time of transition to FS mode in the embodiment of the present invention Timing waveform diagram at the start of HS reception in the embodiment of the present invention

Explanation of symbols

101 12 MHz crystal oscillation 102 40-fold PLL for 480 MHz clock generation
103 1/4 frequency divider for 120 MHz clock generation 104 1/8 frequency divider for 60 MHz clock generation 105 HS data transmission / chirp transmission circuit 106 HS data reception circuit 107 FS data transmission circuit 108 FS data reception circuit 109 Constant clock supply circuit 110 HS DLL
111 Elasticity Buffer 112 Clock Control State Machine 113-118 Clock Supply / Stop Gate Circuit 119 HS Driver 120 FS Driver 121 Squelch Differential Receiver 122 45 Ohm Termination Resistor

Claims (7)

A detection circuit that has a different configuration depending on a plurality of transfer rates and communication protocols, receives a status signal output from the configuration, and detects a status, and supplies an input clock to the configuration by a control signal output from the detection circuit A high-speed interface power management device comprising a control circuit for stopping and optimizing a reduction in power consumption by a combination of a transfer rate and a communication protocol. The configuration according to claim 1 includes an HS (high speed) data circuit / chirp transmission circuit, an HS data reception circuit, an FS (low speed) data transmission circuit, an FS data reception circuit, and a constant clock supply circuit (including a chirp reception circuit). And a high-speed interface power management apparatus comprising an HSDLL and an elasticity buffer for supplying a clock only when the detection circuit is in an HS idle state and an HS data reception state. 2. The high-speed interface power management apparatus according to claim 1, wherein the detection circuit comprises an FS idle state, an FS transmission state, an FS reception state, an HS idle state, an HS transmission / device chirp state, an HS reception state, and a host chirp state. 2. The high-speed interface power management apparatus according to claim 1, wherein the detection circuit performs transition at a lowest frequency at which data can be normally received on the receiving side. The detection circuit according to claim 1, using an HS driver that drives differential data of a communication bus and a signal that controls the FS driver, separates the FS state and the HS / chirp state, and sets the HS transmission state and the chirp transmission state. A high-speed interface power management device that is also used in combination. 2. The high-speed interface power management device according to claim 1, wherein the output of the squelch differential receiver is used as a control signal for transition from the HS idle state to the HS reception state. When the detection circuit according to claim 1 shifts from the handshake protocol to the HS mode, the detection circuit according to claim 4 changes from the HS data transmission / chirp transmission state to the HS idle state through the host chirp state. A high-speed interface power management apparatus using a signal for controlling a termination resistance of a communication bus and an output signal of a squelch differential receiver.

Images