JP2005057263A - Etching method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a etching method for eliminating problems such as unetching or an unopen phenomenon. <P>SOLUTION: An wafer having dielectric layers 14, 16 and an electrode 15' partially projected from a top surface of the dielectric layers 14, 16 is provided. An etching liquid 24 is added to the dielectric layers 14, 16. In this case, in order to prevent air bubbles 27 included in the etching liquid 24 from adhering to the electrode 15', before etching using the etching liquid 24, the projection section is covered with a buffer layer 21 to prevent the air bubbles 27 included in the etching liquid 24 from adhering to the electrode 15'. Therefore, the dielectric layers 14, 16 can be etched using the etching liquid 24 without receiving disturbance by the air bubbles 27 included in the etching liquid 24. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an etching method for manufacturing a semiconductor device such as a lower electrode of a capacitor.

When manufacturing a semiconductor device such as a DRAM (Dynamic Random Access Memory) device, a chemical solution (LAL) or dilution containing hydrogen fluoride (HF) and ammonium fluoride (NH ₄ F) is used in various stages of the semiconductor manufacturing process. Chemical solutions such as oxidized oxide etchant (BOE) are typically used for etching the dielectric layer.

  Unfortunately, additives such as surfactants typically included in chemical solutions cause undesirably various sized bubbles to be generated in the chemical solution. Such bubbles often adhere to the surface of the semiconductor substrate and cause serious problems such as unetching or unopening of the oxide film.

  As design rules decrease, these problems become more serious and significantly reduce production yields. For example, as the lower electrode of the capacitor becomes more circular due to the reduction of the design rule, the bubbles are more easily attached to the lower electrode, resulting in various problems such as an unopened phenomenon.

Therefore, there is an urgent need to develop a new etching method that can solve the problems caused by bubbles contained in the chemical solution.
Korean Published Patent No. 1996-015076 JP 2002-299214 A

  The present invention is to manufacture a semiconductor device free from problems such as unetching or unopened phenomenon caused by bubbles contained in a chemical solution when the dielectric layer is etched using a chemical solution such as LAL. An etching method is provided.

  According to an embodiment of the present invention, a wafer including an electrode having a dielectric layer and a protruding portion partially protruding from an upper surface of the dielectric layer is provided. Then, a chemical solution or an etching solution is added to the dielectric layer to prevent bubbles contained in the chemical solution from adhering to the electrode. In order to prevent bubbles from adhering to the electrode, a buffer layer that covers the protrusions is formed to prevent the bubbles contained in the chemical solution from adhering to the electrode before performing the etching process.

  According to the technical idea of the present invention disclosed herein, the bubbles contained in the chemical solution are transferred to the structure such as the capacitor lower electrode while the etching process of the dielectric layer proceeds. Adhesion can be prevented. Therefore, the dielectric layer can be etched using a chemical solution such as LAL without being disturbed by bubbles contained in the chemical solution. Therefore, if the embodiment of the present invention is used, it is possible to prevent a device failure such as a 1-bit failure caused by an unetching phenomenon, thereby improving the yield.

  According to the present invention, it is possible to prevent an element defect such as a one-bit defect caused by an unetching phenomenon. Therefore, according to the present invention, the yield can be increased considerably.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided by way of example only so that the technical spirit of the present invention can be disclosed thoroughly and thoroughly and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the form of the components is exaggerated for clarity. The same reference numerals denote the same components throughout the specification.

  Referring to FIG. 1A, an interlayer insulating layer 11 or a spare metal dielectric layer is formed on a wafer or a semiconductor substrate 10 in order to manufacture a capacitor of a semiconductor device such as a DRAM. The interlayer insulating layer 11 can be formed of a dielectric material such as silicon oxide.

  Although not shown, a lower structure such as a source / drain region and a gate electrode may be formed on the semiconductor substrate 10 to form a transistor or a memory cell.

  Next, the storage node contact pad 12 is formed on the interlayer insulating layer 11 using a normal technique, and is electrically connected to the lower electrode of the capacitor formed thereon. Storage node contact pad 12 is electrically connected to the active region of semiconductor substrate 10 again. Subsequently, the interlayer insulating layer 11 is planarized.

  Next, an etching stopper layer 13 is formed on the interlayer insulating layer 11. The etch stop layer 13 has a high etch selectivity with respect to the first dielectric layer 14. Such a layer may be formed using conventional conventional manufacturing methods. The etch stop layer 13 may be formed to a thickness of about 500 to 1000 mm using, for example, silicon nitride.

  A first dielectric layer 14 is formed on the etch stop layer 13. The etching stop layer 13 serves as an etching stop point in a subsequent etching lift-off process for removing not only the first dielectric layer 14 but also the second dielectric layer 16 formed thereon.

  The first dielectric layer 14 is preferably formed of silicon oxide having a thickness of about 3000 to 20000 using a conventional method such as a low temperature chemical vapor deposition (LPCVD) process. The first dielectric layer 14 may be a single film of PE-TEOS (plasma-enhanced tetraethylorthosilicate) or a composite film including a PE-TEOS layer.

  Referring to FIG. 1B, the first dielectric layer 14 is etched or patterned using the etch stop layer 13 as an etch stop point to define a storage node opening 18 that exposes a portion of the contact pad 12 as a first dielectric. Formed on body layer 14. Etching or patterning the first dielectric layer 14 uses conventional photolithography and etching processes. Then, the etching stopper layer 13 exposed through the storage node opening 18 is removed.

  Referring to FIG. 1C, the conductive film 15 made of a material such as doped polysilicon, Pt, Ru, or TiN includes the opening 18 to form a capacitor lower electrode 15 ′ (see FIG. 1D). Formed on first dielectric layer 14 and storage node contact pad 12.

  Next, a second dielectric layer 16 is formed on the conductive film 15 connected to the storage node contact pad 12 and in the opening 18. The second dielectric layer 16 is preferably formed of silicon oxide with a thickness of about 10,000 to 30,000 mm. As will be apparent to those skilled in the art, other suitable dielectric materials other than silicon oxide may be used to form the first dielectric layer 14 and the second dielectric layer 16.

  Referring to FIG. 1D, the first dielectric layer 14 and the second dielectric layer 16 including the conductive film 15 are flattened until the upper surfaces of the first dielectric layer 14 and the second dielectric layer 16 are exposed. The capacitor lower electrode 15 ′ separated into nodes is formed.

  The planarization process may be performed using a normal process such as chemical mechanical polishing (CMP) or an etch back process. When the CMP process is used, it is desirable to use a slurry having an etching selectivity with respect to the capacitor lower electrode 15 ′ and the first dielectric layer and the second dielectric layers 14 and 16. When the etch back process is used, it is desirable to use an etchant having an etching selectivity with respect to the capacitor lower electrode 15 ′ and the first dielectric layer and the second dielectric layers 14 and 16.

  Referring to FIG. 1E, HF is preferably used in the cleaning process for removing the etch-back residue or the CMP residue generated as a result of the planarization process. For this reason, for example, the upper part of the circular or elliptical capacitor lower electrode 15 ′ protrudes from the surface of the dielectric layers 14 and 16 due to the wet cleaning process using HF. This is because HF does not substantially etch the capacitor lower electrode formed of polysilicon, but selectively etches a dielectric layer such as a silicon oxide film. In this cleaning step for removing the residue, other appropriate cleaning liquid known in this field may be used.

  Referring to FIG. 1G, the capacitor lower electrode 15 'is completed by simultaneously removing the first dielectric layer 14 and the second dielectric layer 16 using a conventional lift-off process. In particular, the first dielectric layer 14 and the second dielectric layer 16 are etched using a chemical solution such as LAL. In this wet etching process, an etching solution such as LAL whose composition is shown in Table 1 is generally used. However, other appropriate wet etchants other than LAL may be used.

  However, as shown in FIG. 2A, bubbles in a chemical solution or an etchant such as LAL easily adhere to the protruding portion of the capacitor lower electrode 15 '. Such bubble adhesion is particularly likely to occur when the plane of the capacitor lower electrode 15 ′ is circular or elliptical, because this allows the bubbles to be easily captured.

  As the design rules get smaller, this problem becomes more important, as the undesired bubbles trapped in the capacitor lower electrode 15 'block the contact between the chemical solution such as LAL and the dielectric layer 16. As a result, as shown in FIGS. 2B and 2C, an unetching or unopened phenomenon occurs. In other words, due to the bubbles 27 present in the chemical solution 24, a portion of the second dielectric layer 16 remains unetched, thus blocking contact between the chemical solution 24 and the second dielectric layer 16. End up. This also prevents removal of the second dielectric layer 16.

  In order to solve such a problem, in this embodiment, referring to FIG. 1F, a conventional lift-off process, that is, wet etching for removing the first dielectric layer 14 and the second dielectric layer 16 is performed. Before the process is performed, the protruding portion and / or the upper end portion of the capacitor lower electrode 15 ′ is covered with the buffer layer 21, and the bubbles 27 contained in the chemical solution or the etching solution 24 are attached to the electrode 15 ′ or the semiconductor substrate 10. Alternatively, contact is prevented. The buffer layer 21 may cover substantially any upper surface of the semiconductor substrate 10.

  Desirably, a chemical solution or etchant 24 is added over the dielectric layers 14 and 16 before the buffer layer 21 covering the protrusions of the electrode 15 'is substantially dried. More preferably, the chemical solution or etchant 24 is added onto the dielectric layers 14 and 16 within about 5 minutes after the protrusions of the electrode 15 ′ are covered with the buffer layer 210. Most preferably, the chemical solution or etchant 24 is added onto the dielectric layers 14, 16 within about 2 minutes after the protrusions of the electrode 15 'are covered with the buffer layer 210.

  However, those skilled in the art will appreciate that the present invention is not limited to the embodiments described above. For example, any other process can be used as long as the buffer layer 21 is not substantially dried before the chemical solution or etchant 24 is added to the dielectric layers 14,16. In other words, when the protruding portion of the electrode 15 ′ is sufficiently covered with the buffer layer 21 to start the etching process, it is possible to prevent adhesion of bubbles contained in the chemical solution or the etching solution 24 to the electrode 15 ′. It is desirable. If the protrusion of the buffer layer 21 and then the addition of the chemical solution or etchant 24 to the dielectric layers 14 and 16 are delayed, the buffer layer 21 is excessively dried to achieve the effect of the present invention. There is also a risk that it will not be possible.

  On the other hand, in the conventional technique, the substrate 10 is generally completely dried after the cleaning process is performed before the etching of the dielectric films 14 and 16 as the insulating layers. However, in the embodiment of the present invention, when the chemical solution 24 is added to the dielectric layers 14 and 16, the surface of the substrate 10 is sufficiently covered with the buffer layer 21 in order to prevent the bubbles 27 from adhering to the electrode 15 ′. It is desirable to wet.

  According to one aspect of the present invention, once the etching process is started, the buffer layer 21 does not need to cover the protruding portion of the electrode 15 '. The buffer layer 21 is mixed with the chemical solution 24. Since such an etching process is started in a state where the bubbles 27 are not attached to the electrode 15 ′, the problem caused by the bubbles 27 trapped in the electrode 15 ′ can be solved.

In one embodiment of the present invention, in order to cover the electrode 15 ′ with the buffer layer 21, a hydrophilic liquid may be added to the protruding portion of the electrode 15 ′. The hydrophilic liquid may be deionized water (DIW), hydrogen peroxide (H ₂ O ₂ ), or ozone water (O ₃ ), but is not limited thereto. The hydrophilic liquid is substantially less compared to the chemical solution 24 so that the surface of the substrate 10 including the electrode 15 ′ is sufficiently wetted or covered by the buffer layer 21 having a smaller surface tension. It is desirable to have bubbles or impurities.

  The buffer layer 21 may be formed by spraying a hydrophilic liquid on the upper end portion of the electrode 15 '.

  Further, instead of the play, for example, the buffer layer 21 may be formed by immersing the substrate 10 in the hydrophilic solution 34 using the conventional wet-chemical solution bath 33 as shown in FIG. . In particular, it is desirable to immerse the substrate 10 located on the wafer carrier 32 in the hydrophilic solution 34 using the robot arm 35.

  In addition, this invention is not limited to the said Example. One skilled in the art will recognize that the use of other suitable methods that can prevent the bubble 27 from adhering to the electrode 15 'is equally applicable to the present invention.

  According to the idea of the present invention disclosed in the present specification, bubbles 27 contained in the chemical solution 24 are adhered to, for example, the capacitor lower electrode 15 ′ while the dielectric layer is etched. Can be prevented. Therefore, even when a chemical solution such as LAL is used, the dielectric layers 14 and 16 can be etched without being disturbed by the bubbles 27 contained in the chemical solution.

  Even though the present invention illustrates and describes a method for manufacturing a capacitor, the present invention should not be construed as limited thereto. Without departing from the spirit and scope of the present invention as defined by the claims, the present invention is rather intended to etch that dielectric structure with electrodes and other conductive layers protruding from the top surface of the dielectric structure. The present invention can be applied to any wet etching process using a chemical solution containing bubbles inside.

  The present invention can be applied to the semiconductor device manufacturing industry. In particular, it is applicable in the field of semiconductor manufacturing including a wet etching process.

It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows the etching method which concerns on the Example of this invention. It is sectional drawing which shows that the bubble contained in the chemical solution like LAL is adhering to the circular capacitor lower electrode. It is sectional drawing which shows the unetched part in the capacitor lower electrode caused by the bubble which exists in a chemical solution. FIG. 3 is a plan view of a capacitor lower electrode structure of a semiconductor device showing the closed storage node contact of FIG. 2B showing an unopened phenomenon. It is a schematic diagram which shows the immersion method which concerns on the Example of this invention.

Explanation of symbols

10: Semiconductor substrate,
11 ... Interlayer insulating layer,
12 ... Storage node contact pad,
13 ... Etching prevention layer,
14 ... first dielectric layer,
15 ... Conductor film,
15 '... capacitor lower electrode,
16 ... the second dielectric layer,
18 ... Opening,
21 ... Buffer layer,
24 ... Etching solution,
27 ... Bubbles,
32 ... Wafer carrier,
33 ... Bus
34: hydrophilic solution.

Claims (34)

Providing a wafer comprising a dielectric layer and an electrode partially projecting from an upper surface of the dielectric layer;
Adding an etchant to the dielectric layer;
And preventing the bubbles contained in the etchant from adhering to the electrode, wherein the step of preventing the bubbles from adhering to the electrode includes a buffer layer for the protruding portion of the electrode. An etching method comprising a step of covering.   The etching method according to claim 1, wherein the buffer layer contains a hydrophilic liquid.   The etching method according to claim 2, wherein the hydrophilic liquid is selected from deionized water, hydrogen peroxide, or ozone water.   The etching method according to claim 1, wherein the step of adding the etchant includes a step of adding the etchant onto the dielectric layer before the buffer layer is dried.   The etching method according to claim 1, wherein the step of adding the etching solution is performed within 5 minutes after the protrusion is covered with the buffer layer.   6. The etching method according to claim 5, wherein the step of adding the etchant is performed within 2 minutes after the protrusion covers the buffer layer.   The etching method according to claim 1, wherein the step of preventing the bubbles from adhering to the electrode includes a step of covering the entire upper surface of the substrate including the protruding portion of the electrode with the buffer layer.   2. The etching method according to claim 1, wherein the dielectric layer is made of a silicon oxide film, and the etching solution contains hydrogen, nitrogen, fluorine, and deionized water. The etching method according to claim 8, wherein the etchant includes HF, NH ₄ F, deionized water, and a surfactant. Providing a wafer comprising a dielectric layer and an electrode partially projecting from an upper surface of the dielectric layer;
Etching the dielectric layer with a chemical solution;
And a step of covering the protruding portion with a buffer layer to prevent bubbles contained in the chemical solution from adhering to the electrode before the etching step.   The etching method of claim 10, wherein the etching of the dielectric layer includes adding the etchant onto the dielectric layer before the buffer layer is substantially dried.   The method of claim 10, wherein the etching of the dielectric layer is performed within about 5 minutes after the protrusion is covered with the buffer layer.   The etching method of claim 12, wherein the dielectric layer is etched within about 2 minutes after the protrusion is covered with the buffer layer.   The etching method according to claim 10, wherein the buffer layer is made of a hydrophilic liquid.   The etching method according to claim 14, wherein the hydrophilic liquid is selected from deionized water, hydrogen peroxide, or ozone water.   11. The etching method of claim 10, wherein the step of covering the protrusion includes forming the buffer layer on the upper end of the electrode using a spray method.   The etching method according to claim 10, wherein the step of covering the protrusion includes immersing the wafer in a buffer layer solution made of a material forming the buffer layer. The etching method according to claim 10, wherein the chemical solution contains HF or NH ₄ F. Forming a first dielectric layer on a semiconductor substrate;
Forming an opening in the first dielectric layer;
Depositing a conductor layer on the first dielectric layer including the opening;
Depositing a second dielectric layer covering the conductor layer in the opening;
Planarizing the resultant including the conductive layer until the first dielectric layer is exposed to form a lower electrode of a capacitor having an upper end;
Etching the first dielectric layer and the second dielectric layer using a chemical solution to prevent the bubbles contained in the chemical solution from adhering to the electrode.   The step of preventing the bubbles from adhering includes a step of sufficiently covering the upper end of the electrode with a buffer layer to prevent bubbles contained in the chemical solution from adhering to the electrode. Item 20. The etching method according to Item 19.   The etching method of claim 19, wherein the planarization step is performed by a chemical mechanical polishing method.   The etching method according to claim 21, wherein the chemical mechanical polishing method uses a slurry having an etching selectivity with respect to the lower electrode and the first and second dielectric layers.   Cleaning the first and second dielectric layers to reduce etch residue after performing the planarization step on the resulting product and before preventing bubbles from adhering to the electrode; The etching method according to claim 19, further comprising:   The etching method of claim 23, wherein the cleaning step includes using HF.   The etching method according to claim 19, wherein the lower electrode of the capacitor has a substantially circular or elliptical plane. Forming a first dielectric layer on a semiconductor substrate;
Forming an opening in the first dielectric layer;
Depositing a conductor layer on the first dielectric layer including the opening;
Forming a second dielectric layer covering the conductor layer in the opening;
Planarizing the resultant structure including the conductive layer until an upper surface of the first dielectric layer is exposed to form a lower electrode of the capacitor having an upper end;
Generating a buffer layer after the planarization step on the resultant; and
And etching the first and second dielectric layers using a chemical solution, wherein the buffer layer is included in the chemical solution in the etching step. An etching method characterized by preventing adhesion to the substrate.   The method of claim 1, further comprising cleaning the first and second dielectric layers to remove etching residue after the planarization step of the resultant product and before the generation of the buffer layer. 26. The etching method according to 26.   28. The etching method of claim 27, wherein the cleaning step includes using HF.   27. The etching method according to claim 26, wherein the capacitor lower electrode has a circular or elliptical plane.   27. The etching method of claim 26, wherein the first dielectric layer and the second dielectric layer are etched before the buffer layer covering the upper end is substantially dried. .   27. The etching method according to claim 26, wherein the step of forming the buffer layer includes a step of forming a hydrophilic liquid layer on an upper end portion of the electrode.   32. The etching method according to claim 31, wherein the hydrophilic liquid layer is made of a liquid selected from deionized water, hydrogen peroxide, and ozone water.   32. The etching method according to claim 31, wherein the step of forming the hydrophilic liquid layer includes a step of spraying and forming a hydrophilic liquid on an upper end portion of the electrode.   32. The etching method according to claim 31, wherein the step of forming the hydrophilic liquid layer includes a step of immersing the substrate in the hydrophilic liquid.

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