JP2005051239A - Reconnectable chip interface and chip package - Google Patents

Reconnectable chip interface and chip package Download PDF

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Publication number
JP2005051239A
JP2005051239A JP2004210546A JP2004210546A JP2005051239A JP 2005051239 A JP2005051239 A JP 2005051239A JP 2004210546 A JP2004210546 A JP 2004210546A JP 2004210546 A JP2004210546 A JP 2004210546A JP 2005051239 A JP2005051239 A JP 2005051239A
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Japan
Prior art keywords
circuit device
integrated circuit
substrate
protrusion
connection pad
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Pending
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JP2004210546A
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Japanese (ja)
Inventor
Kenneth B Gilleo
ビー. ジレオ ケニス
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Alent Inc
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Cookson Electronics Inc
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Publication of JP2005051239A publication Critical patent/JP2005051239A/en
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00Assembling of devices or systems from individually processed components
    • B81C3/002Aligning microparts
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a reconnectable chip interface and a chip package. <P>SOLUTION: Electrical connection pads 23, 27 on a circuit device and on a substrate are brought into contact with each other when the circuit device and the substrate are connected to each other. At least a single first protrusion 37 on one of the device and the substrate and at least two second protrusions 39 on the other of the device and the substrate have their lengths in the axial direction. The protrusions are so sized and shaped as to be closely friction-fit along their axial lengths when they engage with each other. The integrated circuit device package includes an integrated circuit device and an interconnection board for mounting the integrated circuit device on an electronic circuit board. The interconnection board forms an enclosed space which is combined with the active surface of the integrated circuit device for the formation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、一般に集積回路アセンブリに関し、特にマイクロチップと基板間の電気−機械的接続に関する。この発明はまた、集積回路デバイスを保護するための集積回路デバイスパッケージ、並びにそのようなパッケージを形成するためのプロセスに関する。   The present invention relates generally to integrated circuit assemblies, and more particularly to electro-mechanical connections between a microchip and a substrate. The invention also relates to an integrated circuit device package for protecting an integrated circuit device, and a process for forming such a package.

集積回路デバイス(即ち、マイクロチップ、チップまたはダイ)は、典型的には基板(例えば、チップキャリア、パッケージまたは回路基板)に対し、周知の方法、例えばダイレクト・チップ・アタッチ(DCA)やワイヤボンディングを使用して接続される。DCAは、チップの電気的接続パッド(即ち、ボンドパッド)に典型的に適用される接合材料、例えば冶金半田や高分子導電性接着剤を使用する。このチップは、それから熱を加えて半田を溶解またはリフローすることによって、基板上の対応するボンドパッドに電気機械的に接続される。アンダーフィルと呼ばれる保護性高分子が、チップと基板との間のギャップに塗布され、それから加熱によって硬化される。この結果、液体は重合して固体となり、チップと基板との間にさらなる結合を与える。ワイヤボンディングでは、チップを基板に取り付けることに接着剤や半田が使用される。チップ取り付け後に、細い金属ワイヤが、熱または超音波エネルギを使用して、各チップの電気的接続パッドに対し、並びに対応する基板の電気的接続パッドに対して溶接される。米国特許第5,439,162号および5,665,654号が参照される。これらの双方は、全ての目的について、DCAおよびワイヤボンディング取り付けのプロセスに関する追加的な背景情報について、参照によりここに組み入れられる。DCAおよびワイヤボンディングのプロセスは典型的に信頼性の高いチップ接続を生じさせるものではあるが、この接続は永久的なものと考えられ、チップの除去および再接続を可能とするものではない。また、半田や接着剤をリフローするに必要な熱は、頻繁にマイクロチップにダメージを与えて、製造効率を低下させる。   Integrated circuit devices (i.e., microchips, chips or dies) are typically attached to a substrate (e.g., chip carrier, package or circuit board) in a well-known manner, such as direct chip attach (DCA) or wire bonding. Connected using. DCA uses bonding materials typically applied to the electrical connection pads (ie, bond pads) of the chip, such as metallurgical solder or polymeric conductive adhesive. The chip is then electromechanically connected to corresponding bond pads on the substrate by applying heat to melt or reflow the solder. A protective polymer called underfill is applied to the gap between the chip and the substrate and then cured by heating. As a result, the liquid polymerizes into a solid, providing further bonding between the chip and the substrate. In wire bonding, an adhesive or solder is used to attach a chip to a substrate. After chip attachment, thin metal wires are welded to the electrical connection pads of each chip as well as to the electrical connection pads of the corresponding substrate using heat or ultrasonic energy. Reference is made to US Pat. Nos. 5,439,162 and 5,665,654. Both of these are hereby incorporated by reference for additional background information regarding the DCA and wire bonding attachment process for all purposes. Although the DCA and wire bonding process typically produces a reliable chip connection, this connection is considered permanent and does not allow chip removal and reconnection. Also, the heat required to reflow solder and adhesive frequently damages the microchip and reduces manufacturing efficiency.

熱的ボンディングプロセスを排除する既存の電気−機械的チップ接続法は、従来のマイクロチップデバイスが回路の基板上に電気的および機械的に搭載され、チップや基板を加熱することなく、チップが除去および再接続され得るようにする。これら従来の電気−機械的接続法は、マイクロチップおよび基板の電気的接続パッド上に配置された金属化された連動構造(即ち、フックおよびループ構成、ロック用インサートおよびソケット、連動用微細構造バーブ)を典型的に含んでいる。米国特許第5,411,400号、5,774,341号および5,903,059号が参照される。これらは、全ての目的について、電子デバイスと基板との間の既存の再接続可能な電気−機械的接続に関する追加的な背景情報について、参照によりここに組み入れられる。既存の再接続可能なチップインターフェース構造は、高い製造コストと低い動作の信頼性故に、産業界では広く受け入れられているように見えない。   The existing electro-mechanical chip connection method that eliminates the thermal bonding process is that traditional microchip devices are electrically and mechanically mounted on the circuit board, removing the chip without heating the chip or board. And be able to be reconnected. These conventional electro-mechanical connection methods involve metallized interlocking structures (ie hook and loop configurations, locking inserts and sockets, interlocking microstructured barbs disposed on the microchip and substrate electrical connection pads. ) Is typically included. Reference is made to US Pat. Nos. 5,411,400, 5,774,341 and 5,903,059. These are hereby incorporated by reference for additional background information regarding existing reconnectable electro-mechanical connections between electronic devices and substrates for all purposes. Existing reconnectable chip interface structures do not appear to be widely accepted in industry due to high manufacturing costs and low operational reliability.

MEMS、即ちマイクロ・エレクトロ・メカニカル・システムは、しばしば移動部品を有する集積回路デバイスであるか、(サーマルインクジェットチップでのように)材料を移動させることができる微細構造である。MEMSデバイスをパッケージングするための一般的な必要条件は、チップの能動表面または面に接触できるカプセル材料やエンクロージャがないということである。インダクタコイルを含む無線周波数部品のような移動部品のない集積回路デバイスに対してさえも、自由空間のあるパッケージは良好に役立つ。これは、カプセル材料が高周波デバイスを「離調」するからである。MEMSデバイスを電子的基板に直接接続することに、DCAは使用できない。これは、チップと基板との間の領域に適用されるアンダーフィルが能動表面をカバーしてしまうからである。不幸なことに、従来の低コストのパッケージング法であるトランスファー成形は、プラスチックのカプセル材料をチップ全面に塗布するので、殆どのMEMSデバイスを役に立たないものにしてしまう。針分配により適用される液体カプセル材料についても同様である。現在、MEMSデバイス用に効果的な低コストのパッケージング法は存在しない。   MEMS, or micro electro mechanical systems, are often integrated circuit devices with moving parts, or microstructures that can move material (as in a thermal inkjet chip). A common requirement for packaging MEMS devices is that there is no encapsulant or enclosure that can contact the active surface or surface of the chip. Even with integrated circuit devices that have no moving parts, such as radio frequency components including inductor coils, packages with free space are well served. This is because the capsule material “detunes” the high frequency device. DCA cannot be used to connect a MEMS device directly to an electronic substrate. This is because the underfill applied to the area between the chip and the substrate covers the active surface. Unfortunately, transfer molding, a traditional low-cost packaging method, applies plastic encapsulant to the entire chip surface, making most MEMS devices useless. The same applies to the liquid capsule material applied by needle dispensing. Currently, there is no effective low cost packaging method for MEMS devices.

MEMSデバイスや他の集積回路デバイス用に最も共通したパッケージは、金属またはセラミック製の密封エクロージャであり、これは概念的に、チップが挿入され接続された後に蓋があてがわれる小さな箱とみなされる。絶縁された電気リードは、この箱の外側へ通り抜けなければならないので、このことがコストを増加し、接続の数を制限する。これら既存の密封エクロージャは、金属またはセラミック製であって、トランスファー成形されたプラスチックパッケージの約10から100倍のコストを要する。密封蓋は、溶接、半田付けまたは鑞付けされなければならず、このことが通常は感熱性のデバイスをエンクロージャ内で加熱する。典型的な金属またはセラミック製の密封エクロージャは、一般的にチップのサイズより遙かに大きく、チップが基板上に直接搭載される場合よりも多くの回路基板搭載スペースを必要とする。   The most common package for MEMS devices and other integrated circuit devices is a metal or ceramic hermetic enclosure, which is conceptually considered a small box that is lidded after the chip is inserted and connected. It is. This increases the cost and limits the number of connections, since the insulated electrical leads must pass outside the box. These existing sealed enclosures are made of metal or ceramic and cost about 10 to 100 times as much as transfer molded plastic packages. The sealed lid must be welded, soldered or brazed, which heats the normally heat sensitive device within the enclosure. Typical metal or ceramic sealed enclosures are typically much larger than the size of the chip and require more circuit board mounting space than if the chip were mounted directly on the board.

チップ・スケール・パッケージ(CSP)と呼ばれる代替のチップパッケージングデザインは、少ない回路基板スペースですむようにパッケージのサイズを減少させる。既存のCSPデザインは、集積回路デバイスが搭載されるベース基板に取り付けられたキャップを有する。ベースウエハ上の電気的接続パッドの周辺回りにあるガスケットまたは接着剤層は、このキャップをウエハに結合して封止し、集積回路デバイスの能動面よりも有意に大きなエンクロージャを与える。米国特許第6,228,675号および6,441,481号が参照される。これらは、全ての目的について、既存のCSPデザインに関する追加的な背景情報について、参照によりここに組み入れられる。既存のCSPデザインは、回路基板への直接電気的接続用の相互接続を欠いている。この結果、キャップを被せたマイクロチップは、キャップとベース基板とが結合された後に、相互接続処理(例えば、ワイヤボンディング)を経る必要がある。一般に、チップ・スケール・パッケージ(CSP)は、総パッケージサイズがパッケージ内に封入される回路デバイスのサイズよりも約20%を超えて大きくならないチップ・パッケージとして定義される。技術が高度な微細化に向けて推進されるにつれて、20%ガイドライン付近のサイズのCSPデザインは、電子産業の微細化要請に適合するには不十分になる。それ故、既存のセラミックパッケージよりも経済的で信頼性の高いシンプルなマイクロチップパッケージ、並びに既存のセラミックパッケージよりも製造が容易で小型なマイクロチップパッケージに対する必要性がある。   An alternative chip packaging design called Chip Scale Package (CSP) reduces the size of the package so that less circuit board space is required. Existing CSP designs have a cap attached to a base substrate on which the integrated circuit device is mounted. A gasket or adhesive layer around the periphery of the electrical connection pads on the base wafer bonds and seals the cap to the wafer, providing an enclosure that is significantly larger than the active surface of the integrated circuit device. Reference is made to US Pat. Nos. 6,228,675 and 6,441,481. These are hereby incorporated by reference for additional background information on existing CSP designs for all purposes. Existing CSP designs lack interconnects for direct electrical connection to the circuit board. As a result, the microchip with the cap needs to undergo an interconnection process (for example, wire bonding) after the cap and the base substrate are coupled. In general, a chip scale package (CSP) is defined as a chip package in which the total package size does not grow more than about 20% larger than the size of the circuit device encapsulated within the package. As technology is driven towards advanced miniaturization, CSP designs with sizes near the 20% guideline will become insufficient to meet the miniaturization requirements of the electronics industry. Therefore, there is a need for simple microchip packages that are more economical and reliable than existing ceramic packages, as well as microchip packages that are easier to manufacture and smaller than existing ceramic packages.

[発明の開示]
この発明のいくつかの目的の中で示されるものは、環境温度で集積回路デバイスを基板に対し電気機械的に接続することを可能にするアセンブリの提供であり、経済的な製造を可能にする同様のアセンブリの提供であり、シンプルなテストを可能とする同様のアセンブリの提供であり、簡単な作り直しを可能とする同様のアセンブリの提供であり、そして集積回路デバイスの簡単な除去および交換を可能とする同様のアセンブリの提供である。
[Disclosure of the Invention]
Some of the objects of the present invention are to provide an assembly that allows an electromechanical connection of an integrated circuit device to a substrate at ambient temperature, allowing for economical manufacturing. Provide similar assemblies, provide similar assemblies that allow simple testing, provide similar assemblies that allow easy rework, and allow easy removal and replacement of integrated circuit devices And providing a similar assembly.

更に、この発明のいくつかの目的の中で示されるものは、集積回路デバイスを保護するための製造が簡単なパッケージの提供であり、スケールの小さい同様のパッケージの提供であり、基板に対して信頼性のある電気的および機械的接続を可能とする同様のパッケージの提供であり、回路デバイス用に十分な保護スペースを与える同様のパッケージの提供であり、組立工程を減少させる同様のパッケージの提供であり、そして電子回路基板との再接続可能な電気的接続を可能とする同様のパッケージの提供である。   Further, some of the objects of the present invention are to provide a package that is simple to manufacture to protect integrated circuit devices, to provide a similar package with a small scale, and to a substrate. Providing similar packages that allow reliable electrical and mechanical connections, providing similar packages that provide sufficient protection space for circuit devices, and providing similar packages that reduce assembly processes And the provision of a similar package that allows a reconnectable electrical connection to an electronic circuit board.

一般に、本発明のアセンブリは、基板と、この基板に対し電気的および機械的に接続されるように適用される集積回路デバイスとを有する。前記回路デバイス上および前記基板上の第1の組の電気的接続パッドは、前記回路デバイスと前記基板が接続されるときに互いに接触するように適用される。前記接続パッドの組は、少なくとも1つの第1の突起を前記デバイスおよび前記基板の一方の上に、また少なくとも2つの第2の突起を前記デバイスおよび前記基板の他方の上に有する。各突起はそれぞれの接続パッドの外面から延びたそれぞれの軸方向の長さを有する。前記第1の突起と前記第2の突起は、前記突起が互いに噛み合ったときに、それぞれの軸方向の長さに沿って緊密な摩擦嵌合をするようにサイズおよび形状が設定され、これにより前記デバイスと前記基板との間に電気的および機械的な接続を確立する。   In general, the assembly of the present invention comprises a substrate and an integrated circuit device adapted to be electrically and mechanically connected to the substrate. A first set of electrical connection pads on the circuit device and on the substrate is applied to contact each other when the circuit device and the substrate are connected. The set of connection pads has at least one first protrusion on one of the device and the substrate and at least two second protrusions on the other of the device and the substrate. Each protrusion has a respective axial length extending from the outer surface of the respective connection pad. The first protrusion and the second protrusion are sized and shaped to have a close frictional fit along their axial length when the protrusions are engaged with each other, thereby An electrical and mechanical connection is established between the device and the substrate.

この発明のもう1つの形態のアセンブリは、複数の接続パッドを有する基板を備える。各パッドは、複数の離れて配置された導電性突起を有する。これらの突起は、前記パッドの外面から延びて、それらの間にオープンスペースを形成する。集積回路デバイスは、前記基板に対して電気的および機械的に接続されるように適用される。前記デバイスは、複数の接続パッドを有する。各パッドは、このパッドの外面から延びた少なくとも1つの導電性突起を備える。前記デバイス上の導電性突起は、前記オープンスペースへの挿入に適用される。かくして前記デバイスと基板は、それぞれの突起間の摩擦嵌合による電気的および機械的な接続状態に保持される。   Another form of assembly of the invention comprises a substrate having a plurality of connection pads. Each pad has a plurality of spaced apart conductive protrusions. These protrusions extend from the outer surface of the pad and form an open space between them. The integrated circuit device is adapted to be electrically and mechanically connected to the substrate. The device has a plurality of connection pads. Each pad includes at least one conductive protrusion extending from the outer surface of the pad. Conductive protrusions on the device are applied for insertion into the open space. Thus, the device and the substrate are held in an electrical and mechanical connection by a friction fit between the respective protrusions.

この発明のもう1つの形態のアセンブリは、基板と、この基板に対し電気的および機械的に接続されるように適用される集積回路デバイスとを有する。前記基板上の第1の接続パッドは、1つのパッドの外面から突出した2以上の導電性接続要素の第1の組を備える。第1の組の各接続要素は、前記基板に対して概ね直交する軸方向の長さを有する。前記基板上の第2の接続パッドは、このパッドの外面から突出した1以上の導電性接続要素の第2の組を備える。第2の組の各接続要素は、軸方向の長さを有して、接続要素の第1の組の接続要素との噛み合いに適用される。接続要素の第1および第2の組は、互いに噛み合ったときに、それぞれの軸方向の長さに沿って緊密な摩擦嵌合をするようにサイズおよび形状が設定され、これにより前記デバイスと前記基板との間に電気的および機械的な接続を確立する。   Another form of assembly of the invention comprises a substrate and an integrated circuit device adapted to be electrically and mechanically connected to the substrate. The first connection pads on the substrate comprise a first set of two or more conductive connection elements protruding from the outer surface of one pad. Each connecting element of the first set has an axial length generally orthogonal to the substrate. The second connection pad on the substrate comprises a second set of one or more conductive connection elements protruding from the outer surface of the pad. Each connecting element of the second set has an axial length and is applied to the engagement of the connecting element with the first set of connecting elements. The first and second sets of connecting elements are sized and shaped to provide a tight friction fit along their respective axial lengths when engaged with each other, whereby the device and the Establish electrical and mechanical connections with the substrate.

一般的に、本発明の集積回路デバイスパッケージは、能動面を有し、その上に少なくとも1つの電気的接続パッドを有した集積回路デバイスと、この集積回路デバイスを電子回路基板上に搭載するための相互接続基板とを備える。前記相互接続基板は、囲まれた空間を形成するために前記集積回路デバイスの能動面と組み合わされるように適用される第1面と、前記電子回路基板との電気的および機械的接続に適用される第2面とを有する。前記相互接続基板は、少なくとも1組の電気的接続パッドを有し、各組は、前記集積回路デバイス上の少なくとも1つの電気的接続パッドとの電気的接続に適用される前記相互接続基板の第1面上の第1の電気的接続パッドと、この第1の接続パッドに電気的に接続される前記相互接続基板の第2面上の第2の電気的接続パッドと備える。前記相互接続基板の第2面上の前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続に適用される。   In general, an integrated circuit device package of the present invention has an active surface with at least one electrical connection pad thereon and an integrated circuit device for mounting on an electronic circuit board. Interconnect substrate. The interconnect substrate is applied to electrical and mechanical connections between the electronic circuit board and a first surface applied to be combined with an active surface of the integrated circuit device to form an enclosed space. And a second surface. The interconnect substrate has at least one set of electrical connection pads, each set being adapted for electrical connection with at least one electrical connection pad on the integrated circuit device. A first electrical connection pad on one surface; and a second electrical connection pad on the second surface of the interconnect substrate electrically connected to the first connection pad. The second electrical connection pads on the second surface of the interconnect substrate are applied for electrical and mechanical connection with the electronic circuit board.

この発明のもう1つの形態の集積回路デバイスパッケージは、能動面を有し、その上に少なくとも1つの電気的接続パッドを有した集積回路デバイスを備える。この集積回路デバイスを電子回路基板上に搭載するための相互接続基板は、囲まれた空間を形成するために前記集積回路デバイスの能動面と組み合わされるように適用される第1面と、前記電子回路基板との電気的および機械的接続に適用される第2面とを有する。前記相互接続基板は、少なくとも1組の電気的接続パッドを有し、各組は、前記集積回路デバイス上の少なくとも1つの電気的接続パッドとの電気的接続に適用される前記相互接続基板の第1面上の第1の電気的接続パッドと、この第1の接続パッドに電気的に接続される前記相互接続基板の第2面上の第2の電気的接続パッドと備える。前記相互接続基板の第2面上の前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続に適用される。   Another form of integrated circuit device package of the present invention comprises an integrated circuit device having an active surface and having at least one electrical connection pad thereon. An interconnect substrate for mounting the integrated circuit device on the electronic circuit substrate includes a first surface adapted to be combined with an active surface of the integrated circuit device to form an enclosed space, and the electronic And a second surface applied for electrical and mechanical connection with the circuit board. The interconnect substrate has at least one set of electrical connection pads, each set being adapted for electrical connection with at least one electrical connection pad on the integrated circuit device. A first electrical connection pad on one surface; and a second electrical connection pad on the second surface of the interconnect substrate electrically connected to the first connection pad. The second electrical connection pads on the second surface of the interconnect substrate are applied for electrical and mechanical connection with the electronic circuit board.

この発明のもう1つの形態は、集積回路デバイススケールパッケージを形成するためのプロセスに関する。このプロセスは、能動面を有する集積回路デバイスウエハを作成する工程と、相互接続基板ウエハを、このウエハがその対向する面上に電気的接続パッドを有し、また1つの凹んだ表面を有するように作成する工程とを備える。前記集積回路デバイスウエハと相互接続基板ウエハは電気的および機械的に接続され、前記2つのウエハが、前記集積回路デバイスウエハの能動面と前記相互接続基板ウエハの凹んだ表面との間に囲まれた空間を形成する。前記集積回路デバイスウエハと相互接続基板ウエハはダイシングされ、1以上の個別集積回路デバイスパッケージを形成する。   Another aspect of the invention relates to a process for forming an integrated circuit device scale package. The process includes the steps of creating an integrated circuit device wafer having an active surface and an interconnect substrate wafer such that the wafer has electrical connection pads on its opposing surface and has a single concave surface. And a step of creating. The integrated circuit device wafer and the interconnect substrate wafer are electrically and mechanically connected, and the two wafers are enclosed between an active surface of the integrated circuit device wafer and a recessed surface of the interconnect substrate wafer. Form a space. The integrated circuit device wafer and the interconnect substrate wafer are diced to form one or more individual integrated circuit device packages.

この発明の更に別の形態の相互接続基板は、集積回路デバイスを電子回路基板上に搭載するためのものであって、前記集積回路デバイスの能動面と組み合わされて囲まれた空間を形成することに適用される第1面と、前記電子回路基板との電気的および機械的接続に適用される第2面とを備える。前記相互接続基板の第1面上の第1の電気的接続パッドは、前記集積回路デバイスとの電気的接続に適用される。前記相互接続基板の第2面上の第2の電気的接続パッドは、前記第1の接続パッドに電気的に接続される。前記相互接続基板の第2面上の前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続に適用される。   According to another aspect of the present invention, there is provided an interconnect substrate for mounting an integrated circuit device on an electronic circuit substrate, and forming an enclosed space in combination with an active surface of the integrated circuit device. And a second surface applied for electrical and mechanical connection with the electronic circuit board. A first electrical connection pad on the first surface of the interconnect substrate is applied for electrical connection with the integrated circuit device. A second electrical connection pad on the second surface of the interconnect substrate is electrically connected to the first connection pad. The second electrical connection pads on the second surface of the interconnect substrate are applied for electrical and mechanical connection with the electronic circuit board.

他の目的および特徴は、以下で部分的に明らかとなり、また部分的に指摘される。   Other objects and features will be in part apparent and in part pointed out hereinafter.

図面、特に図1を参照すると、概略1で示されるチップモジュールは、概略3で示される本発明により組み立てられた集積回路デバイスを備える。図1の特別な実施形態では、モジュール1は、プリント回路基板(図示せず)への電気的接続用半田ボール9を有した通常のボールグリッドアレイ5に添付されている。ここで理解されるべき点は、回路基板に対しチップモジュール1を直接取り付けるか、あるいは他の通常の接続基板(例えば、ピン・グリッドアレイやランドグリッドアレイ)を介して取り付けることができるということである。また、モジュール1は、本発明により組み立てられた集積回路デバイス3を1より多く含むことができる。   With reference to the drawings, and in particular with reference to FIG. 1, the chip module shown in schematic 1 comprises an integrated circuit device assembled in accordance with the present invention shown in schematic 3. In the particular embodiment of FIG. 1, the module 1 is attached to a conventional ball grid array 5 having solder balls 9 for electrical connection to a printed circuit board (not shown). The point to be understood here is that the chip module 1 can be directly attached to the circuit board, or can be attached via another normal connection board (for example, pin grid array or land grid array). is there. The module 1 can also contain more than one integrated circuit device 3 assembled according to the invention.

図1及び2に示されるように、モジュール1の集積回路デバイス3は、概略13で示されるチップキャリア基板に対して電気的および機械的に取り付けられる。図示の実施形態では、回路デバイス3は模式的に示されているが、ここで理解されるべき点は、各デバイスが典型的な如何なる集積回路デバイスでもあり得るということである。例えば、マイクロ・エレクトロニック・メカニカル・システム(MEMS)デバイスやオプトエレクトロニック(OE)デバイス、さらには電子回路で使用され得る他のマイクロチップである。図1に示されたモジュール1は、通常の材料(例えば、金属、セラミック、またはプラスチック)で形成された保護キャップ15を含んでいる。このキャップは、集積回路デバイス3を囲んで保護するために、通常の手段(例えば、溶接、半田付け、鑞付け)によってチップキャリア基板13に添付されている。この代わりに、モジュール1のキャップ15は、キャップを通して光を通過させるために、アクセス窓(図示せず)を有することができる。あるいは、モジュールにキャップを設けないこともできる。   As shown in FIGS. 1 and 2, the integrated circuit device 3 of the module 1 is electrically and mechanically attached to a chip carrier substrate, indicated generally at 13. In the illustrated embodiment, the circuit device 3 is shown schematically, but it should be understood that each device can be any typical integrated circuit device. For example, microelectronic mechanical system (MEMS) devices, optoelectronic (OE) devices, and other microchips that can be used in electronic circuits. The module 1 shown in FIG. 1 includes a protective cap 15 formed of a conventional material (eg, metal, ceramic, or plastic). This cap is attached to the chip carrier substrate 13 by conventional means (eg, welding, soldering, brazing) to surround and protect the integrated circuit device 3. Alternatively, the cap 15 of the module 1 can have an access window (not shown) to allow light to pass through the cap. Alternatively, the module may not be provided with a cap.

図1及び2に見られるように、集積回路デバイス3は、このデバイスと一体化された4つのストップ19を有する。これらストップ19は、デバイスの底面から突出して基板13に接触する。一実施形態では、各ストップは、回路デバイス3と同じ半導体材料からチップ製造プロセスの一部として製造され、回路デバイスのそれぞれの隅近くに配設された固体の円筒形本体である。以下で更に詳細に論じられるように、ストップ19は、基板13に対するチップの3の間隔を制限し、またチップと基板が平行な平面に整列されることを確実にする。   As can be seen in FIGS. 1 and 2, the integrated circuit device 3 has four stops 19 integrated with the device. These stops 19 protrude from the bottom surface of the device and come into contact with the substrate 13. In one embodiment, each stop is a solid cylindrical body made from the same semiconductor material as the circuit device 3 as part of the chip manufacturing process and disposed near each corner of the circuit device. As discussed in more detail below, the stop 19 limits the spacing of the chip 3 relative to the substrate 13 and ensures that the chip and the substrate are aligned in a parallel plane.

図2の実施形態では、モジュール1は、集積回路デバイス3上に8組の電気的接続パッド(即ち、ボンドパッド)23を有する。これは、基板13上の対応する電気的接続パッド27と噛み合わせるためである。回路デバイス3上の各接続パッド23は、そのデバイスの表面上に形成された金属パッドであって、チップキャリア基板13の対向する表面上の対応するパッド27と接触するように配置されている。各電気的接続パッド23,27は、通常の手段を介して、マイクロチップ3の回路、または基板13に対し電気的に接続される。この結果、電気信号がパッドを通して送受信される。図示の実施形態において、接続パッド23は、デバイス3の底(受動)面31の周辺近くに配置されているが、ここで理解されるべき点は、これらのパッドがチップの上(能動)面33上に配置され得るということである。また、この発明の範囲を逸脱することなく、8個より多いか少ないパッド23,27を設けることもできる。ここで理解されるべき点は、チップ3及び基板13上の接続パッド23,27の総数は、集積回路デバイスの特異な技術および応用に依存して変わること、並びに数100または数1000個の外部接続端子もまたマイクロチップおよび基板上に存在するということである。各接続パッド23は、基板13上の対応する(組み合わされる)接続パッド27への取り付け用に配置されている。このため、集積回路デバイスと基板との間に導電性経路が設けられる。以下で更に詳細に論じられるように、チップ3及び基板13上の組み合わされる接続パッド23,27の各対は、集積回路デバイスをチップキャリア基板へ電気的および機械的に接続することが可能な協同する接続要素37,39(図3)を含んでいる。   In the embodiment of FIG. 2, the module 1 has eight sets of electrical connection pads (ie, bond pads) 23 on the integrated circuit device 3. This is for meshing with the corresponding electrical connection pads 27 on the substrate 13. Each connection pad 23 on the circuit device 3 is a metal pad formed on the surface of the device, and is arranged so as to contact a corresponding pad 27 on the opposite surface of the chip carrier substrate 13. Each of the electrical connection pads 23 and 27 is electrically connected to the circuit of the microchip 3 or the substrate 13 through normal means. As a result, electrical signals are transmitted and received through the pad. In the illustrated embodiment, the connection pads 23 are located near the periphery of the bottom (passive) surface 31 of the device 3, but it should be understood that these pads are on the top (active) surface of the chip. It can be arranged on 33. Also, more or fewer than eight pads 23, 27 can be provided without departing from the scope of the invention. It should be understood that the total number of connection pads 23, 27 on the chip 3 and the substrate 13 varies depending on the specific technology and application of the integrated circuit device, and hundreds or thousands of external Connection terminals are also present on the microchip and the substrate. Each connection pad 23 is arranged for attachment to a corresponding (combined) connection pad 27 on the substrate 13. For this reason, a conductive path is provided between the integrated circuit device and the substrate. As discussed in more detail below, each pair of mated connection pads 23, 27 on the chip 3 and substrate 13 is a cooperating capable of electrically and mechanically connecting the integrated circuit device to the chip carrier substrate. Connecting elements 37 and 39 (FIG. 3).

図3に示されるように、集積回路デバイス3上の各電気的接続パッド23は、このデバイスに概ね平行な外面43を有し、そして少なくとも1つの、おそらく1より多い導電性接続要素37を備える。各導電性接続要素は、パッドの平坦な外面から突出する第1の突起を備える。図3及び4の実施形態では、各第1の突起37は、固体の円筒形本体を備える。この本体は、平坦で円形の遊端51と、接続パッド23の平坦な外面43にほぼ直交する軸方向の長さの外面53とを有する。ここで理解されるべき点は、この発明の範囲を逸脱することなく、突起37が他の形状及び構成を有してもよいということである。一実施形態では、各突起37は接続パッド23の一体的な部分として形成され、そして適切な金属または金属合金(例えば、銅または銅合金)からなる。各接続要素37は、接続パッド23を金属化する前に、通常の製造プロセス、例えばマイクロエレクトロニック・フォトリソグラフィ技術(即ち、LIGAプロセスまたは表面微細加工およびエッチング)を使用して、マイクロチップデバイス3と同じ半導体材料(例えば、シリコン、セラミック、まは他の適切な半導体材料)で形成された突起を備えることが好ましい。マイクロチップデバイス3の製造後に、デバイスの底面31上の突起37および周辺領域は、通常のプロセス、例えば真空金属蒸着、無電解メッキ、または電解メッキによって金属化され、金属化された突起およびこの突起を囲む平坦な外面43を備えた導電性接続パッド23を形成する。この代わりに、各接続パッド23は、集積回路デバイス側接続パッド23の平坦な表面43に結合された3次元金属突起を作ることに良く適している通常の微細加工プロセス、例えば電気メッキ、スパッタリング、またはLIGAにより加工された固形金属で作ることができる。この代替加工法は、通常のチップ加工ステップが完了した後に、金属突起37を接続パッド23に結合させることができる。   As shown in FIG. 3, each electrical connection pad 23 on the integrated circuit device 3 has an outer surface 43 generally parallel to the device and comprises at least one, possibly more than one conductive connection element 37. . Each conductive connecting element comprises a first protrusion that protrudes from the flat outer surface of the pad. In the embodiment of FIGS. 3 and 4, each first protrusion 37 comprises a solid cylindrical body. The main body has a flat and circular free end 51 and an outer surface 53 having an axial length substantially orthogonal to the flat outer surface 43 of the connection pad 23. It should be understood that the protrusion 37 may have other shapes and configurations without departing from the scope of the present invention. In one embodiment, each protrusion 37 is formed as an integral part of the connection pad 23 and is made of a suitable metal or metal alloy (eg, copper or copper alloy). Each connection element 37 is connected to the microchip device 3 prior to metallization of the connection pads 23 using a normal manufacturing process such as microelectronic photolithography technology (ie, LIGA process or surface micromachining and etching). Preferably, the projections are formed of the same semiconductor material (eg, silicon, ceramic, or other suitable semiconductor material). After the manufacture of the microchip device 3, the protrusion 37 and the peripheral region on the bottom surface 31 of the device are metallized by a normal process such as vacuum metal deposition, electroless plating or electrolytic plating, and the metallized protrusion and the protrusion A conductive connection pad 23 having a flat outer surface 43 is formed. Instead, each connection pad 23 is a conventional microfabrication process, such as electroplating, sputtering, etc., that is well suited for making three-dimensional metal protrusions bonded to the flat surface 43 of the integrated circuit device side connection pad 23. Alternatively, it can be made of a solid metal processed by LIGA. In this alternative processing method, the metal protrusion 37 can be bonded to the connection pad 23 after a normal chip processing step is completed.

図3を再度参照すると、基板13上の各電気的接続パッド27は、複数の離れて配置された導電性接続要素39を備える。各要素39は、基板とほぼ平行であるパッドの平坦な外面61から延びた第2の突起を備える。図3及び4に見られるように、各第2の突起39は、固体の円筒形本体を備える。この本体は、平坦で円形の遊端67と、接続パッド27の平坦な外面61にほぼ直交する軸方向の長さを持つ外面69とを有する。各第2の突起39は、回路デバイス3上の第1の突起37と同様に構成され、そして通常の半導体材料で作られ、金属化されて、導電性外面69を有することが好ましい。ここで理解されるべき点は、基板側接続パッド27上の突起39は、集積回路デバイス3上の第1の突起37について上述したものと同じ製造プロセスを使用して同じ材料で作成されるということである。また、第2の突起39は、この発明の範囲を逸脱することなく、他の形状および構成を有することもできる。   Referring back to FIG. 3, each electrical connection pad 27 on the substrate 13 includes a plurality of spaced apart conductive connection elements 39. Each element 39 comprises a second protrusion extending from the flat outer surface 61 of the pad that is substantially parallel to the substrate. As can be seen in FIGS. 3 and 4, each second projection 39 comprises a solid cylindrical body. The main body has a flat circular free end 67 and an outer surface 69 having an axial length substantially perpendicular to the flat outer surface 61 of the connection pad 27. Each second protrusion 39 is preferably constructed similarly to the first protrusion 37 on the circuit device 3 and is made of conventional semiconductor material, metallized, and has a conductive outer surface 69. It should be understood that the protrusion 39 on the substrate side connection pad 27 is made of the same material using the same manufacturing process as described above for the first protrusion 37 on the integrated circuit device 3. That is. Also, the second protrusion 39 can have other shapes and configurations without departing from the scope of the present invention.

図3〜6に見られるように、集積回路デバイス3上の第1の突起37と基板13上の第2の突起39は、デバイスと基板との間の電気的および機械的接続を形成するための噛み合わせに適用される。より具体的には、第1及び第2の突起37,39は、回路デバイス3が基板13上に搭載されたときに、それらのそれぞれの軸方向の長さに沿って互いに緊密な摩擦嵌合をするために、サイズおよび形状が設定されている。一実施形態では、グループ分けされた4つの第2の突起39が離れて配置されて、1つの第1の突起37を受け入れるための1つのオープンスペースを形成する。この結果、第1の突起の軸方向外面53が4つの第2の突起のそれぞれの軸方向外面61と接触する。この代わりに、第2の突起39が別の方法で配置される場合は、4個より多いか少ない突起が各第1の突起37の外面53に接触することができる。各第1の突起37の軸方向外面53と各周囲の第2の突起の軸方向外面69との接触は、デバイス3と基板13の分離に抵抗する機械的な接続力を与える摩擦嵌合を作り出す。ここで理解されるべき点は、デバイスおよび基板、それぞれ3および13は、マイクロチップ接続に共通する表面吸引力(例えば、静止摩擦力)によって接触状態に保たれる。また、突起37,39が金属化された半導体材料で作られている場合、突起は噛み合ったときに弾性変形することが可能である。この場合、各突起はデバイス3または基板13に直交した位置から数度の円弧だけ撓んで、突起の挿入を容易にする。第1及び第2の突起37,39の噛み合いにより生成される摩擦の表面吸引力および/または機械的力は、接着剤や半田を接続パッド23,27へ適用する必要性なしに、集積回路デバイス3を基板13に対して固定的な位置に保持するに十分な接続力を与える。しかしながら、集積回路デバイス3と基板13を電気機械的接続状態に保持する接続力は十分に小さいので、デバイスは、接続パッド23,27の広範囲な作り直しに対する必要性なしに、除去され、交換され、基板上に再配置され得る。デバイス3は、最終部品組立中または集積回路デバイスのテスト中に第1及び第2の突起37,39が噛み合うことによって基板13上に搭載される。   As seen in FIGS. 3-6, the first protrusion 37 on the integrated circuit device 3 and the second protrusion 39 on the substrate 13 form an electrical and mechanical connection between the device and the substrate. Applicable to meshing. More specifically, the first and second protrusions 37 and 39 are in close frictional engagement with each other along their respective axial lengths when the circuit device 3 is mounted on the substrate 13. In order to do this, the size and shape are set. In one embodiment, the grouped four second protrusions 39 are spaced apart to form one open space for receiving one first protrusion 37. As a result, the axial outer surface 53 of the first protrusion comes into contact with the axial outer surface 61 of each of the four second protrusions. Alternatively, if the second protrusions 39 are arranged in another manner, more or less than four protrusions can contact the outer surface 53 of each first protrusion 37. The contact between the axial outer surface 53 of each first protrusion 37 and the axial outer surface 69 of each surrounding second protrusion provides a friction fit that provides a mechanical connection force that resists separation of the device 3 and the substrate 13. produce. It should be understood that the device and substrate, 3 and 13, respectively, are kept in contact by a surface suction force (eg, static friction force) common to microchip connections. Further, when the protrusions 37 and 39 are made of a metalized semiconductor material, the protrusions can be elastically deformed when engaged. In this case, each protrusion is bent by an arc of several degrees from a position orthogonal to the device 3 or the substrate 13 to facilitate insertion of the protrusion. The frictional surface attractive force and / or mechanical force generated by the engagement of the first and second protrusions 37, 39 allows the integrated circuit device without the need to apply adhesive or solder to the connection pads 23, 27. A connection force sufficient to hold 3 in a fixed position with respect to the substrate 13 is given. However, the connection force that keeps the integrated circuit device 3 and the substrate 13 in an electromechanical connection is sufficiently small so that the device can be removed and replaced without the need for extensive rework of the connection pads 23,27, It can be rearranged on the substrate. The device 3 is mounted on the substrate 13 by the engagement of the first and second protrusions 37, 39 during final component assembly or integrated circuit device testing.

図6に示されるように、集積回路デバイス3は、基板13に取り付けられる。この場合、デバイス上の第1の突起37と基板上の第2の突起39は、完全に噛み合わされる(即ち、それぞれの突起の遊端51,67の少なくとも一方が、それぞれの接続パッド23,27の平坦な表面43,61に接触する)。各第1の突起37をそれぞれの隣接する第2の突起39間のオープンスペースへ完全に挿入すると、突起間の接触面積は増加し、またチップ3を基板13上に保持する機械的接続力は最大になる。   As shown in FIG. 6, the integrated circuit device 3 is attached to the substrate 13. In this case, the first protrusion 37 on the device and the second protrusion 39 on the substrate are completely meshed (that is, at least one of the free ends 51 and 67 of each protrusion is connected to the respective connection pad 23, 27 flat surfaces 43, 61). When each first protrusion 37 is completely inserted into the open space between the respective adjacent second protrusions 39, the contact area between the protrusions increases, and the mechanical connection force for holding the chip 3 on the substrate 13 is as follows. Become the maximum.

代わりに、デバイス3は、隣接するデバイス間の光の転送用に垂直方向の整合を必要とするオプトエレクトリックまたはオプティカルMEMSデバイスでも良い。図2及び7に示されるように、ストップ19は、回路デバイス3の四隅に配置されて、基板13と接触している。このため、集積回路デバイスは、基板から所望の距離D離れて保持されている。デバイスのそれぞれの隅近くで回路デバイスから延びたストップ19は、基板13と接触している。このため、デバイスと基板は、突起37,39が噛み合ったときに互いに平行になる。隣接する回路デバイス(図示せず)は、回路デバイスを同じ高さに整列させるために、同じストップ19を備えている。このため、光学的信号(即ち、光)は、デバイス間を転送される。また、ストップ19は、突起間の重複の量を低減して、電気的および機械的な接触状態にある各突起のそれぞれの軸方向の長さの量を低減する。特別な集積回路用に必要とされるそれぞれの突起の重複する軸方向の長さの量は、集積回路デバイスのサイズと電気回路の必要条件に依存して変化する。典型的に、重複の量は、突起の軸方向の長さの25%から100%の範囲内にある。   Alternatively, device 3 may be an opto-electric or optical MEMS device that requires vertical alignment for the transfer of light between adjacent devices. As shown in FIGS. 2 and 7, the stops 19 are arranged at the four corners of the circuit device 3 and are in contact with the substrate 13. For this reason, the integrated circuit device is held at a desired distance D from the substrate. Stops 19 extending from the circuit device near each corner of the device are in contact with the substrate 13. For this reason, the device and the substrate are parallel to each other when the protrusions 37 and 39 are engaged with each other. Adjacent circuit devices (not shown) have the same stops 19 to align the circuit devices at the same height. For this reason, optical signals (i.e. light) are transferred between devices. Stop 19 also reduces the amount of overlap between the protrusions and reduces the amount of axial length of each protrusion in electrical and mechanical contact. The amount of overlapping axial length of each protrusion required for a particular integrated circuit varies depending on the size of the integrated circuit device and the electrical circuit requirements. Typically, the amount of overlap is in the range of 25% to 100% of the axial length of the protrusion.

1つの例示的実施形態では、デバイス3上の各ボンドパッド23および基板13上の各パッド27は、約100ミクロンの長さと約100ミクロンの幅を有する。各第1の突起37と第2の突起39は、約12ミクロンの最小長と約1ミクロンの最小径を有する。各ストップ19は、約16ミクロンの長さを有する。この場合、デバイス3および基板13間の対応する距離D(図7)は約16ミクロンであり、また噛み合った突起37,39の軸方向の長さの対応する重複は約8ミクロン(それぞれの突起の軸方向の全長の66%)である。突起37,39間の最小間隔は約1ミクロンであって、突起が50行50列に配列された1つの実施形態では、突起の最大数を約250にする。より好ましくは、各突起がより大きな直径を有したより少ない数の突起37,39を使用できる。1つの実施形態では、約100ミクロンの直径と約12ミクロンの長さを有した単一の第1の突起37がマイクロチップデバイス3上に設けられ、そしてそれぞれが約30ミクロンの直径と約12ミクロンの長さを有した3つの第2の突起39が基板13上に設けられる。   In one exemplary embodiment, each bond pad 23 on device 3 and each pad 27 on substrate 13 has a length of about 100 microns and a width of about 100 microns. Each first protrusion 37 and second protrusion 39 has a minimum length of about 12 microns and a minimum diameter of about 1 micron. Each stop 19 has a length of about 16 microns. In this case, the corresponding distance D (FIG. 7) between the device 3 and the substrate 13 is about 16 microns, and the corresponding overlap in the axial length of the mating projections 37, 39 is about 8 microns (each projection (66% of the total length in the axial direction). The minimum spacing between the protrusions 37, 39 is about 1 micron, and in one embodiment where the protrusions are arranged in 50 rows and 50 columns, the maximum number of protrusions is about 250. More preferably, a smaller number of protrusions 37, 39 can be used, each protrusion having a larger diameter. In one embodiment, a single first protrusion 37 having a diameter of about 100 microns and a length of about 12 microns is provided on the microchip device 3, and each has a diameter of about 30 microns and about 12 microns. Three second protrusions 39 having a length of micron are provided on the substrate 13.

ここで理解されるべき点は、上述した第1及び第2の突起37,39は、この発明の範囲を離れることなく、他の寸法を有することができ、また別の方法で配置できるということである。第1及び第2の突起間の接触表面積の量は、突起間の電気伝導度に直接比例し、また集積回路デバイス3と基板13を緊密に保持する機械的接続力に直接比例する。突起37,39の数と、突起の寸法構成と、突起の軸方向の長さの重複量は、特定の応用および必要とされる電気伝導度および機械的接続力の量に基づいて変化する。例えば、大電流応用は、多数の噛み合った突起37,39を必要とする。これは、大量の電流が回路デバイス3と基板13との間を転送できるようにするためである。   It should be understood that the first and second protrusions 37 and 39 described above can have other dimensions and can be arranged in other ways without departing from the scope of the present invention. It is. The amount of contact surface area between the first and second protrusions is directly proportional to the electrical conductivity between the protrusions and directly proportional to the mechanical connection force that holds the integrated circuit device 3 and the substrate 13 tightly. The number of protrusions 37, 39, the dimensional configuration of the protrusions, and the amount of protrusion axial length overlap will vary based on the particular application and the amount of electrical conductivity and mechanical connection force required. For example, high current applications require a large number of intermeshing protrusions 37,39. This is because a large amount of current can be transferred between the circuit device 3 and the substrate 13.

操作時に、本発明の集積回路アセンブリ1は、集積回路デバイス3をチップキャリア基板13に対し電気的および機械的に接続することによって作られる。デバイス3は、回路デバイス上の少なくとも1つの第1の突起37と、対となる基板上の少なくとも2つの第2の突起39との噛み合いによって、チップキャリア基板13に対し電気的および機械的に接続されている。第1の突起37と第2の突起39との間の摩擦係合は、集積回路デバイス3と基板13との間に確実な電気的および機械的接続を作る。チップキャリア基板13は、プリント回路基板(図示せず)や他の電子回路の部品から電気信号を受信する。この電気信号は、導電性の第1の突起と導電性の第2の突起39との接触を通して集積回路デバイス3に転送される。この代わりに、アセンブリ1は、基板13上の第1の突起37と集積回路デバイス3上の第2の突起39とを伴って構成される。この場合、デバイスと基板との間の電気的および機械的接続は、突起の噛み合いを通して確立される。   In operation, the integrated circuit assembly 1 of the present invention is made by electrically and mechanically connecting the integrated circuit device 3 to the chip carrier substrate 13. The device 3 is electrically and mechanically connected to the chip carrier substrate 13 by engagement of at least one first protrusion 37 on the circuit device and at least two second protrusions 39 on the paired substrate. Has been. The frictional engagement between the first protrusion 37 and the second protrusion 39 creates a secure electrical and mechanical connection between the integrated circuit device 3 and the substrate 13. The chip carrier substrate 13 receives electrical signals from printed circuit boards (not shown) and other electronic circuit components. This electric signal is transferred to the integrated circuit device 3 through the contact between the conductive first protrusion and the conductive second protrusion 39. Instead, the assembly 1 is configured with a first protrusion 37 on the substrate 13 and a second protrusion 39 on the integrated circuit device 3. In this case, the electrical and mechanical connection between the device and the substrate is established through the engagement of the protrusions.

図8は、集積回路デバイス側接続パッド203を備えた概略201で示される本発明の第2の実施形態を示している。この実施形態の接続パッド203は、第1の実施形態の接続パッド23と実質的に同じである。但し、この実施形態のパッドは、第1の突起207を含んでいる。集積回路デバイス側接続パッド203の各第1の突起207は、断面を円形とした固体の切頭形本体を有する。この本体は、丸み付けされた遊端即ち先端215と、突起の遊端から基端へ向けて直径が増えるようにテーパ付けされた外面217とを持つ。各第1の突起207は、第1の実施形態でのように、金属や他の導電性材料で作られ、そして基板13上の円筒形の第2の突起39(図5)と噛み合うように構成されている。この代わりに、第1の突起207は、第1の突起と構造が同じである基板上の第2の突起、あるいはこの発明の範囲を離れることのない他の形状および構成を有した第2の突起と噛み合うこともできる。ここで理解されるべき点は、各突起207の丸み付けされた先端215は、基板13上のそれぞれの第2の突起(図8)間に、第1の突起を迅速且つ容易に配置(即ち、案内)することを可能にする。各第1の突起207のテーパ付けされた外面217は、第2の突起39とのより緊密な摩擦嵌合を可能として、基板13に向けたデバイス3のさらなる挿入時に増加する機械的保持力を生じる。この実施形態201は、集積回路デバイス3と基板13との間に耐久性および耐衝撃性のある電気的接続を必要とする応用には特に有用である。   FIG. 8 shows a second embodiment of the present invention, indicated generally at 201 with integrated circuit device side connection pads 203. The connection pad 203 of this embodiment is substantially the same as the connection pad 23 of the first embodiment. However, the pad of this embodiment includes the first protrusion 207. Each first protrusion 207 of the integrated circuit device side connection pad 203 has a solid truncated main body having a circular cross section. The body has a rounded free end or tip 215 and an outer surface 217 tapered to increase in diameter from the free end to the proximal end of the protrusion. Each first protrusion 207 is made of a metal or other conductive material as in the first embodiment, and meshes with a cylindrical second protrusion 39 (FIG. 5) on the substrate 13. It is configured. Instead, the first protrusion 207 is a second protrusion on the substrate that is identical in structure to the first protrusion, or a second protrusion having another shape and configuration that does not depart from the scope of the invention. It can also mesh with the protrusion. It should be understood that the rounded tip 215 of each protrusion 207 allows the first protrusion to be quickly and easily positioned between each second protrusion (FIG. 8) on the substrate 13 (ie, , Guide). The tapered outer surface 217 of each first protrusion 207 allows a tighter friction fit with the second protrusion 39 to increase the mechanical holding force upon further insertion of the device 3 toward the substrate 13. Arise. This embodiment 201 is particularly useful for applications requiring a durable and impact resistant electrical connection between the integrated circuit device 3 and the substrate 13.

図9は、概略301で示される本発明の第3の実施形態の断面図を示す。この実施形態301は、第1の実施形態と実質的に同じであるが、回路デバイス上の第1の突起305と基板13上の第2の突起307は、長円形または楕円形の断面を有する。一実施形態では、各長円形の第1の突起305は、この実施形態の長円形の第2の突起307よりも大きいが、第1及び第2の突起は、この発明の範囲から離れることなく、他のサイズを有することができるか、あるいは別の方法で配置することができる。ここで理解されるべき点は、この実施形態の第1及び第2の突起305,307は、第1の実施形態について上述したと同じプロセスを使用して金属または他の導電性材料で形成できるということである。   FIG. 9 shows a cross-sectional view of the third embodiment of the present invention, indicated generally at 301. This embodiment 301 is substantially the same as the first embodiment, but the first protrusion 305 on the circuit device and the second protrusion 307 on the substrate 13 have an oval or elliptical cross section. . In one embodiment, each oval first projection 305 is larger than the oval second projection 307 of this embodiment, but the first and second projections do not depart from the scope of this invention. , Can have other sizes, or can be arranged in other ways. It should be understood that the first and second protrusions 305, 307 of this embodiment can be formed of metal or other conductive material using the same process as described above for the first embodiment. That's what it means.

図10および11は、先の実施形態と同様に、集積回路デバイス3(図1)上の接続パッド403と基板3(図1)上の接続パッド405を備えた概略401で示される本発明の第4の実施形態を示している。回路デバイス3上の各接続パッド403は第1の突起409を有し、また基板3上の接続パッド405は第2の突起413を有する。各突起409,413は、概ね平坦な接触表面を持つ多角形の断面を有する。図10および11の特別な実施形態では、各第1及び第2の突起409,413は、それぞれの電気的接続パッド403,405から延びた固体の平行四辺形状本体を有する。この実施形態の第1及び第2の突起409,413の噛み合いは、より大きな接触面積を突起間に与えて、より大きな電流搬送能力をデバイス3と基板13との間に許容する。ここで理解されるべき点は、第1及び第2の突起409,413が、この発明の範囲から離れることなく、他の多角形の断面(例えば、矩形、方形、三角形等)を有することができるということである。   10 and 11 of the present invention, shown generally at 401, with connection pads 403 on the integrated circuit device 3 (FIG. 1) and connection pads 405 on the substrate 3 (FIG. 1), as in the previous embodiment. The 4th Embodiment is shown. Each connection pad 403 on the circuit device 3 has a first protrusion 409, and the connection pad 405 on the substrate 3 has a second protrusion 413. Each protrusion 409, 413 has a polygonal cross section with a generally flat contact surface. In the particular embodiment of FIGS. 10 and 11, each first and second protrusion 409,413 has a solid parallelogram body extending from a respective electrical connection pad 403,405. The engagement of the first and second protrusions 409, 413 in this embodiment provides a larger contact area between the protrusions and allows a greater current carrying capacity between the device 3 and the substrate 13. It should be understood that the first and second protrusions 409 and 413 have other polygonal cross sections (eg, rectangles, squares, triangles, etc.) without departing from the scope of the present invention. It can be done.

図12及び13を参照すると、概略701で示される集積回路デバイスパッケージは、相互接続基板707上に搭載された集積回路デバイス703を備えている。図12に示されるように、パッケージ701は、相互接続基板707上の導電性接続要素715によって、電気回路基板711(例えば、プリント回路基板、ボール・グリッドアレイ、またはランド・グリッドアレイ)に対し電気的および機械的に接続されている。一実施形態では、導電性接続要素715は、電子回路基板711上の導電性接続要素717と電気的接触状態に置かれ、電気信号を集積回路デバイスパッケージ701へ通過できるようにする。集積回路デバイス703は模式的に示されているが、ここで理解されるべき点は、回路デバイスは、能動面719を有して、保護された囲まれた空間を必要とする、如何なるタイプの回路デバイス(例えば、MEMSデバイスやOEデバイス)でもよいということである。集積回路デバイス703は、電気的接続パッド723を有する。このパッドは、回路デバイスの周辺部から離れて配置され、且つ図1及び2に示された集積回路デバイス3について上述したパッド23と同様に構成されている。図12に示された回路デバイス703上の接続パッド723は、チップの能動面719上に配置されている。このチップは、典型的には電子回路基板711から受信される電気信号によって作動される移動部品(図示せず)を有する。   Referring to FIGS. 12 and 13, the integrated circuit device package shown generally at 701 includes an integrated circuit device 703 mounted on an interconnect substrate 707. As shown in FIG. 12, the package 701 is electrically connected to an electrical circuit board 711 (eg, a printed circuit board, ball grid array, or land grid array) by conductive connection elements 715 on the interconnect board 707. Connected mechanically and mechanically. In one embodiment, the conductive connection element 715 is placed in electrical contact with the conductive connection element 717 on the electronic circuit board 711 to allow electrical signals to pass to the integrated circuit device package 701. Although integrated circuit device 703 is shown schematically, it should be understood that any type of circuit device that has an active surface 719 and requires a protected enclosed space. It may be a circuit device (for example, a MEMS device or an OE device). The integrated circuit device 703 has electrical connection pads 723. This pad is arranged away from the periphery of the circuit device and is configured similarly to the pad 23 described above for the integrated circuit device 3 shown in FIGS. The connection pads 723 on the circuit device 703 shown in FIG. 12 are disposed on the active surface 719 of the chip. The chip typically has moving parts (not shown) that are actuated by electrical signals received from an electronic circuit board 711.

典型的に、相互接続基板707は、回路デバイス703と同じチップ組立プロセスおよび同じ半導体材料(例えば、シリコン)を使用して作られている。この代わりに、相互接続基板は、窓(図示せず)を有するか、あるいは光が相互接続基板を通過して光学MEMSデバイス703に到達することを可能にする半透明材料からなることができる。相互接続基板707は、集積回路デバイス703の能動面719との接触に適用される第1面741と、電子回路基板711との電気的接続に適用される第2面745とを有する。図14及び15に最も良く見られるように、相互接続基板707は、複数の組の電気的接続パッドを有している。各組は、基板の第1面上の第1のパッド749と、基板の第2面上の第2のパッド753とを備える。各電気的接続パッド749,753は、相互接続基板707の周辺近くに配置されることが好ましい。図13に最も良く見られるように、相互接続基板707の接続パッド749,753は、相互接続基板を貫通する金属化されたビア759によって電気的に接続されている。相互接続基板707上の接続パッド749は、集積回路デバイス703の能動面719上の対応するパッド723と接触するように配列されている。また、相互接続基板の第2面745上のパッド753は、電子回路基板711の電気的接続パッド717との接続に適用される。   Typically, the interconnect substrate 707 is made using the same chip assembly process and the same semiconductor material (eg, silicon) as the circuit device 703. Alternatively, the interconnect substrate can have a window (not shown) or can be made of a translucent material that allows light to pass through the interconnect substrate to the optical MEMS device 703. The interconnect substrate 707 has a first surface 741 applied for contact with the active surface 719 of the integrated circuit device 703 and a second surface 745 applied for electrical connection with the electronic circuit substrate 711. As best seen in FIGS. 14 and 15, the interconnect substrate 707 has multiple sets of electrical connection pads. Each set comprises a first pad 749 on the first surface of the substrate and a second pad 753 on the second surface of the substrate. Each electrical connection pad 749, 753 is preferably disposed near the periphery of the interconnect substrate 707. As best seen in FIG. 13, the connection pads 749, 753 of the interconnect substrate 707 are electrically connected by metallized vias 759 that penetrate the interconnect substrate. The connection pads 749 on the interconnect substrate 707 are arranged to contact the corresponding pads 723 on the active surface 719 of the integrated circuit device 703. Further, the pad 753 on the second surface 745 of the interconnection substrate is applied to the connection with the electrical connection pad 717 of the electronic circuit substrate 711.

一実施形態では、相互接続基板707上の導電性接続要素715は、図1の集積回路デバイス3について上述した接続要素37と同様の導電性接続突起を備える。各突起715は、電気的接続パッド753と一体的に形成された金属化された突起でもよいし、通常の製造プロセスによって接続パッドに結合された金属突起でもよい。図12および14に見られるように、離れて配置された導電性接続要素717は、先の実施形態について上述された接続要素39と同様の突起を備える。相互接続基板707上の突起715と電子回路基板711上の突起717は、チップ・スケールパッケージ701と電子回路基板との間に電気的および機械的接続を形成するための噛み合わせに適用される。ここで理解されるべき点は、相互接続基板707上の突起715と電子回路基板711上の突起717は、先に論じられた導電性接続要素の実施形態のいずれか、あるいは集積回路デバイスを電子回路基板に接続することに一般的に使用される他の接続要素のいずれかを備えることができる。   In one embodiment, the conductive connection elements 715 on the interconnect substrate 707 comprise conductive connection protrusions similar to the connection elements 37 described above for the integrated circuit device 3 of FIG. Each protrusion 715 may be a metallized protrusion integrally formed with the electrical connection pad 753 or a metal protrusion coupled to the connection pad by a normal manufacturing process. As can be seen in FIGS. 12 and 14, the spaced apart conductive connection element 717 comprises a protrusion similar to the connection element 39 described above for the previous embodiment. The protrusions 715 on the interconnect substrate 707 and the protrusions 717 on the electronic circuit board 711 are applied to meshing to form an electrical and mechanical connection between the chip scale package 701 and the electronic circuit board. It should be understood that the protrusions 715 on the interconnect substrate 707 and the protrusions 717 on the electronic circuit board 711 can be integrated into any of the embodiments of the conductive connection elements discussed above or integrated circuit devices. Any of the other connection elements commonly used to connect to a circuit board can be provided.

図14および15に最もよく見られるように、相互接続基板707の第1面741は、相互接続基板の周辺エッジに沿って、回路デバイス703の能動面719に封止接触するための外縁773を有する。ここで理解されるべき点は、相互接続基板707と集積回路デバイス703は、半導体産業で一般的に使用される通常のウエハボンディング法(例えば、接着ボンディング、融合ボンディング、またはアノードボンディング)によって結合され得るということである。相互接続基板707の第1面741は、外縁773に隣接した肩部777を有する。この肩部は、集積回路デバイス703の対応する電気的接続パッド723と組み合う各電気的接続パッド749を支持する。図15の実施形態では、相互接続基板707の第1面741上の各電気的接続パッド749は、平坦な接触平面を有する。この接触平面は、集積回路デバイス703上のそれぞれの電気的接続パッド723の平坦な接触平面と組み合わされる。相互接続基板707は、肩部777に隣接した凹部781を有する。この凹部は、外縁773が集積回路デバイス703の能動面719と接触したときにパッケージの囲まれた空間を形成する。図示の実施形態では、凹部781は相互接続基板707上に配置され、そして相互接続基板の表面積の約60%から75%を備える。ここで理解されるべき点は、変化するサイズの1より多い凹部781が相互接続基板707上に存在できるということである。また、集積回路デバイス703は、凹部781と同様の凹部を備える能動面719を有するように構成できる。この場合、相互接続基板707の第1面791は、実質的に平坦となる。   As best seen in FIGS. 14 and 15, the first surface 741 of the interconnect substrate 707 has an outer edge 773 for sealing contact with the active surface 719 of the circuit device 703 along the peripheral edge of the interconnect substrate. Have. It should be understood that the interconnect substrate 707 and the integrated circuit device 703 are bonded by a conventional wafer bonding method commonly used in the semiconductor industry (eg, adhesive bonding, fusion bonding, or anode bonding). Is to get. The first surface 741 of the interconnect substrate 707 has a shoulder 777 adjacent to the outer edge 773. This shoulder supports each electrical connection pad 749 that mates with a corresponding electrical connection pad 723 of the integrated circuit device 703. In the embodiment of FIG. 15, each electrical connection pad 749 on the first surface 741 of the interconnect substrate 707 has a flat contact plane. This contact plane is combined with a flat contact plane for each electrical connection pad 723 on the integrated circuit device 703. Interconnect substrate 707 has a recess 781 adjacent to shoulder 777. This recess forms a space enclosed by the package when the outer edge 773 contacts the active surface 719 of the integrated circuit device 703. In the illustrated embodiment, the recess 781 is disposed on the interconnect substrate 707 and comprises about 60% to 75% of the surface area of the interconnect substrate. It should be understood that more than one recess 781 of varying size can exist on the interconnect substrate 707. Also, the integrated circuit device 703 can be configured to have an active surface 719 with a recess similar to the recess 781. In this case, the first surface 791 of the interconnect substrate 707 is substantially flat.

図16は、概略801で示される集積回路デバイスパッケージの第2の実施形態を示している。この実施形態801はパッケージ701の第1の実施形態と実質的に同じである。但し、相互接続基板707の第1面741上の電気的接続パッド805は尖った突起即ち歯809を備え、これらは集積回路デバイス703上の電気的接続パッド723と接触する。回路デバイス703が相互接続基板707に結合されるときに、尖った突起809は集積回路デバイス上の電気的接続パッド723に埋まって、集積回路デバイスを相互接続基板707との電気的接続状態に保持する付加的な機械力を与える。ここで理解されるべき点は、この発明の範囲を離れること無しに、突起809は異なるサイズ及び形状(例えば、鈍い端部を持つ円筒形の突起)を有してもよいということである。   FIG. 16 illustrates a second embodiment of an integrated circuit device package indicated generally at 801. This embodiment 801 is substantially the same as the first embodiment of the package 701. However, the electrical connection pads 805 on the first surface 741 of the interconnect substrate 707 include pointed protrusions or teeth 809 that contact the electrical connection pads 723 on the integrated circuit device 703. When the circuit device 703 is coupled to the interconnect substrate 707, the pointed protrusions 809 are embedded in the electrical connection pads 723 on the integrated circuit device to keep the integrated circuit device in electrical connection with the interconnect substrate 707. Gives additional mechanical power to do. It should be understood that the protrusions 809 may have different sizes and shapes (eg, cylindrical protrusions with blunt ends) without departing from the scope of the present invention.

図17は、概略831で示される集積回路デバイスパッケージの第3の実施形態を示している。この実施形態831はパッケージ701の第1の実施形態と実質的に同じである。但し、相互接続基板707の第1面741上の電気的接続パッド835は、この接続パッドから延びた1以上の導電性スプリング839を備える。スプリング839は、回路デバイスが僅かではあるが不整合であるときに、集積回路デバイス703と相互接続基板707との間の電気的接続を可能にする。このため、相互接続基板707上の電気的接続パッド835の平坦な表面は、回路デバイス上の電気的接続パッド723の平坦な表面に対して僅かに平行とはなっていない。スプリング839は、通常の組立技術を使用して通常のスプリング金属材料(例えば、モリブデンおよびクロム)によって、接続パッド835と一体的に形成されることが好ましい。米国特許第6,560,851号および5,613,861号が参照される。これらは、全ての目的について、通常のマイクロスプリング材料および組立プロセスについて、参照によりここに組み入れられる。   FIG. 17 illustrates a third embodiment of an integrated circuit device package, indicated generally at 831. This embodiment 831 is substantially the same as the first embodiment of the package 701. However, the electrical connection pad 835 on the first surface 741 of the interconnect substrate 707 includes one or more conductive springs 839 extending from the connection pad. The spring 839 allows an electrical connection between the integrated circuit device 703 and the interconnect substrate 707 when the circuit devices are slightly misaligned. For this reason, the flat surface of the electrical connection pads 835 on the interconnect substrate 707 is not slightly parallel to the flat surface of the electrical connection pads 723 on the circuit device. The spring 839 is preferably integrally formed with the connection pad 835 using conventional spring metal materials (eg, molybdenum and chrome) using conventional assembly techniques. Reference is made to US Pat. Nos. 6,560,851 and 5,613,861. These are hereby incorporated by reference for all purposes and for conventional microspring materials and assembly processes.

図18は、概略851で示される集積回路デバイスパッケージの第4の実施形態を示している。この実施形態851はパッケージ701の第1の実施形態と実質的に同じであるが、相互接続基板855を含んでいる。この基板は、導電性突起715(図12)の代わりに半田ボール859を備えた導電性要素を有する。パッケージ851を基板上に配置し、そしてパッケージを加熱して半田ボール859をリフローすることによって、パッケージ851は、電子回路基板711の導電性接続パッド(図示せず)上に通常の手段によって直接搭載される。この代わりに、この実施形態の導電性接続要素859は、他の材料からなることもできる。例えば、集積回路デバイスパッケージ851を電子回路基板711に対して電気的および機械的に接続することに使用され得る導電性接着剤である。   FIG. 18 shows a fourth embodiment of an integrated circuit device package, indicated generally at 851. This embodiment 851 is substantially the same as the first embodiment of package 701, but includes an interconnect substrate 855. This substrate has conductive elements with solder balls 859 instead of conductive protrusions 715 (FIG. 12). By placing the package 851 on the substrate and heating the package to reflow the solder balls 859, the package 851 is mounted directly on the conductive connection pads (not shown) of the electronic circuit board 711 by conventional means. Is done. Alternatively, the conductive connecting element 859 of this embodiment can be made of other materials. For example, a conductive adhesive that can be used to electrically and mechanically connect the integrated circuit device package 851 to the electronic circuit board 711.

図19〜21を参照すると、図12〜18に示された集積回路デバイスパッケージ701は、複数の個別集積回路デバイスパッケージを生じるウエハレベル組立プロセスによって形成され得る。このプロセスでは、複数の集積回路デバイス703を有する集積回路デバイスウエハ871を製造する。各デバイスは、能動面719と、この能動面上の複数の電気的接続パッド723とを有する。図19Bに示されているように、相互接続基板ウエハ875は、個別集積回路デバイスパッケージ701について上述された外縁773、肩部777および凹部781に対応する複数の表面を有するように製造される。相互接続基板ウエハ875は、基板の第1面741の肩部777上に作られた複数の電気的接続パッド749と、ウエハの第2面745上に作られた複数の導電性接続要素715とを有する。ここで理解されるべき点は、導電性接続要素715は、集積回路デバイス3上の導電性接続要素37について上述された方法のいずれかによって形成されるということである。またウエハ871,875は、通常のウエハ製造法によって製造される。米国特許第6,475,881号、6,159,826号、5,981,361号および5,685,885号が参照される。これらは、全ての目的について、通常のウエハ組立プロセスについて、参照によりここに組み入れられる。図20に示されるように、回路デバイスウエハ871および相互接続基板ウエハ875は、通常のボンディング法によって一緒に結合される。この場合、相互接続基板ウエハ875の第1面741から突出している外縁773は、集積回路デバイスウエハ871の能動面719に封止接触した状態に配置される。またウエハ871,875は、結合前に整合される。この場合、それらの電気的接続パッド723,749は互いに押し付けられて、集積回路デバイスウエハと相互接続基板ウエハとの間に電気的接続を作る。結合後に、連結されたウエハ871,875は、通常のダイシング法(例えば、レーザダイシングまたはソーイング)によって切断される。一実施形態では、ウエハ871,875は、カットライン879に沿って切断される。このカットラインは、集積回路デバイスウエハ871と接触しているウエハ875の外縁773に対応する相互接続基板ウエハ上の縁構造を通過している。カットライン879は、これら縁構造の中心を通ることが好ましい。切断されたウエハは、個別集積回路デバイスパッケージ701(図21)を生じる。このパッケージは、追加処理を必要とすることなしに、電子回路基板711に対して直接電気的及び機械的に接続する準備のできた導電性接続要素715を有している。   With reference to FIGS. 19-21, the integrated circuit device package 701 shown in FIGS. 12-18 may be formed by a wafer level assembly process resulting in a plurality of individual integrated circuit device packages. In this process, an integrated circuit device wafer 871 having a plurality of integrated circuit devices 703 is manufactured. Each device has an active surface 719 and a plurality of electrical connection pads 723 on the active surface. As shown in FIG. 19B, the interconnect substrate wafer 875 is fabricated to have a plurality of surfaces corresponding to the outer edge 773, shoulder 777, and recess 781 described above for the individual integrated circuit device package 701. The interconnect substrate wafer 875 includes a plurality of electrical connection pads 749 made on the shoulder 777 of the first surface 741 of the substrate and a plurality of conductive connection elements 715 made on the second surface 745 of the wafer. Have It should be understood that the conductive connection element 715 is formed by any of the methods described above for the conductive connection element 37 on the integrated circuit device 3. The wafers 871 and 875 are manufactured by a normal wafer manufacturing method. Reference is made to US Pat. Nos. 6,475,881, 6,159,826, 5,981,361 and 5,685,885. These are hereby incorporated by reference for all purposes and for the normal wafer assembly process. As shown in FIG. 20, the circuit device wafer 871 and the interconnect substrate wafer 875 are bonded together by a conventional bonding method. In this case, the outer edge 773 protruding from the first surface 741 of the interconnect substrate wafer 875 is placed in sealing contact with the active surface 719 of the integrated circuit device wafer 871. Also, the wafers 871 and 875 are aligned before bonding. In this case, the electrical connection pads 723 and 749 are pressed together to make an electrical connection between the integrated circuit device wafer and the interconnect substrate wafer. After bonding, the joined wafers 871 and 875 are cut by a normal dicing method (for example, laser dicing or sawing). In one embodiment, wafers 871 and 875 are cut along cut line 879. This cut line passes through the edge structure on the interconnect substrate wafer corresponding to the outer edge 773 of the wafer 875 in contact with the integrated circuit device wafer 871. The cut line 879 preferably passes through the centers of these edge structures. The cut wafer produces a discrete integrated circuit device package 701 (FIG. 21). The package has a conductive connection element 715 ready for direct electrical and mechanical connection to the electronic circuit board 711 without requiring additional processing.

本発明のパッケージ701は、集積回路デバイス703のサイズに近いチップスケールパッケージ(CSP)であって、直接チップ取り付けによって基板に搭載されるベアチップと比較したときに、必要とされる追加的な回路基板搭載面積は非常に小量である。ここで理解されるべき点は、パッケージ701が、ベア集積回路デバイス703と比較して、相互接続基板707の外縁773の幅とほぼ等しい量だけ大きな基板搭載面積を占有するということである。パッケージ701は、ベア集積回路デバイスの搭載面積よりも約1〜20%大きな基板搭載面積を有することが好ましい。このパッケージの基板搭載面積は、ベア集積回路デバイスの基板搭載面積よりも約1〜10%大きいことが更に好ましい。このパッケージの基板搭載面積は、ベア集積回路デバイスの基板搭載面積よりも約1%大きいことが最も好ましい。   The package 701 of the present invention is a chip scale package (CSP) close to the size of the integrated circuit device 703, which is an additional circuit board required when compared to a bare chip mounted on the board by direct chip attachment. The mounting area is very small. It should be understood that the package 701 occupies a larger substrate mounting area than the bare integrated circuit device 703 by an amount approximately equal to the width of the outer edge 773 of the interconnect substrate 707. The package 701 preferably has a substrate mounting area that is approximately 1 to 20% larger than the mounting area of the bare integrated circuit device. More preferably, the substrate mounting area of this package is approximately 1-10% larger than the substrate mounting area of the bare integrated circuit device. The substrate mounting area of this package is most preferably about 1% larger than the substrate mounting area of the bare integrated circuit device.

上記の点を考慮すると、この発明のいくつかの目的が達成され、そして他の有利な結果が得られることが判明する。チップモジュール1の第1の突起37と第2の突起39との間の摩擦係合は、熱の適用およびその結果の熱的ストレスなしに、基板13に対する集積回路デバイス3の組立および取り付けを可能とする。回路デバイス3及び基板13上の第1の突起37及び第2の突起39は、テスト後にデバイスが容易に基板から除去され、また広範囲な作り直しなしに基板に再接続されることを可能にする。また、第1及び第2の突起37,39間の摩擦係合は、最終アセンブリ内の集積回路デバイス3の容易な修理と交換を可能とする。第1及び第2突起の37,39は、チップまたは基板の製造プロセス中に容易に製造できる。あるいは、これらの突起は、チップまたは基板の組立プロセス完了後の追加工程として組立できる。集積回路デバイスパッケージ701は、パッケージから回路基板711への電気的接続用に追加の処理を必要としない単純なウエハレベルのプロセスで製造できる。集積回路デバイスパッケージ701は、集積回路デバイス703を保護するための囲まれた空間を与え、しかも回路基板搭載面積を最小化する。集積回路デバイスパッケージ701,851上の導電性接続要素715,859は、パッケージが容易に電子基板711に搭載され、またそこから除去されることを可能にする。   In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results are obtained. The frictional engagement between the first protrusion 37 and the second protrusion 39 of the chip module 1 allows the assembly and attachment of the integrated circuit device 3 to the substrate 13 without the application of heat and the resulting thermal stress. And The first protrusion 37 and the second protrusion 39 on the circuit device 3 and the substrate 13 allow the device to be easily removed from the substrate after testing and reconnected to the substrate without extensive rework. Also, the frictional engagement between the first and second protrusions 37, 39 allows for easy repair and replacement of the integrated circuit device 3 in the final assembly. The first and second protrusions 37 and 39 can be easily manufactured during a chip or substrate manufacturing process. Alternatively, these protrusions can be assembled as an additional step after completion of the chip or substrate assembly process. The integrated circuit device package 701 can be manufactured with a simple wafer level process that does not require additional processing for electrical connection from the package to the circuit board 711. The integrated circuit device package 701 provides an enclosed space for protecting the integrated circuit device 703 and minimizes the circuit board mounting area. Conductive connection elements 715, 859 on the integrated circuit device packages 701, 851 allow the package to be easily mounted on and removed from the electronic substrate 711.

この発明の範囲から離れることなしに種々の変形が上記の構成に対してなされ得るので、上記説明に含まれたり、添付の図面に示された全ての事項は、説明用として解釈されるべきものであって、限定するためのものではない。例えば、第1及び第2突起の37,39は、集積回路デバイス3と基板3を電気的および機械的接触状態に保持する摩擦係合を可能とする代替の形状およびサイズを持つことができる。また第1及び/又は第2突起の37,39は、それぞれの電気的接続パッド23,27と一体的に形成されたり、あるいは集積回路デバイス3または基板13の一体的な部分として構成することができる。更には、第1及び/又は第2突起の37,39は、それぞれの電気的接続パッド23,27に取り付けられたか一体的に形成された共通の基部を有する指状の突起でもよい。   Since various modifications can be made to the above configuration without departing from the scope of the present invention, all matters included in the above description and shown in the accompanying drawings should be construed for the purpose of description. And not for limitation. For example, the first and second protrusions 37, 39 may have alternative shapes and sizes that allow for frictional engagement that holds the integrated circuit device 3 and the substrate 3 in electrical and mechanical contact. The first and / or second protrusions 37 and 39 may be formed integrally with the respective electrical connection pads 23 and 27, or may be configured as an integrated part of the integrated circuit device 3 or the substrate 13. it can. Furthermore, the first and / or second protrusions 37 and 39 may be finger-like protrusions having a common base attached to or integrally formed with the respective electrical connection pads 23 and 27.

本発明またはその好ましい実施形態の要素を紹介するときに、冠詞“a”、“an”、“the”および“said”は、これら要素の1以上があることを意味することを意図されている。用語“comprising”、“including”および“having”は、包含的であって、掲載された要素以外に追加の要素もあり得ることを意味することが意図されている。   When introducing elements of the present invention or its preferred embodiments, the articles “a”, “an”, “the” and “said” are intended to mean that there is one or more of these elements. . The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

本発明のアセンブリを示すチップモジュールの一部断面とした立面図である。It is the elevation view made into the partial cross section of the chip module which shows the assembly of this invention. 前記モジュールの集積回路デバイスおよび基板の分解斜視図である。It is a disassembled perspective view of the integrated circuit device and board | substrate of the said module. 前記アセンブリの第1実施形態における集積回路デバイス側電気的接続パッドおよび基板側電気的接続パッドの拡大斜視図である。FIG. 2 is an enlarged perspective view of an integrated circuit device side electrical connection pad and a substrate side electrical connection pad in the first embodiment of the assembly. 図3の線4−4を含んだ面における断面図である。FIG. 4 is a cross-sectional view of a plane including line 4-4 in FIG. 3. 図4の線5−5を含んだ面における断面図である。It is sectional drawing in the surface containing the line 5-5 of FIG. 図5と同様の断面図であるが、集積回路デバイス側電気的接続パッドおよび基板側電気的接続パッドが完全に噛み合った状態を示す。FIG. 6 is a cross-sectional view similar to FIG. 5, but showing a state where the integrated circuit device side electrical connection pads and the substrate side electrical connection pads are completely engaged. 第1実施形態の集積回路デバイスおよび基板の拡大立側面図である。1 is an enlarged side elevational view of an integrated circuit device and a substrate of a first embodiment. 本発明の第2実施形態の集積回路デバイス側電気的接続パッドの拡大斜視図である。It is an expansion perspective view of the integrated circuit device side electrical connection pad of 2nd Embodiment of this invention. 図4と同様の断面図であるが、本発明の第3実施形態を示す。FIG. 5 is a cross-sectional view similar to FIG. 4, but illustrating a third embodiment of the present invention. 本発明の第4実施形態における集積回路デバイス側電気的接続パッドおよび基板側電気的接続パッドの拡大斜視図である。It is an expansion perspective view of the integrated circuit device side electrical connection pad and board | substrate side electrical connection pad in 4th Embodiment of this invention. 図7の線11−11を含んだ面における断面図である。It is sectional drawing in the surface containing the line 11-11 of FIG. 電子回路基板に取り付けられた本発明の集積回路デバイスパッケージの立面図である。1 is an elevational view of an integrated circuit device package of the present invention attached to an electronic circuit board. FIG. 電子回路基板から取り外された図12のパッケージの断面図である。FIG. 13 is a cross-sectional view of the package of FIG. 12 removed from the electronic circuit board. 電子回路基板から取り外されたパッケージの分解立面図である。It is an exploded elevation view of the package removed from the electronic circuit board. 前記パッケージの第1実施形態の一部断面とした集積回路デバイスおよび相互接続基板の断片的拡大図である。FIG. 2 is a fragmentary enlarged view of an integrated circuit device and interconnect substrate in partial cross section of the first embodiment of the package. 前記パッケージの第2実施形態の一部断面とした集積回路デバイスおよび相互接続基板の断片的拡大図である。FIG. 6 is a fragmentary enlarged view of an integrated circuit device and interconnect substrate in partial cross section of a second embodiment of the package. 前記パッケージの第3実施形態の一部断面とした集積回路デバイスおよび相互接続基板の断片的拡大図である。FIG. 6 is a fragmentary enlarged view of an integrated circuit device and interconnect substrate in partial cross section of a third embodiment of the package. 図13と同様の断面図であるが、本発明の第4実施形態を示す。FIG. 14 is a cross-sectional view similar to FIG. 13, but showing a fourth embodiment of the present invention. 本発明の集積回路デバイスパッケージを形成するためのプロセスで使用される集積回路デバイスウエハおよび相互接続基板ウエハの斜視図である。1 is a perspective view of an integrated circuit device wafer and an interconnect substrate wafer used in a process for forming an integrated circuit device package of the present invention. FIG. 集積回路デバイスウエハの拡大立側面図である。It is an enlarged side elevational view of an integrated circuit device wafer. 相互接続基板ウエハの拡大立側面図である。FIG. 3 is an enlarged side elevation view of an interconnect substrate wafer. この発明のプロセスにより接続された集積回路デバイスウエハおよび相互接続基板ウエハの斜視図である。1 is a perspective view of an integrated circuit device wafer and an interconnect substrate wafer connected by the process of this invention. FIG. このプロセスにより作成された集積回路デバイスパッケージの斜視図である。It is a perspective view of the integrated circuit device package created by this process.

符号の説明Explanation of symbols

全図面を通して、対応する部分は、対応する参照符号によって示される。
3 集積回路デバイス
13 チップキャリア基板
23,27 電気的接続パッド
37 第1の突起
39 第2の突起
701 パッケージ
707 相互接続基板
711 電子回路基板
Corresponding parts are designated by corresponding reference numerals throughout the drawings.
DESCRIPTION OF SYMBOLS 3 Integrated circuit device 13 Chip carrier board | substrate 23,27 Electrical connection pad 37 1st protrusion 39 2nd protrusion 701 Package 707 Interconnection board 711 Electronic circuit board

Claims (26)

基板と、
この基板に対し電気的および機械的に接続されるように適用される集積回路デバイスと、
前記集積回路デバイス上および前記基板上にあって、前記回路デバイスと前記基板が接続されるときに互いに接触するように適用される電気的接続パッドとを備え、
前記接続パッドは、少なくとも1つの第1の突起を前記デバイスおよび前記基板の一方の上に、また少なくとも2つの第2の突起を前記デバイスおよび前記基板の他方の上に有し、各突起はそれぞれの接続パッドの外面から延びたそれぞれの軸方向の長さを有し、
前記少なくとも1つの第1の突起と前記少なくとも2つの第2の突起は、互いに噛み合ったときに、それらの軸方向の長さに沿って緊密な摩擦嵌合をするためにサイズおよび形状が設定されたそれぞれの外面を有し、これによりそれぞれの突起の間に軸方向の接触面積を作って、前記デバイスと前記基板との間に電気的および機械的な接続を確立することを特徴とするアセンブリ。
A substrate,
An integrated circuit device adapted to be electrically and mechanically connected to the substrate;
Electrical connection pads on the integrated circuit device and on the substrate and applied to contact each other when the circuit device and the substrate are connected;
The connection pad has at least one first protrusion on one of the device and the substrate, and at least two second protrusions on the other of the device and the substrate, each protrusion being respectively Each having an axial length extending from the outer surface of the connection pad,
The at least one first protrusion and the at least two second protrusions are sized and shaped to provide a tight friction fit along their axial length when engaged with each other. An assembly having a respective outer surface thereby creating an axial contact area between the respective protrusions to establish an electrical and mechanical connection between the device and the substrate .
前記少なくとも1つの第1の突起は、前記集積回路デバイス上にあり、また前記少なくとも2つの第2の突起は、前記基板上にある請求項1に記載のアセンブリ。   The assembly of claim 1, wherein the at least one first protrusion is on the integrated circuit device and the at least two second protrusions are on the substrate. 前記少なくとも1つの第1の突起は、頭部のない突起である請求項1に記載のアセンブリ。   The assembly of claim 1, wherein the at least one first protrusion is a headless protrusion. 前記少なくとも1つの第1の突起は、前記回路デバイスまたは基板と一体的に形成された固体の円筒形本体を備え、そして前記少なくとも2つの第2の突起と接触するための金属外面を備える請求項1に記載のアセンブリ。   The at least one first protrusion comprises a solid cylindrical body integrally formed with the circuit device or substrate and comprises a metal outer surface for contacting the at least two second protrusions. The assembly according to 1. 前記少なくとも2つの第2の突起は、固体の円筒形本体を備え、前記少なくとも1つの第1の突起を受けるオープンスペースを形成するために離れて配置されている請求項4に記載のアセンブリ。   The assembly of claim 4, wherein the at least two second protrusions comprise a solid cylindrical body and are spaced apart to form an open space that receives the at least one first protrusion. 前記少なくとも1つの第1の突起は、前記オープンスペースへ挿入するために適用され、このとき前記デバイスと基板は、前記少なくとも1つの第1の突起と前記少なくとも2つの第2の突起のそれぞれの軸方向の長さの間における摩擦嵌合によって、電気的および機械的に接続された状態に保持される請求項5に記載のアセンブリ。   The at least one first protrusion is adapted for insertion into the open space, wherein the device and the substrate are respectively axes of the at least one first protrusion and the at least two second protrusions. 6. The assembly of claim 5, wherein the assembly is held in an electrically and mechanically connected state by a friction fit between directional lengths. 前記少なくとも1つの第1の突起は、切頭体である請求項1に記載のアセンブリ。   The assembly of claim 1, wherein the at least one first protrusion is a truncated body. 前記少なくとも1つの第1の突起と前記少なくとも2つの第2の突起は、楕円形断面を有する請求項1に記載のアセンブリ。   The assembly of claim 1, wherein the at least one first protrusion and the at least two second protrusions have an elliptical cross section. 前記少なくとも1つの第1の突起と前記複数の第2の突起は、多角形断面を有する請求項1に記載のアセンブリ。   The assembly of claim 1, wherein the at least one first protrusion and the plurality of second protrusions have a polygonal cross-section. 能動面を有し、その上に少なくとも1つの電気的接続パッドを有した集積回路デバイスと、
この集積回路デバイスを電子回路基板上に搭載するための相互接続基板とを備え、
前記相互接続基板は、囲まれた空間を形成するために前記集積回路デバイスの能動面と組み合わされるように適用される第1面と、前記電子回路基板との電気的および機械的接続に適用される第2面とを有し、
前記相互接続基板は、少なくとも1組の電気的接続パッドを有し、各組は、前記集積回路デバイス上の少なくとも1つの電気的接続パッドとの電気的接続に適用される前記相互接続基板の第1面上の第1の電気的接続パッドと、この第1の接続パッドに電気的に接続される前記相互接続基板の第2面上の第2の電気的接続パッドと備え、前記相互接続基板の第2面上の前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続に適用されることを特徴とする集積回路デバイスパッケージ。
An integrated circuit device having an active surface and having at least one electrical connection pad thereon;
An interconnection substrate for mounting the integrated circuit device on the electronic circuit substrate,
The interconnect substrate is applied to electrical and mechanical connections between the electronic circuit board and a first surface applied to be combined with an active surface of the integrated circuit device to form an enclosed space. A second surface,
The interconnect substrate has at least one set of electrical connection pads, each set being adapted for electrical connection with at least one electrical connection pad on the integrated circuit device. A first electrical connection pad on one surface; and a second electrical connection pad on a second surface of the interconnect substrate electrically connected to the first connection pad, the interconnect substrate. The integrated circuit device package, wherein the second electrical connection pads on the second surface of the integrated circuit device are applied for electrical and mechanical connection with the electronic circuit board.
前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続用の半田ボールである請求項10に記載のパッケージ。   The package according to claim 10, wherein the second electrical connection pad is a solder ball for electrical and mechanical connection with the electronic circuit board. 前記第2の電気的接続パッドは、前記第2の電気的接続パッドの外面から延びた実質的に堅い円筒形本体を有する突起である請求項10に記載のパッケージ。   The package of claim 10, wherein the second electrical connection pad is a protrusion having a substantially rigid cylindrical body extending from an outer surface of the second electrical connection pad. 前記第2の電気的接続パッドは、少なくとも1つの導電性接続要素を前記相互接続基板上に備え、更に前記相互接続基板上の少なくとも1つの導電性接続要素と組み合わされることに適用される少なくとも2つの導電性接続要素を前記電子回路基板上に備え、前記電子回路基板上および前記相互接続基板上の導電性接続要素は、互いに緊密に噛み合った摩擦嵌合をするためにサイズおよび形状が設定され、これにより前記パッケージと前記電子回路基板との間に電気的および機械的な接続を確立する請求項10に記載のパッケージ。   The second electrical connection pad comprises at least one conductive connection element on the interconnect substrate and is further adapted to be combined with at least one conductive connection element on the interconnect substrate. Two conductive connecting elements on the electronic circuit board, the conductive connecting elements on the electronic circuit board and the interconnect board being sized and shaped for a close intimate frictional fit The package of claim 10, thereby establishing an electrical and mechanical connection between the package and the electronic circuit board. 前記相互接続基板上の第1の導電性接続パッドは、前記集積回路デバイスの電気的接続パッドとの接触に適用される少なくとも1つの突起を備える請求項10に記載のパッケージ。   The package of claim 10, wherein the first conductive connection pad on the interconnect substrate comprises at least one protrusion adapted for contact with an electrical connection pad of the integrated circuit device. 前記相互接続基板上の第1の導電性接続パッドは、前記集積回路デバイスの電気的接続パッドとの接触に適用される少なくとも1つのスプリングを備える請求項10に記載のパッケージ。   The package of claim 10, wherein a first conductive connection pad on the interconnect substrate comprises at least one spring applied in contact with an electrical connection pad of the integrated circuit device. 前記相互接続基板の第1面は、前記集積回路デバイスに封止接触するための外縁と、この外縁が前記集積回路デバイスと接触したときに前記囲まれた空間を形成する凹部とを備える請求項10に記載のパッケージ。   The first surface of the interconnect substrate includes an outer edge for sealing contact with the integrated circuit device, and a recess that forms the enclosed space when the outer edge contacts the integrated circuit device. The package according to 10. 前記相互接続基板の第1面は、前記凹部と前記外縁との間に、前記相互接続基板の第1の導電性接続パッドを配置するための肩部を更に備える請求項16に記載のパッケージ。   The package of claim 16, wherein the first surface of the interconnect substrate further comprises a shoulder for disposing a first conductive connection pad of the interconnect substrate between the recess and the outer edge. 集積回路デバイスパッケージを形成するためのプロセスであって、
能動面を有する集積回路デバイスウエハを作成する工程と、
相互接続基板ウエハを、このウエハがその対向する面上に電気的接続パッドを有し、また1つの凹んだ表面を有するように作成する工程と、
前記集積回路デバイスウエハと相互接続基板ウエハを電気的および機械的に接続して、前記2つのウエハが、前記集積回路デバイスウエハの能動面と前記相互接続基板ウエハの凹んだ表面との間に囲まれた空間を形成する工程と、
前記集積回路デバイスウエハと相互接続基板ウエハをダイシングして、1以上の個別集積回路デバイスパッケージを形成する工程とを備えることを特徴とするプロセス。
A process for forming an integrated circuit device package comprising:
Creating an integrated circuit device wafer having an active surface;
Creating an interconnect substrate wafer such that the wafer has electrical connection pads on its opposite side and a concave surface;
Electrically and mechanically connecting the integrated circuit device wafer and the interconnect substrate wafer, the two wafers are enclosed between an active surface of the integrated circuit device wafer and a recessed surface of the interconnect substrate wafer. Forming a space,
Dicing the integrated circuit device wafer and the interconnect substrate wafer to form one or more individual integrated circuit device packages.
前記相互接続基板ウエハを作成する工程は、前記相互接続基板ウエハを、電子回路基板への電気的および機械的接続用の少なくとも1つの導電性接続要素を有するように構成する工程を含む請求項18に記載のプロセス。   19. Creating the interconnect substrate wafer includes configuring the interconnect substrate wafer to have at least one conductive connection element for electrical and mechanical connection to an electronic circuit board. The process described in 前記ダイシング工程は、結合したウエハを前記1以上の個別集積回路デバイスパッケージへ切断する工程を含む請求項19に記載のプロセス。   The process of claim 19, wherein the dicing step includes cutting the bonded wafer into the one or more discrete integrated circuit device packages. 集積回路デバイスを電子回路基板上に搭載するための相互接続基板であって、
前記集積回路デバイスの能動面と組み合わされて囲まれた空間を形成することに適用される第1面と、前記電子回路基板との電気的および機械的接続に適用される第2面と、
前記相互接続基板の第1面上にあって、前記集積回路デバイスとの電気的接続に適用される第1の電気的接続パッドと、
前記相互接続基板の第2面上にあって、前記第1の接続パッドに電気的に接続された第2の電気的接続パッドと備え、
前記相互接続基板の第2面上の前記第2の電気的接続パッドは、前記電子回路基板との電気的および機械的接続に適用されるものであることを特徴とする相互接続基板。
An interconnect substrate for mounting an integrated circuit device on an electronic circuit substrate,
A first surface applied to form an enclosed space in combination with an active surface of the integrated circuit device; a second surface applied to electrical and mechanical connection with the electronic circuit board;
A first electrical connection pad on a first surface of the interconnect substrate and applied for electrical connection with the integrated circuit device;
A second electrical connection pad on the second surface of the interconnect substrate and electrically connected to the first connection pad;
The interconnect board according to claim 2, wherein the second electrical connection pad on the second surface of the interconnect board is applied to an electrical and mechanical connection with the electronic circuit board.
前記相互接続基板の第1面は、前記集積回路デバイスに封止接触するための外縁を備える請求項21に記載の相互接続基板。   The interconnect substrate of claim 21, wherein the first surface of the interconnect substrate comprises an outer edge for sealing contact with the integrated circuit device. 前記相互接続基板の第1面は、前記外縁が前記集積回路デバイスと接触したときに前記囲まれた空間を形成する凹部を更に備える請求項22に記載の相互接続基板。   23. The interconnect substrate of claim 22, wherein the first surface of the interconnect substrate further comprises a recess that forms the enclosed space when the outer edge contacts the integrated circuit device. 前記相互接続基板の第1面は、前記凹部と前記外縁との間に、前記第1の導電性接続パッドを配置するための肩部を更に備える請求項22に記載の相互接続基板。   The interconnect substrate according to claim 22, wherein the first surface of the interconnect substrate further includes a shoulder for disposing the first conductive connection pad between the recess and the outer edge. 前記第1の導電性接続パッドは、前記集積回路デバイス上の電気的接続パッドとの接触に適用される少なくとも1つの突起を備える請求項22に記載の相互接続基板。   The interconnect substrate of claim 22, wherein the first conductive connection pad comprises at least one protrusion adapted for contact with an electrical connection pad on the integrated circuit device. 前記第1の導電性接続パッドは、前記集積回路デバイス上の電気的接続パッドとの接触に適用される少なくとも1つのスプリングを備える請求項22に記載の相互接続基板。   The interconnect substrate of claim 22, wherein the first conductive connection pad comprises at least one spring applied in contact with an electrical connection pad on the integrated circuit device.
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