JP2005051045A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of reducing the resistance ratio when connecting the upper electrode of a trench capacitor to the diffusion layer of a transistor, and to provide a semiconductor device. <P>SOLUTION: In the method for manufacturing a semiconductor device, there are provided a process for forming an upper electrode film 15a on a capacitor insulating film 14 so that a trench 12 is buried, and for adjusting the etching rate of the upper electrode film 15a in the trench 12 so that the etching rate becomes lower from an inner-wall side to the center side; a process for etchedly removing the upper electrode film 15a to a trench lower portion 12a to form an upper electrode 15; a process for forming an insulating film on a substrate 11 and the upper electrode 15, so that an inner wall in a trench upper portion 12b is covered before the insulating film is etchedly removed to form a sidewall insulating film 16 on the sidewall of the trench upper portion 12b; and a process for forming an extraction electrode 17 connected to the upper electrode 15 by burying the trench upper portion 12b by a conductive film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a trench capacitor of a DRAM and the semiconductor device.

  With recent miniaturization of semiconductor devices, especially in DRAM cells, the area occupied by capacitors tends to be reduced, and the increase in capacitor capacity is severe. Under such circumstances, studies have been made on increasing the capacitance of the capacitor by devising the capacitor structure, and a trench type capacitor structure in which a trench is formed in a substrate and a capacitor is formed therein has been studied ( For example, refer nonpatent literature 1).

“International Electron Devices Meeting” (USA), 1993, p. 627-630

  Here, a conventional manufacturing method of a semiconductor device provided with a trench capacitor will be described. First, as shown in FIG. 4A, a mask pattern (not shown) is formed on the substrate 11, and etching is performed to form a trench 12 in the substrate 11. Next, a diffusion layer is formed by introducing impurities into the inner wall of the lower region (trench lower portion 12 a) of the trench 12 in the substrate 11, thereby forming the lower electrode 13. Thereafter, a capacitor insulating film 14 is formed on the substrate 11 so as to cover the inner wall of the trench 12.

  Next, as shown in FIG. 4B, for example, by chemical vapor deposition (hereinafter abbreviated as CVD) so as to fill the trench 12 in which the capacitor insulating film 14 is formed, for example, An upper electrode film 15a made of a polysilicon film is formed. At the time of film formation, impurities such as arsenic (As) are added to the process gas to introduce impurities into the upper electrode film 15a.

  In addition, in order to reliably introduce impurities into the upper electrode film 15a in the trench 12, the upper electrode film 15a may be formed of a multilayer film of polysilicon. In this case, the inner wall of the trench 12 is covered. After a thin film of an undoped polysilicon layer is formed, and then a series of steps of adsorbing impurities such as As on the surface of the polysilicon layer are performed a plurality of times, the center side of the trench 12 is undoped polysilicon. Embed with layers.

  In the formation of the upper electrode film 15a, as described above, even if the upper electrode film 15a is a single layer film or a multilayer film, a seam A (joint) is formed on the center side of the upper electrode film 15a in the trench 12. Will occur.

  Next, as shown in FIG. 5C, by performing an etch back, the upper electrode film 15a (see FIG. 4B) is retracted to the depth of the trench lower portion 12a where the lower electrode 13 is provided, The upper electrode 15 is formed.

  Thereafter, the upper region of trench 12 (trench upper portion 12b) and capacitor insulating film 14 exposed on substrate 11 are removed. In this way, a trench capacitor is formed in the trench 12.

  Next, as shown in FIG. 5D, after an insulating film is formed on the upper electrode 15 and the substrate 11 so as to cover the inner wall of the trench upper portion 12b, the insulation on the upper electrode 15 and the substrate 11 is performed. The film is removed by etching to form a sidewall insulating film 16 on the inner wall of the upper trench portion 12b. This sidewall insulating film 16 is for preventing the generation of parasitic transistors, and it is necessary to have a sufficient film thickness. Thereafter, the uppermost sidewall insulating film 16 of the upper trench portion 12b is removed to expose the uppermost sidewall of the trench 12.

  Next, after burying a conductive film in the trench upper part 12b and forming the lead electrode 17 connected to the upper electrode 15, a transistor is formed on the substrate 11, and a diffusion layer (not shown) of this transistor and the trench capacitor are formed. The upper electrode 15 is connected via the extraction electrode 17.

  However, in the semiconductor device manufacturing method as described above, as shown in FIG. 5C, when the upper electrode film 15a (see FIG. 4B) is etched back to form the upper electrode 15, The upper electrode film 15a is retracted to the depth of the trench lower part 12a where the lower electrode 13 is formed. As a result, the etchant also enters from above the seam A of the upper electrode film 15a, the central portion of the surface of the upper electrode 15 is excessively removed, and a deep recess B is formed on the surface of the upper electrode 15.

  Further, when the upper electrode film 15a is formed of a multilayer film, the film forming process and the impurity adsorption process are repeated, so that a plurality of impurity adsorption layers are formed in the film thickness direction of the upper electrode film 15a in the trench 12. Is done. Here, the impurity concentration in the vicinity of the impurity adsorption layer is locally high, and generally the higher the impurity concentration, the higher the etching rate. Therefore, when the upper electrode 15 is formed by etching back the upper electrode film 15a, the vicinity of the plurality of impurity adsorption layers on the surface of the upper electrode 15 is excessively removed, so that the surface of the upper electrode 15 is uneven. There was a tendency to become a shape (not shown).

  In this way, the depression B is formed on the surface of the upper electrode 15 and the surface is uneven, so that the thick sidewall insulating film 16 is formed on the inner wall of the trench upper portion 12a as shown in FIG. When the insulating film is formed on the upper electrode 15 so as to cover the inner wall of the upper portion 12a of the trench, the insulating film on the upper electrode 15 is removed by etching to insulate the recess B or the recess on the surface of the upper electrode 15. The film tends to remain.

  For this reason, there is a tendency that the resistance when the lead electrode 17 is formed on the upper electrode 15 and connected is increased. This increases the resistance when connecting the diffusion layer of the transistor formed on the substrate 11 and the upper electrode 15 of the trench capacitor via the lead electrode 17, resulting in a problem that conduction failure occurs and yield is reduced. It was happening.

  In order to solve the above-described problems, a semiconductor device manufacturing method of the present invention includes a trench capacitor in which at least a capacitor insulating film and an upper electrode are sequentially stacked from the lower layer on an inner wall of a trench formed in a substrate. The upper electrode film is formed on the capacitor insulating film so as to fill the trench, and the etching rate of the upper electrode film in the trench is adjusted so as to decrease from the inner wall side toward the center side. A first step, a second step of forming the upper electrode by etching and removing the upper electrode film to the lower region of the trench, and the substrate and the upper electrode so as to cover the inner wall of the trench in which the upper electrode is formed After the insulation film is formed, the insulation film on the substrate and the upper electrode is removed by etching to form a sidewall insulation film on the inner wall of the upper region of the trench. A third step that, by embedding the upper region of the trench sidewall insulating film is formed of a conductive film, is characterized by a fourth step of forming a lead-out electrode connected to the upper electrode.

  According to such a method for manufacturing a semiconductor device, the etching rate of the upper electrode film in the trench is adjusted so as to decrease from the inner wall side toward the center side. As a result, when the upper electrode film is formed by removing the upper electrode film by etching, the upper electrode film is removed in a state depending on the etching rate, so that the upper electrode film on the center side of the trench, particularly in the vicinity of the seam. Becomes difficult to be etched. For this reason, even if an etchant enters from the seam of the upper electrode film, the central portion of the upper electrode surface is not excessively removed and the formation of a deep depression is prevented as in the semiconductor device described in the prior art. be able to.

  In addition, since there is no portion where the etching rate locally increases at the central portion in the film thickness direction of the upper electrode film in the trench, the upper electrode is formed when the upper electrode film is removed by etching. It is possible to prevent the film from being locally removed excessively, and to suppress the surface of the upper electrode from becoming uneven.

  Therefore, in the subsequent step of forming a thick sidewall insulating film, an insulating film is formed on the substrate and the upper electrode so as to cover the inner wall of the upper region of the trench, and the insulating film on the upper electrode is removed. In this case, the insulating film can be prevented from remaining on the surface of the upper electrode.

  Further, the semiconductor device obtained by the above manufacturing method is a semiconductor device including a trench capacitor in which at least a capacitor insulating film and an upper electrode are sequentially laminated from the lower layer on the inner wall of a trench formed in a substrate, The inner upper electrode is formed such that the etching rate decreases from the inner wall side toward the center side.

  According to such a semiconductor device, the upper electrode in the trench is formed so that the etching rate decreases from the inner wall side toward the center side, so that the surface of the upper electrode is suppressed from being deeply depressed or uneven due to etching. Thus, the insulating film is prevented from remaining in the recesses or recesses. For this reason, the resistance in the case of connecting this upper electrode and the extraction electrode provided on the upper electrode can be lowered. Therefore, it is possible to reduce the resistance when connecting the upper electrode of the trench capacitor and the diffusion layer of the transistor provided on the substrate via the extraction electrode, and conduction can be ensured.

  As described above, according to the method for manufacturing a semiconductor device of the present invention and the semiconductor device obtained thereby, the etching rate of the upper electrode film in the trench is adjusted so as to decrease from the inner wall side toward the center side. . Thus, when the upper electrode film is etched back in a state depending on the etching rate and the upper electrode is formed, even if the etchant enters from the seam of the upper electrode film, the upper electrode film on the center side of the trench is Etching is suppressed. For this reason, it is possible to prevent a deep depression from occurring on the upper electrode surface without excessively removing the central portion of the upper electrode surface. In addition, since there is no portion where the etching rate locally increases at the central portion in the film thickness direction of the upper electrode film in the trench, the upper electrode is formed when the upper electrode film is removed by etching. The film is not locally removed excessively, and the surface of the upper electrode can be prevented from being uneven.

  Therefore, it is possible to prevent the insulating film from remaining on the surface of the upper electrode in the step of forming the sidewall insulating film on the inner wall of the upper region of the trench. For this reason, it is possible to reduce the resistance when the lead electrode is formed and connected on the upper electrode. Therefore, when the upper electrode of the trench capacitor and the diffusion layer of the transistor provided on the substrate are connected via the extraction electrode, the resistance can be reduced, and conduction can be ensured and the yield can be improved. Is possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
An example of an embodiment relating to a method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process sectional views of FIGS. In the present embodiment, the configuration of the semiconductor device will be described in the order of manufacturing steps. In addition, the same number is attached | subjected and demonstrated to the structure similar to what was demonstrated by the prior art.

  First, as shown in FIG. 1A, a mask pattern (not shown) is formed on a substrate 11 made of a silicon substrate, for example, and etching is performed in the same manner as in a technique for forming a normal trench. A trench 12 is formed in 11.

  Next, a diffusion layer is formed by doping, for example, arsenic (As) on the inner wall of the lower portion of the trench 12 (the trench lower portion 12 a) in the substrate 11 by, for example, a solid phase diffusion method, and this diffusion layer is used as the lower electrode 13. Thereafter, a capacitor insulating film 14 made of, for example, silicon oxynitride is formed on the substrate 11 so as to cover the inner wall of the trench 12.

  Next, as shown in FIG. 1B, the upper electrode film made of polysilicon so as to fill the trench 12 in which the capacitor insulating film 14 is formed by, for example, a CVD method using silane gas (SiH 4) as a source gas. 15a is formed. Here, at the time of film formation, an impurity such as As is added to the process gas, and the amount of the impurity added to the process gas is gradually reduced over time until the trench 12 is filled.

  By forming the upper electrode film 15a in this manner, the upper electrode film 15a in the trench 12 has a continuous impurity concentration gradient that gradually decreases in concentration from the inner wall side toward the center side. It is formed. In general, the lower the impurity concentration in the film, the lower the etching rate. Therefore, the etching rate of the upper electrode film 15a in the trench 12 is formed so as to continuously decrease from the inner wall side toward the center side. The

  Here, the amount of impurities added to the process gas when forming the upper electrode film 15a is adjusted according to the etching conditions for etching back the upper electrode film 15a in a later step, Adjustment is made within a range where sufficient conductivity can be obtained as an electrode.

  Further, in the present embodiment, the inner wall of the upper electrode film 15a in the trench 12 is adjusted by adjusting the etching rate of the upper electrode film 15a in the trench 12 so as to continuously decrease from the inner wall side toward the center side. The difference in etching rate between the side and the center is reduced. In this case, when the upper electrode film 15a is removed by etching in a later step to form the upper electrode, the central portion of the surface of the upper electrode in the trench 12 does not become a projecting protrusion, which is preferable.

Next, as shown in FIG. 2C, etch back is performed in a state depending on the etching rate by a dry etching method using, for example, sulfur hexafluoride (SF ₆ ) as an etching gas. The upper electrode film 15a (see FIG. 1B) is removed up to the formed trench lower portion 12a to form the upper electrode 15.

Although SF ₆ is used as the etching gas here, for example, hydrogen bromide (HBr) may be used. In this case, the amount of impurities added to the process gas when forming the upper electrode film 15a Is adjusted as appropriate to adjust the etching rate.

  At this time, since the etching rate of the upper electrode film 15a in the trench 12 is adjusted so as to decrease from the inner wall side toward the center side, the center side is not easily etched. Thus, even if an etchant enters from the upper part of the seam A of the upper electrode film 15a, the central portion of the upper electrode 15 surface is not excessively etched to form a deep depression, and the central portion of the upper electrode 15 surface is raised. Shape.

  Thereafter, the capacitor insulating film 14 exposed in the upper region of the trench 12 (the trench upper portion 12 b) is removed, thereby forming a trench capacitor in the trench 12.

  Next, as shown in FIG. 2D, a thick insulating film made of, for example, tetraethoxysilane (TEOS) is formed on the substrate 11 and the upper electrode 15 so as to cover the inner wall of the upper portion 12b of the trench. Form a film. Next, an etch back process is performed to remove the insulating film on the substrate 11 and the upper electrode 15 and leave the insulating film on the side wall of the trench upper portion 12b, thereby forming a side wall insulating film (color oxide film) 16. . Thereafter, by performing normal lithography and etching, the uppermost sidewall insulating film 16 of the trench upper portion 12b is removed, and the sidewall is exposed.

  Next, as shown in FIG. 3E, a conductive film made of, for example, polysilicon into which As is introduced is buried in the trench upper part 12 b, and the lead electrode 17 is formed on the upper electrode 15.

  Thereafter, a DRAM is formed through a normal DRAM process. A transistor is formed on the substrate 11, and a diffusion layer (not shown) of the transistor is connected to the upper electrode 15 of the trench capacitor via an extraction electrode 17.

  According to such a semiconductor device manufacturing method and semiconductor device, the etching rate of the upper electrode film 15a in the trench 12 is adjusted so as to decrease from the inner wall side toward the center side. As a result, when the upper electrode film 15a is removed by etching to form the upper electrode 15, the upper electrode film 15a is removed depending on the etching rate, and the upper electrode film 15a on the center side of the trench 12 is etched. It becomes difficult to be done. For this reason, even if an etchant enters from the seam A of the upper electrode film 15a, the central portion of the surface of the upper electrode 15 is not excessively removed as described with reference to FIG. Further, it is possible to prevent a deep depression from occurring on the surface of the upper electrode 15.

  Further, the upper electrode film 15a in the trench 12 does not have a portion where impurities are unevenly distributed, and the central portion in the film thickness direction of the upper electrode film 15a in the trench 12 has no portion where the etching rate is locally increased. When the upper electrode film 15a is removed by etching to form the upper electrode 15, the upper electrode film 15a can be prevented from being excessively removed locally. For this reason, it can suppress that the surface of the upper electrode 15 becomes uneven | corrugated.

  Therefore, in the subsequent step of forming the sidewall insulating film 16 on the inner wall of the trench upper portion 12b, a thick insulating film is formed on the upper electrode 15 so as to cover the inner wall of the trench 12b. When the insulating film is removed by etching, the insulating film hardly remains on the surface of the upper electrode 15.

  For this reason, it is possible to reduce the resistance when the lead electrode 17 is formed and connected on the upper electrode 15. Therefore, it is possible to reduce the resistance when the upper electrode 15 of the trench capacitor and the diffusion layer of the transistor formed on the substrate 11 are connected via the lead electrode 17, and conduction can be ensured. Therefore, the yield can be improved.

  Further, in the present embodiment, the amount of impurities added in the process gas is gradually reduced until the upper electrode film 15a is embedded in the trench 12, and the impurity concentration of the upper electrode film 15a in the trench 12 is increased from the inner wall side. By adjusting so as to continuously decrease toward the center side, the etching rate was adjusted to continuously decrease from the inner wall side toward the center side. Thereby, since there is little difference in the etching rate between the inner wall side and the center side of the upper electrode film 15a in the trench 12, it is possible to prevent the central portion of the surface of the upper electrode 15 from protruding significantly, The surface of the electrode 15 can be formed more flat.

  Further, the etching rate of the upper electrode film 15a can be changed by adjusting the amount of impurities added in the process gas during the formation of the upper electrode film 15a, so that the surface shape of the upper electrode 15 can be reproduced with high reproducibility. Can be controlled.

(Second Embodiment)
The semiconductor device of the present invention can also be manufactured by the following method. Here, the manufacturing method of 2nd Embodiment is demonstrated using FIGS. In addition, it carries out by the process similar to 1st Embodiment except the process of forming the upper electrode film 15a in the trench 12. FIG.

In the present embodiment, the upper electrode film 15a shown in FIG. 1B is made of, for example, silicon germanium (SiGe). Here, for example, silane gas (SiH ₄₎ as a source gas for silicon, by CVD using germane gas (GeH ₄₎ as a source gas for germanium, when embedding the SiGe film in the trench 12, GeH ₄ in the process atmosphere Gradually reduce the amount of addition. In this manner, the SiGe film having the film composition continuously changed so that the Ge content gradually decreases from the inner wall side to the center side of the trench 12 is formed. In general, since the SiGe film has a lower etching rate when the Ge content is lower, the etching rate of the upper electrode film 15a in the trench 12 is adjusted so as to continuously decrease from the inner wall side toward the center side. The

  Here, the Ge content of the SiGe film is gradually reduced. However, the center side of the upper electrode film 15a in the trench 12 is etched by making the center side of the trench 12 a polysilicon film not containing Ge. You may adjust so that a rate may become low.

  Further, by gradually reducing the Ge content of the SiGe film, the etching rate of the upper electrode film 15a in the trench 12 is adjusted so as to continuously decrease from the inner wall side toward the center side. However, the etching rate may be adjusted to be lowered stepwise by reducing the Ge content in the SiGe film stepwise from the inner wall side to the center side of the trench 12. In this case, the addition amount of Ge in the process gas is adjusted so as to decrease stepwise.

When forming the upper electrode film 15a, a certain amount of an impurity such as As is added to the process gas to introduce the impurity into the upper electrode film 15a. The subsequent steps are the same as those in the first embodiment, and depend on the etching rate by a dry etching method using, for example, sulfur hexafluoride (SF ₆ ) as an etching gas, as shown in FIG. Etchback is performed in this state, and the upper electrode film 15a (see FIG. 1B) is removed to the trench lower portion 12a to form the upper electrode 15.

  The same effects as those of the first embodiment can also be obtained by such a semiconductor device manufacturing method and the semiconductor device obtained thereby.

In the present embodiment, an example in which a certain amount of impurities made of As is added when the upper electrode film 15a made of SiGe is formed has been described. However, the present invention is not limited to this and is not limited to this. The GeH ₄ addition amount may be gradually reduced, and the impurity addition amount may be gradually reduced as in the first embodiment.

  As a result, the Ge content of the upper electrode film 15a can be reduced from the inner wall side to the center side in the trench 12, and the impurity concentration can be adjusted to be lower. In this case, the etching rate of the upper electrode film 15a can be adjusted not only by the difference in Ge content in the upper electrode film 15a but also by the difference in impurity concentration. Fine control is possible.

(Third embodiment)
The semiconductor device of the present invention can also be manufactured by the following method. Here, the manufacturing method of 3rd Embodiment is demonstrated using FIGS. 1-2. In addition, it carries out by the process similar to 1st Embodiment except the process of forming the upper electrode film 15a in the trench 12. FIG.

  In the present embodiment, an example in which the etching rate of the upper electrode film 15a in the trench 12 is adjusted in a stepwise manner will be described. Here, it is assumed that the upper electrode film 15a is composed of a multilayer film of polysilicon.

  First, as shown in FIG. 1B, a film forming process for forming a thin film of a polysilicon layer constituting the upper electrode film 15a is performed so as to cover the inner wall of the trench 12 in which the capacitor insulating film 14 is formed. Thereafter, for example, an impurity adsorption process for adsorbing impurities made of As on the surface of the polysilicon layer is performed, and the film formation process and the impurity adsorption process are repeated a plurality of times.

  At this time, before the filling of the trench 12 is completed, heat treatment is performed to uniformly diffuse the impurities in the deposited polysilicon layer. After that, by embedding the center side of the trench 12 with an undoped polysilicon layer, the impurity concentration is changed in two steps, with the inner wall side of the trench 12 being a diffused polysilicon layer and the center side being an undoped polysilicon layer. Adjust to As described above, even if the polysilicon layer on the center side of the trench 12 is formed without introducing impurities, the impurities are not removed by the heat treatment when forming the diffusion layer of the transistor on the substrate 11 in the process after the formation of the upper electrode. It diffuses from the polysilicon layer on the inner wall side to the center side.

  Here, the center side of the trench 12 is filled with an undoped polysilicon layer. However, the polysilicon layer on the center side of the trench 12 has a lower concentration than the polysilicon layer on the inner wall side of the trench 12. Impurities may be introduced into the.

  Here, as described in the first embodiment, since the etching rate is generally lower when the impurity concentration in the film is lower, the etching rate of the upper electrode film 15a in the trench 12 is increased from the inner wall side. It is adjusted so as to decrease stepwise toward the center side.

The subsequent steps are the same as those in the first embodiment, and depend on the etching rate by a dry etching method using, for example, sulfur hexafluoride (SF ₆ ) as an etching gas, as shown in FIG. Etchback is performed in this state, and the upper electrode film 15a (see FIG. 1B) is removed to the trench lower portion 12a to form the upper electrode 15.

  The same effects as those of the first embodiment can also be achieved by such a semiconductor device manufacturing method and the semiconductor device obtained thereby. In the first embodiment, the upper electrode film 15a is adjusted to have a continuous impurity concentration gradient that gradually decreases from the inner wall side to the center side of the trench 12, but in the present embodiment, When the trench 12 is embedded with the upper electrode film 15a, the impurity diffusion process is performed after repeating the film formation process and the impurity adsorption process, thereby more reliably introducing impurities into the polysilicon layer on the inner wall side. The electrode film 15a can be adjusted to have a stepwise impurity concentration gradient.

  In the present embodiment, the upper electrode film 15a in the trench 12 is adjusted so that the impurity concentration changes in two stages. However, a series of processes including an undoped polysilicon layer forming process, an impurity adsorption process, and a diffusion process are performed. More precise concentration control may be performed by performing multiple times.

  In this case, when the trench 12 is filled with the upper electrode film 15a, the amount of impurities adsorbed on the surface of the polysilicon layer in the impurity adsorption step is reduced for each layer from the inner wall side of the trench 12 toward the center side. . In addition, after the impurity adsorption step, each layer is subjected to heat treatment to diffuse the impurities into the underlying polysilicon layer. As a result, the impurity concentration of the upper electrode film 15a in the trench 12 is adjusted so as to decrease step by step from the inner wall side toward the center side, and the etching rate is adjusted from layer to layer from the inner wall side toward the center side. It is adjusted so as to be lowered step by step. At this time, the center side in the trench 12 may be filled with an undoped polysilicon layer so that the etching rate on the center side may be adjusted to be low.

  Further, here, the upper electrode film 15a has a stepwise impurity concentration gradient by repeating a series of steps of forming the undoped polysilicon layer, the impurity adsorption step, and the diffusion step a plurality of times. Although formed, the film formation step and the impurity adsorption step are repeated in a state where the amount of impurities to be adsorbed from the inner wall side to the center side of the trench 12 is reduced for each layer, whereby the inside of the trench 12 is formed in the upper electrode film. After the filling with 15a, heat treatment may be performed to form a stepwise impurity concentration gradient.

  Furthermore, the upper electrode film 15a is formed as a single-layer film made of polysilicon, and the amount of impurities added to the process gas when forming the film is reduced stepwise over time. It may be formed so as to have a concentration gradient of impurities.

  In the present embodiment, the example in which the impurity concentration of the upper electrode film 15a is gradually decreased from the inner wall side to the center side of the trench 12 to adjust the etching rate to be gradually decreased has been described. The etching rate may be adjusted by changing the crystal state of the upper electrode film 15a.

  For example, amorphous silicon is formed so as to cover the inner wall side of the upper electrode film 15a in the trench 12, and then polysilicon is formed so as to fill the center side. In general, since the etching rate of polysilicon is lower than that of amorphous silicon, the etching rate of the upper electrode film 15a in the trench 12 can be lowered stepwise from the inner wall side toward the center side. At this time, a certain amount of impurity such as As is added to the process gas during film formation, and the impurity is introduced into the upper electrode film 15a.

  Note that, here, the amount of impurities added during film formation is constant, but a continuous impurity concentration gradient is obtained by reducing the amount of impurities added over time until the trench 12 is buried. You may form in. In this case, since the etching rate of the upper electrode film 15a can be adjusted not only by the difference in crystal state in the upper electrode film 15a but also by the difference in impurity concentration, the etching rate of the upper electrode film 15a can be made finer. It is possible to control.

FIG. 6 is a manufacturing process cross-sectional view (No. 1) for describing the first embodiment of the semiconductor device manufacturing method of the present invention; FIG. 6 is a manufacturing process sectional view (No. 2) for describing the first embodiment of the manufacturing method of the semiconductor device of the invention; It is manufacturing process sectional drawing (the 3) for demonstrating 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing (the 1) for demonstrating the manufacturing method of the semiconductor device in a prior art. It is manufacturing process sectional drawing (the 2) for demonstrating the manufacturing method of the semiconductor device in a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12 ... Trench, 12a ... Trench lower part, 12b ... Trench upper part, 14 ... Capacitor insulating film, 15 ... Upper electrode, 15a ... Upper electrode film, 16 ... Side wall insulating film, 17 ... Extraction electrode

Claims (4)

A method of manufacturing a semiconductor device including a trench capacitor formed by laminating at least a capacitor insulating film and an upper electrode in order from a lower layer on an inner wall of a trench formed in a substrate,
A first step of forming an upper electrode film on the capacitor insulating film so as to fill the trench, and adjusting an etching rate of the upper electrode film in the trench so as to decrease from the inner wall side toward the center side;
Etching away the upper electrode film to the lower region of the trench to form an upper electrode;
An insulating film is formed on the substrate and the upper electrode so as to cover the inner wall of the trench in which the upper electrode is formed, and then the insulating film on the substrate and the upper electrode is removed by etching to form an upper portion of the trench. A third step of forming a sidewall insulating film on the inner wall of the region;
And a fourth step of forming an extraction electrode connected to the upper electrode by embedding an upper region of the trench in which the side wall insulating film is formed with a conductive film. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the etching rate is adjusted so as to continuously decrease from an inner wall side to a center side of the trench. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the etching rate is adjusted so as to decrease stepwise from an inner wall side to a center side of the trench. A semiconductor device comprising a trench capacitor formed by laminating at least a capacitor insulating film and an upper electrode in order from the lower layer on the inner wall of a trench formed in a substrate,
The upper electrode in the trench is formed so that the etching rate decreases from the inner wall side toward the center side.

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