JP2005051038A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005051038A
JP2005051038A JP2003281421A JP2003281421A JP2005051038A JP 2005051038 A JP2005051038 A JP 2005051038A JP 2003281421 A JP2003281421 A JP 2003281421A JP 2003281421 A JP2003281421 A JP 2003281421A JP 2005051038 A JP2005051038 A JP 2005051038A
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semiconductor
semiconductor device
semiconductor chips
semiconductor chip
manufacturing
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Yoshiharu Kaneda
芳晴 金田
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has no appearance of cracks in semiconductor chips when connecting the plurality of semiconductor chips, and does not cost high, and does not reduce working efficiency, and also to provide its manufacturing method. <P>SOLUTION: The semiconductor device is fabricated by mounting the plurality of semiconductor chips on die pads and electrically connecting electrodes of the plurality of semiconductor chips and the electrodes of the plurality of semiconductor chips and inner leads, and then conducting resin-sealing and processing the outlines of the leads. In the semiconductor device, the surface electrode of the first semiconductor chip 2 is connected to the inner leads 5 via flat connection terminal 4, and the surface electrode of the second semiconductor chip 3 and the flat connection terminal 4 are wire-bonded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体装置及びその製造方法に関し、特に複数の半導体チップを用いた半導体装置のチップ間ボンディングに関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to inter-chip bonding of a semiconductor device using a plurality of semiconductor chips.

複数の半導体チップを用いた半導体装置の一例を図３及び図４から説明する。図３において半導体装置は、第１の半導体チップ２と第２の半導体チップ３の裏面電極（図示せず）がダイパッド１に機械的電気的に接続される。次に、第１の半導体チップ２の表面電極（図示せず）は、複数の金球６と複数の金線７によって内部リード５に接続される。   An example of a semiconductor device using a plurality of semiconductor chips will be described with reference to FIGS. In FIG. 3, in the semiconductor device, the back electrodes (not shown) of the first semiconductor chip 2 and the second semiconductor chip 3 are mechanically and electrically connected to the die pad 1. Next, the surface electrode (not shown) of the first semiconductor chip 2 is connected to the internal lead 5 by a plurality of gold balls 6 and a plurality of gold wires 7.

次に、図４（ａ）に示すように、第２の半導体チップ３上にボンダによる金線の引きちぎりによってバンプ９を形成したのち、図４（ｂ）に示すように、第１の半導体チップ２の表面電極から前記第２の半導体チップ上のバンプ９へワイヤボンディングを行う。これら電気的接続の完了後、樹脂封止、リード外形加工を行い半導体装置が得られる。   Next, as shown in FIG. 4A, bumps 9 are formed on the second semiconductor chip 3 by tearing a gold wire with a bonder, and then, as shown in FIG. Wire bonding is performed from the surface electrode of the chip 2 to the bump 9 on the second semiconductor chip. After these electrical connections are completed, resin sealing and lead outline processing are performed to obtain a semiconductor device.

ここで、第１の半導体チップがＩＧＢＴ、バイポーラＴｒ、ＭＯＳＦＥＴ等のスイッチング素子の場合、図５に示すように第１の半導体チップ２の表面電極（図示せず）から平板状接続端子４を介して内部リード５に接続する方法もある。この方法によれば、主電流経路のオン抵抗が小さくなると共に、多数のワイヤボンディングが不要となり製造コストが低減できる。   Here, when the first semiconductor chip is a switching element such as an IGBT, a bipolar Tr, or a MOSFET, as shown in FIG. 5, the surface electrode (not shown) of the first semiconductor chip 2 is connected via the flat connection terminal 4 as shown in FIG. There is also a method of connecting to the internal lead 5. According to this method, the on-resistance of the main current path is reduced, and a large number of wire bondings are not required, and the manufacturing cost can be reduced.

一方、チップ間接続にバンプ９を用いる理由は次の通りである。すなわち、２ｎｄボンディング時には、金線を切断する必要性から１ｓｔボンディングよりも大きな衝撃が半導体チップにかかり、時には半導体チップにクラックを発生させることがある。その対策として、前述のバンプ上に２ｎｄボンディングすることで半導体チップへの衝撃を少なくしている。   On the other hand, the reason for using the bumps 9 for chip-to-chip connection is as follows. That is, at the time of 2nd bonding, a larger impact than the first bonding is applied to the semiconductor chip because of the necessity of cutting the gold wire, and sometimes a crack is generated in the semiconductor chip. As a countermeasure, the impact on the semiconductor chip is reduced by 2nd bonding on the bump.

２ｎｄボンディング時のクラックを防止する別の例としては、図６に示すように、配線パターン１１を形成した絶縁プレート１０をダイパッド１上に載置し、第１の半導体チップ２と第２の半導体チップ３に１ｓｔボンディングを行い、前記配線パターン１１に２ｎｄボンディングする方法（特許文献１参照）が開示されている。
特開２００２−２８０４０８号公報（第３〜４頁、第１図） As another example of preventing a crack at the time of 2nd bonding, as shown in FIG. 6, an insulating plate 10 on which a wiring pattern 11 is formed is placed on a die pad 1, and a first semiconductor chip 2 and a second semiconductor chip are mounted. A method of performing 1st bonding to the chip 3 and 2nd bonding to the wiring pattern 11 is disclosed (see Patent Document 1).
Japanese Patent Laid-Open No. 2002-280408 (pages 3 to 4, FIG. 1)

しかしながら、前述の半導体装置及びその製造方法には下記のような残された課題があった。すなわち、図３及び図５で説明した方法は、バンプ９の形成のための金線や加工時間の増加からコスト増となるとともに、バンプ形成位置を記憶しておきその位置に２ｎｄボンディングできるボンダに作業が限定されるため作業効率が低下するという問題があった。また、図６で説明した方法は、配線パターンを形成した絶縁プレートが必要なためコスト高になると共に、半導体装置が平面的に大きくなるという問題があった。   However, the above-described semiconductor device and its manufacturing method have the following remaining problems. That is, the method described with reference to FIGS. 3 and 5 increases the cost due to the increase in the gold wire for forming the bumps 9 and the processing time, and the bond forming position can be stored in the bonder where 2nd bonding is possible. Since the work is limited, there is a problem that work efficiency is lowered. Further, the method described with reference to FIG. 6 has a problem in that the cost is high because an insulating plate on which a wiring pattern is formed is required, and the semiconductor device becomes large in plan view.

本発明の課題は、複数の半導体チップ間を接続する際に半導体チップにクラックを生ずることが無く、コスト高とならず、作業効率が低下することが無い半導体装置及びその製造方法を提供することである。   An object of the present invention is to provide a semiconductor device that does not cause cracks when connecting a plurality of semiconductor chips, does not increase costs, and does not reduce work efficiency, and a method for manufacturing the same. It is.

本発明の課題は、複数の半導体チップ間を接続する際に半導体チップにクラックを生ずることが無く、平面的に大きくなることの無い半導体装置及びその製造方法を提供することである。   An object of the present invention is to provide a semiconductor device that does not cause cracks in a semiconductor chip when connecting between a plurality of semiconductor chips and does not become large in a plane, and a method for manufacturing the same.

本発明の請求項１記載の半導体装置は、複数の半導体チップをダイパッド上に搭載し、前記複数の半導体チップの電極間及び前記複数の半導体チップの電極と内部リード間を電気的に接続した後、樹脂封止、リード外形加工を行う半導体装置において、第１の半導体チップの表面電極が平板状接続端子を介して内部リードに接続され、第２の半導体チップの表面電極から前記平板状接続端子へワイヤボンディングされている。   According to a first aspect of the present invention, a plurality of semiconductor chips are mounted on a die pad, and the electrodes of the plurality of semiconductor chips and the electrodes of the plurality of semiconductor chips and internal leads are electrically connected. In the semiconductor device that performs resin sealing and lead outer shape processing, the surface electrode of the first semiconductor chip is connected to the internal lead via the plate-like connection terminal, and the plate-like connection terminal from the surface electrode of the second semiconductor chip Wire bonding is used.

本発明の請求項２記載の半導体装置の製造方法は、複数の半導体チップをダイパッド上に搭載し、前記複数の半導体チップの電極間及び前記複数の半導体チップの電極と内部リード間を電気的に接続した後、樹脂封止、リード外形加工を行う半導体装置の製造方法において、第１の半導体チップの表面電極を平板状接続端子を介して内部リードに接続し、第２の半導体チップの表面電極から前記平板状接続端子へワイヤボンディングする。   According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of semiconductor chips are mounted on a die pad, and the electrodes of the plurality of semiconductor chips and the electrodes of the plurality of semiconductor chips and internal leads are electrically connected. In the method of manufacturing a semiconductor device in which resin sealing and lead external shape processing are performed after connection, the surface electrode of the first semiconductor chip is connected to the internal lead via a flat connection terminal, and the surface electrode of the second semiconductor chip Then, wire bonding is performed to the flat connection terminal.

本発明の半導体装置及びその製造方法によれば、複数の半導体チップ間を接続する際に半導体チップにクラックを生ずることが無く、バンプ形成を行わないためコスト高とならず、作業効率が低下することが無いという優れた産業上の効果を奏し得る。   According to the semiconductor device and the manufacturing method thereof of the present invention, when connecting a plurality of semiconductor chips, there is no crack in the semiconductor chips, and bump formation is not performed, so that the cost is not increased and the working efficiency is lowered. There is an excellent industrial effect that there is nothing.

また、本発明の半導体装置及びその製造方法によれば、複数の半導体チップ間を接続する際に半導体チップにクラックを生ずることが無く、配線の中継点を設ける必要がないため平面的に大きくなることが無いという優れた産業上の効果を奏し得る。   In addition, according to the semiconductor device and the manufacturing method thereof of the present invention, when connecting between a plurality of semiconductor chips, there is no crack in the semiconductor chips, and it is not necessary to provide a relay point of wiring, so that the plane becomes large. There is an excellent industrial effect that there is nothing.

以下、本発明の実施の形態を添付図面を参照し、従来例と同一物には同一の符号を用いて説明する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings using the same reference numerals for the same components as in the conventional example.

本発明の実施形態である半導体装置及びその製造方法は、図１及びその断面図である図２に示すように、第１の半導体チップ２と第２の半導体チップ３の裏面電極（図示せず）がダイパッド１に機械的電気的に接続される。次に、第１の半導体チップ２の表面電極（図示せず）から平板状接続端子４を介して内部リード５に接続される。次に、第２の半導体チップ３の表面電極（図示せず）に１ｓｔボンディングされ、前記平板状接続端子４のめっき８上に２ｎｄボンディングされる。これら電気的接続の完了後、樹脂封止、リード外形加工を行い半導体装置が得られる。   As shown in FIG. 1 and FIG. 2 which is a cross-sectional view thereof, the semiconductor device according to the embodiment of the present invention and the manufacturing method thereof are provided with back electrodes (not shown) of the first semiconductor chip 2 and the second semiconductor chip 3. ) Are mechanically and electrically connected to the die pad 1. Next, the surface electrode (not shown) of the first semiconductor chip 2 is connected to the internal lead 5 via the flat connection terminal 4. Next, 1st bonding is performed on the surface electrode (not shown) of the second semiconductor chip 3, and 2nd bonding is performed on the plating 8 of the flat connection terminal 4. After these electrical connections are completed, resin sealing and lead outline processing are performed to obtain a semiconductor device.

第１の半導体チップ２と平板状接続端子４の接続及び平板状接続端子４と内部リード５の接続は、低融点金属及びその合金、導電性ペースト、導電性接着シート等の公知の技術で可能であるが、コストと作業性の点で銀ペースト等の導電性ペーストが好ましい。   The connection between the first semiconductor chip 2 and the flat connection terminal 4 and the connection between the flat connection terminal 4 and the internal lead 5 can be made by a known technique such as a low melting point metal and its alloy, a conductive paste, a conductive adhesive sheet or the like. However, a conductive paste such as a silver paste is preferable in terms of cost and workability.

平板状接続端子４のめっき８は、銀、金等のボンディング性に優れた公知の材料から選択される。また、そのめっき領域は、図１の例で示したように少なくとも２ｎｄボンディング領域を含んでいれば良い。   The plating 8 for the flat connection terminals 4 is selected from known materials having excellent bonding properties such as silver and gold. Moreover, the plating area | region should just contain at least 2nd bonding area | region, as shown in the example of FIG.

本実施形態によれば、２ｎｄボンディングが半導体チップ上に行われないため、クラックを生ずることが無い。また、バンプ形成が不要であるため、コスト高とならず、作業効率が低下することが無い。また、ダイパッド上に配線の中継点を設ける必要がないため、平面的に大きくなることが無い。   According to this embodiment, since the 2nd bonding is not performed on the semiconductor chip, no crack is generated. Further, since bump formation is unnecessary, the cost is not increased and the working efficiency is not lowered. In addition, since there is no need to provide a wiring relay point on the die pad, there is no increase in plan view.

尚、本発明の半導体装置及びその製造方法は、上記のスイッチング素子と還流ダイオードを想定した実施形態に限定されるものではなく、内蔵される半導体チップの種類やパッケージに応じて本発明の要旨を逸脱しない範囲内において種々変更を加え得る。   Note that the semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment assuming the switching element and the freewheeling diode, and the gist of the present invention depends on the type and package of the built-in semiconductor chip. Various changes can be made without departing from the scope.

以上、説明したように、本発明の半導体装置及びその製造方法によれば、複数の半導体チップ間を接続する際に半導体チップにクラックを生ずることが無く、コスト高とならず、作業効率が低下することが無く、平面的に大きくなることが無いという優れた産業上の効果を奏し得るため、本発明は、複数の半導体チップを内蔵したＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）全般に利用可能な技術である。   As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, when connecting a plurality of semiconductor chips, the semiconductor chips are not cracked, the cost is not increased, and the working efficiency is lowered. Therefore, the present invention is a technology that can be used for all MCMs (Multi Chip Modules) incorporating a plurality of semiconductor chips. .

本発明の実施形態を示す平面図。The top view which shows embodiment of this invention. 本発明の実施形態を示す断面図。Sectional drawing which shows embodiment of this invention. 従来の半導体装置を示す平面図。The top view which shows the conventional semiconductor device. （ａ）従来の半導体装置の製造方法を示す断面図。 （ｂ）従来の半導体装置の製造方法を示す断面図。(A) Sectional drawing which shows the manufacturing method of the conventional semiconductor device. (B) Sectional drawing which shows the manufacturing method of the conventional semiconductor device. （ａ）従来の別の半導体装置を示す平面図。 （ｂ）従来の別の半導体装置を示す断面図。(A) The top view which shows another conventional semiconductor device. (B) Sectional drawing which shows another conventional semiconductor device. 従来のさらに別の半導体装置を示す平面図。The top view which shows another conventional semiconductor device.

符号の説明Explanation of symbols

１ ダイパッド
２ 第１の半導体チップ
３ 第２の半導体チップ
４ 平板状接続端子
５ 内部リード
６ 金球
７ 金線
８ めっき
９ バンプ
１０ 絶縁プレート
１１ 配線パターン DESCRIPTION OF SYMBOLS 1 Die pad 2 1st semiconductor chip 3 2nd semiconductor chip 4 Flat connection terminal 5 Internal lead 6 Gold ball 7 Gold wire 8 Plating 9 Bump 10 Insulating plate 11 Wiring pattern

Claims (2)

複数の半導体チップをダイパッド上に搭載し、前記複数の半導体チップの電極間及び前記複数の半導体チップの電極と内部リード間を電気的に接続した後、樹脂封止、リード外形加工を行う半導体装置において、第１の半導体チップの表面電極が平板状接続端子を介して内部リードに接続され、第２の半導体チップの表面電極から前記平板状接続端子へワイヤボンディングされていることを特徴とする半導体装置。   A semiconductor device in which a plurality of semiconductor chips are mounted on a die pad, and resin sealing and lead outer shape processing are performed after electrically connecting the electrodes of the plurality of semiconductor chips and between the electrodes of the plurality of semiconductor chips and internal leads. The semiconductor device is characterized in that the surface electrode of the first semiconductor chip is connected to the internal lead through the flat connection terminal, and is wire-bonded from the surface electrode of the second semiconductor chip to the flat connection terminal. apparatus. 複数の半導体チップをダイパッド上に搭載し、前記複数の半導体チップの電極間及び前記複数の半導体チップの電極と内部リード間を電気的に接続した後、樹脂封止、リード外形加工を行う半導体装置の製造方法において、第１の半導体チップの表面電極を平板状接続端子を介して内部リードに接続し、第２の半導体チップの表面電極から前記平板状接続端子へワイヤボンディングすることを特徴とする半導体装置の製造方法。   A semiconductor device in which a plurality of semiconductor chips are mounted on a die pad, and resin sealing and lead outer shape processing are performed after electrically connecting the electrodes of the plurality of semiconductor chips and between the electrodes of the plurality of semiconductor chips and internal leads. In this manufacturing method, the surface electrode of the first semiconductor chip is connected to the internal lead through the flat connection terminal, and wire bonding is performed from the surface electrode of the second semiconductor chip to the flat connection terminal. A method for manufacturing a semiconductor device.
JP2003281421A 2003-07-29 2003-07-29 Semiconductor device and its manufacturing method Pending JP2005051038A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008060256A (en) * 2006-08-30 2008-03-13 Renesas Technology Corp Semiconductor device
CN106229307A (en) * 2016-08-01 2016-12-14 长电科技（宿迁）有限公司 The Welding Structure of aluminum steel pad surface secondary load and process thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008060256A (en) * 2006-08-30 2008-03-13 Renesas Technology Corp Semiconductor device
US8232629B2 (en) 2006-08-30 2012-07-31 Renesas Electronics Corporation Semiconductor device
US9129979B2 (en) 2006-08-30 2015-09-08 Renesas Electronics Corporation Semiconductor device
CN106229307A (en) * 2016-08-01 2016-12-14 长电科技（宿迁）有限公司 The Welding Structure of aluminum steel pad surface secondary load and process thereof

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