JP2005049194A - Capacitance detection device and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitance detection device which can improve processing speed by reducing the amount of detection information to be sent out. <P>SOLUTION: The shape of the surface of a finger is read, by detecting the capacitance which varies according to the distance from the finger by a plurality of capacitance detection circuits 31. The fingerprint information read out from each capacitance detection circuit 31 is converted into a 1-bit digital signal by an A/D converter. In processing the detection information from the capacitance detection circuits 31, there is no need for processing the signal of a plurality of bits. Thus, the processing speed can be improved, and the power consumption thereof, as the fingerprint sensor 1, can be reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitance detection device and an electronic apparatus that read a surface shape of a detected object having fine irregularities such as fingerprints by detecting a capacitance that changes in accordance with a distance from the detected object surface. .

  Conventionally, as a capacitance detection device in which sensor cells are arranged in a matrix, a fingerprint sensor that detects the uneven shape of a fingerprint by detecting the capacitance that changes according to the distance from the finger surface (for example, Patent Documents 1 to 3). 4) is known. Conventionally, the fingerprint sensor has been mainly used for a device that authenticates that a person entering a highly confidential room is the person himself. For example, a capacitive fingerprint sensor using a semiconductor ( For example, Patent Documents 2 to 4) can be made small and light and inexpensive, and are considered to be used for portable small electronic devices such as mobile phones, PDAs (personal digital assistants), portable personal computers, and IC cards. Yes. In addition, even in a stationary electronic device, a fingerprint sensor for identifying the person is used to protect privacy for personal use.

A conventional capacitive fingerprint sensor using a semiconductor is formed on single crystal silicon of about 20 mm × 20 mm. The structure and detection principle of a capacitive fingerprint sensor occurs between an electrode made in a matrix sensor cell formed on the surface of a semiconductor and the irregularities of the fingerprint via a dielectric thin film on the electrode. The distribution of capacitance is detected by a transistor circuit. In addition, each sensor cell as a detection circuit normally has an A / D converter built-in. The sensor cells are sequentially scanned by scanning lines, and the data lines are sequentially connected to the output terminals of the A / D converter. Detection information was read out from. At this time, detection information from the sensor cell is output as a multi-bit digital signal by the A / D converter, and a high personal authentication rate is realized in an entrance / exit management system or the like.
JP-A-11-118415 JP 2000-346608 A JP 2001-56204 A JP 2001-133213 A

  However, since a conventional capacitive fingerprint sensor has a sensor electrode and a dielectric film provided on a single crystal silicon substrate, if the finger is strongly pressed against the dielectric film as the detection surface, the silicon substrate will be broken. Inferior in durability. Furthermore, the fingerprint sensor is inevitably required to have a size of about 20 mm × 20 mm for its use, and enormous energy and labor are required to form it on a single crystal silicon substrate. Moreover, in order to mount the fingerprint sensor on a thin plate-like IC card, the single crystal silicon substrate has to be polished very thin, and there is a problem that it becomes expensive.

  As a method for solving the above problems, the applicant of the present application previously proposed a capacitive fingerprint sensor that can be formed on a glass substrate or a plastic substrate by using a MIS thin film semiconductor device (signal amplification TFT) as a sensor cell. is doing.

  By the way, since the personal authentication in the IC card only needs to determine whether or not it is the owner, it does not require as much accuracy as the entrance / exit management system for fingerprint verification. Further, the performance of an IC chip mounted on an IC card is naturally limited due to physical specifications. Therefore, when a multi-bit A / D converter is built in each sensor cell as in a conventional fingerprint sensor, the IC chip is forced to perform multi-bit signal processing with a heavy load, resulting in a reduction in processing speed. It was.

  SUMMARY OF THE INVENTION In view of the above-described circumstances, the present invention has an object to provide a capacitance detection device and an electronic apparatus that can reduce the amount of detection information to be sent, reduce the memory capacity, and improve the processing speed. And

  The capacitance detection device according to the present invention is a capacitance detection device that detects the capacitance of the detection object by a plurality of detection circuits and reads the surface shape of the detection object. It comprises a converter that converts detection information read from each detection circuit into a 1-bit digital signal.

  According to the present invention, the detection information of the analog signal read by each detection circuit is converted into a 1-bit digital signal instead of a plurality of bits by the converter and output. Therefore, when processing the detection information from the detection circuit, it is not necessary to perform signal processing of a plurality of bits, and it becomes possible to reduce the memory capacity and improve the processing speed.

  The capacitance detection device of the present invention is configured to provide the converter in each of the detection circuits and to output digital signal detection information from the selected detection circuit.

  In this way, even if a part of the detection circuit is damaged, a 1-bit digital signal is provided from another normal detection circuit via the converter, so that various processes using the detection information can be continued.

  The capacitance detection device of the present embodiment is configured such that the common converter is provided on the output side of each detection circuit, and the detection information from the selected detection circuit is converted and output by the converter. .

  In this case, it is not necessary to provide a converter for each detection circuit, and the structure of the detection unit can be simplified.

  In each of the above-mentioned inventions, it is preferable that the detection circuit and the converter are constituted by MIS type thin film semiconductor devices. In this way, not only each detection circuit but also the converter is released from the single crystal silicon substrate and can be formed on a glass substrate or a plastic substrate, and an inexpensive and highly durable electrostatic capacitance detection device can be provided. .

  In each of the above-described inventions, the detection circuit can detect electrostatic capacitances of various objects to be detected, but it is preferably applied particularly to one that detects unevenness of a fingerprint. This makes it possible to perform various controls using the fingerprint of the finger as detection information. In addition, it is possible to provide an ultra-small and ultra-lightweight capacitance detection device that outputs fingerprint information.

  In the present invention, the capacitance detection device that outputs fingerprint information may be incorporated into various electronic devices.

  Examples of such electronic devices include smart cards, PDAs, and mobile phones. In either case, provision as an ultra-compact and ultra-light electronic device is possible.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. The embodiments described below do not limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily essential requirements of the present invention. In each embodiment, a capacitance detection device that outputs detection information read from each detection circuit as a 1-bit digital signal will be described.

  FIG. 1 is a block diagram of a capacitance fingerprint sensor 1 applied as a capacitance detection device. The fingerprint sensor 1 includes a data driver 10 for selecting a data line 36, a scanning driver 20 for selecting a scanning line 35, and an active matrix unit 30 formed as a detection area for a fingerprint that is an object to be detected. Composed. The active matrix unit 30 serving as an information collecting unit for collecting the finger surface shape includes m scanning lines 35 (m is an integer of 2 or more) arranged in a matrix of m rows and n columns, and n lines. The capacitance detection circuit 31 corresponding to the detection circuit provided at the intersection of the data line 36 and the scanning line 35 and the data line 36 (n is an integer of 2 or more) is a minimum component. Thereby, the high potential VDD generated in the active scanning line 36 is applied to the electrostatic capacitance detection circuit 31.

  The data driver 10 includes a shift register 11 for realizing sequential driving of analog points in a normal display device, and an array-like analog switch 12 configured by inserting and connecting switch elements 14 to the respective data lines 36. Become. One end of each data line 36 is connected to the common data trunk line 16. When a start pulse is applied from the outside, the shift register 11 sequentially outputs a selection signal in a timely manner to the n switch elements 14 in synchronization with a separately applied clock. When the switch element 14 is turned on by the selection signal, electrical connection between the selected data line 36 connected to the switch element 14 and the data trunk line 16 is sequentially taken.

  The scan driver 20 includes a shift register 21 for sequentially selecting the scan lines 35. When a start pulse is applied from the outside, the shift register 21 selectively scans all the scanning lines 35 in order in synchronization with a separately applied clock. As a result, detection information including a 1-bit digital signal is extracted from the capacitance detection circuit 31 at the intersection of the active scanning line 35 and the selected data line 36 through the data trunk line 16.

  The capacitance detection circuit 31 is arranged in a matrix of m rows and n columns in the active matrix unit 30 and detects a capacitance that changes according to the distance to the object to be detected. More specifically, as shown in FIG. 2, a selection transistor 32 that is a selection element, and a signal detection element 33 in which the capacitance Cd changes depending on the uneven shape of the surface of the detection object such as a fingerprint. A reference capacitor 37 having a fixed capacitance Cs, and a 1-bit A / D converter 38 that converts an analog signal output from the signal detection element 33 into a 1-bit digital signal. The selection transistor 32 is preferably composed of a MIS thin film semiconductor device for selection composed of a gate electrode, a gate insulating film, and a semiconductor film. The A / D converter 38 is also preferably composed of a combination of MIS type thin film semiconductor devices for signal conversion comprising a gate electrode, a gate insulating film and a semiconductor film. The input terminal of the A / D converter 38 is connected to the connection point between the signal detection element 33 and the reference capacitor 37, while the output terminal of the A / D converter 38 is connected to the source of the selection MIS type thin film semiconductor device. In this embodiment, the drain region of the selection MIS type thin film semiconductor device is connected to the data line 36, and the gate electrode of the selection MIS type thin film semiconductor device is connected to the connection point between the scanning line 35 and the reference capacitor 37. .

  In the present invention, the charge Q generated between the capacitor having the electrostatic capacitance Cs and the capacitor having the electrostatic capacitance Cd that changes in accordance with the surface shape of the object to be detected is caused at the input terminal of the A / D converter 38. The input voltage Vi is changed. Then, by comparing the reference voltage VR in the A / D converter 38 and the input voltage Vi, the output voltage Vo generated at the output terminal of the A / D converter 38 is either H (high) level or L (low) level. Become one.

  The MIS type thin film semiconductor device composed of the above-mentioned metal-insulating film-semiconductor film is known as a technique for manufacturing a semiconductor integrated circuit requiring a large area at a low cost because it is usually formed on a glass substrate. It is applied to display devices. Therefore, when the capacitance detection circuit 31 applied to a fingerprint sensor or the like is formed by a thin film semiconductor device, it is not necessary to use an expensive substrate made by consuming a great amount of energy such as a single crystal silicon substrate. The device can be produced at low cost without consuming precious earth resources. In addition, a thin film semiconductor device applies a transfer technique called SUFTLA (Japanese Patent Laid-Open No. 11-312811 and S. Utsunomiya et. Al. Society for Information Display p.916 (2000)), so that a semiconductor integrated circuit is formed on a plastic substrate. Since the capacitance detection circuit 31 can be formed on the plastic substrate, the capacitance detection circuit 31 can also be released from the single crystal silicon substrate.

  The operation of the fingerprint sensor 1 will be described. When one specific scanning line 35 is sequentially selected from the m scanning lines 35 by a start pulse and a clock signal supplied to the scanning driver 20, the scanning line 35 becomes active and becomes the high potential VDD. As a result, the selection transistor 32 of the capacitance detection circuit 31 connected to the scanning line 35 is turned on. On the other hand, the input voltage Vi of the A / D converter 38 is determined by the capacitance ratio of the input capacitance Ct (see FIG. 2) of the A / D converter 38 itself and the capacitance Cs of the reference capacitor 37 and the capacitance Cd of the signal detection element 33. .

  When the crest (convex portion) of the fingerprint is in contact with the surface of the capacitance detection circuit 31, the capacitance Cd of the signal detection element 33 is sufficiently larger than the capacitances Ct and Cs, and the input voltage Vi of the A / D converter 38 is It approaches the GND (ground) potential. As a result, the output voltage Vo of the A / D converter 38 becomes L level. By measuring the output voltage Vo at the L level, it can be determined that the measurement location is a peak of the fingerprint pattern. On the contrary, when the valley of the fingerprint (concave portion) faces the surface of the capacitance detection circuit 31, the capacitance Cd of the signal detection element 33 is sufficiently smaller than the capacitances Ct and Cs, and the input voltage of the A / D converter 38 Vi approaches the high potential VDD. As a result, the output voltage Vo of the A / D converter 38 becomes H level. By measuring this H-level output voltage Vo, it can be determined that the measurement location is a valley of the fingerprint pattern.

  In a state where the specific scanning line 35 is active, one specific switch from among the n switching elements 14 connected to each data line 36 by a start pulse and a clock signal applied to the data driver 10. Element 14 is selected and activated. As a result, the unevenness information of the fingerprint from the capacitance detection circuit 31 is taken out as an H level or L level digital signal to the output OUT of the data trunk line 16 through the active switch element 14. By repeating the above operation in the active matrix section 30 that is the detection surface, fingerprint information from each capacitance detection circuit 31 can be output as a 1-bit digital signal, and is in contact with the surface of the active matrix section 30. Fingerprint pattern detection is realized. More specifically, the capacitance detection circuit detects the fingerprint irregularities in the second row after detecting the fingerprint irregularities in order from the capacitance detection circuit 31 located in each column of the first row. The irregularities of the fingerprint are detected every 31. As a result, it is possible to periodically capture a fingerprint image using the fingerprint sensor 1.

  The capacitance detection circuit 31 can be formed on a plastic substrate using the above-described SUFTLA technology. Fingerprint sensors based on single crystal silicon technology are not practical because they are easily cracked on plastic or are not large enough. On the other hand, the capacitance detection circuit 31 on the plastic substrate according to the present embodiment can be used as the fingerprint sensor 1 on the plastic substrate without any fear of breaking even if the area is sufficiently large to cover the finger on the plastic substrate. .

  The fingerprint sensor 1 having the above configuration is applied to a smart card having a personal authentication function. Smart cards are used in cash cards, credit cards, identity cards, etc., and their security levels are significantly increased, and personal fingerprint information is not leaked outside the card. It has an excellent function to protect. FIG. 3 shows an application example to an IC card 4 which is a kind of smart card. In addition to the electrostatic capacitance type fingerprint sensor 1, the thin plate-shaped card base material 6 is mounted with an IC chip 40 and a microcontroller 41 as a control means for driving the fingerprint sensor 1. When reading a fingerprint, the fingerprint sensor 1 is driven based on a signal supplied from the microcontroller 41, and a 1-bit digital signal corresponding to the unevenness information of the fingerprint is output from the fingerprint sensor 1. Although not shown here, a display device such as a liquid crystal panel may be connected to the microcontroller 41.

  In a card that does not perform personal authentication, the card can be used when the password stored and registered in the card in advance is equal to the password entered by the card user. Therefore, if a person other than the card owner can know the password, the card can be used illegally. On the other hand, in the IC card 4 that performs personal authentication by the fingerprint sensor 1 as shown in FIG. 3, the fingerprint data stored in the memory (IC chip 40) in the card in advance matches the fingerprint information from the fingerprint sensor 1. Issue a PIN only for If the issued password is equal to the password entered by the card user, the IC card 4 can be used.

  As described above, in this embodiment, the capacitance detecting device that detects the surface shape of the finger by detecting the capacitance changing according to the distance to the finger as the detection object by the plurality of capacitance detecting circuits 31. The A / D converter 38 converts the fingerprint information read from each capacitance detection circuit 31 into a 1-bit digital signal. In this way, the detection information of the analog signal read by each capacitance detection circuit 31 is converted by the A / D converter 38 into a 1-bit digital signal instead of a plurality of bits and output. Therefore, when the detection information from the capacitance detection circuit 31 is processed by the microcontroller 41 of the IC card 4, for example, the microcontroller 41 does not need to perform signal processing of a plurality of bits, and the processing speed is improved with a small memory capacity. In addition, the power consumption of the fingerprint sensor 1 can be reduced.

  Further, in this embodiment, each capacitance detection circuit 31 is provided with an A / D converter 38, and the selected capacitance detection circuit 31 at the intersection of the active scanning line 35 and the data line 36 is used. Fingerprint information of a 1-bit digital signal is output. Thus, even if a part of the capacitance detection circuit 31 is damaged, a 1-bit digital signal is provided from the other normal capacitance detection circuit 31 via the A / D converter 38. Various processes using the information can be continued by the microcontroller 41.

  Each circuit example of the A / D converter 38 is shown in FIGS. In each circuit example, in addition to the above-described high-potential VDD power supply, a low-potential VSS power supply, a pulsed clock signal CLK, and a reference voltage VR for comparing the input voltage Vi are given. It is done. The A / D converter 38 shown in FIG. 4 is configured by combining four P-channel transistors 81 to 84, two N-channel transistors 85 and 86, and each element of an inverter 87 that is an inverter. More specifically, a series circuit of transistors 82 and 85 and a series circuit of transistors 83 and 86 are connected between the high potential VDD line and the low potential VSS line, respectively. The gate of the transistor 82 is connected to the connection point between the transistors 83 and 86, and the gate of the transistor 83 is connected to the connection point between the transistors 82 and 85, while the input voltage Vi is applied to the gate of the transistor 85, while the transistor 86 A reference voltage VR is applied to the gates of. A transistor 81 is connected between the high potential VDD line and the connection point between the transistors 82 and 85, and another transistor 84 is connected between the high potential VDD line and the connection point between the transistors 83 and 86. Is done. A clock CLK is commonly supplied to the gates of these transistors 81 and 84. Further, the input terminal of the inverter 87 is connected to the connection point of the transistors 82 and 85, and the output signal (output voltage Vo) is taken out from the output terminal of the inverter 87.

  In this circuit example, when the clock signal CLK applied to the A / D converter 38 is at the L (= VSS) level, both the transistors 81 and 84 are turned on, and the input terminal of the inverter 87 is at the H (= VDD) level. Thus, the output voltage Vo from the output terminal of the inverter 87 becomes L level.

  On the other hand, when the clock signal CLK applied to the A / D converter 38 is at the H (= VDD) level, the transistors 81 and 84 are both turned off. At this time, since the reference voltage VR is applied to the gate of the transistor 86, the transistor 86 is in a conductive state, and as the transistor 84 is turned off, the gate potential of the transistor 82 is lowered, and the transistor 82 is turned on. It becomes conductive. Here, if the input voltage Vi is lower than the reference voltage VR, the drain-source resistance of the transistor 85 in the conductive state is higher than the drain-source resistance of the transistor 86 in the conductive state, so that the transistor 85 Is higher than the drain voltage of the transistor 86. Since the drain voltage of each of the transistors 85 and 86 is applied to the gates of the transistors 82 and 83 which are the loads of both the transistors 85 and 86, positive feedback is applied and the input terminal of the inverter 87 connected to the drain of the transistor 85. Becomes H level, and the output voltage Vo becomes L level. Conversely, if the input voltage Vi is higher than the reference voltage VR, the output voltage Vo becomes H level.

  In this circuit example, a comparison output circuit (transistors 82, 83, 85, 86, an inverter, which compares an input voltage Vi with a reference voltage VR and outputs an H level or L level output voltage Vo according to the comparison result) 87) is built in the A / D converter 38. Therefore, the comparison output circuit compares the input voltage Vi corresponding to the capacitance with the reference voltage VR, and outputs a 1-bit digital signal based on the comparison result. By changing the level of the reference voltage VR, the switching condition of the H level or L level of the output signal Vo can be easily adjusted. In addition, a synchronization circuit (transistors 81 and 84) that operates the comparison output circuit when the clock signal CLK is at the H level, that is, in synchronization with the selected switch element 14 being turned on, is also provided. Only when 31 is selected, an H-level or L-level output signal Vo serving as fingerprint information can be output.

  The A / D converter 38 shown in FIG. 5 is configured by combining three N-channel transistors 90 to 92, a capacitor 93, and an inverter 94 that is an inverter. More specifically, the transistor 90 to which the reference voltage VR is applied to the drain and the source of another transistor 91 to which the input voltage Vi is applied to the drain are connected to each other, and one end of the capacitor 93 is connected to this source connection point. The other end of the capacitor 93 is connected to the input terminal of the inverter 94, and the drain and source of the transistor 92 are connected between the input terminal and the output terminal of the inverter 94, respectively. The gates of the transistors 90 and 92 are supplied with the clock inversion signal INV (CLK), while the gate of the transistor 91 is supplied with the clock signal CLK and output from the connection point between the output terminal of the inverter 94 and the source of the transistor 92. A signal (output voltage Vo) is taken out.

  In this circuit example, when the clock signal CLK is at the L (= VSS) level, the transistor 92 which is a feedback switch is turned on, so that negative feedback is applied to the inverter 94 and the capacitor 93 connected to the input terminal of the inverter 94 is provided. The end side potential becomes the threshold voltage of the inverter 94. In addition, since the transistor 90 that is a reference voltage switch is on and the transistor 91 that is an input voltage switch is off, the potential at one end of the capacitor 93 becomes the reference voltage VR. Therefore, the capacitor 93 is charged by the difference between the threshold voltage of the inverter 94 and the reference voltage VR. The output voltage Vo at this time becomes the threshold voltage of the inverter 94.

  When the clock signal CLK becomes H (= VDD) level, the transistor 92 is turned off, so that the inverter 94 performs an amplification operation as a normal inverter. Further, the transistor 90 is turned off and the transistor 91 is turned on, so that the potential at one end of the capacitor 93 is switched to the input voltage Vi. Therefore, if the input voltage Vi is lower than the reference voltage VR, the voltage level on the input terminal side of the inverter 94 is lower than the threshold voltage, and the output voltage Vo is H level. Conversely, if the input voltage Vi is higher than the reference voltage VR, the voltage level on the input terminal side of the inverter 94 becomes higher than the threshold voltage, and the output voltage Vo becomes the L level.

  In this circuit example, when the clock signal CLK is at the L level, the difference between the reference voltage VR and the threshold voltage of the inverter 94 is stored in the capacitor 93. When the clock signal CLK is switched to the H level, the stored reference voltage VR and the input are input. Based on the result obtained by amplifying the difference from the voltage Vi, an output signal Vo of H level or L level is output from the output terminal of the inverter 94. Thus, since the inverter 94 amplifies the difference between the reference voltage VR and the input voltage Vi to obtain a 1-bit digital signal, the sensitivity in generating the digital signal is improved. Therefore, even if the reference voltage VR and the input voltage Vi are slightly different, a digital signal as correct fingerprint information can be output. Further, by changing the level of the reference voltage VR, the switching condition of the output signal Vo between the H level and the L level can be easily adjusted.

  Note that a comparator composed of the transistor 92, the capacitor 93, and the inverter 94 may be connected in multiple stages so as to increase the gain of the output signal so as to increase the sensitivity of the fingerprint sensor 1. FIG. 6 shows a configuration in which the comparators are connected in two stages.

  FIG. 7 is a block diagram of the capacitive fingerprint sensor 1 in the second embodiment. In this embodiment, the A / D converter 38 is not provided in each capacitance detection circuit 31. Instead, an A / D converter circuit 50 for converting an analog signal detected by the active matrix unit 30 into a digital signal is connected to the data trunk line 16. Further, each capacitance detection circuit 31 is connected to a supply line 39 connected to a low potential side power source (not shown), and the high potential VDD generated in the active scanning line 35 and the low potential generated in the supply line 39 are connected. A potential difference from the potential VSS is applied to the capacitance detection circuit 31. Other configurations are the same as those in the first embodiment.

  FIG. 8 shows a circuit configuration of the capacitance detection circuit 31. The capacitance detection circuit 31 of the present embodiment includes a selection transistor 32 that is a selection element, and a signal detection element 33 whose capacitance Cd changes depending on the uneven shape of the surface of an object to be detected such as a fingerprint. The signal amplifying transistor 34, which is a signal amplifying element, and a reference capacitor 37 having a fixed capacitance Cs are included. The signal amplifying transistor 34 is preferably composed of a signal amplifying MIS thin film semiconductor device including a gate electrode, a gate insulating film, and a semiconductor film. The selection transistor 32 is preferably composed of a selection MIS type thin film semiconductor device including a gate electrode, a gate insulating film, and a semiconductor film. In the present embodiment, the drain of the MIS thin film semiconductor device for signal amplification is connected to the source of the MIS thin film semiconductor device for selection, the source of the MIS thin film semiconductor device for signal amplification is connected to the supply line 39, and The gate electrode of the MIS type thin film semiconductor device is connected to the connection point between the capacitance detection electrode constituting the signal detection element 33 and the reference capacitor 37. In this way, the source of the selection MIS thin film semiconductor device and the supply line 39 are connected to each other via the signal amplification MIS thin film semiconductor device sensitive to the charge Q detected by the capacitance detection electrode. In this embodiment, the drain of the selection MIS type thin film semiconductor device is connected to the data line 36, and the gate electrode of the selection MIS type thin film semiconductor device is connected to the scanning line 35 and one end of the reference capacitor 37.

  In this embodiment, a signal amplifying MIS type thin film semiconductor device is generated by a charge Q generated between a capacitor having a capacitance Cs and a capacitor having a capacitance Cd that changes in accordance with the surface shape of an object to be detected. The gate potential is changed. Then, when a predetermined voltage is applied to the drain of the signal amplification MIS thin film semiconductor device by making the drain-source of the selection MIS thin film semiconductor device conductive, a signal amplification MIS type according to the induced charge Q. The current I flowing between the drain and source of the thin film semiconductor device is significantly amplified. Since the induced charge Q itself is stored without flowing anywhere, the current I can be easily measured by increasing the drain voltage or extending the measurement time. The advantages of the MIS type thin film semiconductor device are as described in the first embodiment.

  FIG. 9 is a circuit diagram of the A / D converter circuit 50. The A / D converter circuit 50 is configured by two-stage current mirror circuits 51 and 52, and a part of the first-stage current mirror circuit 51 is replaced by the capacitance detection circuit 31. More specifically, the current mirror circuit 51 includes P-channel transistors 61 to 65 and N-channel transistors 66 and 67 in addition to the capacitance detection circuit 31, and includes a high potential VDD line and a low potential VSS line. A series circuit in which the transistor 61, the selection transistor 32, and the signal amplifying transistor 34 are sequentially connected and a series circuit in which the transistors 64, 66, and 67 are sequentially connected are respectively connected. The drain and source of the transistor 65 are connected between the connection point of the transistors 61 and 32 and the connection point of the transistors 64 and 66, respectively, and the clock CLK is supplied to the gates of the transistors 61, 64, and 65, respectively. The drains of the transistors 62 and 63 are connected between the high potential VDD line and the drain of the transistor 65 and between the high potential VDD line and the source of the transistor 65, respectively, and the gates of these transistors 62 and 63 are connected to the drain of the transistor 63. Connected to. When the clock CLK is at the H (high) level, the current I flows into the transistors 32 and 34 of the capacitance detection circuit 31 and the reference voltage VR applied to the gate of the transistor 67 flows into the transistors 66 and 67. A difference from the current amount I ′ is generated as a voltage between the drain and source of the transistor 65.

  On the other hand, the second-stage current mirror circuit 52 includes P-channel transistors 68 to 70 and N-channel transistors 71 to 73. The series circuit of the transistors 68 and 71 and the series circuit of the transistors 69 and 72 have a high potential. Each is connected between the VDD line and the drain of the transistor 73. Further, the drain and source of the transistor 70 are connected between the connection point of the transistors 68 and 71 and the connection point of the transistors 69 and 72, respectively, and the clock CLK is supplied to the gates of the transistors 70 and 73. Further, the gates of the transistors 68 and 69 are connected to the drain of the transistor 69, and the source of the transistor 73 is connected to the low potential VSS line. When the clock CLK is at the H level, a voltage corresponding to the difference between the current amounts I and I ′ is applied to the gates of the transistors 71 and 72, and the output OUT amplified from the connection point of the transistors 68 and 71 is output. It is taken out. The A / D converter circuit 50 shown in the drawing is merely an example, and may be appropriately replaced with another circuit configuration.

  The operation of the fingerprint sensor 1 will be described. When one specific scanning line 35 is sequentially selected from the m scanning lines 35 by the digital code signal given to the scanning driver 20, the scanning line 35 is It becomes active and becomes the high potential VDD. As a result, the selection amplification transistor 32 of the capacitance detection circuit 31 connected to the scanning line 35 is turned on. On the other hand, the gate voltage of the signal amplification transistor 34 is determined by the capacitance ratio of the capacitance Ct (see FIG. 8) parasitic to the signal amplification transistor 34 itself, the capacitance Cs of the reference capacitor 37, and the capacitance Cd of the signal detection element 33.

  When the crest (convex portion) of the fingerprint is in contact with the surface of the capacitance detection circuit 31, the capacitance Cd of the signal detection element 33 is sufficiently larger than the capacitances Ct and Cs, and the gate voltage of the signal amplification transistor 34 is GND ( Near ground) potential. As a result, the signal amplification transistor 34 is substantially turned off, and a very weak current I flows between the drain and source of the signal amplification transistor 34. On the other hand, when the valley of the fingerprint (concave portion) faces the surface of the capacitance detection circuit 31, the capacitance Cd of the signal detection element 33 is sufficiently smaller than the capacitances Ct and Cs, and the gate voltage of the signal amplification transistor 34 is It approaches the high potential VDD. As a result, the signal amplification transistor 34 is substantially turned on, and a large current I flows between the drain and source of the signal amplification transistor 34. Of course, when the distance between the fingerprint and the surface of the capacitance detection circuit 31 is intermediate, the gate voltage of the signal amplifying transistor 34 also takes an intermediate value, and between the drain and source of the signal amplifying transistor 34. The flowing current amount I is also an analog value.

  Here, since the source of the signal amplification transistor 34 is connected to the supply line 39 of the low potential VSS, the current I flows in the direction from the data line 36 to the capacitance detection circuit 31. In a state where the specific scanning line 35 is active, a specific one of the n analog switches 12 connecting the data line 36 and the A / D converter circuit 50 by a digital code signal applied to the data driver 10. The analog switches 12 are sequentially selected and activated. As a result, a current I corresponding to the fingerprint unevenness information flows from the A / D converter circuit 50 to the electrostatic capacitance detection circuit 31 through the active analog switch 12. The A / D converter circuit 50 serving as an output unit that outputs detection information from the capacitance detection circuit 31 is configured by the two-stage current mirror circuits 51 and 52 as described above. In the first-stage current mirror circuit 51, when an H-level clock CLK is applied, a current amount I flowing toward the capacitance detection circuit 31 and a current amount I ′ flowing into the transistors 66 and 67 by the reference voltage VR. Are applied to the gates of the transistors 71 and 72 constituting the second-stage current mirror circuit 52 and sufficiently amplified. As a result, an output OUT as a digital voltage is taken out.

  Here, the configuration of the A / D converter circuit 50 will be described in more detail. When the clock CLK is at L level, both the transistors 61 and 64 are turned on. The transistor 65 is also turned on, and both ends (source and drain) of the transistor 65 are both at the H level. This voltage is applied to the second-stage current mirror circuit 42. In the second-stage current mirror circuit 42, the transistor 73 is off and the transistor 70 is on. It approaches the threshold voltage (threshold voltage).

  On the other hand, when the clock CLK is at the H level, the transistors 61 and 64 are both turned off. In addition, the transistor 65 is also turned off, and the transistors 66 and 66 are connected to both ends (source and drain) of the transistor 65 by the current I flowing through the transistors 32 and 34 of the capacitance detection circuit and the reference voltage VR applied to the gate of the transistor 67. A difference from the current I ′ flowing through 67 occurs at both ends (source and drain) of the transistor 65. This voltage is applied to the gates of the transistors 71 and 72 of the second-stage current mirror circuit 42. The transistor 73 is turned on and functions as a kind of resistor, and the transistor 70 is turned off. Therefore, the voltage applied to the gates of the transistors 71 and 72 is amplified and output from the drain of the transistor 71.

  The above operation is repeatedly performed on each of the capacitance detection circuits 31 provided in m rows and n columns in the active matrix unit 30 to detect the fingerprint pattern in contact with the surface of the active matrix unit 30. Is realized. More specifically, for example, after detecting the unevenness of the fingerprint in order from the capacitance detection circuit 31 located in each column of the first row, the unevenness of the fingerprint of the second row is detected, and then the fingerprint is detected for each sensor cell. Detect irregularities in the surface. As a result, it is possible to periodically capture a fingerprint image using the fingerprint sensor 1.

  The fingerprint sensor 1 in this embodiment can also be applied to an IC card 4 that is a kind of smart card as shown in FIG. When reading a fingerprint, the fingerprint sensor 1 is driven based on a signal supplied from the microcontroller 41, and a 1-bit digital signal corresponding to the unevenness information of the fingerprint is output from the fingerprint sensor 1. Here, since the fingerprint sensor 1 has a built-in common A / D converter circuit 50 for converting the analog current value output from each capacitance detection circuit 31 into a digital voltage value, the fingerprint sensor 1 is connected to the micro-sensor. The fingerprint information output to the controller 41 is a 1-bit digital signal of H level or L level.

  This embodiment also includes an A / D converter circuit 50 that converts fingerprint information read from the capacitance detection circuit 31 into a 1-bit digital signal. Therefore, when processing fingerprint information from the capacitance detection circuit 31, it is not necessary to perform signal processing of a plurality of bits, the processing speed can be improved with a small memory capacity, and the fingerprint sensor 1 has low power. Consumption becomes possible. In addition, a single A / D converter circuit 50 is provided in common on the output side of the capacitance detection circuit 31, and the fingerprint from the selected capacitance detection circuit 31 at the intersection of the active scanning line 35 and the data line 36 is provided. Information is converted by an A / D converter circuit 50 and output. Therefore, it is not necessary to provide a converter for each capacitance detection circuit 31, and the structure of the active matrix unit 30 that is a detection unit of the fingerprint sensor 1 can be simplified.

  In addition, the A / D converter circuit 50 has a current mirror circuit 51 as a differential amplifier that amplifies the difference between the current amount I corresponding to the capacitance and the reference current amount I ′, and sufficiently detects the detected difference. A current mirror circuit 52 that amplifies and outputs a 1-bit digital signal is provided. As described above, since the difference between the reference voltage VR and the input voltage Vi is amplified to obtain a 1-bit digital signal, the sensitivity in generating the digital signal is improved. Therefore, even if the reference voltage VR and the input voltage Vi are slightly different, a digital signal as correct fingerprint information can be output. Further, by changing the level of the reference voltage VR, the switching condition of the output signal Vo between the H level and the L level can be easily adjusted. In this case, a plurality of amplifier circuits may be provided.

  For the A / D converter circuit 50, for example, the circuit examples shown in FIGS. FIG. 10 is an application of the circuit example of FIG. In the figure, a global bit line GBL corresponding to the data trunk line 16 is connected to the gate of the transistor 85. Reference numeral 88 denotes a transistor that resets the comparison node by setting the gate of the transistor 85 to the low potential VSS when the clock CLK is at the L level. The operation is the same as that of the circuit example shown in FIG. 4 except that an analog voltage value corresponding to the capacitance is given from each capacitance detection circuit 31 to the gate of the transistor 85.

  In this circuit example, a comparison is made between the analog voltage value sequentially sent from each capacitance detection circuit 31 and the reference voltage VR, and an output voltage Vo of H level or L level is output according to the comparison result. Output circuits (transistors 82, 83, 85, 86 and inverter 87) are built in the A / D converter circuit 50. Therefore, the comparison output circuit compares the analog voltage value corresponding to the capacitance with the reference voltage VR, and outputs a 1-bit digital signal based on the comparison result. By changing the level of the reference voltage VR, the switching condition of the H level or L level of the output signal Vo can be easily adjusted. In addition, a synchronization circuit (transistors 81, 84, 88) that operates the comparison output circuit when the clock signal CLK is at the H level, that is, in synchronization with the selected switch element 14 being turned on, is also provided. Only when the detection circuit 31 is selected, an H-level or L-level output signal Vo serving as fingerprint information can be output.

  In any of the above-described embodiments, it is preferable that each capacitance detection circuit 31 and the A / D converters 38 and 50 are configured by MIS type thin film semiconductor devices. In this way, not only each capacitance detection circuit 31 but also the A / D converters 38 and 50 can be released from the single crystal silicon substrate and formed on a glass substrate or a plastic substrate, for example, a smart card 81 or the like. It is possible to provide a low-cost and highly durable electrostatic capacity detection device suitable for the above.

  Further, in each of the above embodiments, the capacitance detection circuit 31 having a sufficient degree of integration for detecting the unevenness of the fingerprint is used. This makes it possible to perform various controls using the fingerprint of the finger as detection information. In addition, an ultra-small and ultra-lightweight fingerprint sensor 1 that outputs fingerprint information can be provided.

  Furthermore, such a fingerprint sensor 1 can be used by being incorporated in an electronic device such as a PDA or a mobile phone in addition to the smart card 81, for example. This makes it possible to provide an electronic device that is ultra-compact and ultra-lightweight and suitable for fingerprint registration and fingerprint authentication.

  In addition, this invention is not limited to each Example mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, the object to be detected may be other than a fingerprint, and can be applied to various capacitance detection devices other than the fingerprint sensor 1 for that purpose. In each embodiment, the fingerprint information extracted from the fingerprint sensor 1 is used for personal authentication, but can also be used for various other processes. For example, the movement of the fingerprint in the six-axis direction may be captured and used for display control such as movement of the pointer in the display device or scrolling of the display image.

Explanatory drawing which shows the whole structure of the fingerprint sensor in a 1st Example. The circuit diagram of an electrostatic capacitance detection circuit. The external appearance block diagram which shows the example of application to an IC card. The circuit diagram of an A / D converter. The circuit diagram of an A / D converter. The circuit diagram of an A / D converter. Explanatory drawing which shows the whole structure of the fingerprint sensor in a 2nd Example. The circuit diagram of an electrostatic capacitance detection circuit. The circuit diagram of an A / D converter circuit. The circuit diagram of an A / D converter circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Fingerprint sensor, 31 Capacitance detection circuit, 38 A / D converter, 50 A / D converter circuit, 51 Current mirror circuit, 52 Current mirror circuit, 81 Smart card, 82, 83, 85, 86, 90-92 transistor 93 capacitors 94 inverters

Claims (6)

In the electrostatic capacitance detection device that detects the capacitance changing according to the distance to the detected object by a plurality of detection circuits and reads the surface shape of the detected object.
A capacitance detection device comprising a converter that converts detection information read from each detection circuit into a 1-bit digital signal. 2. The capacitance detection device according to claim 1, wherein each of the detection circuits is provided with the converter and outputs detection information of a digital signal from the selected detection circuit. 2. The capacitance detection according to claim 1, wherein the common converter is provided on the output side of each of the detection circuits, and the detection information from the selected detection circuit is converted and output by the converter. apparatus. The capacitance detection device according to claim 1, wherein the detection circuit and the converter are configured by an MIS type thin film semiconductor device. The capacitance detection device according to claim 1, wherein the detection circuit detects unevenness of a fingerprint. An electronic apparatus comprising any one of the capacitance detection devices according to claim 1.

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