JP2005045413A - Low noise amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low noise amplifier circuit having a good noise figure. <P>SOLUTION: The low noise amplifier circuit comprises an input matching unit 102, an amplifier 103 and an output matching unit 104. The amplifier 103 comprises FETs 31, 32 connected in two stages. The first stage FET 31 has a wider gate width than the second stage FET 32. The wider gate width of the FET 31 allows the inductance of an inductor L<SB>21</SB>of the input matching unit 102 to be reduced, resulting in a low resistance component of the inductor L<SB>21</SB>. This improves the loss of the inductor L<SB>21</SB>and hence the noise figure of the low noise amplifier circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a low-noise amplifier circuit for high-frequency signals, and more particularly to a low-noise amplifier circuit formed by connecting a plurality of field effect transistors.
[0002]
[Prior art]
A conventional low noise amplifier circuit will be described with reference to FIGS.
FIG. 4 is a schematic block diagram of a conventional low noise amplifier circuit. The low noise amplification circuit shown in FIG. 4 includes an amplification unit 3 in which amplification elements 301 and 302 are connected in two stages, an input matching unit 2 connected between the amplification unit 3 and the input terminal 1, and an amplification unit 3. And an output matching unit 4 connected between the output terminal 5 and the output terminal 5.
[0003]
In such a low-noise amplifier circuit in which a plurality of amplification elements are connected, the noise figure (Noise Figure) NF of the entire circuit is greatly affected by the minimum noise figure NF _min of the first-stage amplification element.
[0004]
Here, as the amplifying elements 301 and 302, field effect transistors (hereinafter simply referred to as “FETs”) are generally used. FIG. 5 shows a general structure of an FET formed on a semiconductor integrated circuit substrate.
FIG. 5 is a partial plan view showing a schematic structure of an FET, where G is a gate, D is a drain, and S is a source. As shown in FIG. 5, FET is provided between the drain D and the source S, and forms a predetermined if the gate length L, the gate finger electrode G _F formed at a predetermined gate width W are arranged structure. Here, the gate length L is the length of the direction from the drain D to the source S, the gate width W is perpendicular to the direction of the gate length L, it refers to the length of the direction in which the gate finger electrode G _F extends.
[0005]
In FET having such a structure, the gate width W is small, that is, the gate finger electrode G _F is short improved minimum noise figure NF _min, the gate width W is large, that is the minimum noise figure gate finger electrode G _F is long NF _min deteriorates. This is in accordance with the size of the gate width W, the gate finger electrode G _F is increased, the resistance component included in the gate finger electrode G _F (series resistance) increases, between the ground and the gate finger electrode This is because the parasitic capacitance increases.
[0006]
The minimum noise figure NF _min also depends on the bias current (drain current) flowing through the FET.
FIG. 6 shows the relationship between the drain current and the minimum noise figure NF _min .
As shown in FIG. 6, the minimum noise figure NF _min has a minimum point with respect to the bias current, and the characteristic of the minimum noise figure NF _min depends on the gate width W. By driving under the conditions considered, it is possible to operate the FET so that the minimum value nf _min of the minimum noise figure NF _min is obtained.
[0007]
From the above, in the conventional low-noise amplifier circuit, an FET with a small gate width that is driven with an appropriate bias current is used as the first stage amplifying element.
By the way, when a high frequency signal is input to the FET, the input impedance of the FET becomes a problem. In terms of DC, the input impedance is high because no current flows through the gate of the FET. However, in terms of high frequency, the input impedance is low due to the parasitic capacitance between the gate finger electrode and the ground. However, in a FET with a small gate width, since the gate finger electrode is small, parasitic capacitance is not easily generated, and the input impedance is hardly reduced.
[0008]
When a high-frequency signal is transmitted to a FET with a high input impedance with a reduced gate width, the transmission loss of the high-frequency signal increases unless impedance matching is performed between the circuit on the input terminal side and the FET. Therefore, in the low noise amplifier circuit, as shown in FIG. 4 described above, the input matching unit 2 is provided between the input terminal 1 and the first stage FET 301 of the amplifier unit 3. Specifically, an inductor such as a spiral inductor is used for the input matching unit 2 (see, for example, Patent Document 1 and Patent Document 2).
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 5-308229 [Patent Document 2]
JP-A-8-321726
[Problems to be solved by the invention]
When the input impedance of the first stage FET is high, the inductance value of the inductor must be increased in order to achieve matching between the FET and the input terminal side. However, in order to increase the inductance value of a spiral inductor formed by forming electrodes on a substrate in a spiral shape, it is necessary to lengthen the electrodes forming the inductor. For this reason, the resistance component (series resistance) of the inductor is increased and the loss is increased. Therefore, even if an FET having a small minimum noise figure NF _min is used at the first stage, the noise figure NF as a low noise amplification circuit eventually deteriorates. End up.
[0011]
In addition, if the electrodes are lengthened as described above, the shape of the inductor increases accordingly, and the low noise amplifier circuit cannot be formed in a small size.
[0012]
An object of the present invention is to provide a small low-noise amplifier circuit having a good noise figure.
[0013]
[Means for Solving the Problems]
The present invention provides a low noise amplifying circuit comprising an amplifying unit comprising a plurality of stages of field effect transistors connected, and an input matching unit including at least one inductor connected to the preceding stage of the amplifying unit. The gate width of the field effect transistor is larger than that of the second-stage field effect transistor.
[0014]
Further, the present invention is characterized in that a spiral inductor or a meander inductor is used as the inductor of the input matching section.
[0015]
In this configuration, by making the gate width of the first-stage field effect transistor (FET) larger than the gate width of the second-stage FET, the input impedance of the first stage of the amplifying unit is lowered. When the input impedance of the amplifying unit is lowered, the inductance value of the inductor constituting the input matching unit can be reduced, so that the electrode length forming the inductor is shortened and the resistance component included in the inductor is lowered. Thereby, the loss of an inductor falls and the noise superimposed on the high frequency signal input into an amplifier is suppressed.
[0016]
Here, for example, the gate of the first-stage FET is set so that the amount of loss reduction due to the decrease in the resistance component of the inductor is larger than the increase amount of the minimum noise figure NF _min of the first-stage FET with respect to the second-stage FET of the amplifier section. By forming the width, the noise figure of the low-noise amplifier circuit is improved even if the minimum noise figure NF _min of the first stage FET of the amplification unit is not relatively small (even if large).
[0017]
The present invention is characterized in that the bias current between the first-stage field effect transistor and the second-stage field effect transistor is set to a bias current that minimizes the minimum noise figure of the second-stage field effect transistor.
[0018]
In this configuration, the smaller the gate width, the smaller the bias current that minimizes the minimum noise figure, and the bias current of the second stage FET with a smaller gate width is the same as that of the other stage FET including the first stage FET. By matching the bias current, the consumption current of the amplifying unit is suppressed as compared with matching the bias current of the first-stage FET having a large gate width with the bias current of the other-stage FET. As a result, a power-saving low-noise amplifier circuit is configured.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
A low noise amplifier circuit according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a schematic equivalent circuit diagram of a low-noise amplifier circuit according to this embodiment. In FIG. 1, 101 is an input terminal, 102 is an input matching unit, 103 is an amplification unit, 104 is an output matching unit, 105 is an output terminal, and 31 and 32 are FETs. In FIG. 1, the bias voltage supply circuits for the FETs 31 and 32 are omitted for the sake of simplicity.
[0020]
The input matching unit 102 includes an L-type circuit including an inductor L ₂₁ and a capacitor C _21, and both ends of the inductor L ₂₁ are connected to the input terminal 101 and the gate G ₁ of the FET 31 of the amplifying unit 103, respectively. The capacitor C ₂₁ is connected between the ends of the amplifier 103 side of the inductor L ₂₁ and the ground.
[0021]
Amplifying unit 103 includes a FET31 of the gate _{G 1} is connected to the input matching unit 102, is connected to the gate _{G 2} to the drain _{D 1} of the FET31 via the capacitor _{C 33,} the drain _{D 2} is connected to the output matching unit 104 FET 32 is provided. Capacitors C ₃₁ and C ₃₂ and resistors R ₃₁ and R ₃₂ are connected between the sources S ₁ and S _{2 of the} FETs ₃₁ and ₃₂ and the ground, respectively. Further, the drive voltage supply terminals V _DD1 and V _DD2 are connected to the drains D ₁ and D ₂ of the FETs ₃₁ and ₃₂ via inductors L ₃₁ and L ₃₂ , respectively. The drive voltage supply terminals V _DD1 and V _DD2 A driving voltage (drain voltage) is supplied from FET 31 to FET 31 and 32.
[0022]
The high-frequency signal input from the input terminal 101 is input to the gate G ₁ of the first stage FET 31 of the amplifying unit 103 via the input matching unit 102. FET31 amplifies the input high-frequency signal is output from the drain _{D 1.} The amplified radio frequency signal in FET31 is via a DC cutting capacitor _{C 33,} it is input to the gate _{G 2} of the FET32 of the second stage. FET32 will further amplifies the input high-frequency signal is output from the drain _{D 2.} The high-frequency signal thus amplified in two stages is output from the output terminal 105 via the output matching unit 104.
[0023]
2A and 2B are plan views of a low-noise amplifier circuit portion formed on a circuit board, in which FIG. 2A shows the input matching unit 102 and the amplifier unit 103, FIG. 2B shows the FET 31, and FIG. The FET 32 is shown. In FIG. 2, the same components as those in FIG. A ground electrode (not shown) is formed on the back side of the circuit board. The drive voltage supply circuit and the circuit grounded from each source through a resistor are omitted.
[0024]
As shown in FIG. 2, the input terminal 101 is formed of a substantially square electrode, and this input terminal 101 is connected to one end of a spiral inductor L ₂₁ formed of the spiral electrode 21. The electrode at the other end of the spiral inductor L ₂₁ is branched and one electrode is connected to the gate G ₁ of the FET 31. The other electrode is formed so as to overlap in the stacking direction with a portion of the ground electrode 22, the capacitor C ₂₁ of the MIM type is composed of this electrode and the ground electrode 22 and the ground electrode.
[0025]
The gate _{G 1} of the FET31 is branched into four gate fingers _G F1 _{~G F4.} The source _{S 1} of FET31 is branched to the three source finger _S F1 _{to S F3,} the drain _{D 1} has two drain fingers _{D F1,} branches into _{D F2.} A gate finger G _F1 is disposed between the source finger S _F1 and the drain finger D _F1, and a gate finger G _F2 is disposed between the drain finger D _F1 and the source finger S _F2 . Further, a gate finger G _F3 is disposed between the source finger S _F2 and the drain finger D _F2, and a gate finger G _F4 is disposed between the drain finger D _F2 and the source finger S _F3 .
[0026]
The source S ₁ of the FET 31 is connected to the source grounding electrode 33 and constitutes a capacitor C ₃₁ that generates a capacitance between the source grounding electrode 33 and the ground electrode.
[0027]
The drain _{D 1} of the FET31 is connected to one electrode 35 which constitute the DC cut capacitors _{C 33,} the other electrode 35 of the DC cut capacitor _{C 33} 'is connected to the gate _{G 2} of the FET 32.
[0028]
The gate _{G 2} of FET32 are two gate fingers _{G F1,} branches into _{G F2.} The source _{S 1} of FET32 are two source fingers _{S F1,} branches into _{S F2.} A gate finger G _F1 is disposed between the source finger S _F1 and the drain finger D _F, and a gate finger G _F2 is disposed between the drain finger D _F and the source finger S _F2 .
[0029]
The source S ₂ of the FET 32 is connected to the source grounding electrode 34, and a capacitor C ₃₂ that generates a capacitance is formed between the source grounding electrode 34 and the ground electrode.
[0030]
The drain _{D 2} of FET32 is connected downstream of the output matching unit 104.
[0031]
In such a configuration, the FET 31 and the FET 32 have the same gate finger shape. On the other hand, the FET 31 has four gate fingers, and the FET 32 has two gate fingers. Since the gate width of the FET is the sum of the lengths of the gate fingers, the gate width of the FET 31 (the length of the gate finger) is substantially larger than the gate width of the FET 32. Accordingly, since the input impedance of FET31 is smaller than the input impedance of the FET 32, is possible to reduce the inductance of the spiral inductor _{L 21} of the input matching unit 102 that performs impedance matching between FET31 circuit and the first stage of the input terminal 101 side it can. For this reason, the electrode length of the spiral electrode 21 is reduced, and the resistance component of the electrode is reduced. That is, the resistance component of the spiral inductor L ₂₁ is reduced, the loss can be improved.
[0032]
FIG. 3 shows the bias current characteristics of the minimum noise figure NF _min and gain of each FET in this case.
3 (a) shows the minimum noise figure _{NF min} and gain of the first-stage FET 31 (gain), FIG. 3 (b) shows a minimum noise figure _{NF min} and gain FET32 the second stage (gain). Note that nf _min in the figure indicates a minimum point of the minimum noise figure NF _min .
[0033]
Thus, since the first stage minimum noise figure _{NF min} characteristic is worse than a minimum noise figure _{NF min} of the second stage, the use of the FET31 large gate width in the first stage, when using the FET32 gate widths small first stage As a result, the minimum noise figure NF _min in the amplifying unit 103 is deteriorated.
[0034]
However, as described above, by using the FET 31 having a large gate width in the first stage, the electrode length of the spiral inductor L ₂₁ of the input matching unit 102 can be shortened, so that the loss of the inductor L ₂₁ is reduced and the amplification unit The noise component of the high-frequency signal input to 103 is suppressed. Accordingly, even if no better than the first-stage FET31 minimum noise figure _{NF min} is the second-stage FET32 minimum noise figure _{NF min} of the amplifier 103, it is possible to improve the noise figure NF of the low noise amplifier circuit .
[0035]
As described above, the noise figure NF of the low-noise amplifier circuit is based on the minimum noise figure NF _min of the FET 32 and the loss of the inductor L ₂₁ when the first stage FET is the FET 32 having a small gate width. By setting the gate width of the first stage FET 31 so as to be smaller than the noise figure NF, it is possible to suppress the deterioration of the noise figure NF as a low noise amplifier circuit.
[0036]
In the configuration of the present embodiment, the gain of the first stage of the amplifying unit 103 is smaller than when a FET having a small gate width is used in the first stage, but the gain is set to be supplemented in the second stage. By doing so, it is possible to configure a low-noise amplifier circuit that is excellent in noise figure and obtains a desired gain.
[0037]
With such a configuration, it is possible to form a low noise amplifier circuit with a good noise figure.
[0038]
Moreover, since the electrode length of a spiral inductor becomes short by setting it as such a structure, a spiral inductor can be formed small. Thereby, a low noise amplifier circuit can be reduced in size. Further, the manufacturing yield is improved by downsizing the spiral inductor.
[0039]
Conventionally, a capacitor is formed between the gate electrode and the source electrode to reduce the input impedance, but the number of components of the low-noise amplifier circuit can be reduced, the manufacturing yield is improved, and the cost is reduced. Can do.
[0040]
In the above-described embodiment, the FET 31 and the FET 32 are driven with different bias currents (drain currents). However, the FET 32 drives the FETs 31 and 32 with a bias current at which the FET 32 has a minimum value nf _min of the minimum noise figure NF _min. You may let them. Thereby, the current consumption of FET31 and FET32 can be suppressed, and a low-noise amplifier circuit with reduced power consumption can be formed. In this case, the minimum noise figure NF _min of the FET 31 is deteriorated, but the noise figure NF as an amplifier is greatly affected by the noise figure NF of the input matching unit 102, so that the deterioration of the noise figure NF of the amplifier is small. As a result, a low-noise amplifier circuit having an excellent noise figure and saving power can be realized.
[0041]
In the above-described embodiment, the low-noise amplifier circuit including two stages of FETs has been described. However, the above-described configuration is applied to the first stage and the second stage also for low-noise amplifier circuits including three or more stages of FETs. The above-mentioned effect can be expected.
[0042]
In the above-described embodiment, the inductor of the input matching unit is formed of a spiral inductor, but may be formed of an inductor having another shape such as a meander inductor.
[0043]
【The invention's effect】
According to the present invention, by using an FET having a large gate width at the first stage of the amplifying unit, the noise figure (loss) of the input matching unit is improved, and a low noise amplifying circuit having an excellent noise figure can be formed.
[0044]
In addition, according to the present invention, the operation of each FET in the amplifying unit is performed under the operation condition of the second-stage FET having a small gate width, thereby suppressing the bias current in each FET and reducing power consumption. An amplifier circuit can be formed.
[Brief description of the drawings]
Schematic equivalent circuit diagram of the low noise amplifier circuit according to the embodiment of the invention; FIG 2 shows a partial plan view of the low noise amplifier circuit on the circuit board in FIG. 3 FET31,32 minimum noise characteristics NF _min and Fig. 4 is a schematic block diagram of a conventional low noise amplifier circuit. Fig. 5 is a partial plan view showing a schematic structure of an FET. Fig. 6 is a bias current characteristic diagram of a minimum noise characteristic NF _min of the FET. Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,101-Input terminal 2,102-Input matching part 3,103-Amplifier part 4,104-Output matching part 5,105-Output terminal 21-Spiral electrode 22-Grounding electrode 31,32,301,302-FET
33, 34-Common source electrode 35, 35 '-DC cut capacitor electrode

Claims (3)

In a low noise amplifying circuit including an amplifying unit formed by connecting a plurality of stages of field effect transistors, and an input matching unit including at least one inductor connected to the previous stage of the amplifying unit,
A low noise amplifier circuit characterized in that the gate width of the first stage field effect transistor of the amplification section is made larger than the gate width of the second stage field effect transistor. The low-noise amplifier circuit according to claim 1, wherein the inductor of the input matching unit is a spiral inductor or a meander inductor. Among the field effect transistors at each stage of the amplifying unit, at least the bias current of the first stage field effect transistor and the second stage field effect transistor is biased so that the minimum noise figure of the second stage field effect transistor is minimized. The low noise amplifier circuit according to claim 1, wherein the current is a current.

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