JP2005044427A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which has an ECC (Error Check and Correct) function and a defect-relieving function and reduces the number of redundancy cells. <P>SOLUTION: The semiconductor storage device 1 stores a p-bit error correction signal for ECC in a redundancy cell group 4 and serves as a memory with the ECC function which corrects an error of n-bit data stored in a main cell group 2 in an ECC circuit 6, when the ECC circuit is turned on. The storage device 1 uses the redundancy cell group 4 as spare cells for relieving defective cells and serves as a defective cell relieving memory which relieves a maximum number p of defective cells among a number n of data bit cells storing n-bit data by means of a defective cell relieving part 7 in the main cell group 2, when the ECC circuit is turned off. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant cell group used for error correction or defective cell repair.
[0002]
[Prior art]
In order to improve reliability when using the semiconductor memory device, an error correction code is stored in addition to the data signal in the semiconductor memory device, and an ECC (Error Check and Correct) circuit mounted on the semiconductor memory device is used. Means for outputting the data signal after correcting the error of the generated data signal is used.
[0003]
Thus, for example, by adding a 5-bit error correction code to 16-bit data, it is possible to correct and output a 1-bit error generated in the 16-bit data.
[0004]
On the other hand, a redundant cell and a defective cell repair circuit are provided in advance to repair defective cells generated during the manufacture of a semiconductor memory device. If a defective cell is found during a product shipment test, Means are used to replace defective cells with redundant cells to make them non-defective.
[0005]
Therefore, a semiconductor device that can efficiently repair defects using both of these means has been proposed (see, for example, Patent Document 1).
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-326497 (page 3-4, FIG. 1)
[0007]
[Problems to be solved by the invention]
However, when both of these means are used together, it is necessary to provide a redundant cell for storing an error correction code for ECC and a redundant cell for failure relief in addition to the original memory cell. This increases the chip size.
[0008]
Some users require only the ECC function or only the defective cell repair function. Alternatively, there is a demand for enhancing ECC error correction capability.
[0009]
In particular, in the case of an embedded memory in which a memory according to a user's specifications is incorporated in a custom LSI, it is necessary to immediately provide a wide variety of semiconductor memory devices according to the user's request. At this time, efficient use of redundant cells and improvement in yield are required.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having an ECC function and a defect relieving function and having a reduced number of redundant cells.
[0011]
[Means for Solving the Problems]
According to one aspect of the present invention, a data main cell group storing n-bit data, a p-bit redundant cell group, an ECC circuit having a function of correcting an error occurring in the n-bit data, and the main cell A defective cell remedy unit having a function of executing the remedy of defective cells in the group, and the ECC circuit uses the redundant cell group for storing p-bit error correction codes for ECC. A semiconductor memory device is provided.
[0012]
According to another aspect of the present invention, a data main cell group for storing n-bit data, a p-bit redundant cell group, an ECC circuit having a function of correcting an error generated in the n-bit data, A defective cell repair unit having a function of executing repair of defective cells in the main cell group, wherein the defective cell repair unit replaces a part of the main cell group with at least a part of the redundant cell group A semiconductor memory device is provided.
[0013]
According to still another aspect of the present invention, a main cell group for storing 2m-bit data and a first ECC circuit for correcting an error occurring in the 2m-bit data in m-bit units are corrected in 2m-bit units. ECC circuit unit having error correction bit length switching means for switching to any one of the second ECC circuit, the first ECC circuit, and the second ECC circuit, a 2q-bit redundant cell group, and the main cell group A defective cell repair unit capable of repairing defective cells therein, switching the ECC circuit unit to the first ECC circuit, and applying a q-bit error correction code for m-bit data to the redundant cell group. There is provided a semiconductor memory device which is stored in a set and performs error correction of the 2m-bit data in units of m bits.
[0014]
According to still another aspect of the present invention, a main cell group for storing 2m-bit data and a first ECC circuit for correcting an error occurring in the 2m-bit data in m-bit units are corrected in 2m-bit units. ECC circuit unit having error correction bit length switching means for switching to any one of the second ECC circuit, the first ECC circuit, and the second ECC circuit, a 2q-bit redundant cell group, and the main cell group A defective cell repair unit capable of executing repair of defective cells therein, switching the ECC circuit unit to the second ECC circuit, and providing an error correction code of r (r <2q) bits for 2m-bit data. What is claimed is: 1. A semiconductor memory device which stores in a redundant cell group and repairs a maximum of (2q-r) defective cells in 2m bit data with an ECC function in 2m bit units It is subjected.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention.
[0017]
The semiconductor memory device 1 includes a main cell group 2 that stores a plurality of n-bit data, a sense amplifier group 3 with a disable fuse that amplifies the output of the main cell group 2, and a p-bit for n-bit data. It has a redundant cell group 4 that can store an error correction code or can be used as p defective repair cells, and a sense amplifier group 5 that amplifies the output of the redundant cell group 4.
[0018]
In addition, the semiconductor memory device 1 includes an ECC circuit unit 6 including an ECC circuit that corrects a 1-bit error in n-bit data read from the main cell group 2, and a defective cell in the main cell group 2. Are mounted on the defective cell remedy section 7 that enables switching to a cell in the redundant cell group 4 and an input / output circuit 8 for outputting n-bit data to the outside.
[0019]
The ECC circuit unit 6 receives an ECC ON / OFF control signal, and can switch whether the ECC circuit is operated or not. The ECC ON / OFF control signal may be given from the outside of the semiconductor memory device 1 or may be given fixedly to either ON or OFF inside the semiconductor memory device 1.
[0020]
In the case where the semiconductor memory device 1 is provided in a fixed manner, for example, a glass mask used in a wiring process at the time of manufacturing the semiconductor memory device 1 is an option, and the glass mask is replaced by ON / OFF of an ECC ON / OFF control signal. The potential of the ECC ON / OFF control signal is switched.
[0021]
When the ECC ON / OFF control signal is ON, the ECC circuit unit 6 operates, and the semiconductor memory device 1 operates as a memory with an ECC function. At this time, the redundant cell group 4 stores a p-bit error correction code for n-bit data.
[0022]
Incidentally, when the number of bits of data n is expressed as n = 2 ^k, while the number of bits p of the bit number n and the error correction code data, a relationship of p = (k + 1). Thus, for example, when the n = 16 = ^{2 4,} the p = 5.
[0023]
On the other hand, when the ECC ON / OFF control signal is OFF, the defective cell relieving unit 7 can be used after the ECC circuit unit 6 is not operated. In this case, the cells of the redundant cell group 4 used for storing the error correction code are used as defective relief cells. As a result, the semiconductor memory device 1 operates as a defective repairable memory capable of repairing a maximum of p defective cells in the data bit cells storing n-bit data.
[0024]
FIG. 2 is a circuit connection diagram showing an example of connection between the defective cell repair unit 7 and the peripheral block. In this example, the number of data bits n is 16 and the number of redundant cells p is 5. For the sake of clarity, only one set of 16-bit data cells 21 in the main cell group 2 and one set of 5-bit redundant cells 41 in the redundant cell group 4 are shown.
[0025]
The defective cell repair unit 7 includes sixteen cell switching circuits 71 that perform conduction when defective cells are repaired. One end of each cell switching circuit 71 is connected to each cell (D1 to D16) of the 16-bit data cell 21. ) To outputs R1 to R16 output through the sense amplifier group 3 with disable fuse.
[0026]
On the other hand, the other end of the cell switching circuit 71 is connected to one of output lines output from each cell (P1 to P5) of the 5-bit redundant cell 41 via the sense amplifier group 4.
[0027]
In the example of FIG. 2, the line output from the redundant cell P1 via the sense amplifier group 4 is commonly connected to the cell switching circuit 71 connected to R1 to R3. Hereinafter, the redundant cell P2 is commonly connected to the cell switching circuit 71 connected to R4 to R6, the redundant cell P3 is R7 to R9, the redundant cell P4 is R10 to R12, and the redundant cell P5 is connected to each of R13 to R16. Yes.
[0028]
With this connection, when a defective cell is generated in the 16-bit data cell 21, the cell switching circuit 71 can be operated to replace the defective cell with a redundant cell.
[0029]
At this time, a defective cell generated in any one of the data cells D1 to D3 is in the redundant cell P1, a defective cell generated in any one of the data cells D4 to D6 is in the redundant cell P2, and the data cells D7 to D9. The defective cell generated in any one of the data cells is generated in the redundant cell P3, the defective cell generated in any one of the data cells D10 to D12 is generated in the redundant cell P4, and any one of the data cells D13 to D16 is generated. The defective cell is replaced with a redundant cell P5.
[0030]
The correspondence relationship between the data cells D1 to D16 and the redundant cells P1 to P5 is not limited to this example, and can be set arbitrarily.
[0031]
FIG. 3 is a circuit diagram showing an example of the cell switching circuit 71 used in the embodiment of the present invention.
[0032]
A pair of P-channel MOSFET 711 and N-channel MOSFET 712 constitutes an analog switch, and conduction between the source and drain terminals is controlled by the potential of the gate terminal.
[0033]
The gate terminal of the P-channel MOSFET 711 is connected to the power supply terminal via the fuse 713 and is connected to the ground terminal via the high resistance 714. Therefore, normally, the power supply potential is applied to the gate terminal of the P-channel MOSFET 711. On the other hand, a ground potential opposite to that of the gate terminal of the P-channel MOSFET 711 is applied to the gate terminal of the N-channel MOSFET 712 via the inverter 715.
[0034]
As a result, the P-channel MOSFET 711 and the N-channel MOSFET 712 are normally OFF and are in a non-conductive state as an analog switch.
[0035]
On the other hand, when the fuse 713 is cut, a ground potential is applied to the gate terminal of the P-channel MOSFET 711, and a power supply potential is applied to the gate terminal of the N-channel MOSFET 712.
[0036]
Therefore, the P-channel MOSFET 711 and the N-channel MOSFET 712 are turned on, and the analog switch is in a conductive state.
[0037]
FIG. 4 is a circuit diagram showing an example of a circuit of a sense amplifier with a disable fuse terminal used in the embodiment of the present invention.
[0038]
The sense amplifier 31 has an enable terminal, and this enable terminal is connected to a power supply terminal via a disable fuse 32, and is connected to a ground terminal via a high resistance.
[0039]
Therefore, the power supply potential is applied to the normal enable terminal, and at this time, the sense amplifier 31 is in the output enable state.
[0040]
On the other hand, when the disable fuse 32 is disconnected, the enable terminal is at the ground potential, and the sense amplifier 31 is in the output disable state.
[0041]
FIG. 5 is a circuit connection diagram showing an example of how a defective cell is repaired in the present embodiment. FIG. 5 shows only the portion related to the redundant cell P1 in the circuit connection of FIG. In addition, the cell switching circuit 71 and the sense amplifier group 3 with the disable fuse terminal are illustrated using the circuit examples shown in FIGS. At this time, suffixes 1, -2, and -3 are attached to the circuit elements, respectively, to show the correspondence with FIGS. Note that a sense amplifier 4-1 which is one sense amplifier in the sense amplifier group 4 is connected to the output of the redundant cell P1.
[0042]
FIG. 5 shows a state of relief when the data cell D1 is defective. When the defect of the data cell D1 is remedied, the fuse 713-1 of the cell switching circuit 71-1 corresponding to this cell is cut by a laser cutter or the like. Then, the P-channel MOSFET 711-1 and the N-channel MOSFET 712-1 are turned on, and the source-drain terminals are in a conductive state.
[0043]
At the same time, the disable fuse 32-1 is disconnected, and the sense amplifier 31-1 is set in the output disable state.
[0044]
As a result, the output of the redundant cell P1 is output to the output line R1 instead of the data cell D1, and the defect of the data cell D1 is relieved.
[0045]
According to the semiconductor memory device 1 of this embodiment as described above, an ECC function-equipped memory or a defect-relief function-equipped memory is provided by switching on / off of the ECC and changing the utilization form of the redundant cell accordingly. It becomes possible.
[0046]
(Second Embodiment)
FIG. 6 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention.
[0047]
The semiconductor memory device 11 according to the present embodiment is configured such that 2 m-bit data is divided into m bits and data errors can be corrected in units of m bits. Therefore, the semiconductor memory device 11 of this embodiment has twice the error correction capability as compared with the semiconductor memory device 1 of the first embodiment.
[0048]
However, the bit length of error correction can be switched, and error correction with 2 m bits as a whole is possible as in the semiconductor memory device 1 of the first embodiment.
[0049]
Similarly to the semiconductor memory device 1 of the first embodiment, the semiconductor memory device 11 of the present embodiment also functions as a memory function unit, which amplifies the main cell group 12 storing a plurality of 2m-bit data and the output of the main cell group 12 A sense amplifier group with disable fuse 13, a redundant cell group 14 capable of storing two sets of q-bit error correction codes for performing error correction in units of m bits of 2 m-bit data, and redundant cell group 14 And a sense amplifier group 15 for amplifying the output.
[0050]
The semiconductor memory device 11 also includes a first ECC circuit (not shown) that performs error correction on the 2m-bit data read from the main cell group 12 in units of m bits and the 2m-bit data in units of 2m bits. An ECC circuit unit 16 including a second ECC circuit (not shown) that performs error correction, and a defective cell remedy that enables a defective cell in the main cell group 12 to be switched to a cell in the redundant cell group 14. The unit 17 and an input / output circuit 18 for outputting 2m-bit data to the outside are mounted.
[0051]
The ECC circuit unit 16 is supplied with an error correction bit length switching signal, and can switch between error correction in m bit units and error correction in 2 m bit units. This error correction bit length switching signal may be given from the outside of the semiconductor memory device 11, or may be fixedly given as to whether it is in m bit units or 2 m bit units inside the semiconductor memory device 11. .
[0052]
In the case where the semiconductor memory device 11 is fixedly provided, for example, a glass mask used in a wiring process at the time of manufacturing the semiconductor memory device 11 is an option, and the glass mask is replaced with an error correction bit length to be used. The potential of the switching signal is switched.
[0053]
Also in the present embodiment, the cell switching circuit 71 shown in FIG. 3 is used for the defective cell remedy unit 17, and the sense amplifier with disable fuse included in the sense amplifier group 13 with disable fuse is shown in FIG. Use what is shown in.
[0054]
FIG. 7 is an explanatory diagram showing how the error correction bit length is switched and defect repair is performed in the semiconductor memory device 11. Here, a case of 16-bit data will be described as an example.
[0055]
FIG. 7A is a schematic diagram showing the configuration of one set of data bit cells in the main cell group 12 and one set of redundant cells in the redundant cell group 14. When error correction is performed on the 16-bit cell data cell 121 in units of 8 bits, the processing is divided into the 8-bit data cell 121-1 and the 8-bit data cell 121-2.
[0056]
When error correction is performed in units of 8 bits, since 8 = 2 ³ , the number of bits q of the required error correction code is q = (3 + 1) = 4 according to the formula described above.
[0057]
Therefore, eight redundant cells are required for a set of redundant cells. In FIG. 7A, this set of redundant cells is represented as an 8-bit redundant cell 141, which is divided into a 4-bit redundant cell 141-1 and a 4-bit redundant cell 141-2, and an 8-bit data cell, respectively. Error correction codes corresponding to 121-1 and 8-bit data cell 121-2 are used.
[0058]
FIG. 7B is a schematic diagram showing a data flow when performing error correction in units of 8 bits using the data shown in FIG.
[0059]
The data of the 8-bit data cell 121-1 and the data of the 4-bit redundant cell 141-1 are respectively sent to the 8-bit ECC circuit 16-1 via the sense amplifier group 13-1 and the sense amplifier group 15-1 having a disable fuse terminal. And error correction processing in units of 8 bits is performed.
[0060]
Similarly, the data of the 8-bit data cell 121-2 and the data of the 4-bit redundant cell 141-2 are respectively sent to the 8-bit ECC circuit via the sense amplifier group 13-2 with the disable fuse terminal and the sense amplifier group 15-2. 16-2 and error correction processing in units of 8 bits is performed.
[0061]
Then, the output of the 8-bit ECC circuit 16-1 and the output of the 8-bit ECC circuit 16-2 are connected, and 16-bit data after error correction is obtained.
[0062]
Next, FIG. 7C is a schematic diagram showing a data flow when error correction is performed on the 16-bit cell data cell 121 in units of 16 bits.
[0063]
If the number of bits of the error correction code is required when performing error correction in units of 16 bits and r, it becomes r = (4 + 1) = 5 since it is 16 = 2 ^4.
[0064]
Therefore, in this case, only the 5-bit redundant cell 141-3 among the 8-bit redundant cell 141 may be used for the error correction code. Here, the remaining 3-bit redundant cells 141-4 are used as defective cell relief cells of the 16-bit cell data cell 121.
[0065]
The 3-bit redundant cell 141-4 is connected to one end of 16 cell switching circuits 71 provided in the defective cell repair unit 17, and the other end of the 16 cell switching circuits 71 is a disable fuse. The data cells D1 to D16 of the 16-bit cell data cell 121 output through the sense amplifier group with terminal 13 are connected to each other.
[0066]
It is possible to arbitrarily determine which of the 16 cell switching circuits 71 each cell of the 3-bit redundant cell 141-4 is connected to.
[0067]
On the other hand, the 5-bit redundant cell 141-3 is connected to the 16-bit ECC circuit 16-3 and used for error correction processing of 16-bit data. Then, 16-bit data after error correction processing is obtained from the 16-bit ECC circuit 16-3.
[0068]
Here, the relationship between the number of redundant cells 2q when error correction is performed in units of m bits and the number of redundant cells r when error correction is performed in units of 2m bits will be described.
[0069]
As described above, when m = 2 ^k , the number of bits q of the error correction code is represented as q = (k + 1). Therefore, the number of redundant cells 2q at this time is 2q = 2 (k + 1) = (2k + 2).
[0070]
On the other hand, when error correction processing is performed in units of 2m bits, since 2m = ^{2k + 1} , r = (k + 1 + 1) = (k + 2).
[0071]
Therefore, the difference is 2q−r = (2k + 2) − (k + 2) = k. That is, when error correction processing is performed in units of 2 m bits as compared with the case where error correction processing is performed on 2 m bits of data for each m bits, k redundant cells are generated in the redundant cells.
[0072]
Therefore, these k surplus cells can be used as spare cells for defect relief.
[0073]
According to the semiconductor memory device 11 of the present embodiment as described above, the ECC function memory having higher error correction capability than usual by switching the ECC error correction bit length and changing the use form of the redundant cell accordingly. Alternatively, it is possible to provide a memory having an error correction capability but an ECC function and a defect relief function.
[0074]
【The invention's effect】
According to the semiconductor memory device of the present invention, for example, the same circuit configuration can be used in the manufacturing stage, and the redundant cells can be set for storing error correction codes for ECC or for repairing defects immediately before shipment. Therefore, the redundant cells can be effectively used, the number thereof can be suppressed, and the manufacturing yield can be improved. Moreover, it can be used properly as a memory having the same circuit configuration but different error correction capability.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a circuit connection diagram showing an example of connection with the periphery of the defective cell repair portion according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram showing an example of a cell switching circuit according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example of a sense amplifier with a disable fuse according to an embodiment of the present invention.
FIG. 5 is a circuit connection diagram showing an example of a defective cell remedy state of the defective cell remedy section according to the first embodiment of the present invention;
FIG. 6 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 7 is an explanatory diagram showing a state of error correction bit length switching and defect relief in a semiconductor memory device according to a second embodiment of the present invention;
[Explanation of symbols]
1, 11 Semiconductor memory device 2, 12 Main cell group 3, 13 Sense amplifier group 4 with disable fuse 4, 14 Redundant cell group 5, 15 Sense amplifier group 6, 16 ECC circuit unit 16-1, 16-2 8-bit ECC Circuit 16-3 16-bit ECC circuit 7, 17 Defective relief unit 8, 18 Input / output circuit 21, 121 16-bit data cell 121-1, 121-2 8-bit data cell 31 Sense amplifier 32 Disable fuse 33 High resistance 41 5 Bit redundant cell 141 8-bit redundant cell 141-1, 141-2 4-bit redundant cell 141-3 5-bit redundant cell 141-4 3-bit redundant cell 71 Cell switching circuit 711 P-channel MOSFET
712 N-channel MOSFET
713 fuse 714 high resistance 715 inverter

Claims (13)

a data main cell group for storing n-bit data;
a p-bit redundant cell group;
An ECC circuit having a function of correcting an error generated in the n-bit data;
A defective cell relief section having a function of performing relief of defective cells in the main cell group,
A semiconductor memory device characterized in that the ECC circuit uses the redundant cell group to store a p-bit error correction code for ECC. 2. The semiconductor memory device according to claim 1, wherein a control signal for turning on the ECC circuit is input from an external terminal. 2. The semiconductor memory device according to claim 1, wherein a control signal for turning on the ECC circuit is fixedly provided therein. The defective cell relief unit includes a cell switching circuit including a changeover switch for switching a defective cell in the main cell group to a redundant cell and a fuse, and maintains an energized state of the fuse when the ECC circuit is ON. The semiconductor memory device according to claim 1, wherein the cell changeover switch is turned off. a data main cell group for storing n-bit data;
a p-bit redundant cell group;
An ECC circuit having a function of correcting an error generated in the n-bit data;
A defective cell relief section having a function of performing relief of defective cells in the main cell group,
A semiconductor memory device according to claim 1, wherein a part of the main cell group is replaced with at least a part of the redundant cell group by the defective cell repair unit. 6. The semiconductor memory device according to claim 5, wherein a control signal for turning off the ECC circuit is input from an external terminal. 6. The semiconductor memory device according to claim 5, wherein a control signal for turning off the ECC circuit is fixedly provided therein. The defective cell repair unit includes a cell switching circuit including a changeover switch for switching a defective cell in the main cell group to a redundant cell and a fuse. When the ECC circuit is OFF, the cell is disconnected by cutting the fuse. 6. The semiconductor memory device according to claim 5, wherein the changeover switch is turned on. A main cell group for storing 2 m-bit data;
Any one of a first ECC circuit that corrects an error occurring in the 2m-bit data in units of m bits, a second ECC circuit that corrects an error in units of 2m bits, and the first ECC circuit and the second ECC circuit. An ECC circuit unit having error correction bit length switching means for switching;
A 2q-bit redundant cell group;
A defective cell relief unit capable of performing relief of defective cells in the main cell group,
The ECC circuit unit is switched to the first ECC circuit, two sets of q-bit error correction codes for m-bit data are stored in the redundant cell group, and error correction of the 2m-bit data is performed in units of m bits. A semiconductor memory device. A main cell group for storing 2 m-bit data;
Any one of a first ECC circuit that corrects an error occurring in the 2m-bit data in units of m bits, a second ECC circuit that corrects an error in units of 2m bits, and the first ECC circuit and the second ECC circuit. An ECC circuit unit having error correction bit length switching means for switching;
A 2q-bit redundant cell group;
A defective cell relief unit capable of performing relief of defective cells in the main cell group,
The ECC circuit unit is switched to the second ECC circuit, and an error correction code of r (r <2q) bits for 2m-bit data is stored in the redundant cell group, and 2m-bit data with an ECC function in 2m-bit units A maximum of (2q−r) defective cells are repaired. 11. The semiconductor memory device according to claim 9, wherein a control signal to the error correction bit length switching means is given from an external terminal. 11. The semiconductor memory device according to claim 9, wherein a control signal to said error correction bit length switching means is fixedly given therein. The defective cell repair unit includes a cell switching circuit including a changeover switch for switching a defective cell in the main cell group to a redundant cell and a fuse, and electrically connects the cell changeover switch by cutting the fuse. The semiconductor memory device according to claim 10.

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