JP2005043914A - Display controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display controller which can keep a frame frequency constant without restricting a driving line at the time of partial display and can easily change over the frame frequency itself. <P>SOLUTION: The liquid crystal display controller is provided with a register for setting a frequency dividing ratio of an original clock and the number of clocks of one scanning period and is so constituted that a set value can be inputted to the register from the outside. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a control device for displaying a dot matrix type liquid crystal.

  As a display control device for a liquid crystal panel, there is a device described in JP-A-11-31980. This device can selectively drive a part of the liquid crystal panel, and can set a drive voltage, a drive bias ratio, and a reference clock frequency according to the number of drive lines of the selected portion. Thereby, when it is not necessary to display the entire screen, only a necessary portion can be displayed under an appropriate driving condition, and power consumption can be reduced.

JP-A-11-31980

  The above-described prior art describes a method of keeping the frame frequency constant by switching the frequency division ratio of the original clock according to the number of drive lines and using this as the reference clock.

  For example, consider a case in which 16 lines are driven during partial display in a liquid crystal panel in which 8 lines are one line and 32 lines (4 lines) are a full screen display. In this case, if the frequency of the reference clock remains constant, the drive time for 16 lines is half that for 32 lines, so the frame frequency increases twice. As a result, the image quality may be deteriorated. Therefore, the frame frequency can be kept constant by dividing the frequency of the original clock by one half, that is, by dividing it by two and using this as the reference clock. Similarly, by dividing the dividing ratio of the original clock to be divided by 4 or 8, the frame frequency can be kept constant even in partial display of 8 lines (2 rows) and 4 lines (1 row). Is possible.

  However, liquid crystal panels used in recent cellular phones and the like increase in number of display lines exceeding 100 lines, and there is a demand to set the number of lines per line to other than 8. For this reason, various settings are required for the number of lines to be partially displayed. On the other hand, the number of partial display lines capable of making the frame frequency constant in the prior art is limited to 1/2, 1/4, 1/8, etc. of the full screen display. Therefore, it is difficult to keep the frame frequency constant without limiting the drive line.

  On the other hand, it is conceivable that the optimum value of the frame frequency varies depending on the characteristics of the liquid crystal panel used or the driving conditions. For example, in general, when using a liquid crystal having a quick luminance response, sufficient contrast cannot be obtained unless the frame frequency is increased. However, increasing the frame frequency leads to an increase in power consumption. Therefore, an operation of switching the frame frequency according to the purpose, such as preparing a contrast priority mode and a power consumption priority mode, can be considered.

  However, in the conventional liquid crystal display control device, switching the frame frequency according to the operation mode of the device has not been considered.

  In addition, mobile phones with liquid crystal display devices and information terminals with schedule management functions are expected to reduce power consumption and extend usage time, especially when waiting for mobile phones and operating information terminals. Sometimes, when only an arbitrary partial area required by a clock, animation, or application is displayed, it is necessary to efficiently drive an arbitrary partial area required by the application instead of driving the entire screen.

  Therefore, an object of the present invention is to provide a liquid crystal display control device that realizes low power consumption by enabling partial display within an arbitrary range.

  Another object of the present invention is to provide a liquid crystal display control device that can easily switch the frame frequency itself by matching the frame frequency to the characteristics of the liquid crystal panel.

  Another object of the present invention is to provide a liquid crystal display control device that realizes gradation display in the above liquid crystal display control device.

  Another object of the present invention is to provide a good image quality and power consumption when the liquid crystal display control device changes display data in a standby area of a mobile phone or in an arbitrary partial area of a screen of an information terminal. An object of the present invention is to provide a liquid crystal display control device capable of reducing the above.

  In solving the above-mentioned problem, first, the frame frequency can be obtained by Equation 1 from one scanning period which is a time for driving one line and the driving line.

Frame frequency = 1 / (1 scan period x number of drive lines) (Equation 1)
As can be seen from Equation 1, when the number of drive lines is changed, the length of one scanning period may be adjusted in order to keep the frame frequency constant. Here, one scanning period is a value determined by the number of reference clocks that define the scanning period. Focusing on this point, if the number of reference clocks per scanning period is set in addition to the frequency division ratio of the original clock, the frame frequency can be kept substantially constant according to an arbitrary drive line. I thought it was easy to adjust itself.

  As a specific example of the setting method, various setting values of the reference clock for keeping the frame frequency around 60 [Hz] and 70 [Hz] are shown in FIG. Here, the frequency of the original clock is 200 [kHz], and the number of drive lines during full screen display is 160. As can be seen from FIG. 2, it is possible to keep the frame frequency substantially constant for various numbers of drive lines. Therefore, in the liquid crystal display control device of the present invention, a register for setting the frequency division ratio of the original clock and the number of clocks in one scanning period is provided, and a set value can be input to the register from the outside.

  The liquid crystal display control device of the present invention can realize low power consumption by enabling partial display within an arbitrary range.

  In addition, the liquid crystal display control device can easily switch the frame frequency itself according to the characteristics of the liquid crystal panel, and can realize a good display contrast according to the characteristics of the liquid crystal panel.

  In addition, the liquid crystal display control device can reduce power consumption and realize gradation display with good contrast.

  Furthermore, it is possible to realize display of an arbitrary area of a screen during standby of a mobile phone and data communication with good image quality and low power consumption.

  Hereinafter, an embodiment of the first liquid crystal display control device of the present invention will be described with reference to FIGS.

  FIG. 1 shows a block configuration of a liquid crystal display control device according to the present invention and a connection relationship with an external device. In FIG. 1, 101 is a CPU (central processing unit), 113 is a memory, 114 is a bus connecting the CPU 101 and the memory 113, 102 is a liquid crystal display control device of the present invention, 103 is a plurality of scanning lines and data lines. This is a so-called passive matrix type liquid crystal panel in which pixels are formed at intersections. The liquid crystal display control apparatus 101 includes a system interface 104, a control register 105, a reference clock generation unit 106, a timing generation unit 107, an address decoder 108, a display memory 109, a data line driving unit 110, a scanning line driving unit 111, a driving voltage. The generation unit 112 is configured.

  First, basic operations in the MPU 101, the liquid crystal display control device 102, and the liquid crystal panel 103 will be described.

  The MPU 101 gives display data for displaying an image on the liquid crystal panel 103 and various drive parameters of the liquid crystal panel 103 to the liquid crystal display control device 102. The various drive parameters include information on the frequency division ratio of the original clock and the number of clocks in one scanning period, which are features of the present invention, in addition to information on the number of drive lines, drive voltage, drive bias ratio, and the like. Yes. This operation is executed by the MPU 101 based on an operating system and application software that controls the entire apparatus stored in the memory 113. Therefore, the memory 113 stores a table in which the number of drive lines, the frequency division ratio, and the reference clock number for one scanning period shown in FIG. 2 are associated with each other, and the MPU 101 is divided according to the number of lines to be driven. The peripheral ratio and the number of reference clocks for one scanning period are determined and supplied to the liquid crystal display control device 102 as drive parameters. As an example of the program, if there is an input from the operator to the device, an operation to give new display data so that a display corresponding to this is given, or conversely, if there is no input from the operator for a certain period, the number of drive lines is set. There is an operation to give a new driving parameter so as to change.

  The liquid crystal display control device 102 stores display data and various drive parameters given from the external information processing device 101 in the display memory 109 and the control register 105, respectively. Then, in accordance with the stored drive parameter, display data is read from the display memory 109, converted into a data signal, and further output as a data line drive voltage supplied to the data line. On the other hand, the scan drive voltage is output to the scan line that scans corresponding to the data line driven by the data drive voltage. Therefore, the frequency at which the data line driving voltage and the scanning line driving voltage for display are switched under control and other driving conditions are determined by the driving parameters.

  The liquid crystal panel 103 displays an image by inputting the data line driving voltage and the scanning line driving voltage supplied from the liquid crystal display control device 102 to the data line and the scanning line, respectively. Here, the voltage waveforms of the data line driving voltage and the scanning line driving voltage follow the liquid crystal driving waveforms described in, for example, Nikkan Kogyosha Publishing, Japan Society for the Promotion of Science, volume 142, “Liquid Crystal Device Handbook” P394 to P399.

  With the configuration and operation described above, the frequency division ratio of the original clock and the number of clocks in one scanning period can be set from the outside, and the liquid crystal panel can be driven according to these values. Therefore, the frame frequency can be kept substantially constant for various numbers of drive lines, which is the object of the present invention, and an arbitrary number of scanning lines of the display panel can be driven, so that the display panel can display with good image quality.

  Next, a more detailed operation of the liquid crystal display control apparatus 102 will be described.

  First, the interface of the external information processing apparatus 101 conforms to, for example, a so-called 68-system bus interface, and the liquid crystal display control apparatus 102 receives information whose display data has changed from the external information processing apparatus 101. More specifically, when the gradation is different between the previous frame and the current frame for each pixel, the external information processing apparatus 101 transfers display data representing the gradation to the liquid crystal display control apparatus 102, and the gradation is Display data is not transferred for pixels that do not change. As shown in FIG. 3, the interface between the system interface 101C of the external information processing apparatus 101 and the system interface 104 of the liquid crystal display control apparatus 102 includes a CS signal indicating chip selection, an RS signal selecting address / data of the control register, It consists of an E signal for instructing the start of operation, an RW signal for selecting writing / reading of data, and a D signal which is the actual value of the address / data. These control signals have a cycle for designating the address of the control register 105 and a cycle for writing data. The operation of the control signal in these cycles will be described with reference to FIG. First, in the addressing cycle, the CS signal is set to “low”, the RS signal is set to “low”, the RW signal is set to “low”, the D signal is set to a predetermined address value, and then the E signal is set to “high” for a certain period. Set to. On the other hand, in the data write cycle, the CS signal is set to “low”, the RS signal is set to “high”, the RW signal is set to “low”, the D signal is set to desired data, and then the E signal is set to “high” for a certain period. set.

  The system interface 104 is a part that decodes the control signal, and outputs to the control register 105 a signal for setting the corresponding address to the write state in the addressing cycle and data to be written in the data write cycle. .

  In the control register 105, the register at the instructed address is in a write state, and data is stored in this register. The data written to the control register 105 includes various driving parameters, display data, and display position data, and are written to different addresses. That is, various drive parameters and display data given from the information processing apparatus 101 once pass through the control register 105. Various data stored in the control register 105 is output to each block.

  The reference clock generation unit 106 receives the division ratio data of the original clock from the control register 105, divides the original clock based on this value, generates a reference clock, and outputs this to the timing generation unit 107. Note that the original clock is generated by a built-in oscillation circuit.

  The timing generator 107 receives a reference clock and receives data of the number of reference clocks and the number of drive lines for one scanning period from the control register 105, and synchronizes with a line pulse synchronized with one scanning period and one frame period based on the received data. The generated frame pulse is generated and output to the data line driving unit 110 and the scanning line driving 111. At the same time, a display memory read address is generated and output to the address decoder 108.

  When the display data is written, the address decoder 108 decodes the display position data supplied from the control register 105 and selects a bit line and a word line in the display memory 109 corresponding to the display position data. Thereafter, the display data supplied from the control register 105 is output to the data line of the display memory 109, and the writing operation is completed. On the other hand, at the time of reading, the read address output from the timing generation unit 108 is decoded and the corresponding word line in the display memory 109 is selected. Thereafter, display data for one line is collectively output from the data lines of the display memory 109. Note that the above read address is switched one line at a time, for example, from the address where the data of the first line of the screen is stored, and after the last line address, the operation returns to the first line again and this operation is repeated. The address switching timing is synchronized with the line pulse output from the timing generation unit 117, and the timing for outputting the address of the head line is synchronized with the frame pulse output from the timing generation unit 117. Note that the address decoder 108 has a so-called arbitration function that gives priority to either one of a write operation and a read operation.

  The data line driving unit 110 converts display data read from the display memory 109 into a predetermined on voltage or off voltage, and outputs the data to the data line of the liquid crystal panel 103 as a data line driving voltage. Note that both the on-voltage and the off-voltage of the data line driving voltage are generated and given by the driving voltage generation unit 112.

  A frame pulse and a line pulse are input to the scanning line driving unit 111, and a selection voltage or a non-selection voltage is output to the scanning line of the liquid crystal panel 103 as a scanning line driving voltage in accordance with these signals. Here, it is assumed that the application timing of the playing voltage is applied to the first line in synchronization with the frame pulse, and then sequentially applied to the next line in synchronization with the line pulse. In addition, the non-selection voltage is applied except for the period during which the scanning line driving voltage is applied. Note that both the selection voltage and the non-selection voltage of the scanning line driving voltage are generated and given by the driving voltage generation unit 112.

  The drive voltage generation unit 112 generates an on-voltage and an off-voltage among the above-described data line drive voltages and a selection voltage and a non-selection voltage among the scanning line drive voltages from a system power supply given from the outside. Further, the drive voltage generation unit 112 receives the drive voltage and drive bias ratio data from the control register 105 and adjusts the level of each drive voltage accordingly.

  Here, timing charts of the above-described frame pulse, line pulse, reference clock, display data, data signal, and scanning signal are summarized in FIG. Here, the number of reference clocks in one scanning period is 15.

  By the operation of the liquid crystal display control apparatus 102 described above, the external information processing apparatus 101 gives information on the clock frequency division ratio and the number of clocks in one scanning period, so that the liquid crystal panel 103 is set in a desired frame according to this data. It becomes possible to drive at a frequency. Therefore, the frame frequency can be kept substantially constant for various drive lines, which is the object of the present invention, and the change of the frame frequency itself can be easily realized. In addition, since the drive voltage and the drive bias ratio can be adjusted according to the number of drive lines, display can be performed under appropriate drive conditions during partial display, and power consumption can be reduced. In the above description, a detailed description of so-called AC switching in which the polarity of the voltage applied to the liquid crystal is inverted at a constant period is omitted, but this operation generates a signal instructing AC switching by the timing generation unit 107. In response to this, the voltage level output by the data signal and the scanning signal can be easily realized by switching to an appropriate voltage level.

  Next, a second embodiment will be described as a partial modification of the present invention with reference to FIGS.

  The liquid crystal display control device according to the second embodiment of the present invention is a liquid crystal display control device that realizes gradation display.

  First, the gradation display method to be applied is a PWM (pulse width modulation) method. As shown in FIG. 6, the PWM method relates to a data signal applied to a data line of a liquid crystal panel. One scanning period is divided into a plurality of periods, and the ratio of on voltage and off voltage in each divided period is expressed as display data. This is a method of obtaining intermediate display luminance by determining the gradation information (hereinafter simply referred to as gradation display data).

  Here, consider a method of obtaining 16 gradations by applying the PWM method to the liquid crystal display control device of the present invention. First, the division of one scanning period necessary in the PWM method is simple if it is divided by the period of the reference clock. Since the data signal is supplied to each data line over a period selected by the scanning signal, that is, one scanning period defined by the line pulse, for example, as shown in FIG. 7, 16 gradations are realized. In this case, the number of reference clocks in one scanning period is set to 15, and the ratio of the ON voltage is set to 0/15, 1/15, 2/15. . . It may be 15/15.

  However, as described above, in the liquid crystal display control device of the present invention, the number of reference clocks in one scanning period is not fixed to 15 in order to adjust the frame frequency. For this reason, for example, when the number of reference clocks is 15 or less, 16 gradations cannot be realized. On the other hand, when the number of reference clocks is 15 or more, the ratio of the ON voltage cannot be increased continuously, and the linear effective voltage characteristic cannot be realized.

  In solving this problem, first, when displaying m gradations, the number n of reference clocks must be (m−1) or more. Therefore, one scan period is divided into n, where n ≧ (m−1). Next, with regard to the linearity of the effective voltage when n is larger than (m−1), attention was paid to the fact that the ratio of the ON voltage in the selection voltage application period determines the effective voltage applied to the liquid crystal. That is, if the selection voltage is given only during the first to (m−1) th periods of n divisions instead of applying the selection voltage for one scanning period, the same condition as in the case of n = (m−1) is obtained. I found out that I can do it. Therefore, the first to (m−1) -th divided period is set as the effective period, and the remaining divided periods are set as the invalid period, and the ratio of the on-voltage is continuously increased in the effective period. For example, when 16 gradation display is performed in 16 divisions, as shown in FIG. 8, each gradation is realized by continuously increasing the on-voltage ratio in the 1st to 15th division periods. I decided to output the voltage as it is. In conjunction with this, the scanning signal outputs a selection voltage in the first to fifteenth division periods and a non-selection voltage in the number 16th. With the above operation, the above-described problems can be solved.

  The configuration and operation of the liquid crystal display control device according to the second embodiment of the present invention will be described below.

  FIG. 9 shows a block configuration of a liquid crystal display control device according to the second embodiment of the present invention and a connection relationship with an external device. In FIG. 9, 901 is a CPU, 902 is a liquid crystal display control device of the present invention, and 903 is a passive matrix type color liquid crystal panel. Further, the liquid crystal display control device 902 includes a system interface 904, a control register 905, a reference clock generation unit 906, a timing generation unit 907, an address decoder 908, a display memory 909, a data line driving unit 910, a scanning line driving unit 911, a driving voltage. A generation unit 912, a gradation processing unit 913, and a gradation palette register 914 are included.

  First, basic operations in the information processing device 901, the liquid crystal display control device 902, and the liquid crystal panel 903 will be described.

  The information processing device 901 includes an MPU 901a, a memory 901b, a system interface 901c, and a bus 901d that connects them, gradation display data for displaying an image on the liquid crystal panel 903, various drive parameters of the liquid crystal panel 903, and The gradation palette data is given to the liquid crystal display control device 902. First, various drive parameters are the same as those in FIG. Since gradation display data is premised on color display in this embodiment, it has 8-bit color information for each pixel, among which red (R) and green (G) are 3 bits, blue (B ) Shall be assigned 2 bits. The gradation palette data is base data that determines which gradation corresponds to the color specified by the gradation display data. Here, the information processing apparatus 901 selects a total of 20 types of RG: 8 types (3 bits) and B: 4 types (2 bits) from the gradation palette data of 16 gradations for each of RGB, and displays the liquid crystal display. It is given to the control device 902. As a result, 256 colors (8-bit color information per pixel) can be selected from 4096 colors (16 gradations for RGB) and displayed. The operation of giving information from the information processing device 901 to the liquid crystal display control device 902 is the same as that of the liquid crystal display control device of FIG.

  The liquid crystal display control device 902 stores the gradation display data, various drive parameters, and gradation palette data supplied from the information processing device 901 in the display memory 909, the control register 905, and the gradation palette register 914, respectively. Then, according to the stored drive parameters, gradation display data is read from the display memory 909 and converted into RGB PWM signals based on the gradation palette data. Further, the PWM signal is converted into a data signal and outputted, and a corresponding scanning signal is outputted.

  The liquid crystal panel 903 has color filters corresponding to RGB and data lines corresponding thereto. The liquid crystal panel 903 inputs RGB data signals supplied from the liquid crystal display control device 902 to the corresponding data lines, and scans the scanning signals. To display the image.

  Note that the voltage waveforms of the data signal and the scanning signal follow the liquid crystal driving waveforms described in, for example, Nikkan Kogyo Co., Ltd., Japan Society for the Promotion of Science, volume 142 “Liquid Crystal Device Handbook” P394 to P399, as in the first embodiment of the present invention. Shall.

  With the configuration and operation described above, the liquid crystal display control device according to the second embodiment of the present invention can keep the frame frequency substantially constant for various drive lines as in the liquid crystal display control device of FIG. it can. In addition, color multicolor display by the PWM method is possible.

  Next, a more detailed operation of the liquid crystal display control device 902 will be described.

  First, since the system interface 904, the control register 905, the reference clock generation unit 906, and the address decoder 908 are the same as the liquid crystal display control device of FIG.

  The timing generation unit 907 outputs a line pulse, a frame pulse, and a display memory read address in the same manner as the timing generation unit 107 of FIG. 1, and in addition, a grayscale enable signal for instructing the valid period / invalid period described above. Is output to the gradation processing unit 913 and the scanning line drive 911.

  As shown in FIG. 10, the gradation processing unit 913 includes a PWM signal generation unit 1001 and a PWM signal selection unit 1002. First, the PWM signal generation unit 1001 includes a reference clock counter 1101 and a comparator 1102 as shown in FIG. The input of the reference clock counter is a line pulse, a reference clock, and a gradation enable signal. Then, the count pulse is reset by the line pulse, and the count value is incremented in synchronization with the reference clock during the active period of the gradation enable signal. For example, when 16 gradations are displayed by dividing one scanning period into 16, as shown in FIG. 12, the line pulse is reset to 1, and after counting up to 15, the count value of 15 remains as it is for the remaining period. Output. The comparator 1102 receives the count value of the reference clock and the gradation palette data given from the gradation palette register 914. When (count value) ≦ (gradation palette data), the comparator 1102 is “low” (count value). )> (Gradation palette data), output “high”. For example, as shown in FIG. 12, when the gradation palette data is “2”, the reference clock count value is “low” from 1 to 2, and 3 to 15 is “high”. Since there are 20 types of gradation palette data, RG: 8 types and G: 4 types, the PWM signal generation unit 1001 generates 20 types of PWM signals corresponding to each gradation palette data. . Next, as shown in FIG. 13, the PWM signal selection unit 1002 includes two 8-to-1 selectors (for RG) and one 4-to-1 selector (for B) for each pixel. . Then, the PWM signal is selected and output according to the gradation display data for one line read from the display memory 909.

  The data line driving unit 910 converts the PWM signal supplied from the gradation processing unit 913 to an on voltage when the PWM signal is “low”, and converts it to an off voltage when it is “high”, and outputs the data signal to the data line of the liquid crystal panel 103 as a data signal. To do.

  A frame pulse, a line pulse, and a gradation enable signal are input to the scanning line driver 911, and a selection voltage or a non-selection voltage is output as a scanning signal to the scanning line of the liquid crystal panel 103 in accordance with these signals. Here, the selection voltage is applied to the first line in synchronization with the frame pulse, and then applied in sequence to the next line in synchronization with the line pulse. Only when is active. Note that the non-selection voltage is applied for all other periods.

  By the operation of the liquid crystal display control device 902 described above, the frame frequency can be kept almost constant in various drive lines as in the liquid crystal display control device of FIG. 1, and the frame frequency itself can be easily changed. It becomes feasible. In addition to this, since it is possible to output the data signal and the scanning signal shown in FIG. 8, a linear effective voltage characteristic can be realized using the PWM method.

  It should be noted that the number of colors, the number of gradations, the number of divisions of the scanning period, etc. shown in the second embodiment of the present invention are all examples and are not limited thereto.

  In the second embodiment of the present invention, the PWM method is applied to the gradation method, but the present invention is not limited to this. For example, it is also possible to apply an FRC (Frame Rate Control) system in which several frames are set as one unit and the number of frames for displaying on and off is controlled. In the case of this method, on-voltage and off-voltage are not mixed in one scanning period, and either voltage is applied. Therefore, it is not necessary to divide one scanning period into a valid period and an invalid period.

  Next, a third embodiment will be described with reference to FIGS. 14 to 18 as a partial modification of the present invention.

  The third embodiment of the present invention describes a method for realizing a PWM method for realizing higher image quality and lower power consumption in the liquid crystal display control device of the present invention.

  First, the data signal for realizing the PWM method shown in FIG. 8 always has a voltage level change point twice per scanning period except for black and white gradations. This is because the start of one scan period is an on-voltage and the end is an off-voltage. Therefore, it was considered that the number of changes in the data signal can be halved by reversing this relationship for each scanning period. Thereby, the power consumption related to charging / discharging of the liquid crystal is halved, and the power consumption of the apparatus can be reduced. In order to realize this operation, for example, as shown in FIG. 14, if the reference clock count is incremented from 1 in a certain scanning period, it may be decremented from 15 in the next scanning period.

  Here, if there is a time difference between the output timing of the data signal and the scanning signal, the effective value of the liquid crystal applied voltage may differ depending on whether the start of one scanning period is an on voltage or an off voltage. For this reason, even if, for example, the same gradation is displayed, there is a possibility that a difference in density occurs for each line. In order to solve this, as shown in FIG. 15, the scanning period in which the start of one scanning period is turned on and the scanning period in which it is turned off are switched for each frame, and the difference between the effective values of applied voltages is averaged. Just do it. For example, as shown in FIG. 15, this operation may be performed by decrementing the scanning period in which the reference clock count is incremented from 1 in the even-numbered frame from 15 in the odd-numbered frame. That is, when the gradation palette data 2 is supplied, in the even frame, the PWM signal is “low” in the first frame when the reference clocks 1 and 2 are used, and in the second frame, the PWM signal is the reference clocks 14, 15, At 16, it goes “low”. Here, since the reference clock 16 is not selected, data is effectively supplied for two pulses of the reference clock in each frame. Similarly, in the odd frame, the PWM signal is “low” at the reference clocks 14, 15 and 16 in the first frame, and “low” at the reference clocks 1 and 2 in the second frame. In this case, since the reference clock 16 of the first frame is not selected, the gradation palette data “2” can be realized.

  Furthermore, for example, when the same gradation is displayed, the voltage level of the data signal shown in FIG. 15 changes at the same timing for all data lines. For this reason, a large peak current flows temporarily. In order to reduce the peak current, it was considered to shift the data signal change timing for each data line. For example, as shown in FIG. 16, two types of reference clock counters are prepared for even data lines and odd data lines, and the increment and decrement timings of the counters are reversed. Thereby, the phase of the data signal applied to the even data line and the odd data line can be shifted by 180 degrees. Further, as shown in FIG. 17, it is possible to disperse the voltage level change of the data signal by preparing a plurality of reference clock counters and shifting the timing of the count values by one reference clock. .

  Next, the voltage level of the data signal for realizing the PWM method described so far does not change in black and white gradations. For this reason, in an image in which halftone and black or white are mixed, display unevenness due to the difference in the number of change points in the voltage level may occur. In order to solve this, the voltage level of the data signal may be changed in the black and white gradations as in the case of other intermediate gradations. Therefore, for example, as shown in FIG. 18, the reference clock number of the effective period is set to 17 instead of 15, and the start of the count value is set to 0 and the end is set to 16. Thereby, as shown in FIG. 18, for example, it can be understood that the PWM signal changes once in one scanning period even when the gradation palette data is “0” (black).

  Here, if the data signal is changed in black or white gradation, the power consumption increases. Therefore, it was considered to switch whether to change the black and white data signals according to whether priority is given to display unevenness suppression or low power consumption. Specifically, as shown in FIG. 18, when the data signal is not changed, “0” and “16” in the count value of the reference clock may be switched to “1” and “15”. This operation can be realized by giving a command from the external information processing apparatus, similarly to the setting of the drive parameter described above.

  The above embodiments described above can be freely combined. In addition to the drive parameters described in the present invention, various settings such as contrast adjustment and display off function are conceivable. These are all set in the control register from the external information processing apparatus described in the embodiment of the present invention. This can be easily realized by giving a set value and controlling each block therefrom. Further, the liquid crystal display control device described in the embodiment of the present invention has been described on the assumption that it is configured by a one-chip LSI. However, the present invention is not limited to this, and a two-chip, three-chip configuration divided according to function. But it ’s okay.

  Next, a fourth embodiment of the present invention will be described with reference to FIG.

  The fourth embodiment of the present invention shows a mobile phone system using the liquid crystal display control device of the present invention. FIG. 19 is a block diagram of a mobile phone system, 1901 is a liquid crystal module including a liquid crystal display control device of the present invention and a liquid crystal panel, 1902 is an ADPC codec circuit for compressing / decompressing audio, 1903 is a speaker, 1904 is a microphone, Reference numeral 1905 denotes a keyboard, 1906 denotes a TDMA circuit for time-division multiplexing digital data, 1907 denotes an EEPROM for storing a registered ID number, 1908 denotes a ROM for storing a program, and 1909 denotes temporary storage of data and a work area of the microcomputer. The SRAM 1910 is a PLL circuit for setting a carrier frequency of a radio signal, 1911 is an RF circuit for transmitting / receiving a radio signal, and 1912 is a system control microcomputer.

  The mobile phone system according to the fourth embodiment of the present invention is, for example, a full screen display when displaying a received electronic mail or a stored telephone number book, and a partial screen display when waiting. This full screen / partial screen display state is switched by the system control microcomputer 1912 based on the keyboard input from the operator and the state of the received radio wave, and is programmed in advance so that information on the number of drive lines is output to the liquid crystal module 1901 at that time. It is assumed that In conjunction with this, information on the division ratio of the original clock, the number of clocks in one scanning period, and other driving parameters are also output to the liquid crystal module 1901. Here, with respect to the number of drive lines determined by the system control microcomputer 1912, how to determine the frequency division ratio of the original clock and the number of clocks in one scanning period is, for example, a table as shown in FIG. Can be determined by referring to this table. It is assumed that this table data is stored in the ROM 1908 together with the program. Further, information regarding other drive parameters can be determined by preparing tables for the number of drive lines.

  With the above operation, the mobile phone system according to the fourth embodiment of the present invention can switch between full screen display and partial screen display according to the application. That is, when it is not necessary to display the entire screen, only a necessary part can be displayed, and power consumption can be reduced. Furthermore, the mobile phone system according to the fourth embodiment of the present invention can keep the frame frequency, which is the driving frequency of the liquid crystal module, substantially constant regardless of the full screen / partial screen display. As a result, it is possible to prevent image quality degradation accompanying an increase in the frame frequency.

  In addition, the mobile phone system according to the fourth embodiment of the present invention can change only the frame frequency, for example, while maintaining full screen display. The purpose of this operation is to realize a contrast priority mode driven at a high frame frequency and a power consumption priority mode driven at a low frame frequency. For example, information on the frequency division ratio of the original clock and the number of clocks in one scanning period is obtained from the system control microcomputer 1912 (information processing apparatus 101, (Corresponding to 901) can be realized by outputting to the liquid crystal module 1901. As in the previous example, for example, a table as shown in FIG. 2 is prepared as to how to determine the division ratio of the original clock and the number of clocks in one scanning period in each mode. This can be determined by referring to this table.

  With the above operation, the mobile phone system according to the fourth embodiment of the present invention can switch the frame frequency of the liquid crystal module according to the application. That is, it is possible to display high image quality with high frame frequency drive during an operator's operation, and to reduce power consumption of the liquid crystal module with low frame frequency drive during standby.

Of course, the above-described full screen / partial screen display mode and high frame / low frame frequency drive modes can be used in combination.
As described above, according to the liquid crystal display control device of the first embodiment, a register for setting the frequency division ratio of the original clock and the number of clocks in one scanning period is provided, and a set value is input to the register from the outside. I was able to do it. As a result, the frame frequency can be kept substantially constant for various numbers of drive lines, and the frame frequency itself can be easily changed.

  Further, according to the liquid crystal display control device of the second embodiment, when a gradation display function by the PWM method is provided, one scanning period is divided into an effective period and an invalid period, and display data is supported only in the effective period. The data voltage of the selected time width and the selection voltage level of the scanning signal are given. Thereby, even if the number of clocks in one scanning period changes, a linear effective voltage characteristic can be obtained with respect to gradation display data.

  In addition, according to the liquid crystal display control device of the third embodiment, various data signal waveforms for realizing the PWM method are presented. Thereby, low power consumption and high image quality can be realized.

  Furthermore, by applying the liquid crystal display control device of the present invention to a mobile phone, even when display data changes in an arbitrary partial area during standby, the image quality can be reduced and power consumption can be reduced. it can.

It is a block diagram which shows the structure of the liquid crystal display control apparatus concerning the 1st Embodiment of this invention. It is a figure explaining the setting method of the frame frequency concerning the 1st Embodiment of this invention. It is a figure explaining the content of the control signal group concerning the 1st Embodiment of this invention. It is a timing diagram which shows the operation | movement of the control signal group concerning the 1st Embodiment of this invention. FIG. 3 is a timing chart showing the operation of the liquid crystal display control device according to the first embodiment of the present invention. It is a figure explaining the principle of the PWM system concerning the 2nd Embodiment of this invention. It is a timing diagram which shows the operation | movement of a PWM system concerning the 2nd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal display control apparatus concerning the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the gradation process part concerning the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the PWM signal generation part concerning the 2nd Embodiment of this invention. It is a timing diagram which shows the operation | movement of the PWM signal generation part concerning the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the PWM signal selection part concerning the 2nd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 3rd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 3rd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 3rd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 3rd Embodiment of this invention. It is a timing diagram which shows operation | movement of the liquid crystal display control apparatus concerning the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the mobile telephone system concerning the 4th Embodiment of this invention.

Explanation of symbols

101 ... CPU
DESCRIPTION OF SYMBOLS 102 ... Liquid crystal display control apparatus 103 ... Liquid crystal panel 104 ... System interface 105 ... Control register 106 ... Reference clock selection part 107 ... Timing generation part 108 ... Address decoder 109 ... Display memory 110 ... Data line drive part 111 ... Scanning line drive part 112 ... Drive voltage generator 913 ... Gradation processor 1001 ... PWM signal generator 1002 ... PWM signal selector 1901 ... Liquid crystal module

Claims (3)

In a display control apparatus for displaying an arbitrary image on a display panel in which a plurality of data lines and scanning lines are arranged in a matrix,
An oscillation circuit that oscillates the original clock; and
A display memory for storing display data given from outside;
A control register for storing a division ratio of the original clock given from the outside, a reference clock number for one scanning period, and the number of drive lines of the liquid crystal panel;
A reference clock generation unit configured to divide the original clock from the oscillation circuit by a division ratio of the original clock in the control register to generate a reference clock;
A line pulse and one frame synchronized with one scanning period are obtained by calculating the reference clock number in the control register and the number of drive lines in the control register in the reference clock from the reference clock generation unit. Generate a frame pulse synchronized with the period,
A decoder for reading the display data from the display memory according to the line pulse and the frame pulse;
A display control device comprising: a data line driving unit that converts the display data read from the display memory into a driving voltage and outputs the driving voltage to the data line of the display panel.   The decoder collectively reads display data for one line from the address of the display memory corresponding to the top line of the display panel according to the line pulse, and corresponds to the top line of the display panel according to the frame pulse. The display control device according to claim 1, wherein the display control device returns to the address of the display memory to repeat reading of display data for one line. The display control device according to claim 1, further comprising: a scanning line driving unit that outputs a selection voltage and a non-selection voltage to the scanning lines of the display panel according to the line pulse and the frame pulse.

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