JP2005039742A - Solid state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device which is suitable for speed-up of a signal output and speed-up of a latter-stage signal processing. <P>SOLUTION: The solid-state image pickup device is provided with a scanning circuit 6 for outputting a driving signal for selecting a column; a timing generating circuit 7 for outputting a driving signal for selecting a row; a pixel switching section 8 having memory elements for two columns for temporarily storing a pixel signal in its inside, and allowing a memory element to store each pixel signal in a pixel group by switching connection between a row signal line outputting a pixel signal from an image pickup section and the memory element; and an output section 9 for outputting the pixel signal stored in the memory element using the pixel group as a unit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device used for a digital camera or the like.

  Conventionally, as this type of solid-state imaging device, for example, there is a device described in Patent Document 1.

  FIG. 14 is a block diagram illustrating a configuration of a main part of a conventional solid-state imaging device described in Patent Document 1. The solid-state imaging device shown in the figure holds a pixel unit 104 having pixels of a plurality of colors arranged two-dimensionally, a vertical scanning circuit 102, a horizontal scanning circuit 103, and a color signal read from the pixel unit 104. A temporary memory 105, and an amplifier / synchronization processing circuit 106 that synchronizes color signals output from the pixel unit 104 via the temporary memory 105.

FIG. 15 shows a pixel signal finally output from the amplifier / synchronization processing circuit 106.
First, at the timing of the scanning signal ΦH1 of the vertical scanning circuit 102, the G11 signal and the B21 signal are sequentially read from the pixel unit 104 to the temporary memory 105 and are simultaneously output via the amplifier / synchronization processing circuit 106. At that time, the B21 signal is held in an S / H (sample / hold) circuit in order to further delay the horizontal scanning signal by one clock period.

  Next, at the timing of the scanning signal ΦH2, the G22 signal and the R12 signal are sequentially read out from the pixel unit 104 to the temporary memory 105, and the G22 signal and the R12 signal together with the delayed B21 signal are converted into an amplifier / simulation processing circuit. 106 simultaneously output. At this time, the R12 signal is held in the S / H circuit to further delay the horizontal scanning signal by one clock period. Thereafter, the same is repeated.

In this way, the conventional solid-state imaging device is configured to simultaneously output two signals read to the temporary memory 105 and one signal read one clock before. At that time, the temporary memory 105 enables pixel variation correction for two vertical pixels.
Japanese Unexamined Patent Publication No. 2000-133596 (FIGS. 2 and 3)

  By the way, for example, G11, B21, R12, and G22 constitute one pixel in an image by four pixel signals. However, according to the solid-state imaging device in the above-described prior art, in one output of three synchronized pixel signals, One pixel in the image cannot be constructed. In order to configure one pixel in the image, it is necessary to configure one pixel in the image from two times of the three synchronized pixel signals in the signal processing in the subsequent stage of the solid-state imaging device. Therefore, when a solid-state imaging device is mounted on a camera, there is a problem that it is difficult to increase the speed of signal processing and thus to operate the camera at high speed.

  Further, although signals for three pixels are synchronized, one pixel is a delay signal and is the same signal as one clock before, so that it is practically only the synchronization of two pixels. Even in this respect, there is a problem that it is not suitable for speeding up the output operation.

  An object of the present invention is to provide a solid-state imaging device suitable for speeding up signal output and speeding up subsequent signal processing.

  In order to solve the above-described problems, a solid-state imaging device according to the present invention is a solid-state imaging device including an imaging unit that is provided in a matrix and has a plurality of color pixel units that perform photoelectric conversion, and corresponds to one pixel in an image. A pixel signal constituting the pixel group is output in units of pixel groups each including a color pixel portion.

Here, the pixel group may have a configuration corresponding to four pixel portions extending over two adjacent rows and two columns.
According to this configuration, since the pixel group constituting one pixel in the image is output as a unit, the signal output speed can be increased. Further, in the subsequent signal processing, processing for forming a pixel group from pixel signals that are input in a discrete manner is not necessary, so that the speed of signal processing can be increased.

  Here, the solid-state imaging device outputs a pixel signal from a driving unit that outputs a driving signal for selecting a row and a column, a memory element for two rows for temporarily holding a pixel signal, and an imaging unit. Switching means for holding each pixel signal in the pixel group in the memory element by switching the connection between the column signal line and the memory element, and outputting the pixel signal held in the memory element in units of the pixel group It is good also as a structure provided with an output means.

  Here, the driving unit sequentially outputs a column selection signal in units of two columns, and the switching unit holds two pixels located in two rows from each of the two columns corresponding to the column selection signal in the memory element. It is good also as a structure which switches a connection so that it may carry out.

Here, the output means may be configured to simultaneously output four pixel signals constituting the pixel group in synchronization with a column selection signal.
Here, the output means may output two pixel signals constituting the pixel group in synchronization with a column selection signal.

Here, the solid-state imaging device may further include a sample hold circuit that holds each of the pixel signals output from the output unit, and a multiplexer that multiplexes the pixel signals held in the sample hold circuit. .
According to this configuration, since it is not necessary to provide a plurality of A / D converters in the subsequent signal processing, a signal processing circuit similar to the conventional one can be used.

  Also, the driving method of the solid-state imaging device and the camera including the solid-state imaging device of the present invention have the same configuration, operation, and effect as described above.

According to the solid-state imaging device of the present invention, since the pixel group constituting one pixel in the image is output as a unit, the signal output speed can be increased.
Further, in the subsequent signal processing, processing for forming a pixel group from pixel signals that are input in a discrete manner is not necessary, so that the speed of signal processing can be increased.

Furthermore, by providing a signal holding circuit for multiplexing pixel signals, it is not necessary to provide a plurality of A / D converters in the subsequent signal processing, and a signal processing circuit similar to the conventional one can be used.
In addition, a high-speed signal can be obtained even in a timing generator with a low operating speed.
Furthermore, according to the camera provided with the solid-state imaging device of the present invention, it can be operated at high speed.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a main part of the solid-state imaging device according to Embodiment 1 of the present invention. This solid-state imaging device includes an imaging unit 2 having a plurality of unit pixels 1 that perform photoelectric conversion in a matrix, a row scanning circuit 6 that sequentially outputs a row selection signal to a plurality of row selection signal lines 5, and a plurality of column selection signals. A pixel signal switching unit 8 having a timing generation circuit 7 that sequentially outputs to the column selection signal line 4, a row memory that temporarily stores pixel signals that constitute a unit pixel group, and a switch that switches a pixel signal storage destination memory; The pixel signal switching unit 8 includes an output unit 9 that outputs pixel signals held in the row memory for each color to output signal lines Aout, Bout, Cout, and Dout. A unit pixel group 3 indicated by a broken line in the figure includes four unit pixels 1 arranged in two columns and two rows. The unit pixel group is composed of four unit pixels constituting one pixel in the image, like the unit pixel group 3 including A11, B11, C11, and D11. A, B, C, and D in the figure correspond to, for example, G (green), R (red), B (blue), and G (green) colors in the Bayer array.

  The timing generation circuit 7 outputs the column selection signals S1, S2,... As a shift register for every two columns of the imaging unit 2, and switches the pixel signals so as to sequentially read out the pixel signals from the unit pixels in the unit pixel group. Various timing signals are generated in the unit 8 and the output unit 9. The timing generation circuit 7 is different from the conventional column scanning circuit in that it outputs a column selection signal for every two columns instead of outputting a column selection signal for each column of the imaging unit 2.

  The pixel signal switching unit 8 includes unit switching circuits 81, 82,. The unit switching circuit 81 temporarily holds four pixel signals sequentially read from four unit pixels (for example, A11, B11, C11, and D11) constituting the unit pixel group 3. Similarly, the unit switching circuit 82 temporarily holds four pixel signals obtained from four unit pixels (for example, A12, B12, C12, and D12) constituting the unit pixel group.

  The output unit 9 includes unit output circuits 91, 92,..., And synchronizes the four pixel signals constituting the unit pixel group corresponding to the column selection signal with the column selection signal from the timing generation circuit 7. Output.

  FIG. 2 is a diagram illustrating the timing of the output signal of the solid-state imaging device. In the figure, S 1 is a column selection signal output from the timing generation circuit 7 and corresponds to the first column and the second column of the imaging unit 2. Similarly, S2 corresponds to the third column and the fourth column of the imaging unit 2, and S3 corresponds to the fifth column and the sixth column of the imaging unit 2. Aout to Dout indicate output signal lines of the output unit 9.

  In the period T1, the signal of the unit pixel A11 is output to the output signal line Aout, the signal of the unit pixel B11 is output to the output signal line Bout, the signal of the unit pixel C11 is output to the output signal line Cout, and the unit is output to the output signal line Dout. The signal of the pixel D11 is output in synchronization with the column selection signal S1 of the timing generation circuit 7. Similarly, four pixel signals A12, B12, C12, and D12 are output in the period T2, and A13, B13, C13, and D13 are output in the period T3.

  FIG. 3 is a block diagram illustrating a configuration example of the unit switching circuit 81 in the pixel signal switching unit 8 and the unit output circuit 91 in the output unit 9.

  As shown in the figure, the unit switching circuit 81 includes two switches SW1 and SW2 corresponding to two columns, and capacitors Ca to Cd that hold pixel signals as memory elements. In the clock cycle immediately before the column selection signal S1 becomes active (the clock cycle immediately before the cycle T1 in FIG. 2), first, the switches SW1 and SW2 connect the pixel signal lines of the corresponding columns to the capacitors Ca and Cb, respectively. To do. In this state, pixel signals are read from the unit pixel A11 and the unit pixel B11 from the imaging unit 2, and are held in the capacitors Ca and Cb via the switches SW1 and SW2. Subsequently, the switches SW1 and SW2 connect the pixel signal lines in the corresponding columns to the capacitors Cc and Cd, respectively. In this state, pixel signals are read from the unit pixel C11 and the unit pixel D11 from the imaging unit 2, and are held in the capacitors Cc and Cd via the switches SW1 and SW2.

  The unit output circuit 91 includes switch transistors TrA to TrD, is turned on by the column selection signal S1, and each pixel signal of the unit pixels A11, B11, C11, D11 held in the capacitors Ca to Cd in the unit switching circuit 81 Are output from the output signal lines Aout to Dout.

  In this way, in order to simultaneously output four pixel signals of a plurality of colors constituting a unit pixel group extending over 2 rows and 2 columns, one unit switching circuit among the plurality of unit switching circuits is Two pixel signals read simultaneously or sequentially from one row are held in two of the four memory elements (capacitors) in the unit switching circuit. Next, the unit switching circuit switches the two switches that connect the two columns and the memory elements so as to be connected to the other two memory elements. Further, the unit switching circuit holds two pixel signals read simultaneously or sequentially from another row in two columns in the other two memory elements among the four memory elements in the unit switching circuit. To do.

The unit output circuit 91 outputs the four pixel signals thus held in the memory element onto the four output signal lines Aout to Dout in synchronization with the column selection signal. As described above, according to the solid-state imaging device of the present invention. For example, in order to output all the pixel signals constituting one image, the period of the output signal can be reduced to ¼ as compared with a case where pixel signals are output one by one. In other words, a quarter cycle is sufficient to output the same number of pixel signals, so it is easy to shorten the cycle and increase the speed. Further, compared with the solid-state imaging device disclosed in Patent Document 1 that synchronizes two pixel signals, the output cycle can be halved, and speeding up can be facilitated.

  In addition, since a unit pixel group consisting of unit pixels of a plurality of colors constituting one pixel in an image is simultaneously output, pixel signals output in a discrete manner in signal processing (usually DSP is used) in the subsequent stage of the solid-state imaging device. Therefore, the processing for configuring the unit pixel group is not necessary, so that the signal processing amount can be reduced and the speeding up can be facilitated.

Next, the subsequent signal processing of the solid-state imaging device will be described.
Since the solid-state imaging device shown in FIG. 1 outputs four pixel signals in the unit pixel group at the same time, in the subsequent signal processing, if four A / D converters are provided corresponding to the output signals Aout to Dout. Good.

  In order to process the output signal for each pixel signal group of the solid-state imaging device shown in FIG. 1 by a conventional signal processing circuit that does not include four A / D converters, the configuration shown in FIG. 4 is provided. That's fine.

  FIG. 4 is a block diagram showing a configuration of a signal holding circuit provided in the subsequent stage of the solid-state imaging device shown in FIG. 1 and corresponding to the input portion of the signal processing circuit. As shown in the figure, the signal holding circuit includes sample and hold circuits (hereinafter abbreviated as S / H circuits) 13 a to 13 d, a multiplexer 14, and an A / D (analog / digital) converter 15. The S / H circuit 13a holds the pixel signal from the output signal line Aout. The S / H circuits 13b, 13c, and 13d are the same for the output signal lines Bout, Cout, and Dout. The multiplexer 14 multiplexes the pixel signals held in the S / H circuits 14a to 14d by selecting them in order, and outputs them to the output signal line Mout as a pixel signal string. The A / D converter 15 inputs a pixel signal string from the output signal line Mout, and converts the pixel signal into a digital value one by one.

  Among these, the S / H circuits 14a to 14d and the multiplexer 14 may be formed in the same chip as the solid-state imaging device shown in FIG. In that case, the chip may include output terminals corresponding to the output signal lines Aout to Dout and Mout so that the output signal lines Aout to Dout and the output signal line Mout can be selectively output.

  FIG. 5 is a time chart for explaining the operation of the signal holding circuit shown in FIG. In the figure, S1 and S2 indicate column selection signals output from the timing generation circuit 7. Although Aout to Dout are collectively shown in the figure, four pixel signals output from the output unit 9 are shown. Although ha to hd are collectively shown in the figure, they indicate four output signals output from the S / H circuits 13a to 13d. The output signals ha to hd output the held pixel signal over a period twice as long as the period T of the column selection signal. Select is a selection signal input to the multiplexer 14 and instructs the multiplexer 14 to select the output signals ha, hb, hc, and hd in the order indicated by the four arrows in FIG. The output signal line Mout shows a state in which pixel signals are output from the multiplexer 14 in the order of output signals ha, hb, hc, and hd.

  As described above, according to the time chart of FIG. 5, the multiplexer 14 includes four multiplexers within a period from the rising edge of the column selection signal S1 to the next rising edge of S2, that is, within a period twice the period T of the column selection signal. Pixel signals are output one by one in order.

  According to this, when there is only one A / D converter provided in the conventional signal processing circuit, the output signals Aout to Dout of the solid-state imaging device shown in FIG. Can be transmitted.

As described above, when the signal holding circuit is provided in the same chip as the solid-state imaging device or outside the chip, a conventional signal processing circuit including only one A / D converter can be used. Even in this case, since the pixel signal sequence multiplexed by the multiplexer 14 includes pixel signals constituting the unit pixel group, the signal processing circuit does not need to perform the rearrangement process. As a result, the amount of signal processing is reduced, which is suitable for speeding up.
Note that the switches SW1 and SW2 shown in FIG. 3 may be formed of switch transistors. Each of the switch transistors TrA to TrD may have an amplifier function.

(Embodiment 2)
FIG. 6 is a block diagram showing the configuration of the main part of the solid-state imaging device according to Embodiment 2 of the present invention. This solid-state imaging device is compared with the solid-state imaging device shown in FIG.
A point provided with a timing generation circuit 17 and a timing generation circuit 22 instead of the timing generation circuit 7, a point provided with a pixel signal switching unit 18 and a pixel signal switching unit 20 instead of the pixel signal switching unit 8, and a place of the output unit 9 And the output unit 19 and the output unit 21 are provided. Hereinafter, the description of the same configuration will be omitted, and different points will be mainly described.

  The timing generation circuit 17 outputs column selection signals S11, S12, S13 (see FIG. 7) similar to those of the timing generation circuit 7 shown in FIG. 1, and various kinds of signals for the pixel signal switching unit 18 and the output unit 19. A timing signal is generated.

  The timing generation circuit 22 outputs the column selection signals S21, S22, S23,... (See FIG. 7) at timings different from the timing generation circuit 17 (timing shifted by a half cycle of the clock signal), and a pixel signal switching unit. 20 and various timing signals for the output unit 21 are generated.

  The pixel signal switching unit 18 includes unit switching circuits 181, 182, 183... Among the functions of the pixel signal switching unit 8 illustrated in FIG. 1, two of the unit pixels A and B in the unit pixel group. It has a function corresponding to a pixel signal. That is, it has a row memory for temporarily storing the two pixel signals and a switch for switching the pixel signal storage destination memory.

  The pixel signal switching unit 20 includes unit switching circuits 201, 202, 203,..., And is similar to the pixel signal switching unit 18 for two pixel signals corresponding to the unit pixels C and D in the unit pixel group. .

  The output unit 19 includes unit output circuits 191, 192, 193..., And two pixel signals held in the unit switching circuits 181, 182. , S12, S13...

  The output unit 21 includes unit output circuits 211, 212, 213..., And selects the two pixel signals held in the unit switching circuits 201, 202, 203. Output in synchronization with the signals S21, S22, S23.

FIG. 7 is a diagram illustrating output timing of pixel signals of the solid-state imaging device illustrated in FIG. In the figure, only output timings of the two unit pixel groups A11 to D11 and A12 to D12 are shown. In the figure, S11 and S12 indicate column selection signals output from the timing generation circuit 22, and S21 and S22 indicate column selection signals output from the timing generation circuit 7. Aout and Bout indicate pixel signals output to the output signal line of the output unit 19, and Cout and Dout indicate pixel signals output to the output signal line of the output unit 21. In the period T1, the pixel signal of the unit pixel A11 is output to the output signal line Aout, and the pixel signal of the unit pixel B11 is output to the output signal line Bout in synchronization with the column selection signal S11. Similarly, in the period T2, the pixel signals of the unit pixels A12 and B12 are output in synchronization with the column selection signal S12. In the period T3, the pixel signal of the unit pixel C11 is output to the output signal line Cout, and the pixel signal of the unit pixel D11 is output to the output signal line Dout in synchronization with the column selection signal S21. Similarly, in the period T4, the pixel signals of the unit pixels C12 and D12 are output in synchronization with the column selection signal S22.
As described above, the solid-state imaging device shown in FIG. 6 outputs two pixel signals of unit pixels of a plurality of colors constituting the unit pixel group.

  FIG. 8 is a block diagram illustrating the configuration of the unit switching circuit 201 and the unit output circuit 211. The unit switching circuit 201 has switches SW21 and SW22 and memory elements (capacitors) Cc and Cd and is a subset of the unit switching circuit 81 shown in FIG. The unit output circuit 211 includes switch transistors TrC and TrD and is a subset of the unit output circuit 91 shown in FIG.

  FIG. 9 is a block diagram showing the configuration of the unit switching circuit 181 and the unit output circuit 191. The configuration of this figure is the same as that of FIG. However, the column selection signal S11 in FIG. 8 has the same timing as the column selection signal S1 shown in FIG. 3, but the column selection signal S21 in FIG. 9 is shifted from the column selection signal S1 shown in FIG. The timing is different (see FIG. 7).

  FIG. 10 is a time chart showing various timing signals output by the timing generation circuits 17 and 22. ST in the figure indicates a start pulse common to the timing generation circuits 17 and 22. As shown in the figure, the timing generation circuit 17 generates column selection signals S11, S12,... By two clock pulses H101, H102 having opposite phases. The timing generation circuit 22 generates column selection signals S11, S12,... By two clock pulses H201, H202 having opposite phases.

FIG. 11 is a circuit diagram showing a specific example of the timing generation circuit 17 that generates the column selection signal. The circuit shown in the figure is an example constituted by CMOS transistors, and constitutes a shift register that sequentially shifts and outputs column selection signals using clock pulses H1 and H2 having opposite phases as operation clocks. The timing generation circuit 22 can also have the same circuit configuration. That is, as shown in the time chart of FIG. 12A, the timing generation circuit 22 uses the clock pulses H1 and H2 in the phases indicated by H201 and H202. On the other hand, as shown in the time chart of FIG. 12B, the timing generation circuit 17 uses the clock pulses H1 and H2 in the phases indicated by H101 and H102.
As described above, the timing generation circuits 17 and 22 operate by the clock signal obtained by switching the start pulse ST and the two clock pulses H1 and H2.

  The solid-state imaging device in the present embodiment is different from the solid-state imaging device shown in the first embodiment in that the pixel signal is output in that it has two outputs instead of four outputs. The time required to output all the pixel signals is the same. This is because, in the solid-state imaging device shown in the first embodiment, the column selection signals S1 and S2 are output once in one cycle of the clock signals (H1 and H2), whereas the solid-state imaging in the present embodiment. This is because the device outputs the clock signal (H1, H2) twice in one cycle. As described above, the solid-state imaging device according to the present embodiment has substantially the same capability as the solid-state imaging device shown in the first embodiment as long as the clock pulses (H1 and H2) are the same speed.

  As described above, the solid-state imaging device according to the second embodiment is suitable for increasing the speed as in the first embodiment. In addition, since two pixel signals are output, the processing signal circuit in the subsequent stage only needs to include two A / D converters, and the circuit scale is smaller than when four A / D converters are provided. And cost reduction.

  In order to process the output signal of the solid-state imaging device shown in FIG. 6 by a conventional signal processing circuit that does not include two A / D converters, the configuration shown in FIG. 4 may be provided. However, since the pixel signals are output two by two instead of by four, the operation timing is different from that in FIG.

  FIG. 13 is a time chart for explaining the operation when the signal holding circuit shown in FIG. 4 is provided in the subsequent stage of the solid-state imaging device of FIG.

A description will be given of the unit pixels A11, B11, C11, and D11 in the unit pixel group as an example in the signal holding circuit.
The output signals Aout and Bout (overlapped in the figure) are sampled by the S / H circuits 13a and 13b at the start of the period T1, and the signal voltage values are held until the start of the period T2. The output signals Cout and Dout (overlapped in FIG. 7) are sampled by the S / H circuits 13c and 13d at the start of the period T3, respectively, and the signal voltage values are held until the start of the period T4.

  Output signals ha and hb (shown in an overlapped manner in FIG. 7) of the S / H circuits 13a and 13b are output to the period multiplexer 14 which is twice the period T1. Further, the output signals hc and hd of the S / H circuits 13c and 13k (overlapped in FIG. 7) are also output to the period multiplexer 14 which is twice the period T3.

  The output signal Mout of the multiplexer 14 outputs the two parallel output signals ha and hb1 one by one continuously by applying the selection signal at the timing of 34, 35 (dotted ellipse inner arrow line). The output signals hc and hd are continuously output one by one.

In this way, a signal processing circuit having only one A / D converter in the subsequent stage of the solid-state imaging device can be used.
Further, a camera capable of operating at high speed can be realized by mounting the solid-state imaging device according to Embodiment 1 or 2 on the camera.

  The present invention is suitable for a MOS type solid-state imaging device used for a digital camera or the like, specifically, for a built-in camera of a mobile phone, a digital still camera, a camera unit connected to an information processing device, or the like. Yes.

It is a block diagram which shows the structure of the principal part of the solid-state imaging device in Embodiment 1 of this invention. It is a figure which shows the timing of the output signal of a solid-state imaging device. It is a block diagram which shows the structural example of the unit switching circuit in a pixel signal switching part, and the unit output circuit in an output part. It is a block diagram which shows the structure of the signal holding circuit provided in the back | latter stage of a solid-state imaging device and corresponded to the input part of a signal processing circuit. It is a time chart explaining operation | movement of a signal holding circuit. It is a block diagram which shows the structure of the principal part of the solid-state imaging device in Embodiment 2 of this invention. It is a figure which shows the output timing of the pixel signal of a solid-state imaging device. It is a block diagram which shows the structure of a unit switching circuit and a unit output circuit. It is a block diagram which shows the structure of a unit switching circuit and a unit output circuit. It is a time chart which shows the various timing signals output by a timing generation circuit. It is a circuit diagram which shows the specific example of the timing generation circuit which produces | generates a column selection signal. (A) (b) It is a figure which shows the operation timing of the timing generation circuit 22. FIG. FIG. 5 is a time chart for explaining the operation of the signal holding circuit. It is a block diagram which shows the structure of the principal part of the conventional solid-state imaging device. The pixel signal finally output from the conventional amplifier and simultaneous processing circuit is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Unit pixel 2 Imaging part 3 Unit pixel group 4 Column selection signal line 5 Row selection signal line 6 Row scanning circuit 7 Timing generation circuit 8 Pixel signal switching part 9 Output part SW1, SW2 Switch 13a-13d, 14a-14d S / H Circuit 14 Multiplexer 15 A / D converter 17 Timing generation circuit 18 Pixel signal switching unit 19 Output unit 20 Pixel signal switching unit 21 Output unit 22 Timing generation circuit 81, 82, 181, 182, 201 Unit switching circuit 91, 191, 211 Unit Output circuit

Claims (9)

A solid-state imaging device including an imaging unit having a plurality of color pixel units that are provided in a matrix and perform photoelectric conversion,
A solid-state imaging device that outputs a pixel signal that constitutes a group of pixels composed of a plurality of color pixel portions corresponding to one pixel in an image. The solid-state imaging device according to claim 1, wherein the pixel group corresponds to four pixel units extending over two adjacent rows and two columns. The solid-state imaging device
Driving means for outputting a driving signal for selecting a row and a column;
Two rows of memory elements for temporarily holding pixel signals;
Switching means for holding each pixel signal in the pixel group in the memory element by switching the connection between the column signal line for outputting the pixel signal from the imaging unit and the memory element;
The solid-state imaging device according to claim 2, further comprising: an output unit that outputs a pixel signal held in a memory element in units of the pixel group. The driving means sequentially outputs a column selection signal in units of two columns,
The solid-state imaging device according to claim 3, wherein the switching unit sequentially switches the connection so that the memory element holds two pixels located in two rows from each of two columns corresponding to the column selection signal. The solid-state imaging device according to claim 4, wherein the output unit simultaneously outputs four pixel signals constituting the pixel group in synchronization with a column selection signal. The solid-state imaging device according to claim 4, wherein the output unit outputs two pixel signals constituting the pixel group in synchronization with a column selection signal. The solid-state imaging device further includes:
A sample hold circuit for holding each of the pixel signals output from the output means;
The solid-state imaging device according to claim 4, further comprising: a multiplexer that multiplexes the pixel signals held in the sample hold circuit. A plurality of color pixel units that are provided in a matrix and perform photoelectric conversion, a drive unit that outputs a drive signal for selecting a row and a column, a memory element for two rows for temporarily holding the pixel signal, and imaging A driving method of a solid-state imaging device including an imaging unit having a column signal line that outputs a pixel signal from the unit and a switching unit that switches connection between the memory elements,
With respect to four pixels in two rows and two columns, a step of holding two pixel signals read from one row in two columns by driving of the driving unit in two memory elements, and the two columns and the other two in the switching unit Switching to connect the memory element;
Holding two pixel signals read from the other one row in the two columns by driving the driving unit in the other two memory elements;
And a step of outputting pixel signals for four pixels held in the four memory elements. A camera provided with the solid-state imaging device according to claim 1.

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