JP2005039615A - Programmable transmission packet data extracting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet data extracting circuit capable of extracting data at any position in a packet. <P>SOLUTION: The packet data extracting circuit comprises a program accumulating means for accumulating a program describing the position of data to be extracted from a packet, a command interpreting means for interpreting program commands read from the program accumulating means, and a data extracting means for extracting data from an input packet according to the commands interpreted by the command interpreting means. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a hardware circuit necessary for a network node device that extracts data stored at an arbitrary position in a packet flowing on a network for packet communication and thereby determines handling of the packet in the network. About.

  Since the advent of the Internet, computer networks have exchanged data using IP (Internet Protocol). What is mainly used today is what is called IPv4. The extension version of IPv6 is also being promoted. Conventionally, a network node device such as a router has been able to fulfill its role simply by performing packet processing with reference to an IP address. There is a need to perform packet processing with reference (application filter, etc.).

  The format of application data is rarely standardized and diverse. Therefore, in order to respond to individual applications, it is necessary to extract data at an arbitrary place in the packet.

  However, conventionally, a data extraction circuit is fixedly designed according to a standardized packet header structure and a data structure in a packet payload whose structure is clear in advance, and a node device such as a router is configured using the data extraction circuit. . Therefore, data at an arbitrary location in the packet cannot be extracted.

  Here, by using a general-purpose CPU and its program, it is possible to realize a packet information extraction function that can be programmed so as to extract data at an arbitrary place in a packet. However, since the general-purpose CPU realizes its operation by a program, it is difficult to guarantee the end time. If the end time cannot be guaranteed, the processing time when the packets arrive continuously cannot be ensured and packet loss occurs.

  As a conventional packet information extraction circuit, there are techniques disclosed in Patent Document 1 and Patent Document 2, for example.

  The information relay apparatus disclosed in Patent Document 1 is intended to efficiently provide a router function specialized for IPv6, and performs packet information extraction dedicated to IPv6. Therefore, it is difficult to respond flexibly to other protocols and to applications. The packet switching device disclosed in Patent Document 2 is a node device combined with a CPU, and aims to reduce the transfer time of blocking packets between the CPUs. Since packet information is extracted by the CPU, it is difficult to ensure the performance to guarantee the line speed.

JP 2002-77262 A

Japanese Patent Laid-Open No. 10-173704

  The present invention has been made in view of the above points, and a node device capable of realizing network services according to various applications by extracting data in the packet flexibly according to various applications that generate packets. An object of the present invention is to provide a packet data extraction circuit for constructing the above.

  The above-described problem is a packet data extraction circuit for extracting data at an arbitrary position in a packet from a communication packet, the program storing means for storing a program describing the position of the data extracted from the packet, and program storage This can be solved by a packet data extraction circuit having instruction interpretation means for interpreting a program instruction read from the means and data extraction means for extracting data from the input packet in accordance with the instruction interpreted by the instruction interpretation means.

  According to this packet data extraction circuit, data is extracted from the input packet by a program describing the position of data extracted from the packet stored in the program storage means, so that the extraction position can be arbitrarily changed by changing the program. It is possible to extract data in the packet flexibly according to the application.

  The instructions of the program include a movement instruction in a predetermined data unit in the packet, a data extraction instruction from at least one data unit location continuous from the movement position, and an extraction operation end instruction.

  The packet data extraction circuit further includes first extraction position storage means for storing the extraction position of the data unit in the packet in accordance with an instruction of the program, and the data extraction means stores the packet in the data unit. Is temporarily stored, and data extraction is performed when the position in the packet of the data stored by the data extraction means matches the position indicated by the first extraction position storage means.

  Further, the packet data extraction circuit has second extraction position storage means for storing data extraction positions in the data unit data according to instructions of the program, and the data extraction means includes the second extraction position. Data extraction within the data unit is performed according to the data extraction position output from the storage means.

  The packet data extraction circuit further includes an address designating unit for designating a program reading position from the program storage unit, stores a plurality of programs in the program storage unit, and a plurality of programs are stored by the address designating unit. By selecting a program by designating the start head position of one of the programs, the program can be arbitrarily changed among a plurality of programs.

  Furthermore, the program can be changed by having a program change means for changing the program stored in the program storage means.

  According to the present invention, a packet data extraction circuit for configuring a node device capable of realizing a network service according to various applications by flexibly extracting data in the packet according to various applications that generate packets. Can be provided.

  FIG. 1 shows a schematic configuration of a circuit according to an embodiment of the present invention. As shown in FIG. 1, the circuit according to the present embodiment includes a program storage unit 1, a program reading unit 2, an instruction interpretation unit 3, a data extraction unit 4, an extraction data storage unit 5, and a program change unit 6. Each of these means is constituted by hardware.

  In the figure, reference numeral 7 is a program read signal sent from the program read means 2 to the program storage means 1. This program read signal is, for example, an address of a semiconductor memory that is one of means for realizing the program storage means 1. Reference numeral 8 denotes one program instruction output from the program storage means 1 in association with the program read signal 7. Reference numeral 9 denotes information on the instruction 8 temporarily stored in the program reading means 2. Reference numeral 10 denotes a signal necessary for the data extraction means 4 to execute the contents of the instruction 9 interpreted by the instruction interpretation means 3.

  11 indicates the flow of input packets, and 12 indicates the flow of output packets. Information 13 is sequentially extracted from the input packet 11 in accordance with the signal 10. Reference numeral 14 denotes data obtained by collectively storing one packet of extracted data from the data extracting means 4 in the extracted data accumulating means 5.

  Reference numeral 15 denotes a data flow for externally changing the data extraction program stored in the program storage means 1 via the program change means 6, and 16 denotes a flow of data exchange with the outside for program change. . The general operation of this circuit is as follows.

  From one packet that is input to the data extraction means 4 as an input packet 11 and output as an output packet 12, data at an arbitrary position in the packet including the header is obtained in accordance with the program stored in the program storage means 1. The extraction unit 4 extracts the data, and the extracted data storage unit 5 stores the extracted data for one packet. After the extraction is completed, the extraction data storage unit 5 outputs the extracted data. The extraction position of the in-packet data is determined by the program stored in the program changing means 1. Further, the program stored in the program changing means 1 can be changed, whereby the extraction position of the in-packet data can be arbitrarily changed.

  Next, the circuit of this embodiment will be described in more detail.

  FIG. 2 shows a configuration at a mounting level, which is a more detailed configuration of the circuit according to the present embodiment. The circuit shown in FIG. 2 includes a program storage unit 20 composed of memory elements, an address counter 21 that generates an address of the program storage unit 20, an instruction interpretation unit 22 that interprets one instruction of a program output from the program storage unit 20, and a command Extraction position storage means 23 for temporarily storing the extracted position information in the word output by the interpretation means 22, a packet position counter 24 for indicating the position in the extracted packet in word units, and an in-packet extraction position for storing the extraction target position in word units The counter 25, the comparator 26 for detecting the coincidence portion of the packet position counter 24 and the in-packet extraction position counter 25, the operation suppressor 27 for suppressing the output of the extraction position storage means 23 by the output of the comparator 26, Packet information extraction means 28 to extract, the extracted data for one packet The extracted information storage means 29 to be loaded, the program change means 30 for changing the contents of the program storage means 20, and the head of the program for selecting which of the plurality of extraction programs stored in the program storage means 20 is to be used A start address changing unit 31 is provided. Further, the packet information extracting means 28 has extracted packet word storage means for temporarily storing the extraction target packet in units of words.

  In the figure, reference numeral 32 indicates an address flow of the program storage means 20, and 33 indicates a data output flow from the program storage means 20. Reference numeral 34 denotes a flow of a signal for advancing the value of the address counter 21, 35 denotes a flow of extracted position information in a word in the data 33 temporarily stored in the instruction interpretation unit 22, and 36 denotes a temporary transfer to the instruction interpretation unit 22. The flow of the extraction position of the word unit in the accumulate | stored packet is shown. Reference numeral 37 denotes a flow of extraction positions in the word output from the extraction position storage means 23, and 38 denotes a flow of packet position information in units of words output from the packet position counter 24. Reference numeral 39 denotes the flow of the extraction position in the packet in units of words output from the extraction position counter 25 in the packet. Reference numeral 40 denotes a signal flow for advancing the packet position counter of the packet position counter 24. The packet position counter 24 is reset when a packet arrives at the packet information extraction means 28.

  Reference numeral 41 denotes a signal flow for outputting the extracted position information 37 in the word via the operation restrictor 27 when the position 38 of the word unit in the extraction target packet matches the extracted position 39. Reference numeral 42 denotes a flow of output from the operation restrictor 27, and 43 denotes a flow of in-packet information extracted by the packet information extraction means 28. Reference numeral 44 denotes a data flow for changing the program. Reference numeral 45 denotes a flow of extraction target packets, and 46 denotes a flow of packets output after passing through the packet information extraction means 28.

  Reference numeral 47 denotes a flow of extracted packet information stored in the extracted information storage means 29 collectively for one packet. Reference numeral 48 denotes a data flow for designating the execution start position of the extracted program stored in the program storage means 20 given from the outside. Indicates.

  FIG. 3 shows the configuration of instructions used in the packet information extraction program of this embodiment. The control instruction format 50 includes a data field 51, an instruction field 52, and a parameter field 53. The data field 51 is a field for the instruction interpreting means 22 shown in FIG. 2 to classify the instructions output from the program storage means 20 according to the counter value 32 into control instructions or extraction instructions. The command field 52 is a field for storing commands, and the parameter field 53 is a parameter field used by the commands stored in the command field 52. The format of the extraction instruction is as indicated by reference numeral 51.

  FIG. 4 shows an instruction system used in this embodiment. There are three types of instructions: a jump (JMP) instruction 60, a stop instruction 61, and an extraction instruction 62.

  The jump (JMP) instruction 60 is an instruction for moving the extraction position in units of words, and as a parameter, a relative value of the number of words to be moved is designated backward as a positive integer. The stop instruction 61 is an instruction for stopping the processing, and after this, data extraction is not performed and the arrival of the next packet is awaited. The extraction instruction 62 is an instruction for extracting data from the packet, and extracts a place where 1 is specified in the extraction instruction 62. In the present embodiment, a place where 1 is specified is extracted in units of bytes from the word at the extraction position.

  FIG. 5 shows an example of the contents of the program storage means 20 shown in FIG. Reference numeral 70 indicates the entire memory space of the program storage means 20. In the example of FIG. 5, a first extraction program 71, a second extraction program 72, and a third extraction program 73 exist in the memory space 70. The start address 1 (74) is the start address of the first extraction program 71, the start address 2 (75) is the start address of the second extraction program 72, and the start address 3 (76) is the third address. Extraction program 73. The number of programs that can be stored in the memory space 70 is determined by the total capacity of the memory space 70 and the size of each program. The head addresses 74, 75 and 76 are given from the outside as the address 48 input to the start address changing means 31 in FIG. 2 for the purpose of changing the extraction position for each packet.

  FIG. 6 shows an operation flowchart of the circuit shown in FIG. The operation will be described with reference to FIG.

  After the circuit is activated, it waits for packet arrival (step 1). When the packet arrives, the address counter 21, the packet position counter 24, and the in-packet extraction position counter 25 are initialized (step 2).

  Next, the instruction interpreting means 22 reads one line (one word) of the program from the address determined by the address counter 21 in the program storing means 20 (step 3), and judges the control instruction / extraction pattern (step 4).

  In the case of a control command, it is determined whether the command is STOP or JMP (step 5). If the instruction is STOP, the process returns to waiting for packet arrival.

  In the case of JMP, the offset value is added to the in-packet extraction position counter 25 (step 6), and the operation returns to the operation of reading the next program line.

  If the program is an extraction pattern in the determination of step 4, the extraction target determination is made by the comparator 26, and the word in the packet in the packet information extraction means 28 (the word at the position indicated by the packet position counter 24) is the extraction target. It is determined whether or not it is a word (step 7). If it is not the extraction target, the packet position counter 24 is added (step 8), and the process returns to the extraction target determination. When it is an extraction target (when the value of the packet position counter 24 = the extracted position counter 25 in the packet), data extraction is executed according to the pattern in the extracted word position storage means 23 (step 9), and the packet position counter 24, The in-packet extraction position counter 25 and the address counter 21 are added (step 10). It is determined whether or not the packet is finished (step 11). When the packet is finished, the process returns to waiting for arrival of the packet. If the packet has not ended, the program returns to reading one line.

  Next, a specific operation of the present embodiment will be described.

  FIG. 7 shows an example of the input packet 80 and the extraction program 83. In the figure, the black portion (81) in the input packet 80 indicates the extraction target byte data (8 bits) in the packet 80, and the white portion (82) indicates the non-extraction byte data (8 bits) in the packet 80. . The packet 80 is input to the packet information extraction unit 28 in a form in which 4 bytes are one word.

  The description indicated by reference numeral 83 is a program description for extracting the extraction target byte data at a plurality of positions in the packet 80 using the mechanism of FIG. Hereinafter, the program will be described step by step in accordance with the program execution order.

  Here, the extracted program 83 is stored at the seventh word from the head of the program storage means 20 of FIG. 2, and the start address of the program storage means 20 is designated as the start address at the input 48 of the start address changing means 31. And

  The program extraction command uses the lower 4 bits as the extraction position within one word. Also, 1 Bit means 1 byte extraction.

  When the packet 80 is input to the packet information extraction means 28, the packet position counter 24 is set to the first word position 0. The address counter 21 is set with the start address of the program.

  As a result, the head address is output to the program storage means 20 and the first word (84) of the program is output from the program storage means 20 to the instruction interpretation means 22. The instruction interpreting means 22 takes in the first word (84) of the program, interprets that the first word (84) of the program is a control instruction, a jump, and the parameter is 2, and sets the packet to an initial value 0. Parameter 2 is added to the inner extraction position counter 25. As a result, the value of the in-packet extraction position counter 25 becomes 2.

  Then, the packet information extraction unit 28 advances the input packet 80 by two words from the head. At this point, the instruction of the first word (84) of the program ends.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the head address + 1, and the instruction 85 of the second word of the extraction program 83 is output from the program storage means 20. The instruction interpreting means 22 determines that the instruction 85 is an extraction instruction, and extracts 1 part of “0010”, and outputs “0010” to the in-word extraction position storage means 23. Also, one in-packet extraction position counter 25 is added. At this time, the in-word extraction position accumulating means 23 stores “0010”. The packet position counter 24 stores a value “2”, and the in-packet extraction position counter 25 stores a value “3”. Here, since the in-packet extraction position counter 25 and the packet position counter 24 do not match, the signal 41 is not activated, and the output of the operation restrictor 27 is “0000”.

  Here, the packet information extraction means 28 reads one word from the packet 80 and adds one to the packet position counter 24. Then, the value of the packet position counter 24 becomes “3”, which coincides with the value of the in-packet extraction position counter 25, 41 is activated by the comparator 26, the operation restrictor 27 operates, and the packet information extraction means 28 37, the value “0010” is output.

  The packet information extraction unit 28 extracts data from the packet 80 in accordance with the output “0010” and outputs the data to the extraction information storage unit 29. The extraction information storage unit 29 stores the data. This completes 85 instructions.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the head address +2, and the instruction 86 in the third word of the extraction program 83 is output from the program storage means 20 to the instruction interpretation means 22. The instruction interpreting means 22 determines that the instruction 86 is an extraction instruction and extracts one part of “0011”, and outputs “0011” to the in-word extraction position storage means 23. Also, one in-packet extraction position counter 25 is added. At this time, the in-word extraction position accumulating means 23 stores “0011”. The packet position counter 24 stores a value “3”, and the in-packet extraction position counter 25 stores a value “4”. Here, since the in-packet extraction position counter 25 and the packet position counter 24 do not match, the signal 41 is not activated, and the output of the operation restrictor 27 is “0000”.

  Here, the packet information extraction means 28 reads one word from the packet 80 and adds one to the packet position counter 24. Then, the value of the packet position counter 24 becomes “4”, which coincides with the value of the in-packet extraction position counter 25, 41 is activated by the comparator 26, the operation restrictor 27 operates, and the packet information extraction means 28 37, the value “0011” is output.

  The packet information extraction unit 28 extracts data from the packet 80 in accordance with the output “0011”, and outputs the data to the extraction information storage unit 29. The extraction information storage unit 29 stores the data. This completes 86 instructions.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the head address +3, and the instruction 87 of the fourth word of the extraction program 83 is output from the program storage means 20 to the instruction interpretation means 22. The instruction interpreting means 22 judges that the instruction 87 is an extraction instruction, and extracts 1 part of “1110”, and outputs “1110” to the word storage means 23. Also, one in-packet extraction position counter 25 is added. At this time, the in-word extraction position storage means 23 stores “1110”. The packet position counter 24 stores a value “4”, and the in-packet extraction position counter 25 stores a value “5”. Here, since the in-packet extraction position counter 25 and the packet position counter 24 do not match, the signal 41 is not activated, and the output of the operation restrictor 27 is “0000”.

  Here, the packet information extraction means 28 reads one word from the packet 80 and adds one to the packet position counter 24. Then, the value of the packet position counter 24 becomes “5”, which coincides with the value of the in-packet extraction position counter 25, 41 is activated by the comparator 26, the operation restrictor 27 operates, and the packet information extraction means 28 In contrast, a value of “1110” of 37 is output.

  The packet information extraction unit 28 extracts data from the packet 80 in accordance with the output “1110” and outputs the data to the extraction information storage unit 29. The extraction information storage unit 29 stores the data. This completes 87 instructions.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the head address +4, and the instruction 88 of the fifth word of the extraction program 83 is output from the program storage means 20. The instruction interpreting means 22 takes in the instruction 88, interprets that the instruction 88 is a control instruction, a jump, and the parameter is 7, and sets the parameter 7 of the instruction 88 to the in-packet extraction position counter 25 which is currently “5”. Is added. The value of the in-packet extraction position counter 25 is 12. The packet information extraction means 28 advances the packet 80 by 7 words from the head. At this point, 88 instructions are complete.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the start address +5, and the instruction 89 of the sixth word of the extraction program 83 is output from the program storage means 20 to the instruction interpretation means 22. The instruction interpreting means 22 determines that the instruction 89 is an extraction instruction and extracts 1 part of “0101”, and outputs “0101” to the word storage means 23. Also, one in-packet extraction position counter 25 is added. At this time, the in-word extraction position accumulation means 23 stores “0101”. The packet position counter stores a value “12”, and the in-packet extraction position counter 25 stores a value “13”. Here, since the in-packet extraction position counter 25 and the packet position counter 24 do not match, the signal 41 is not activated, and the output of the operation restrictor 27 is “0000”.

  Here, the packet information extraction means 28 reads one word from the packet 80 and adds one to the packet position counter 24. Then, the value of the packet position counter 24 becomes “13”, which coincides with the value of the in-packet extraction position counter 25, 41 is activated by the comparator 26, the operation restrictor 27 operates, and the packet information extraction means 28 In contrast, a value “0101” of 37 is output.

  The packet information extraction unit 28 extracts data from the packet 80 in accordance with the output “0101” and outputs the data to the extraction information storage unit 29. The extraction information storage unit 29 stores the data. This completes 89 instructions.

  Next, the instruction interpreter 22 advances the address counter 21 by one. The address becomes the start address +6, and the instruction 90 in the seventh word of the extraction program 83 is output from the program storage means 20 to the instruction interpretation means 22. The instruction interpreting means 22 takes in the instruction 90, interprets that the instruction 90 is a control instruction and is a stop (STOP), outputs all the packets 80 via the packet information extracting means 28, and extracts the in-word extraction position. The storage means 23, the packet position counter 24, the in-packet extraction position counter 25, and the address counter 21 are initialized, and the next packet arrival is awaited.

  Next, the packet information extraction means 28 in the circuit of FIG. 2 will be described in more detail. FIG. 8 is a detailed configuration example of the packet information extraction means 28. The example shown in FIG. 8 is an example in which the packet information extraction means 28 is configured with a 4-byte (32-bit) width.

  As shown in FIG. 8, the packet information extraction means 28 includes selectors 281 to 284 for each byte. A shift register 285 is also provided.

  In response to the in-word extraction position instruction (4 bits), the selector duplicates and outputs the byte data to the shift register 285. The shift register 285 packs the Byte data from each selector in accordance with the in-word extraction position instruction so that no empty Byte is generated. If the shift register 285 is 4 bytes and all 4 bytes are extracted by the input word extraction position instruction, the shift register 285 operates in the same manner as a normal 4 byte register.

  When a specific Byte is an extraction target in the input word extraction position instruction (for example, when the word extraction position instruction is 0101), the part designated by 0 is shifted and filled with 1 part. That is, when the in-word extraction position instruction is 0101, a space of 2 bytes is created. When 2 bytes are extracted by the next input word extraction position instruction, the extracted data is transferred to the extraction information storage means 29 at that time. If the extracted data specified by the next input word extraction position instruction is 1 byte, there is 1 byte of space, so when the next extracted data in the next input word extraction position instruction becomes 1 byte or more, it is extracted. Data is transferred to the extracted information storage means.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

It is a figure which shows schematic structure of the data extraction circuit in embodiment of this invention.

It is a figure which shows the detailed structure of the data extraction circuit in embodiment of this invention.

It is a figure which shows the structure of the command in the packet information extraction program used with a data extraction circuit.

It is a figure which shows the command system in a packet information extraction program.

4 is a diagram illustrating an example of contents of a program storage unit 20. FIG.

It is an operation | movement flowchart of the data extraction circuit of embodiment of this invention.

It is a figure which shows an example of the input packet 80 and the extraction program 83.

3 is a detailed configuration example of a packet information extraction unit 28.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Program storage means 2 Program reading means 3 Instruction interpretation means 4 Data extraction means 5 Extracted data storage means 6 Program change means 20 Program storage means 21 Address counter 22 Instruction interpretation means 23 Extraction position storage means 24 Packet position counter 25 Extraction position in packet Counter 26 Comparator 27 Operation suppressor 28 Packet information extraction means 29 Extracted information storage means 30 Program change means 31 Start address change means 281 to 284 Selector 285 Shift register

Claims (6)

A packet data extraction circuit for extracting data at an arbitrary position in a packet from a communication packet,
Program storage means for storing a program describing the position of data extracted from a packet;
Instruction interpreting means for interpreting program instructions read from the program storage means;
And a data extraction means for extracting data from the input packet in accordance with the instruction interpreted by the instruction interpretation means.   The instruction of the program includes an instruction to move in a predetermined data unit in a packet, an instruction to extract data from at least one location of the data unit continuous from the moving position, and an instruction to end extraction operation. The packet data extraction circuit described. The packet data extraction circuit further includes first extraction position storage means for storing extraction positions of predetermined data units in the packet in accordance with instructions of the program,
The data extraction means temporarily stores the data of the packet in the data unit, and the position in the packet of the data stored by the data extraction means matches the position indicated by the first extraction position storage means The packet data extraction circuit according to claim 1, wherein data extraction is performed in the event of a failure. The packet data extraction circuit has second extraction position storage means for storing a data extraction position in the data of the data unit according to an instruction of the program,
4. The packet data extraction circuit according to claim 3, wherein the data extraction unit extracts data in the data unit in accordance with a data extraction position output from the second extraction position storage unit. The packet data extraction circuit further includes address designating means for designating a program reading position from the program storage means,
2. The packet data extraction circuit according to claim 1, wherein a plurality of programs are stored in the program storage means, and a program is selected by designating a start head position of one of the plurality of programs by the address designation means. 2. The packet data extraction circuit according to claim 1, further comprising program changing means for changing a program stored in the program storing means.

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