JP2005039006A - Interposer substrate, interposer substrate with semiconductor device, package with interposer substrate, structure consisting of semiconductor device, interposer substrate and package, and method of manufacturing interposer substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To build up a substrate for making an IC chip compromise with an IC package, focusing attention on a difference in role between each interconnection owned by the IC package, and to stabilize electrical propagation between the IC chip and the IC package via each interconnection. <P>SOLUTION: A main body of the interposer substrate 10 comprises a capacitor 11 wherein a multilayer ceramic capacitor 12 which has a ceramic layer 14 between internal electrodes 13 is arranged, and a section 20 having a low dielectric constant which is formed of a material having a lower dielectric constant than that of the ceramic layer 14. The capacitor 12 has many via electrodes 15 in a passing-through structure having a conductivity path established between the internal electrodes 13 and themselves. The via electrodes 15 are used as power lines and ground lines to the IC chip 30. The section 20 having a low dielectric constant is equipped with columnar electrodes 22 which are extended through the section 20 having a low dielectric constant without any contact with the ceramic layer 14. The columnar electrodes 22 are used as signal lines to the IC chip 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a relay substrate having a wiring interposed between a semiconductor element and a package in which the semiconductor element is housed, and electrically connecting the semiconductor element and the package.
[0002]
[Prior art]
In semiconductor elements, circuit elements such as transistors and resistors are formed on a small silicon chip (hereinafter, such a chip is referred to as an IC chip). Due to advances in integrated circuit technology in recent years, semiconductor devices have been increasingly integrated with LSI (Large Scale Integration), VLSI (Very Large Scale Integration), and ULSI (Ultra Large Scale Integration), and the operation of IC chips is also increasing. Increasingly faster.
[0003]
The IC chip is mounted on a wiring board on which wiring such as power supply lines and ground lines for supplying power and various signal lines for data transmission / reception and flow control are drawn. A wiring board on which an IC chip is mounted (hereinafter referred to as a mounting board) is connected to a printed board such as a mother board. The IC chip operates by receiving supply of power from a power supply terminal provided on the printed circuit board via the power supply line. In recent years, a form in which an IC chip is encapsulated in a package having the above wiring (hereinafter referred to as an IC package) has been adopted as one form of the mounting substrate. This IC package is usually made of plastic. By adopting such an IC package, the IC chip can be appropriately protected from the external environment, the IC chip can be easily mounted and handled, and the heat generated by the operation of the IC chip can be effectively radiated.
[0004]
On the other hand, with respect to a method for connecting a mounting board such as an IC package and a printed board, a technique for connecting the mounting board and the printed board via a relay board called an interposer has been proposed (for example, (See Patent Document 1).
[Patent Document 1]
JP 2000-208661 A
[0005]
[Problems to be solved by the invention]
However, there has been no proposal for a structure in which a relay substrate is interposed between an IC chip and a wiring substrate such as an IC package.
[0006]
In view of the above, the present invention is configured such that the relay substrate between the IC chip and the IC package is configured by paying attention to the difference in the role of each wiring included in the IC package, and the electrical connection between the IC chip and the IC package through each wiring. The following configuration was adopted for the purpose of making stable propagation stable.
[0007]
[Means for solving the problems and their functions and effects]
The relay board of the present invention is
A relay board having a wiring interposed between a semiconductor element and a package to which the semiconductor element is mounted, and electrically connecting the semiconductor element and the package;
A capacitor portion in which a capacitor having a dielectric is disposed between the electrode plates;
A low dielectric constant portion formed of a material having a relative dielectric constant lower than that of the dielectric;
With
The low dielectric constant portion is provided around at least a part of the signal line of the wiring.
Is the gist.
[0008]
The relay substrate according to the invention includes a capacitor portion in which a capacitor having a dielectric is disposed between electrode plates, and a low dielectric constant portion formed of a material having a relative dielectric constant (for example, 15 or less) lower than the dielectric. With. The low dielectric constant portion is provided around at least a part of the signal line in the wiring that electrically connects the semiconductor element and the package. As a result, the contact range of the signal lines with the dielectric can be reduced, and capacitive coupling between the signal lines can be prevented. Therefore, according to the relay board of the present invention, it is possible to prevent erroneous signal exchange between the semiconductor element and the package, and stable electrical propagation between the semiconductor element and the package through the signal line is possible. Can be made.
[0009]
A via electrode penetrating through the capacitor and connected to one of the electrode plates serving as a positive electrode and a negative electrode of the capacitor, and at least a part of the via electrode is used as a power source for the semiconductor element in the wiring It is also preferable to use a wire or a ground wire. In this way, the via electrode is directly connected to the semiconductor element as a power supply line and a ground line to the semiconductor element, so that the impedance is smaller than in the conventional case, and the responsiveness when supplying power to the semiconductor element is improved. As a result, even when the semiconductor element consumes power suddenly due to its high-speed operation, power suitable for consumption is immediately supplied by the capacitor. Therefore, the voltage of the power source supplied to the semiconductor element can be stably maintained regardless of the operating state of the semiconductor element, and abnormal operation of the semiconductor element due to power shortage can be prevented. For example, when a capacitor is connected to a power supply terminal or a ground terminal of a package in which a semiconductor element is enclosed, a sudden current change caused by the operation of the semiconductor element may occur before the package side terminal or Although obstructed by the impedance component of the wiring to the semiconductor element, the voltage of the power source supplied to the semiconductor element may drop (sufficient current does not flow to the semiconductor element). According to the relay board, the occurrence of such a situation can be suppressed.
[0010]
A configuration may be adopted in which the low dielectric constant portion is provided for each signal line. It is also preferable to form the low dielectric constant portion in a range surrounding the capacitor portion. In semiconductor elements and packages, power lines and ground lines are often provided in the inner area, and signal lines are often provided in the outer area. Therefore, it is possible to provide a relay board suitable for the wiring form of the semiconductor element and the package, and the versatility of the relay board can be improved.
[0011]
It is also possible to adopt a form in which a semiconductor element and a package are mounted in advance on the relay board. As such a form, a relay board with a semiconductor element in which a semiconductor element is connected to the wiring of the relay board, a package with a relay board in which a package is connected to the wiring of the relay board, and a semiconductor element through the relay board A structure or the like formed by connecting a package and a package can be considered.
[0012]
The manufacturing method of the relay board of the present invention is as follows:
A method of manufacturing a relay substrate having a wiring interposed between a semiconductor element and a package in which the semiconductor element is housed, and electrically connecting the semiconductor element and the package,
(A) providing a low dielectric constant portion using a substance having a relative dielectric constant lower than that of the dielectric in a region connected to the capacitor portion where a capacitor having a dielectric is provided between the electrode plates;
(B) providing a signal line of the wiring in the low dielectric constant portion without contacting the dielectric;
(C) providing the capacitor having a via electrode connected to one of the electrode plates serving as a positive electrode and a negative electrode as a power supply line and a ground line for the semiconductor element of the wiring in a capacitor unit;
The main point is that
[0013]
In the method for manufacturing a relay substrate according to the invention, a substance having a relative dielectric constant lower than that of the dielectric is used in a region connected to the capacitor portion in which the capacitor having a dielectric is provided between the electrodes in step (a). A low dielectric constant part is provided. Subsequently, in the step (b), a signal line among wirings for electrically connecting the semiconductor element and the package is provided in the low dielectric constant portion without being in contact with the dielectric. Subsequently, in step (c), the via electrode connected to one of the positive and negative electrodes is connected to the power supply line to the semiconductor element in the wiring for electrically connecting the semiconductor element and the package, and the ground. A capacitor provided as a wire is provided in the capacitor portion. Therefore, it is possible to manufacture a relay substrate in which electrical propagation between the semiconductor element and the package through the signal line, the power supply line, and the ground line is stable. In addition, the process order of each process (a)-(c) is not restricted to the order of said process (a), process (b), and process (c), It can replace suitably according to manufacturing conditions etc.
[0014]
It is also preferable that the step (c) is a step of forming the capacitor in the capacitor portion by forming the capacitor integrally with the low dielectric constant portion. In this way, in a plurality of manufactured relay boards, it becomes easy to keep the positional relationship between the power supply line and ground line provided in the capacitor portion and the signal line provided in the low dielectric constant portion substantially constant. The reliability of the connection can be increased.
[0015]
The step (c) may be a step of providing the capacitor in the capacitor portion by fitting the capacitor formed in advance into the capacitor portion. In this way, it is possible to separately manufacture the substrate body including the low dielectric constant portion and the capacitor. Therefore, various relay boards can be provided by freely combining various capacitors and various board bodies. In this case, when the capacitor is fitted into the capacitor portion, a step of providing the capacitor portion with a position adjusting material for adjusting the position where the capacitor is fitted may be provided. In this way, in a plurality of manufactured relay boards, it becomes easy to keep the positional relationship between the power supply line and ground line provided in the capacitor portion and the signal line provided in the low dielectric constant portion substantially constant. The reliability of the connection can be increased.
[0016]
In the step (a) or the step (b), the low dielectric constant portion and the signal line are provided by sequentially filling the substance and the signal line forming material in a through hole provided in the region. The step is also preferable in that the amount of a substance having a relative dielectric constant lower than that of the dielectric can be reduced.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In order to further clarify the configuration and operation of the present invention described above, embodiments of the present invention will be described in the following order.
A. Example
A-1. Configuration of relay board 10
A-2. Manufacturing process A of relay board 10
A-3. Manufacturing process B of relay board 10
A-4. Effect
B. Modified example
[0018]
A. Example:
A-1. Configuration of the relay board 10:
FIG. 1 is an explanatory view showing a connection structure of an IC package 60 using a relay board 10 according to an embodiment of the present invention. FIG. 2 is an explanatory view showing an arrow shape of a longitudinal section along line 2-2 in FIG. As shown in FIG. 1, the IC package 60 is configured by connecting an IC chip 30 and a package 50 via a relay substrate 10. FIG. 3 shows a state where the relay substrate 10 is attached to the package 50 before the IC chip 30 is attached.
[0019]
The IC chip 30 is a strip in which a large number of circuit elements such as transistors and resistors are formed on a single silicon substrate (wafer). The formed circuit elements are connected by a number of aluminum wirings. The aluminum wiring connected to the circuit element is drawn out to the lower surface of the IC chip 30 and connected to the pump-like pad 32. A large number of pads 32 are arranged in a lattice pattern on the lower surface of the IC chip 30 corresponding to the drawing position of the aluminum wiring.
[0020]
The package 50 is a container on which the relay substrate 10 with the IC chip 30 is mounted, and includes a lower layer 54 as an insulating layer on which the relay substrate 10 is disposed. In this embodiment, the lower layer 54 is formed using an epoxy resin. Of course, the lower layer 54 can be formed of other insulating materials (for example, a resin material other than epoxy resin or ceramic). In addition to the lower layer 54, an upper layer 52 may be provided as an insulating layer that covers the IC chip 30 and the relay substrate 10 arranged in the lower layer 54 (two points in FIGS. 1 and 2). See chain line). In this way, since the IC chip 30 and the relay substrate 10 are enclosed in the insulating layer, the IC chip 30 and the relay substrate 10 can be effectively protected from the outside.
[0021]
The lower layer 54 is formed by laminating a number of epoxy resin plate-like bodies having a rectangular shape. The respective layers of the lower layer 54 are electrically connected by leads 56 formed of a copper plating layer or a copper foil. The lead 56 includes a first terminal 57 exposed on the upper surface (upper surface in FIG. 2) of the lower layer 54 and a second terminal 58 exposed on the lower surface (lower surface in FIG. 2) of the lower layer 54. Prepare. The first terminals 57 are terminals connected to the relay substrate 10, and a large number of first terminals 57 are arranged in a lattice pattern on the upper surface of the lower layer 54. The second terminal 58 is connected to a terminal on the printed board side using solder when the assembled IC package 60 is mounted on a printed board (not shown) such as a mother board.
[0022]
The substrate body of the relay substrate 10 is composed of a capacitor portion 11 and a low dielectric constant portion 20. The capacitor unit 11 is an area where the multilayer ceramic capacitor 12 is disposed, and the upper surface 12 a and the lower surface 12 b of the multilayer ceramic capacitor 12 are directly exposed on the upper surface and the lower surface of the capacitor unit 11.
[0023]
The multilayer ceramic capacitor 12 includes a ceramic layer 14 as a dielectric between internal electrodes 13 functioning as electrode plates, and a structure in which a large number of these ceramic layers 14 and internal electrodes 13 are alternately stacked (hereinafter referred to as a multilayer structure). Have For this reason, each ceramic layer 14 is sandwiched between the two internal electrodes 13. In this embodiment, barium titanate (BaTiO 3), which is a material having a relatively high dielectric constant (2000 or more), is used as a material for forming the ceramic layer 14.
[0024]
Each internal electrode 13 is electrically connected to a via electrode 15 connected to an external power source, circuit, etc. every other layer. The via electrode 15 has a shape penetrating from the upper surface 12a to the lower surface 12b of the multilayer ceramic capacitor 12, and a plurality of via electrodes 15 are formed at predetermined intervals.
[0025]
In this way, the internal electrodes 13 are alternately stacked in the dielectric, and the internal electrodes 13 are connected to the via electrodes 15, thereby forming the multilayer ceramic capacitor 12. In the multilayer ceramic capacitor 12 having such a multilayer structure, a large number of portions where charges are accumulated are formed hierarchically, so that a small and large capacitance can be realized.
[0026]
As shown in FIG. 3, the low dielectric constant portion 20 is in a range that surrounds the outer periphery of the side portion of the capacitor portion 11 over the entire circumference, more specifically, a multilayer ceramic capacitor constituting the outer periphery of the side portion of the capacitor portion 11. 12 is formed in a range surrounding all of the four side surfaces 12c to 12f. The upper surface 20a and the lower surface 20b of the low dielectric constant portion 20 and the upper surface and the lower surface of the capacitor portion 11 (that is, the upper surface 12a and the lower surface 12b of the multilayer ceramic capacitor 12) are located on substantially the same plane. The low dielectric constant portion 20 is formed of alumina, which is a material having a relative dielectric constant lower than that of the material for forming the ceramic layer 14 (barium titanate).
[0027]
A large number of columnar electrodes 22 having a shape penetrating from the upper surface 20a to the lower surface 20b are formed in the low dielectric constant portion 20 at a predetermined interval. The low dielectric constant portion 20 is not formed with a barium titanate layer like the ceramic layer 14. For this reason, the columnar electrode 22 is not in contact with the barium titanate layer.
[0028]
In this embodiment, nickel is used as a material for forming the internal electrode 13, the via electrode 15, and the columnar electrode 22. In this embodiment, the internal electrode 13, the via electrode 15, and the columnar electrode 22 correspond to “wiring” in the claims.
[0029]
As shown in FIG. 3, the upper ends of the via electrodes 15 or the upper ends of the columnar electrodes 22 are arranged on the upper surface 12 a to the upper surface 20 a in a lattice shape substantially the same as the pads 32 of the IC chip 30. As shown in FIG. 2, bumps 16 and 23 made of solder are formed on the upper ends of the via electrodes 15 and the columnar electrodes 22 so as to protrude in a substantially hemispherical shape from the upper surface 12a and the upper surface 20a. Yes. On the lower surface 12b to the lower surface 20b, the lower end of the via electrode 15 or the lower end of the columnar electrode 22 is arranged in a lattice shape substantially the same as the first terminal 57 of the package 50. As shown in FIG. 2, solder bumps 17 and bumps 24 are formed at the lower ends of the via electrodes 15 and the columnar electrodes 22 in a shape protruding substantially hemispherically from the lower surface 12 b.
[0030]
As described above, the low dielectric constant portion 20 is formed in a range surrounding the capacitor portion 11. Therefore, the columnar electrodes 22 to the bumps 23 and 24 are arranged in the outer region (region near the outer peripheral side surface) of the relay substrate 10, and the via electrodes 15 to the bumps 16 and 17 are regions inside the outer region. (See FIG. 3).
[0031]
In the present embodiment, a large number of via electrodes 15 provided in the capacitor unit 11 are used as wirings for supplying driving power (voltage) to the IC chip 30. That is, of the via electrodes 15, the via electrode 15 connected to the internal electrode 13 serving as the positive electrode is used as a power supply line to the IC chip 30, and the via electrode 15 connected to the internal electrode 13 serving as the negative electrode is the IC chip 30. Used as a ground line to In the IC chip 30 thus supplied with power, various processes DM (for example, data transmission / reception and flow control) are executed. A number of columnar electrodes 22 provided in the low dielectric constant portion 20 are used as signal lines for transmitting electrical signals representing the contents of the processing DM.
[0032]
A-2. Manufacturing process A of the relay substrate 10:
The relay substrate 10 having the above configuration is manufactured through steps S100 to S195 by the manufacturing process A shown in FIG. The contents of each process will be described below in the order of the processes. In the following description, the relay substrate 10 will be described with reference to FIG.
[0033]
First, an alumina base sheet 89 is prepared, and a low dielectric layer 80a made of alumina is formed on the peripheral edge of the base sheet 89 (step S100 in FIG. 4, FIG. 5A). Next, a high dielectric layer 74a made of barium titanate having a relative dielectric constant of 2000 or more is formed in a range where the low dielectric layer 80a on the base sheet 89 is not formed, and a wiring pattern 73a is printed on the high dielectric layer 74a. (Steps S110 and S120 in FIG. 4, FIG. 5B).
[0034]
Next, the low dielectric layer 80b is formed on the low dielectric layer 80a (step S130), and the high dielectric layer 74b is formed on the high dielectric layer 74a on which the wiring pattern 73a is printed. A wiring pattern 73b is printed thereon (steps S140 and S150 in FIG. 4). By repeating such a process a predetermined number of times, as shown in FIG. 5C, the low dielectric layers 80 a to 80 e are laminated in the peripheral region of the base sheet 89, and in the region inside the peripheral edge of the base sheet 89. The high dielectric layer 74a, the wiring pattern 73a, the high dielectric layer 74b, the wiring pattern 73b, the high dielectric layer 74c, the wiring pattern 73a, the high dielectric layer 74d, the wiring pattern 73b, and the high dielectric layer 74e are laminated in this order ( Such a structure in which high dielectric layers and wiring patterns are alternately stacked is hereinafter referred to as a stacked body CS). Note that the thickness of each of the low dielectric layers 80a to 80e and each of the high dielectric layers 74a to 74e is such that the upper surface 20a and the lower surface 20b of the low dielectric constant portion 20 and the capacitor portion 11 in the relay substrate 10 formed after the firing process described later. The upper surface and the lower surface (that is, the upper surface 12a and the lower surface 12b of the multilayer ceramic capacitor 12) are positioned so as to be substantially in the same plane.
[0035]
Next, the through holes 82 are formed in the laminated low dielectric layers 80a to 80e, and the through holes 75 are formed in the laminated body CS (steps S160 and S170 in FIG. 4, FIG. 5D). The through hole 82 and the through hole 75 are formed at positions corresponding to the positions of the pads 32 arranged on the IC chip 30. The formation of the through hole 82 and the through hole 75 can be realized by laser irradiation or the like.
[0036]
Next, each through hole 82 and each through hole 75 are filled with a conductive material QM (in this embodiment, nickel) (step S180 in FIG. 4, FIG. 5E). Thereby, the columnar electrode 22 and the via electrode 15 described above are formed. The wiring patterns 73a and 73b are electrically connected to the via electrode 15 every other layer of the high dielectric layers 74a to 74e in each through hole 75. The wiring patterns 73a and 73b and the high dielectric layers 74a to 74e function as the internal electrode 13 and the ceramic layer 14 described above, respectively.
[0037]
Subsequently, after the base sheet 89 is peeled from the low dielectric layers 80a to 80e and the stacked body CS (step S185 in FIG. 4), the low dielectric layers 80a to 80e and the stacked body CS are pressure-bonded by a high temperature / high pressure press. The low dielectric layers 80a to 80e and the stacked body CS are degreased and then fired (step S190 in FIG. 4). Thus, the low dielectric layers 80a to 80e and the stacked body CS are fired in a state where the low dielectric layers 80a to 80e and the stacked body CS are in close contact with each other and the upper and lower high dielectric layers 74a to 74e are in close contact with each other. The
[0038]
Next, bumps 23 and 24 and bumps 16 and 17 are formed on the upper and lower ends of the columnar electrode 22 and the via electrode 15 formed by firing, so that the bumps 23 and 24 and the bumps 16 and 17 are formed (step S195 in FIG. 4). Thereby, the relay substrate 10 including the low dielectric constant portion 20 made of alumina is formed around the capacitor portion 11 as shown in FIG.
[0039]
In the manufacturing process A, the formation of the through holes 82 in the low dielectric layers 80a to 80e and the filling of the conductive material QM into the through holes 82 are performed after the low dielectric layers 80a to 80e are stacked. For each of the low dielectric layers 80a to 80e, through holes may be formed one by one or the conductive material QM may be filled in the through holes, and then the low dielectric layers 80a to 80e may be stacked. In the manufacturing process A, the base sheet 89 is peeled off and then fired. However, the base sheet 89 may be fired with the base sheet 89 attached, and the base sheet 89 may be scraped off after firing.
[0040]
A-3. Manufacturing process B of the relay substrate 10:
It is also possible to manufacture the relay substrate 10 having the above configuration by a process other than the manufacturing process A described above. An example of this is shown in FIG. 6 as a manufacturing process B including the steps S200 to S270. The contents of each process will be described below in the order of the processes. In the following description, the relay substrate 10 will be described with reference to FIG.
[0041]
First, the required number of low dielectric sheets 80p made of alumina are prepared, and a through hole 71p having a predetermined opening area is formed in the center of each low dielectric sheet 80p (steps S200 and S210 in FIG. 6, FIG. 7 (A)). Next, after a through hole 82 is formed in the low dielectric sheet 80p around the through hole 71p, the through hole 82 is filled with a conductive material QM (steps S220 and S230 in FIG. 6, FIG. 7B).
[0042]
Next, the low dielectric sheet 80p is laminated, and the plurality of laminated low dielectric sheets 80p are pressure-bonded by a high temperature / high pressure press (step S240 in FIG. 6, FIG. 7C). Thus, as shown in FIG. 7C, the conductive material QM in the through hole 82 is connected between the upper and lower low dielectric sheets 80p, and the columnar electrode 22 described above is formed by such connection. Also, a capacitor housing space PF is formed by the through holes 71p of the laminated low dielectric sheets 80p.
[0043]
Next, the low dielectric sheet 80p after pressure bonding is degreased and fired (step S250 in FIG. 6). As a result, a substrate body made of the low dielectric constant portion 20 made of alumina and having the space PF at the center thereof is formed. The space PF in the substrate body is the capacitor unit 11 described above.
[0044]
Next, the separately manufactured multilayer ceramic capacitor 12 is accommodated in the space PF of the substrate body (step S260 in FIG. 6, FIG. 7D). Note that the shape of the space PF in the substrate body after firing is determined according to the shape of the capacitor 12 so as to be substantially the same as the shape of the capacitor 12 accommodated in the space PF. Therefore, as shown in FIG. 7D, when the capacitor 12 is accommodated in the space PF, the capacitor 12 is fitted to the inner peripheral wall of the low dielectric constant portion 20 constituting the space PF with almost no gap. The upper surface 12a and the lower surface 12b of the low dielectric constant portion 20 and the upper surface 20a and the lower surface 20b of the low dielectric constant portion 20 are located on substantially the same plane. Thereby, the low dielectric constant part 20 and the multilayer ceramic capacitor 12 are integrated.
[0045]
Next, bumps 23 and 24 and bumps 16 and 17 are formed on the upper and lower ends of the columnar electrode 22 and the via electrode 15 by surface printing (step S270 in FIG. 6). Thereby, the relay substrate 10 including the low dielectric constant portion 20 made of alumina is formed around the capacitor portion 11 as shown in FIG.
[0046]
In the manufacturing process B, the formation of the through hole 82 in the low dielectric sheet 80p and the filling of the through hole 82 with the conductive material QM are performed for each low dielectric sheet 80p. It is good also as carrying out collectively after lamination | stacking. Further, a capacitor (for example, a single plate ceramic capacitor, a film capacitor, an aluminum electrolytic capacitor, etc.) other than the multilayer ceramic capacitor may be accommodated in the space PF of the substrate body.
[0047]
A-4. Effect:
As described above, in the relay substrate 10 of this embodiment, the substrate body has the capacitor portion 11 in which the multilayer ceramic capacitor 12 having the ceramic layer 14 using barium titanate as the dielectric is disposed between the internal electrodes 13. And a low dielectric constant portion 20 formed of a material (alumina) having a relative dielectric constant lower than that of barium titanate. The low dielectric constant portion 20 includes a large number of columnar electrodes 22 used as signal lines between the IC chip 30 and the package 50 in a form penetrating the low dielectric constant portion 20. Thereby, the entire circumference of the columnar electrode 22 is covered with the low dielectric constant portion 20, and the low dielectric constant portion 20 is provided around the columnar electrode 22. For this reason, the columnar electrode 22 as a signal line does not contact the ceramic layer 14 as a dielectric, and capacitive coupling between the columnar electrodes 22 can be prevented. Therefore, according to the relay substrate 10 of the present embodiment, it is possible to prevent erroneous signal exchange between the IC chip 30 and the package 50, and between the IC chip 30 and the package 50 through the signal line. Electrical propagation can be made stable.
[0048]
Further, in the relay substrate 10 of the present embodiment, the capacitor 12 disposed in the capacitor unit 11 uses a large number of via electrodes 15 conducted to the internal electrode 13 as power supply lines and ground lines to the IC chip 30. 12 in a shape penetrating the inside. As a result, the via electrode 15 connected to the internal electrode 13 serving as the positive electrode and the negative electrode is directly connected to the IC chip 30 as a power supply line and a ground line to the IC chip 30, respectively. Thus, the response when supplying power to the IC chip 30 is improved. Therefore, even when the IC chip 30 rapidly consumes power due to its high-speed operation, the power corresponding to the consumption is immediately supplied by the capacitor 12. Therefore, the voltage of the power source supplied to the IC chip 30 can be stably maintained regardless of the operating state of the IC chip 30, and abnormal operation of the IC chip 30 due to power shortage can be prevented. For example, when a capacitor is connected to the power supply terminal and ground terminal of an IC package in which an IC chip is encapsulated, a sudden current change caused by the operation of the IC chip reaches the capacitor side before reaching the capacitor. Although it is hindered by the impedance component of the lead wire to the terminal and the IC chip, this may cause a situation where the voltage of the power source supplied to the IC chip drops (sufficient current does not flow to the IC chip). According to the relay board 10 of this embodiment, the occurrence of such a situation can be suppressed.
[0049]
In addition, since the low dielectric constant portion 20 is formed in the range surrounding the capacitor portion 11 in the relay substrate 10 of the present embodiment, it is possible to provide the relay substrate 10 suitable for the wiring form of the IC chip 30 and the package 50. The versatility of the relay substrate 10 can be improved. This is because the IC chip and its package are often provided with a power supply line and a ground line in the inner region and a signal line in the outer region.
[0050]
Further, when the relay substrate 10 is manufactured by the manufacturing process A (FIG. 4), the multilayer ceramic capacitor 12 is formed integrally with the low dielectric constant portion 20, whereby the capacitor 12 is provided in the capacitor portion 11. . For this reason, in the manufactured plurality of relay boards 10, the positional relationship between the power supply line and ground line (via electrode 15) provided in the capacitor unit 11 and the signal line (columnar electrode 22) provided in the low dielectric constant unit 20 is determined. It becomes easy to keep almost constant, and the reliability of connection with the IC chip 30 and the package 50 can be improved.
[0051]
Further, when the relay substrate 10 is manufactured by the manufacturing process B (FIG. 6), the multilayer ceramic capacitor 12 manufactured separately is fitted into the space PF of the substrate body made of the low dielectric constant portion 20 to obtain the capacitor. A capacitor 12 is provided in the part 11. This makes it possible to separately manufacture the low dielectric constant portion 20 and the capacitor 12 as the substrate body. Therefore, various relay boards 10 can be provided by freely combining various capacitors having different shapes and characteristics and the low dielectric constant portions 20 having various space PF shapes.
[0052]
B. Variation:
As mentioned above, although embodiment of this invention was described using the Example, this invention is not restricted to the said Example, It is possible to implement in a various aspect in the range which does not deviate from the summary.
[0053]
For example, in the manufacturing process B described above, the capacitor 12 is formed with an external shape such that the horizontal cross-sectional area thereof is slightly smaller than the space PF of the low dielectric constant portion 20, and the produced capacitor is formed with a low dielectric constant. A step of inserting a filler into a gap formed between the capacitor and the low dielectric constant portion 20 when fitting into the space PF of the portion 20 may be provided. The relay board 110 manufactured through such processes is shown in FIG. 8 as a first modification. FIGS. 8A and 8B show a relay board 110 as a first modified example, corresponding to FIGS. 3 and 2, respectively. In the following description of each modification, for each part common to the above embodiment, the tens place or less of the reference numeral is expressed using the same numerals or letters as in the embodiment.
[0054]
As shown in FIG. 8, a filler 190 is inserted in the gap between the low dielectric constant portion 20 and the multilayer ceramic capacitor 112. The filler 190 is formed by filling the above gap with a paste-like resin material and curing it. By this curing, the low dielectric constant portion 120 and the multilayer ceramic capacitor 112 are integrated. By adopting such a manufacturing method, the position where the capacitor 112 is fitted in the space PF (capacitor portion 111) of the low dielectric constant portion 120 can be finely adjusted. Therefore, in the manufactured plurality of relay substrates 110, the positional relationship between the via electrode 115 (power supply line, ground line) provided in the capacitor part 111 and the columnar electrode 122 (signal line) provided in the low dielectric constant part 120 is almost the same. It becomes easy to keep constant, and the reliability of connection with the IC chip 130 and the package 150 can be improved. Further, the filler 190 made of resin is interposed between the capacitor part 111 made of barium titanate and the low dielectric constant part 120 made of alumina, so that the mechanical strength of the relay substrate 110 is increased by the elasticity of the filler 190. be able to.
[0055]
In the relay substrate 10 of the above embodiment, the columnar electrode 22 is provided in a shape that penetrates almost linearly from the upper surface 20 a to the lower surface 20 b of the low dielectric constant portion 20. It is also possible to adopt. For example, the pitch at which the columnar electrode 22 is separated from the capacitor unit 11 may be configured to vary depending on the height position of the columnar electrode 22. FIG. 9 shows a part of the process of manufacturing the relay substrate having such a configuration as a second modification example of the manufacturing process B. In the second modification, the through hole 82 is formed in the low dielectric sheet 80p so that the distance from the through hole 71p to the through hole 82 is different for each low dielectric sheet 80p in the process of step S220 in FIG. After the wiring layer 92 for connecting between the through holes is printed on each low dielectric sheet 80p, the through hole 82 is filled with the conductive material QM, and the low dielectric sheet 80p is laminated. The wiring layer 92 is formed in a range that covers from the through hole 82 of the low dielectric sheet 80p to be printed to the through hole 82 of the low dielectric sheet 80p to be laminated next. As a result, the through holes 82 of the upper and lower low dielectric sheets 80p are conducted through the wiring layer 92. According to the relay board manufactured by such a manufacturing method, the position of the pad (corresponding to the pad 32 in the embodiment) related to the signal line of the IC chip is the first terminal (the first terminal in the embodiment) related to the signal line of the package. Even when it is not opposed to the position of one terminal 57), the connection between the IC chip and the package can be realized.
[0056]
Further, in the relay substrate 10 of the above embodiment, the low dielectric constant portion 20 is formed in a range surrounding the outer periphery of the side portion of the capacitor portion 11 over the entire circumference. You may form so that a part of outer periphery may be surrounded.
[0057]
In the above embodiment, the entire range outside the capacitor portion 11 is the low dielectric constant portion 20, but the range of the low dielectric constant portion 20 formed on the substrate body can be changed as appropriate. For example, the low dielectric constant portion 20 can be divided and provided for each of the one or more columnar electrodes 22. An example of such partitioning is shown in FIGS. 10 to 12 as a third modification. FIG. 10A and FIG. 10B show a relay board 210 as a third modified example, corresponding to FIGS. 3 and 2, respectively. As shown in FIG. 10, in the relay substrate 210, the ceramic layer 214 of the multilayer ceramic capacitor 212 is extended outside the capacitor portion 211, and a large number (20 in FIG. 10) penetrates the extended range. ) Columnar electrodes 222 and a low dielectric constant portion 220 that covers the entire side surface of the columnar electrode 222. The low dielectric constant portion 220 extends around each columnar electrode 222.
[0058]
The relay substrate 210 having the above configuration is manufactured through steps S300 to S395 by the manufacturing process C shown in FIG. The contents of each process will be described below in the order of the processes. In the following description, the relay substrate 210 will be described with reference to FIG.
[0059]
First, the stacked body CS1 including a large number of via electrodes 215 is formed (step S300 in FIG. 11, FIG. 12A). Specifically, after a stacked body CS1 is formed by alternately stacking high dielectric layers 274a to 274e of barium titanate and wiring patterns 273a and 273b on an alumina base sheet 289, the center of the stacked body CS1 is formed. A large number of through holes are formed in the region, and the through holes are filled with a conductive material QM (nickel in this modification) to function as the via electrode 215. The wiring patterns 273a and 273b are electrically connected to the via electrode 215 every other layer of the high dielectric layers 274a to 274e in each through hole. The wiring patterns 273a and 273b and the high dielectric layers 274a to 274e function as the internal electrode 213 and the ceramic layer 214, respectively.
[0060]
Next, a large number of through holes 282 are formed in the stacked body CS1 (step S310 in FIG. 11, FIG. 12B). Each through hole 282 is formed at a predetermined interval in a range where the wiring patterns 273a and 273b at the edge of the stacked body CS1 are not formed. Next, the base sheet 289 is peeled off, and a low dielectric layer 280 made of alumina is formed on the peripheral surface constituting each through-hole 282 (step S320 in FIG. 11, FIG. 12C). The low dielectric layer 280 is formed by applying paste-like alumina to the upper surface of the stacked body CS1 after the inside of the through hole 282 is evacuated. As a result, the pasty alumina is sucked along the peripheral wall constituting the through hole 282 and welded onto the peripheral wall. Thereby, in the through hole 282, the low dielectric layer 280 is formed in the area where alumina is applied, and the hole 282a is formed in the area where alumina is not applied. The coating thickness of the alumina and the diameter of the holes 282a can be adjusted by the viscosity of the alumina paste and the degree of vacuum in the printing process. Next, the hole 282a formed inside each low dielectric layer 280 is filled with a conductive material QM (nickel in this modification) (step S330 in FIG. 11, FIG. 12D), and functions as the columnar electrode 222. .
[0061]
Subsequently, the laminated body CS1 is pressure-bonded by a high-temperature / high-pressure press, and the laminated body CS1 after pressure bonding is degreased and fired (step S390 in FIG. 11). Next, bumps 223, 224, bumps 216, and 217 are formed on the upper and lower ends of the columnar electrodes 222 and via electrodes 215 formed by firing to form bumps 223, 224, bumps 216, and 217 (step S395 in FIG. 11). Thereby, the columnar electrode 222 covered with the low dielectric constant portion 220 is formed on the ceramic layer 214 outside the capacitor portion 211 (region where the multilayer ceramic capacitor 212 is disposed) as shown in FIG. The provided relay substrate 210 is formed.
[0062]
Further, according to the manufacturing process C described above, the multilayer ceramic capacitor 212 is formed integrally with the low dielectric constant portion 220, and thereby the capacitor 212 is provided in the capacitor portion 211. For this reason, in the manufactured plurality of relay boards 210, the positional relationship between the power supply line and ground line (via electrode 215) provided in the capacitor unit 211 and the signal line (columnar electrode 222) provided in the low dielectric constant unit 20 is determined. It becomes easy to keep almost constant, and the certainty of connection with an IC chip or a package can be improved.
[0063]
In the third modified example, the low dielectric constant portion 220 is individually formed for each columnar electrode 222. However, the low dielectric constant portion 220 is formed for an electrode group including a plurality of columnar electrodes 222. Also good. An example of this is shown in FIG. 13 as a fourth modification. FIG. 13 shows a relay substrate 310 as a fourth modified example in a diagram corresponding to FIG. In FIG. 13, the illustration of bumps loaded in the via electrode 315 and the columnar electrode 322 is omitted. As shown in FIG. 13, in the relay substrate 310, one low dielectric constant portion 320 is formed for an electrode group composed of five columnar electrodes 322 spaced apart from each other. As a result, in the relay substrate 310, the entire circumference of each columnar electrode 322 is covered with the low dielectric constant portion 320, as in the relay substrates 10, 110, and 210 described above, and the low dielectric constant portion 320 is surrounded around the columnar electrode 322. Is provided.
[0064]
In the third and fourth modifications described above, it is possible to provide a metal shielding material between the ceramic layers 214 and 314 and the low dielectric constant portions 220 and 320. A configuration in which a shield material is provided between the ceramic layer 214 and the low dielectric constant portion 220 of the relay substrate 210 of the third modification is shown in FIG. 14 as a fifth modification. FIG. 14 shows a vertical cross section in the vicinity of the low dielectric constant portion 420 in the relay substrate 410 as a fifth modification, omitting the description of bumps loaded on the columnar electrodes 422. As shown in FIG. 14, in the relay substrate 410, a metal shield material 494 is provided between the ceramic layer 414 and the low dielectric constant portion 420. As a result, the low dielectric constant portion 420 is insulated from the ceramic layer 414. Therefore, it is possible to reliably prevent the electrical signal transmitted through the columnar electrode 422 from being affected by charging / discharging by the multilayer ceramic capacitor 412 disposed in the capacitor unit 411. Note that such a relay substrate 410 is formed by applying step S320 of the manufacturing process C shown in FIG. 11 to a metal layer by applying a metal paste on the peripheral surface constituting each through hole. It can manufacture by changing to the process of apply | coating an alumina paste on the surface.
[0065]
In the third, fourth, and fifth modified examples, the columnar electrode having the low dielectric constant portion is provided in the edge region of the relay substrate. The position where the columnar electrode is provided on the relay substrate. Can be appropriately changed.
[0066]
In addition, in the said Example and each modification, although the low dielectric constant part 20,120,220,320,420 was provided in the perimeter of columnar electrode 22,122,222,322,422, columnar electrode 22,122, Low dielectric constant portions 20, 120, 220, 320, and 420 may be provided around part of 222, 322, and 422. Such a configuration example is shown in FIG. 15 as a sixth modification. FIG. 15A and FIG. 15B respectively show the upper surface of the relay substrate 610 modified from the above embodiment and the upper surface of the relay substrate 710 modified from the third modified example. As shown in FIG. 15, in the relay substrates 610 and 710, among the many columnar electrodes 622 and 722, the columnar electrodes 622a and 722a are provided with the low dielectric constant portions 620 and 720 over the entire circumference thereof. The columnar electrodes 622b and 722b are provided with low dielectric constant portions 620 and 720 in a part of the entire circumference. According to such a configuration, the low dielectric constant portion 620, the electrical signal transmitted through the columnar electrodes 622, 722 is affected by charging / discharging by the multilayer ceramic capacitors 612, 712 disposed in the capacitor portions 611, 711. In the range where 720 is formed, it can be prevented.
[0067]
In the above-described embodiments and modifications, the ceramic layer 14 is formed using barium titanate, but a material having a high relative dielectric constant other than barium titanate (for example, strontium titanate (SrTiO3) or lead titanate (PbTiO3)). , Titanium oxide (TiO2)) may be used. In the above-described embodiments and modifications, the low dielectric constant portion 20 is formed using alumina. However, the low dielectric constant portion 20 is made of a material having a relative dielectric constant lower than that of the material for forming the ceramic layer 14. It only has to be formed. For example, when the forming material of the ceramic layer 14 is barium titanate, the surrounding portion 20 may be formed using a composite material (glass ceramic) of alumina and glass. When glass ceramic is used as the material of the enclosure portion 20, the glass ceramic is sintered at a lower temperature (900 ° C. or lower) than alumina, so even when copper is used as the material for forming the columnar electrode 22, it is excessively caused by firing. It does not melt, and the occurrence rate of disconnection or the like can be reduced. Regarding the relative dielectric constant, it is preferable that the relative dielectric constant of the material forming the ceramic layer is larger than 15 and the relative dielectric constant of the material forming the low dielectric constant portion is 15 or less.
[0068]
In the third, fourth, and fifth modifications, alumina is not filled around the columnar electrodes 222, 322, and 422, and the columnar electrodes 222, 322, 422 and the ceramic layers 214, 314, and 414 are not filled. An air layer may be formed. Such a configuration example is shown in FIG. 16 as a seventh modification. FIG. 16 shows a longitudinal section in the vicinity of the columnar electrode 522 in the relay substrate 510 as a seventh modified example. As shown in FIG. 16, in the relay substrate 510, an area where the low dielectric constant portion 220 and the columnar electrode 222 made of alumina in FIG. By disposing the columnar electrode 522 having a smaller cross-sectional area than the aperture 596 in the aperture 596, the entire circumference of the columnar electrode 522 is covered with air that is a substance having a lower relative dielectric constant than the ceramic layer 514. An air layer (low dielectric constant layer) is provided around the columnar electrode 522. Therefore, the columnar electrode 522 as a signal line does not come into contact with the ceramic layer 514 as a dielectric, and an electric signal transmitted through the columnar electrode 522 is not easily affected by charging / discharging by the capacitor 512. Accordingly, erroneous signal exchange between the IC chip and the package can be prevented, and electrical propagation between the IC chip and the package through the signal line can be stabilized. Note that such a relay substrate 510 does not open the through-hole portion without performing steps S320 and S330 (filling the through-hole with alumina or conductive material QM) in the manufacturing process C shown in FIG. The relay board provided as the hole 596 is manufactured, and the columnar electrode 522 manufactured by a separate process is disposed in the opening 596 of the relay board, thereby manufacturing the relay board.
[0069]
It is also possible to adopt a form in which an IC chip and a package are mounted in advance on the relay substrate of the above-described embodiments and modifications. As such a form, a relay substrate with an IC chip in which an IC chip is connected to a via electrode or a columnar electrode of a relay substrate, a package with a relay substrate in which a package is connected to a via electrode or a columnar electrode of the relay substrate, and the above relay substrate A structure or the like formed by connecting an IC chip and a package through the interface can be considered.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a connection structure of an IC package 60 using a relay substrate 10 according to an embodiment of the present invention.
FIG. 2 is an explanatory view showing an arrow shape of a longitudinal section along line 2-2 in FIG.
FIG. 3 is an explanatory view showing a state in which the relay substrate 10 is attached to the package 50 before the IC chip 30 is attached.
FIG. 4 is an explanatory diagram showing a manufacturing process A of the relay substrate 10;
FIG. 5 is an explanatory view showing a state in which the relay board 10 is manufactured by the manufacturing process A.
6 is an explanatory view showing a manufacturing process B of the relay substrate 10. FIG.
7 is an explanatory view showing a state in which the relay substrate 10 is manufactured by the manufacturing process B. FIG.
FIG. 8 is an explanatory diagram showing a first modification.
FIG. 9 is an explanatory diagram showing a second modification.
FIG. 10 is an explanatory diagram showing a third modification.
11 is an explanatory diagram showing a manufacturing process C of the relay substrate 210. FIG.
12 is an explanatory diagram showing a state where the relay substrate 210 is manufactured by the manufacturing process C. FIG.
FIG. 13 is an explanatory diagram showing a fourth modification.
FIG. 14 is an explanatory diagram showing a fifth modification.
FIG. 15 is an explanatory diagram showing a sixth modification.
FIG. 16 is an explanatory diagram showing a seventh modification.
[Explanation of symbols]
10, 110, 210, 310, 410, 510, 610, 710 ... relay board
11, 111, 211, 311, 411, 511, 611, 711 ... capacitor section
12, 112, 212, 312, 412, 512, 612, 712 ... multilayer ceramic capacitor
12a, 212a ... upper surface
12b, 212b ... lower surface
12c to f, 212c to f ... side surface
13 ... Internal electrode
14,114,214,314,414,514,614,714 ... ceramic layer
15, 115, 215, 315, 415, 615, 715 ... via electrodes
16, 17 ... Bump
20, 120, 220, 320, 420, 620, 720 ... low dielectric constant part
20a ... upper surface
20b ... lower surface
22, 122, 222, 322, 422, 522, 622, 622a, 622b, 722a, 722b, 722...
23, 24 ... Bump
30, 130, 230 ... IC chip
32 ... Pad
50, 150, 250 ... package
52 ... Upper layer
54 ... Lower layer
56 ... Lead
57 ... 1st terminal
58 ... Second terminal
71p ... through hole
73a, 73b, 273a, 273b ... wiring pattern
74a-e, 274a-e ... high dielectric layer
75 ... Through hole
80a-e, 280 ... low dielectric layer
80p ... Low dielectric sheet
82,282 ... through hole
89,289 ... Base sheet
92 ... wiring layer
190 ... Filler
282a ... hole
494 ... Shielding material
596 ... Open hole
CS, CS1, CS2 ... Laminate
PF ... space
QM: Conductive material

Claims (12)

A relay board having a wiring interposed between a semiconductor element and a package to which the semiconductor element is mounted, and electrically connecting the semiconductor element and the package;
A capacitor portion in which a capacitor having a dielectric is disposed between the electrode plates;
A low dielectric constant portion formed of a material having a relative dielectric constant lower than that of the dielectric,
A relay substrate in which the low dielectric constant portion is provided around at least a part of a signal line of the wiring. The relay board according to claim 1,
A via electrode penetrating through the capacitor and connected to one of the electrode plates serving as a positive electrode and a negative electrode of the capacitor;
A relay substrate in which at least a part of the via electrode is a power line or a ground line to the semiconductor element in the wiring. The relay substrate according to claim 1, wherein the low dielectric constant portion is provided for each signal line. The relay substrate according to claim 1, wherein the low dielectric constant portion is formed in a range surrounding the capacitor portion. The relay board | substrate with a semiconductor element with which the semiconductor element was connected to the said wiring of the relay board | substrate in any one of Claim 1 thru | or 4. A package with a relay board, wherein a package is connected to the wiring of the relay board according to any one of claims 1 to 4. A structure formed by connecting a semiconductor element and a package through the relay substrate according to claim 1. A method of manufacturing a relay substrate having a wiring interposed between a semiconductor element and a package in which the semiconductor element is housed, and electrically connecting the semiconductor element and the package,
(A) providing a low dielectric constant portion using a substance having a relative dielectric constant lower than that of the dielectric in a region connected to the capacitor portion where a capacitor having a dielectric is provided between the electrode plates;
(B) providing a signal line of the wiring in the low dielectric constant portion without contacting the dielectric;
(C) providing a capacitor having a via electrode connected to one of the electrode plates serving as a positive electrode and a negative electrode as a power supply line and a ground line for the semiconductor element in the wiring, in a capacitor unit; A method of manufacturing a relay board provided. 9. The method of manufacturing a relay board according to claim 8, wherein the step (c) is a step of providing the capacitor in the capacitor portion by forming the capacitor integrally with the low dielectric constant portion. The method of manufacturing a relay board according to claim 8, wherein the step (c) is a step of providing the capacitor in the capacitor portion by fitting the capacitor formed in advance into the capacitor portion. The method for manufacturing a relay board according to claim 10, further comprising a step of providing a position adjusting material for adjusting a position where the capacitor is fitted when the capacitor is fitted into the capacitor portion. In the steps (a) to (b), the low dielectric constant portion and the signal line are provided by sequentially filling the substance and the signal line forming material in the through holes provided in the region. The method for manufacturing a relay board according to claim 8, which is a process.

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