JP2005038683A - Inverter circuit for discharge tube - Google Patents

Inverter circuit for discharge tube Download PDF

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Publication number
JP2005038683A
JP2005038683A JP2003199387A JP2003199387A JP2005038683A JP 2005038683 A JP2005038683 A JP 2005038683A JP 2003199387 A JP2003199387 A JP 2003199387A JP 2003199387 A JP2003199387 A JP 2003199387A JP 2005038683 A JP2005038683 A JP 2005038683A
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Prior art keywords
circuit
discharge tube
voltage
transformer
booster
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JP2003199387A
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JP3905868B2 (en
Inventor
Shinichi Suzuki
伸一 鈴木
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Minebea Co Ltd
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Minebea Co Ltd
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Priority to JP2003199387A priority Critical patent/JP3905868B2/en
Priority to EP04254206A priority patent/EP1499166B1/en
Priority to DE602004007856T priority patent/DE602004007856T2/en
Priority to US10/891,578 priority patent/US7067988B2/en
Priority to CNA2004100636954A priority patent/CN1578577A/en
Publication of JP2005038683A publication Critical patent/JP2005038683A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/2825—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage
    • H05B41/2828—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage using control circuits for the switching elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/285—Arrangements for protecting lamps or circuits against abnormal operating conditions
    • H05B41/2851—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
    • H05B41/2855—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions against abnormal lamp operating conditions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/36—Controlling
    • H05B41/38—Controlling the intensity of light
    • H05B41/39—Controlling the intensity of light continuously
    • H05B41/392—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor
    • H05B41/3921—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor with possibility of light intensity variations
    • H05B41/3927—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor with possibility of light intensity variations by pulse width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4815—Resonant converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Circuit Arrangements For Discharge Lamps (AREA)
  • Inverter Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter circuit for a discharge tube having a simple circuit construction with stable circuit operation of which, efficiency is further improved and power consumption is reduced. <P>SOLUTION: The inverter circuit for the discharge tube is provided with a transformer 1 with a resonance circuit formed by parasitic capacitance of the discharge tube, an H-bridge circuit 17 driving a primary side of the transformer 1 at a frequency less than a resonance frequency of the resonance circuit and yet at a frequency where phase difference with voltage and current of the primary side of the transformer 1 is within a given range from the minimum point, a logic circuit 29 creating gate signals operating the H-bridge circuit 17 by output signals of an oscillation circuit 4 based on power supply voltage, and a booster circuit 100 boosting direct current voltage based on the output signals of the oscillation circuit 4 and supplying the boosted direct current power supply voltage to the logic circuit 29 as power supply voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、液晶表示ユニットなどに使用される放電管用インバータ回路に関し、特に高い電力効率を引き出す放電管用インバータ回路に関する。
【０００２】
【従来の技術】
従来の放電管用インバータ回路には、トランスの二次側のリーケージインダクタンスと負荷として接続される放電管の持つ寄生容量とで共振回路が形成され、共振回路の共振周波数でトランスの一次側を駆動するものがあるがある（例えば、特許文献１参照）。この共振周波数で駆動する従来の放電管用インバータ回路は、トランスの一次側の電圧と電流とに位相差を伴うため、必ずしもトランスの電力効率のよいものとはいえなかった。
【０００３】
このような問題に対し、トランスの一次側の電圧と電流の位相差が少ない範囲が電力効率の良いことに着目し、その周波数の範囲でトランスを駆動し、トランスの電力効率を向上させた放電管用インバータ回路がある（例えば、特許文献２参照）。
【０００４】
この特許文献２の放電管用インバータ回路は、放電管の持つ寄生容量と補助容量とにより共振回路が形成されるトランスと、共振回路の直列共振周波数未満で、かつトランスの一次側の電圧と電流との位相差が最小点より予め定めた範囲内にある周波数でトランスの一次側を駆動するＨブリッジ回路とを備えた回路構成となっており、電力効率の向上が行われている。
【０００５】
【特許文献１】
米国特許第６，１１４，８１４号公報
【特許文献２】
特開２００３−１６８５８５号公報
【発明が解決しようとする課題】
液晶表示ユニットとして、例えば、液晶テレビがあり、この液晶テレビのバックライトに使用される放電管用インバータ回路の電源電圧は１２Ｖ〜２４Ｖの範囲であり、特許文献２の放電管用インバータ回路に記載された漏洩磁束型のトランスを使用した他励駆動型インバータを例にとれば、放電管用インバータ回路の制御部を形成するインバータ制御ＩＣは、５．０Ｖの電源電圧で動作させ、トランスを駆動し放電管を点灯させるＦＥＴのＨブリッジ回路は、放電管の点灯用として１２Ｖ〜２４Ｖの電源電圧を供給して動作させている。
【０００６】
ところが、近年、液晶テレビの画面の大型化に伴い、放電管の数量も８〜２４本と多く使用され、長さも、例えば、１３００ｍｍと長くなり、それに伴って消費電力も１８０Ｗと大きくなっている。そのため、特に大型の液晶テレビの場合には、消費電力のほとんどが放電管用インバータ回路と放電管で消費されるため、省エネルギーなどの観点から放電管用インバータ回路のさらなる効率改善をして消費電力を削減することが求められている。
【０００７】
そこで、放電管用インバータ回路の効率改善をするものとして、Ｈブリッジ回路に供給される放電管の点灯用の電源電圧を従来の１２〜２４Ｖよりも高い、例えば１２０Ｖとするものがある。この放電管用インバータ回路では、電源電圧を高くすることによってＦＥＴを流れる電流が小さくできるため、ＦＥＴのオン抵抗による損失を小さくでき、また、トランスの一次巻線に流れる電流を少なくできるため銅損を低減でき、効率改善を行っている。このとき、電源電圧はＨブリッジに供給される放電管の点灯用の１２０Ｖと、インバータ制御ＩＣに供給される５Ｖの２つとなる。
【０００８】
この場合、Ｈブリッジ回路のＦＥＴの耐圧を従来よりも高くする必要があるが、耐圧の高いＦＥＴを駆動するためには大きいゲート−ソース電圧が必要であり、例えば、Ｈブリッジ回路のＦＥＴの耐圧を２００Ｖに設定すると、Ｈブリッジ回路のＦＥＴのゲート−ソース電圧は１０Ｖ以上が必要となる。そのため、インバータ制御ＩＣに供給される５Ｖの電源電圧をそのまま用いてもＦＥＴを駆動することができず、チャージポンプまたはブートストラップ、あるいは昇圧型ＤＣ−ＤＣコンバータ回路を接続して昇圧し、昇圧した電圧でＦＥＴを駆動する必要がある。
【０００９】
しかしながら、このようなチャージポンプまたはブートストラップ、あるいは昇圧型ＤＣ−ＤＣコンバータ回路などの昇圧回路の接続は、回路構成が複雑になると共に部品点数が増えてしまうという問題があり、またＨブリッジ回路を動作させるための発振回路の周波数と、昇圧回路を動作させるための発振回路の発振周波数の違いによりインバータ制御ＩＣの基準電圧に干渉が生じて回路動作が安定しなくなるという問題があった。
【００１０】
本発明は、このような従来の問題に鑑みてなされたもので、回路動作の安定した簡潔の回路構成でインバータの効率をさらに改善し消費電力を削減する放電管用インバータ回路を提供することを目的とする。
【００１１】
【課題を解決するための手段】
本発明の放電管用インバータ回路は、放電管の持つ寄生容量により共振回路が形成されるトランスと、前記共振回路の共振周波数未満で、かつ前記トランスの一次側の電圧と電流との位相差が最小点より予め定めた範囲内にある周波数で前記トランスの一次側を駆動するＨブリッジ回路と、前記Ｈブリッジ回路を作動するゲート信号を発振回路の出力信号により電源電圧を基に作るロジック回路と、前記発振回路よりの前記出力信号に基づいて直流電圧を昇圧し、前記昇圧した直流電源電圧を前記ロジック回路に前記電源電圧として供給する昇圧回路とを備えることとした。
【００１２】
また、前記共振回路は、前記放電管の持つ前記寄生容量と、前記放電管に並列に接続する補助容量とにより形成することとした。
【００１３】
また、前記昇圧回路は、前記昇圧回路の出力電圧に応じた電圧を出力するエラーアンプと、前記発振回路よりの前記出力信号に基づき、前記エラーアンプの出力電圧に応じたパルス幅のパルス電圧を出力するＰＷＭ回路とを備えることとした。
【００１４】
また、前記昇圧回路は、前記ＰＷＭ回路に接続するスロースタート回路を設けることとした。
【００１５】
また、前記昇圧回路に設けたスロースタート回路は、前記Ｈブリッジ回路をスロースタートさせるスロースタート回路より短い立ち上がり時間とすることとした。
【００１６】
さらに、前記トランスの前記放電管側の異常を検出したとき、前記昇圧回路の動作を停止するプロテクト回路を備えることとした。
【００１７】
【発明の実施の形態】
以下、本発明の実施の形態について、図面に基づいて説明する。
【００１８】
図１は、本発明の実施の形態の放電管用インバータ回路のブロック図である。
【００１９】
説明を分かりやすくするため、まず、端子２８ａの所定電圧Ｖａがエラーアンプ１１の反転入力部１１ａに入力されず調光が行なわれない場合について説明する。
【００２０】
図１に示すように、発振回路４の三角波７の出力はＰＷＭ回路８に入力する。トランス１の二次側の液晶表示ユニット２には液晶のバックライト用の放電管９が設置され、この放電管９に流れる電流を電圧に変換する電流電圧変換回路１０によってその電圧９ａをエラーアンプ１１の反転入力部１１ａに入力する。放電管９の持つ寄生容量３と、放電管９に並列に接続されたコンデンサ（容量）３１、３２と、トランス１の漏れインダクタンスとにより直列共振回路が形成されている。なお、コンデンサ３１、３２は寄生容量３に対する補助容量として機能する。
【００２１】
エラーアンプ１１は放電管９の電流に応じた出力電圧１２をＰＷＭ回路８に出力し、ＰＷＭ回路８は三角波７とエラーアンプ１１の出力電圧１２を比較し、パルス信号１３をカウンタ回路１４に入力する。
【００２２】
スロースタート回路３４は、比較的なだらかな立ち上げのスタート駆動信号５６の出力信号をＰＷＭ回路８に出力し、スタート時に瞬間的な過電圧が発生することを防止している。
【００２３】
また、発振回路４の出力信号の三角波７は、抵抗５とコンデンサ６の値により設定され、三角波７と同期した発振回路４の出力パルス信号１６は、カウンタ回路１４、１５とロジック回路２９に入力する。発振回路４の出力パルス信号１６とカウンタ回路１４、１５の出力パルス信号により、ロジック回路２９は、昇圧回路１００より供給される１０Ｖの電源電圧７６を基に、Ｈブリッジ回路１７へ入力するパルス振幅１０Ｖのゲート信号１８、１９、２０、２１を作る。
【００２４】
Ｈブリッジ回路１７は、ＰＭＯＳ（Ａ１）とＮＭＯＳ（Ｂ２）の直列回路と、ＰＭＯＳ（Ａ２）とＮＭＯＳ（Ｂ１）の直列回路が並列に接続されて構成され、ゲート信号１８、１９、２０、２１により作動する。Ｈブリッジ回路１７は、供給される放電管の点灯用の１２０Ｖの直流の電源電圧Ｖｂが、パルス振幅１０Ｖのゲート信号１８、１９、２０、２１により変換され、トランス１を介し放電管９を点灯する。
【００２５】
したがって、バースト回路２２が動作せず、端子２８ａから所定電圧Ｖａがエラーアンプ１１の反転入力部１１ａに入力されない場合には、調光は行われず、放電管９の電流がエラーアンプ１１の反転入力部１１ａに入力され、放電管９はフィードバック制御され点灯する。
【００２６】
図２は、本発明の実施の形態の放電管用インバータ回路における、二次側に共振回路が形成されたときのトランス一次側のアドミタンス｜Ｙ｜の周波数特性と、電圧と電流の位相差θの周波数特性である。
【００２７】
図２に示すように、トランス１の一次側を周波数Ａの範囲の交流電流が流れ、電力効率のよい範囲で定電流制御が行なわれて図１に示す放電管９を点灯する。
【００２８】
次に昇圧回路１００の動作について説明する。
【００２９】
昇圧回路１００は、５Ｖの直流の電源電圧Ｖｃｃを昇圧し、昇圧した直流電圧をロジック回路２９に電源電圧７６として供給する。この昇圧回路１００を制御するために、Ｈブリッジ回路１７の制御に用いられる発振回路４からの出力信号の三角波７が昇圧回路１００にも入力されている。
【００３０】
図３は、本発明の実施の形態の放電管用インバータ回路における昇圧回路のブロック図である。
【００３１】
図３に示すように、昇圧回路１００は、５Ｖの直流電圧の電源電圧Ｖｃｃが供給され、この電源電圧Ｖｃｃが、三角波７を基に作動するトランジスタ７３と、インダクタ７４と、ダイオード７７とからなる昇圧型チョッパー回路によって昇圧される。さらにコンデンサ７８で平滑されて１０Ｖの直流電圧になり、ロジック回路２９の直流の電源電圧７６として昇圧回路１００から出力される。
【００３２】
昇圧回路１００では、エラーアンプ７１とＰＷＭ回路７２を用いてＰＷＭ制御を行い、定電圧出力を得るようにしている。昇圧回路１００の出力電圧は抵抗８１、８２によって検出されてエラーアンプ７１で基準電圧Ｖｅと比較され、エラーアンプ７１は昇圧回路１００の出力電圧に応じた電圧を出力する。ＰＷＭ回路７２ではエラーアンプ７１の出力と発振回路４から出力する三角波７が比較され、パルス幅がフィードバック制御されたパルス信号がＰＷＭ回路７２から出力する。このパルス信号によりトランジスタ７３がスイッチングされ一定電圧の直流の電源電圧７６の出力が得られる。
【００３３】
したがって、ロジック回路２９は、電源電圧７６が供給され、Ｈブリッジ回路１７に用いられる高耐圧のＦＥＴを駆動できる高い電圧のゲート信号１８、１９、２０、２１を出力することができる。
【００３４】
また、発振回路４から出力する三角波７は、Ｈブリッジ回路１７の制御と昇圧回路１００の制御とに共通して用いられており、両方の回路で共有されているため、昇圧回路１００には独立した発振回路を設ける必要がなく、昇圧回路１００の回路構成を簡略化することができる。また、Ｈブリッジ回路１７と昇圧回路１００は発振回路４から出力される三角波７を共通して用いているため両方の回路の動作周波数は同一となり、動作周波数が異なる場合に基準電圧に発生する干渉を避け回路動作の不安定を解消し、安定した回路動作を得ることができる。
【００３５】
スロースタート回路７５は、昇圧回路１００が動作を開始するときに比較的緩やかに立ち上がる出力信号をＰＷＭ回路７２に出力し、ＰＷＭ回路７２が出力するパルス信号の幅が過大にならないように制限して昇圧回路１００の出力に過渡的な過大電圧が発生しないようにするものである。
【００３６】
図４は、本発明の実施の形態の放電管用インバータ回路における昇圧回路１００とＰＷＭ回路８とに使用されるスロースタート回路７５および３４の出力信号の波形図である。
【００３７】
図４に示すように、昇圧回路１００に使用されるスロースタート回路７５の立ち上がり時間Ｔ１は、ＰＷＭ回路８に使用されるスロースタート回路３４の立ち上がり時間Ｔ２よりも短く設定し、電源電圧７６を安定させた後にスロースタート回路３４によりロジック回路２９の立ち上げを行うため、ロジック回路２９を安定して立ち上げることができ、ロジック回路２９に接続するＨブリッジ回路１７も安定した立ち上げとなる。
【００３８】
図５は、本発明の実施の形態の放電管用インバータ回路の動作タイミングチャート図である。
【００３９】
次に、図１と図５を用いてバースト回路２２により放電管９の調光を行なうときの動作について説明する。
【００４０】
図１に示すように、バースト回路２２は、抵抗２３を所定値以上とすることでＤＵＴＹ端子２４ａに入力した所定のパルス信号２４が第１のバースト信号２５ｂ（図５の（Ｄ）参照）としてバースト回路２２から出力されるモードと、抵抗２３を所定値未満とすることで抵抗２３とコンデンサ２６とで決まり発振する三角波電圧２７（図５の（Ｂ）参照）とＤＵＴＹ端子２４ａに入力する直流電圧３６（図５の（Ｂ）参照）とが比較されパルス波の第２のバースト信号２５ａ（図５の（Ｃ）参照）が出力されるモードとのいずれかに設定することができる。
【００４１】
バースト回路２２よりの第１のバースト信号２５ｂが「Ｈ」のときは、トランジスタ２８は「ＯＮ」となり、エラーアンプ１１は放電管９の電流に応じた出力電圧１２をＰＷＭ回路８に出力し、図５の（Ａ）に示す三角波７を基に形成される図５の（Ｅ）に示すＨブリッジ回路１７の出力により放電管９は作動状態となる。
【００４２】
バースト回路２２の第１のバースト信号２５ｂが「Ｌ」のときは、トランジスタ２８は「ＯＦＦ」となり、エラーアンプ１１の反転端子１１ａは端子２８ａに与えられている所定電圧Ｖａにプルアップされ、エラーアンプ１１は非作動状態となり、Ｈブリッジ回路１７の作動を停止し、放電管９は非作動状態となる。このように第１のバースト信号２５ｂにより放電管９は断続的に作動し、調光が行なわれる。
【００４３】
なお、第２のバースト信号２５ａを使用する場合にも、同様にして放電管９の調光が行われ、いずれかのバースト信号を選択的に使用することができる。
【００４４】
図６は、本発明の実施の形態の放電管用インバータ回路におけるゲート信号のタイミングチャート図である。
【００４５】
図１に示す昇圧回路１００よりの電源電圧７６によりロジック回路２９で形成される図６の（Ｂ）に示すパルス振幅１０Ｖのゲート信号１８と、同じく図６の（Ｃ）に示すパルス振幅１０Ｖのゲート信号１９との立ち上がりは、図１に示すカウンタ回路１４、１５とロジック回路２９とにより、図６の（Ａ）に示すように、三角波７の上限側の頂点１８ｕ、１９ｕごとに交互に行なわれ、ゲート信号１８とゲート信号１９との立ち下りは、三角波７とエラーアンプ１１の出力信号１２とのクロスポイント１８ｄ、１９ｄで行なわれる。このパルス振幅１０Ｖのゲート信号１８とゲート信号１９とにより、ＰＭＯＳ（Ａ１）、ＰＭＯＳ（Ａ２）とのゲートの立ち上がりと立ち下がりがそれぞれ行なわれる。
【００４６】
また、昇圧回路１００よりの電源電圧７６によりロジック回路２９で形成される図６の（Ｄ）に示すパルス振幅１０Ｖのゲート信号２０と、同じく図６の（Ｅ）に示すパルス振幅１０Ｖのゲート信号２１との立ち上がりは、三角波７の下限側の頂点２０ｕ、２１ｕごとに交互に行なわれ、ゲート信号２０とゲート信号２１との立ち下がりは、三角波７とエラーアンプ１１の出力電圧１２とのクロスポイント２０ｄ、２１ｄで行なわれる。このパルス振幅１０Ｖのゲート信号２０とゲート信号２１とにより、ＮＭＯＳ（Ｂ１）とＮＭＯＳ（Ｂ２）とのゲートの立ち上がりと立ち下りがそれぞれ行なわれる。
【００４７】
さらに、図６の（Ｂ）から図６の（Ｄ）に示すように、ゲート信号１８、１９の立ち下りに対し、ゲート信号２０、２１の立ち上がりが遅延しており、また図６の（Ｆ）に示すように、ゲート信号２０、２１の立ち下りに対し、ゲート信号１８、１９の立ち下りを遅延回路３５により予め定めた時間ｔ１だけ遅延させている。そのため、ＰＭＯＳ（Ａ１）、ＰＭＯＳ（Ａ２）とＮＭＯＳ（Ｂ１）、ＮＭＯＳ（Ｂ２）が同時に「ＯＮ」にならないようにすることができる。
【００４８】
したがって、三角波７と出力電圧１２とにより、ＰＭＯＳ（Ａ１）、ＰＭＯＳ（Ａ２）とＮＭＯＳ（Ｂ１）、ＮＭＯＳ（Ｂ２）が同時に「ＯＮ」にならないよう適切なゲート信号１８、１９、２０、２１を容易に作ることができる。
【００４９】
また、図１に示すように、電圧帰還用のエラーアンプ５１は、反転入力部５１ａに入力する放電管９の印加電圧信号５５と予め定めた設定値Ｖｃとを比較し、放電管９への印加電圧に応じた出力電圧５２をプロテクト回路５０とＰＷＭ回路８に出力する。プロテクト回路５０は、内部にコンパレータ回路（図示せず）を有しており、電圧帰還用のエラーアンプ５１からの出力電圧５２と、トランス１の二次側と直列に設けられた抵抗５７からのトランス出力電流信号５３とを入力する。印加電圧信号５５は、トランス１の出力側に並列に設けられたコンデンサ３１、３２同士の接続部の電圧を、抵抗５８、５９で分圧した電圧である。
【００５０】
電圧帰還用のエラーアンプ５１は、反転入力部５１ａに放電管９の印加電圧信号５５が入力すると、印加電圧信号５５と予め定めた設定値Ｖｃとを比較して出力電圧５２をＰＷＭ回路８に出力し、放電管９への印加電圧のフィードバック制御が行なわれる。そのため、例えば、放電管９が接続されていないときや、接続不良などのときに開放電圧を設定値にすることができる。
【００５１】
また、放電管９が接続されていないときや接続不良などのときはトランス１の二次側の出力電圧が異常な値となることがあるが、その場合、プロテクト回路５０に入力する電圧帰還用エラーアンプ５１の出力電圧５２とトランス出力電流信号５３がプロテクト回路５０のコンパレータ回路（図示せず）の基準電圧と比較され、この基準電圧を電圧帰還用エラーアンプ５１の出力電圧５２または、トランス出力電流信号５３が上回ったとき、ロジック回路２９の動作を停止し、放電管９への過電流や、トランス１への過電圧を防止することができる。また、プロテクト回路５０は、エラーアンプ１１の出力電圧１２を入力し、放電管９への過電流や、トランス１への過電圧を防止することもできる。このように、プロテクト回路５０は、トランス１の放電管側の異常な状況を検出したとき、ロジック回路２９の動作を停止してトランス１や各回路が破損されることを防止する。
【００５２】
なお、なんらかの原因による瞬間的な過電圧に対応するため、プロテクト回路５０は、内蔵するタイマーにより予め定めた値を上回ったときにロジック回路２９の動作を停止し、誤ってロジック回路２９の動作を停止することがないようにしている。
【００５３】
図７は、本発明の実施の形態の放電管用インバータ回路におけるプロテクト回路が作動するときの動作説明図である。
【００５４】
図７に示すように、電源電圧Ｖｃｃは、昇圧回路１００、発振回路４、ＰＷＭ回路８、エラーアンプ１１、５１、プロテクト回路５０および、基準電圧回路９０などに供給されるが、基準電圧回路９０では、電源電圧Ｖｃｃがより低い基準電圧Ｖｃと基準電圧Ｖｅに変換され、基準電圧Ｖｃはエラーアンプ１１、５１と、プロテクト回路５０に入力し、基準電圧Ｖｅは昇圧回路１００に入力する。
【００５５】
プロテクト回路５０がトランス１の放電管側の異常な状況を検出したとき、ロジック回路２９の動作を停止してトランス１（図１参照）や各回路が破損されることを防止するが、Ｈブリッジ回路１７には１２０Ｖの放電管の点灯用の電源電圧Ｖｂが供給されるため、動作を確実に停止する必要がある。
【００５６】
プロテクト回路５０は、トランス１の放電管側の異常な状況を検出したとき、基準電圧回路９０の動作を停止させ、昇圧回路１００に供給する基準電圧Ｖｅをゼロ電圧とし、昇圧回路１００からロジック回路２９に供給する電源電圧７６の出力を停止して、確実にロジック回路２９の動作を停止する。そのため、Ｈブリッジ回路１７の動作を確実に停止することができる。
【００５７】
以上述べたごとく、本発明の実施の形態の放電管用インバータ回路は、発振回路を共用した構成としているため昇圧回路に専用の発振回路を必要とせず、部品点数を削減しコストを低減させる簡潔の構成でＨブリッジ回路の高耐圧のＦＥＴの制御を行うことができる。そのため、Ｈブリッジ回路の電源電圧を高くすることが簡潔の構成ででき、ＦＥＴを流れる電流を小さくしてＦＥＴのオン抵抗による損失を低減することができる。また、本発明の実施の形態の放電管用インバータ回路は、トランスの昇圧比も小さくて済むためトランスの一次側の電流を少なくできることから銅損の低減もでき、効率を改善し液晶表示ユニットの消費電力を削減することができる。
【００５８】
また、発振回路を共用した構成としているため、基準電圧に発生する干渉を避け回路動作の不安定を解消し、安定した回路動作を得ることができる。
【００５９】
また、基準電圧を必要とする回路に基準電圧を供給する基準電圧回路を共有するため、誤動作の恐れのない安定性が良い回路とすることができる。
【００６０】
また、本発明の実施の形態の放電管用インバータ回路は、共振周波数より低い周波数でトランスを作動させるため、高次の周波数の影響を受け難くできトランス設計を容易にすることができる。
【００６１】
なお、本発明の実施の形態の放電管用インバータ回路は、Ｈブリッジ回路１７と、トランス１と、放電管９を除いた回路をインバータ制御ＩＣとすることもできる。
【００６２】
【発明の効果】
本発明の放電管用インバータ回路は、放電管の持つ寄生容量により共振回路が形成されるトランスと、前記共振回路の共振周波数未満で、かつ前記トランスの一次側の電圧と電流との位相差が最小点より予め定めた範囲内にある周波数で前記トランスの一次側を駆動するＨブリッジ回路と、前記Ｈブリッジ回路を作動するゲート信号を発振回路の出力信号により電源電圧を基に作るロジック回路と、前記発振回路よりの前記出力信号に基づいて直流電圧を昇圧し、前記昇圧した直流電源電圧を前記ロジック回路に前記電源電圧として供給する昇圧回路とを備えることとしたため、昇圧回路に専用の発振回路を必要とせず、部品点数を削減しコストを低減させる簡潔の構成でＨブリッジ回路の高耐圧のＦＥＴの制御を行うことができる。そのため、Ｈブリッジ回路の電源電圧を高くすることが簡潔の構成ででき、ＦＥＴを流れる電流を小さくしてＦＥＴのオン抵抗による損失を低減することができる。また、トランスの昇圧比も小さくて済むためトランスの一次側の電流を少なくできることから銅損の低減もでき、効率を改善し消費電力を削減することができる。さらに、発振回路を共有した構成としているため、基準電圧に発生する干渉を避け、安定した回路動作を得ることができる。
【００６３】
また、前記共振回路は、前記放電管の持つ前記寄生容量と、前記放電管に並列に接続する補助容量とにより形成することとしたため、補助容量により所望の共振周波数を容易に得ることができる。
【００６４】
また、前記昇圧回路は、前記昇圧回路の出力電圧に応じた電圧を出力するエラーアンプと、前記発振回路よりの前記出力信号に基づき、前記エラーアンプの出力電圧に応じたパルス幅のパルス電圧を出力するＰＷＭ回路とを備えることとしたため、安定した一定電圧を容易に出力することができる。
【００６５】
また、前記昇圧回路は、前記ＰＷＭ回路に接続するスロースタート回路を設けることとしたため、昇圧回路の出力に過渡的な過大電圧が発生しないようにすることができる。
【００６６】
また、前記昇圧回路に設けたスロースタート回路は、前記Ｈブリッジ回路をスロースタートさせるスロースタート回路より短い立ち上がり時間とすることとしたため、ロジック回路を安定して立ち上げることができ、ロジック回路に接続するＨブリッジ回路も安定した立ち上げにすることができる。
【００６７】
さらに、前記トランスの前記放電管側の異常を検出したとき、前記昇圧回路の動作を停止するプロテクト回路を備えることとしたため、確実にロジック回路の動作を停止すると共に、Ｈブリッジ回路の動作も確実に停止することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態の放電管用インバータ回路のブロック図である。
【図２】本発明の実施の形態の放電管用インバータ回路における、二次側に共振回路が形成されたときのトランス一次側のアドミタンス｜Ｙ｜の周波数特性と、電圧と電流の位相差θの周波数特性である。
【図３】本発明の実施の形態の放電管用インバータ回路における昇圧回路のブロック図である。
【図４】本発明の実施の形態の放電管用インバータ回路における昇圧回路とＰＷＭ回路とに使用されるスロースタート回路の出力信号の波形図である。
【図５】本発明の実施の形態の放電管用インバータ回路の動作タイミングチャート図である。
【図６】本発明の実施の形態の放電管用インバータ回路におけるゲート信号のタイミングチャート図である。
【図７】本発明の実施の形態の放電管用インバータ回路におけるプロテクト回路が作動するときの動作説明図である。
【符号の説明】
１ トランス
２ 液晶表示ユニット
４ 発振回路
８、７２ ＰＷＭ回路
９ 放電管
１０ 電流電圧変換回路
１１、５１、７１ エラーアンプ
１７ Ｈブリッジ回路
１８、１９、２０、２１ ゲート信号
２２ バースト回路
２９ ロジック回路
３４、７５ スロースタート回路
５０ プロテクト回路
７３ トランジスタ
７７ ダイオード
９０ 基準電圧回路
１００ 昇圧回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inverter circuit for a discharge tube used for a liquid crystal display unit or the like, and more particularly to an inverter circuit for a discharge tube that draws out high power efficiency.
[0002]
[Prior art]
In a conventional discharge tube inverter circuit, a resonance circuit is formed by the leakage inductance on the secondary side of the transformer and the parasitic capacitance of the discharge tube connected as a load, and the primary side of the transformer is driven at the resonance frequency of the resonance circuit. There are some (see, for example, Patent Document 1). A conventional inverter circuit for a discharge tube that is driven at this resonance frequency has a phase difference between the voltage and current on the primary side of the transformer, so that it cannot always be said that the power efficiency of the transformer is good.
[0003]
With regard to such problems, focusing on the fact that the range where the phase difference between the voltage and current on the primary side of the transformer is small is good in power efficiency, the transformer is driven in that frequency range, and the discharge improves the power efficiency of the transformer. There is a tube inverter circuit (see, for example, Patent Document 2).
[0004]
The inverter circuit for a discharge tube of Patent Document 2 includes a transformer in which a resonance circuit is formed by a parasitic capacitance and an auxiliary capacitance of the discharge tube, a voltage and a current on the primary side of the transformer that are less than the series resonance frequency of the resonance circuit. The circuit configuration includes an H-bridge circuit that drives the primary side of the transformer at a frequency that is within a predetermined range from the minimum point, and power efficiency is improved.
[0005]
[Patent Document 1]
US Pat. No. 6,114,814
[Patent Document 2]
JP 2003-168585 A
[Problems to be solved by the invention]
As the liquid crystal display unit, for example, there is a liquid crystal television, and the power supply voltage of the discharge tube inverter circuit used for the backlight of the liquid crystal television is in the range of 12V to 24V, which is described in the discharge tube inverter circuit of Patent Document 2. Taking a separately-excited drive type inverter using a leakage flux type transformer as an example, an inverter control IC that forms a control unit of a discharge tube inverter circuit is operated with a power supply voltage of 5.0 V to drive the transformer and discharge the discharge tube. The FET H-bridge circuit is operated by supplying a power supply voltage of 12V to 24V for lighting the discharge tube.
[0006]
However, in recent years, with an increase in the size of the screen of a liquid crystal television, the number of discharge tubes is often used as 8 to 24, and the length is increased to, for example, 1300 mm, and the power consumption is increased to 180 W accordingly. . Therefore, especially in the case of large-sized LCD TVs, most of the power consumption is consumed by the inverter circuit for the discharge tube and the discharge tube. Therefore, the efficiency of the inverter circuit for the discharge tube is further improved from the viewpoint of energy saving and the power consumption is reduced. It is requested to do.
[0007]
In order to improve the efficiency of the discharge tube inverter circuit, the power supply voltage for lighting the discharge tube supplied to the H bridge circuit is higher than the conventional 12 to 24V, for example, 120V. In this discharge tube inverter circuit, the current flowing through the FET can be reduced by increasing the power supply voltage, so that the loss due to the on-resistance of the FET can be reduced, and the current flowing through the primary winding of the transformer can be reduced, thereby reducing the copper loss. We can reduce it and improve efficiency. At this time, the power supply voltage is two, 120V for lighting the discharge tube supplied to the H bridge and 5V supplied to the inverter control IC.
[0008]
In this case, the withstand voltage of the FET of the H bridge circuit needs to be higher than the conventional one, but a large gate-source voltage is required to drive the FET with a high withstand voltage. Is set to 200V, the gate-source voltage of the FET of the H bridge circuit needs to be 10V or more. Therefore, even if the power supply voltage of 5V supplied to the inverter control IC is used as it is, the FET cannot be driven, and the charge pump, the bootstrap, or the step-up DC-DC converter circuit is connected to boost and boost the voltage. It is necessary to drive the FET with a voltage.
[0009]
However, the connection of such a charge pump or bootstrap or a booster circuit such as a boost DC-DC converter circuit has a problem that the circuit configuration becomes complicated and the number of parts increases, and the H bridge circuit is There is a problem that the circuit operation becomes unstable due to interference between the reference voltage of the inverter control IC due to the difference between the frequency of the oscillation circuit for operating and the oscillation frequency of the oscillation circuit for operating the booster circuit.
[0010]
The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an inverter circuit for a discharge tube that further improves the efficiency of the inverter and reduces power consumption with a simple circuit configuration with stable circuit operation. And
[0011]
[Means for Solving the Problems]
The inverter circuit for a discharge tube according to the present invention has a minimum phase difference between a transformer in which a resonance circuit is formed by the parasitic capacitance of the discharge tube and a resonance frequency of the resonance circuit and a primary side voltage and current of the transformer. An H bridge circuit that drives the primary side of the transformer at a frequency within a predetermined range from a point; and a logic circuit that generates a gate signal for operating the H bridge circuit based on a power supply voltage based on an output signal of the oscillation circuit; And a booster circuit that boosts a DC voltage based on the output signal from the oscillation circuit and supplies the boosted DC power supply voltage to the logic circuit as the power supply voltage.
[0012]
The resonant circuit is formed by the parasitic capacitance of the discharge tube and an auxiliary capacitor connected in parallel to the discharge tube.
[0013]
The booster circuit outputs an error amplifier that outputs a voltage corresponding to the output voltage of the booster circuit, and a pulse voltage having a pulse width corresponding to the output voltage of the error amplifier based on the output signal from the oscillation circuit. And an output PWM circuit.
[0014]
The booster circuit is provided with a slow start circuit connected to the PWM circuit.
[0015]
The slow start circuit provided in the booster circuit has a shorter rise time than the slow start circuit for slow starting the H bridge circuit.
[0016]
Furthermore, a protection circuit is provided that stops the operation of the booster circuit when an abnormality on the discharge tube side of the transformer is detected.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a block diagram of an inverter circuit for a discharge tube according to an embodiment of the present invention.
[0019]
In order to make the description easy to understand, first, a case where the predetermined voltage Va of the terminal 28a is not input to the inverting input unit 11a of the error amplifier 11 and dimming is not performed will be described.
[0020]
As shown in FIG. 1, the output of the triangular wave 7 of the oscillation circuit 4 is input to the PWM circuit 8. The liquid crystal display unit 2 on the secondary side of the transformer 1 is provided with a discharge tube 9 for a liquid crystal backlight, and the voltage 9a is converted into an error amplifier by a current-voltage conversion circuit 10 that converts the current flowing through the discharge tube 9 into a voltage. 11 to the inverting input unit 11a. A series resonance circuit is formed by the parasitic capacitance 3 of the discharge tube 9, capacitors (capacitances) 31 and 32 connected in parallel to the discharge tube 9, and the leakage inductance of the transformer 1. The capacitors 31 and 32 function as auxiliary capacitors for the parasitic capacitance 3.
[0021]
The error amplifier 11 outputs an output voltage 12 corresponding to the current of the discharge tube 9 to the PWM circuit 8. The PWM circuit 8 compares the triangular wave 7 with the output voltage 12 of the error amplifier 11, and inputs the pulse signal 13 to the counter circuit 14. To do.
[0022]
The slow start circuit 34 outputs an output signal of a relatively gentle start drive signal 56 to the PWM circuit 8 to prevent an instantaneous overvoltage from occurring at the start.
[0023]
The triangular wave 7 of the output signal of the oscillation circuit 4 is set by the values of the resistor 5 and the capacitor 6, and the output pulse signal 16 of the oscillation circuit 4 synchronized with the triangular wave 7 is input to the counter circuits 14 and 15 and the logic circuit 29. To do. Based on the output pulse signal 16 of the oscillation circuit 4 and the output pulse signals of the counter circuits 14 and 15, the logic circuit 29 inputs the pulse amplitude input to the H bridge circuit 17 based on the 10 V power supply voltage 76 supplied from the booster circuit 100. 10V gate signals 18, 19, 20, 21 are created.
[0024]
The H bridge circuit 17 is configured by connecting a series circuit of PMOS (A1) and NMOS (B2) and a series circuit of PMOS (A2) and NMOS (B1) in parallel, and gate signals 18, 19, 20, 21. It operates by. The H bridge circuit 17 converts the supplied 120 V DC power supply voltage Vb for lighting the discharge tube by the gate signals 18, 19, 20, and 21 having a pulse amplitude of 10 V and lights the discharge tube 9 through the transformer 1. To do.
[0025]
Therefore, when the burst circuit 22 does not operate and the predetermined voltage Va is not input from the terminal 28a to the inverting input portion 11a of the error amplifier 11, dimming is not performed and the current of the discharge tube 9 is input to the inverting input of the error amplifier 11. The discharge tube 9 is input to the unit 11a and is turned on under feedback control.
[0026]
FIG. 2 shows the frequency characteristics of the transformer primary side admittance | Y | and the phase difference θ between the voltage and current when the resonant circuit is formed on the secondary side in the inverter circuit for a discharge tube according to the embodiment of the present invention. It is a frequency characteristic.
[0027]
As shown in FIG. 2, an alternating current in the range of frequency A flows on the primary side of the transformer 1, constant current control is performed in a range where power efficiency is good, and the discharge tube 9 shown in FIG.
[0028]
Next, the operation of the booster circuit 100 will be described.
[0029]
The booster circuit 100 boosts the DC power supply voltage Vcc of 5V and supplies the boosted DC voltage to the logic circuit 29 as the power supply voltage 76. In order to control the booster circuit 100, a triangular wave 7 of an output signal from the oscillation circuit 4 used for controlling the H bridge circuit 17 is also input to the booster circuit 100.
[0030]
FIG. 3 is a block diagram of a booster circuit in the discharge tube inverter circuit according to the embodiment of the present invention.
[0031]
As shown in FIG. 3, the booster circuit 100 is supplied with a power supply voltage Vcc of a DC voltage of 5 V, and this power supply voltage Vcc includes a transistor 73 that operates based on the triangular wave 7, an inductor 74, and a diode 77. The voltage is boosted by a boost chopper circuit. Further, the voltage is smoothed by the capacitor 78 to become a DC voltage of 10 V, and is output from the booster circuit 100 as the DC power supply voltage 76 of the logic circuit 29.
[0032]
The booster circuit 100 performs PWM control using the error amplifier 71 and the PWM circuit 72 to obtain a constant voltage output. The output voltage of the booster circuit 100 is detected by the resistors 81 and 82 and compared with the reference voltage Ve by the error amplifier 71. The error amplifier 71 outputs a voltage corresponding to the output voltage of the booster circuit 100. The PWM circuit 72 compares the output of the error amplifier 71 with the triangular wave 7 output from the oscillation circuit 4, and outputs a pulse signal whose pulse width is feedback-controlled from the PWM circuit 72. The transistor 73 is switched by this pulse signal, and an output of a DC power supply voltage 76 having a constant voltage is obtained.
[0033]
Therefore, the logic circuit 29 is supplied with the power supply voltage 76 and can output the high-voltage gate signals 18, 19, 20, and 21 that can drive the high-breakdown-voltage FET used in the H-bridge circuit 17.
[0034]
Further, the triangular wave 7 output from the oscillation circuit 4 is commonly used for the control of the H bridge circuit 17 and the control of the booster circuit 100, and is shared by both circuits. Thus, the circuit configuration of the booster circuit 100 can be simplified. In addition, since the H bridge circuit 17 and the booster circuit 100 commonly use the triangular wave 7 output from the oscillation circuit 4, the operating frequencies of both circuits are the same, and interference generated in the reference voltage when the operating frequencies are different. Avoiding instability of the circuit operation, and stable circuit operation can be obtained.
[0035]
The slow start circuit 75 outputs an output signal that rises relatively slowly when the booster circuit 100 starts operation to the PWM circuit 72 and limits the pulse signal output from the PWM circuit 72 so that the width of the pulse signal does not become excessive. This prevents a transient excessive voltage from occurring in the output of the booster circuit 100.
[0036]
FIG. 4 is a waveform diagram of output signals of the slow start circuits 75 and 34 used in the booster circuit 100 and the PWM circuit 8 in the discharge tube inverter circuit according to the embodiment of the present invention.
[0037]
As shown in FIG. 4, the rise time T1 of the slow start circuit 75 used in the booster circuit 100 is set shorter than the rise time T2 of the slow start circuit 34 used in the PWM circuit 8, and the power supply voltage 76 is stabilized. Then, the logic circuit 29 is started up by the slow start circuit 34, so that the logic circuit 29 can be started up stably, and the H bridge circuit 17 connected to the logic circuit 29 is also started up stably.
[0038]
FIG. 5 is an operation timing chart of the discharge tube inverter circuit according to the embodiment of the present invention.
[0039]
Next, the operation when the discharge tube 9 is dimmed by the burst circuit 22 will be described with reference to FIGS.
[0040]
As shown in FIG. 1, in the burst circuit 22, the predetermined pulse signal 24 input to the DUTY terminal 24a is set as a first burst signal 25b (see FIG. 5D) by setting the resistance 23 to a predetermined value or more. A mode output from the burst circuit 22, a triangular wave voltage 27 (see FIG. 5B) determined by the resistor 23 and the capacitor 26 by making the resistor 23 less than a predetermined value, and a direct current input to the DUTY terminal 24a. The voltage 36 (see FIG. 5B) is compared, and the mode can be set to any mode in which the second burst signal 25a of the pulse wave (see FIG. 5C) is output.
[0041]
When the first burst signal 25 b from the burst circuit 22 is “H”, the transistor 28 is “ON”, and the error amplifier 11 outputs the output voltage 12 corresponding to the current of the discharge tube 9 to the PWM circuit 8. The discharge tube 9 is activated by the output of the H bridge circuit 17 shown in FIG. 5E, which is formed based on the triangular wave 7 shown in FIG.
[0042]
When the first burst signal 25b of the burst circuit 22 is “L”, the transistor 28 is “OFF”, and the inverting terminal 11a of the error amplifier 11 is pulled up to a predetermined voltage Va applied to the terminal 28a, and an error occurs. The amplifier 11 is deactivated, the operation of the H bridge circuit 17 is stopped, and the discharge tube 9 is deactivated. As described above, the discharge tube 9 is intermittently operated by the first burst signal 25b, and light control is performed.
[0043]
Even when the second burst signal 25a is used, the discharge tube 9 is dimmed in the same manner, and any one of the burst signals can be selectively used.
[0044]
FIG. 6 is a timing chart of gate signals in the discharge tube inverter circuit according to the embodiment of the present invention.
[0045]
A gate signal 18 having a pulse amplitude of 10V shown in FIG. 6B formed by the logic circuit 29 by the power supply voltage 76 from the booster circuit 100 shown in FIG. 1 and a pulse signal having a pulse amplitude of 10V shown in FIG. As shown in FIG. 6A, the rising edge of the gate signal 19 is alternately performed by the counter circuits 14 and 15 and the logic circuit 29 shown in FIG. 1 at every vertex 18u and 19u on the upper limit side of the triangular wave 7. The falling of the gate signal 18 and the gate signal 19 is performed at cross points 18d and 19d between the triangular wave 7 and the output signal 12 of the error amplifier 11. By the gate signal 18 and the gate signal 19 having a pulse amplitude of 10 V, the rise and fall of the gates of the PMOS (A1) and the PMOS (A2) are respectively performed.
[0046]
Further, the gate signal 20 having a pulse amplitude of 10V shown in FIG. 6D formed by the logic circuit 29 by the power supply voltage 76 from the booster circuit 100 and the gate signal having a pulse amplitude of 10V shown in FIG. 21 rises alternately at the lower limit side vertices 20u and 21u of the triangular wave 7, and the falling edge of the gate signal 20 and the gate signal 21 is a cross-point between the triangular wave 7 and the output voltage 12 of the error amplifier 11. 20d, 21d. By the gate signal 20 and the gate signal 21 having the pulse amplitude of 10 V, the gates of the NMOS (B1) and the NMOS (B2) rise and fall, respectively.
[0047]
Further, as shown in FIG. 6B to FIG. 6D, the rise of the gate signals 20 and 21 is delayed with respect to the fall of the gate signals 18 and 19, and the (F) of FIG. ), The delay circuit 35 delays the fall of the gate signals 18 and 19 by a predetermined time t1 with respect to the fall of the gate signals 20 and 21. Therefore, the PMOS (A1), the PMOS (A2), the NMOS (B1), and the NMOS (B2) can be prevented from being “ON” at the same time.
[0048]
Therefore, appropriate gate signals 18, 19, 20, and 21 are set so that the PMOS (A1), the PMOS (A2), the NMOS (B1), and the NMOS (B2) are not simultaneously turned ON by the triangular wave 7 and the output voltage 12. Can be made easily.
[0049]
Further, as shown in FIG. 1, the error amplifier 51 for voltage feedback compares the applied voltage signal 55 of the discharge tube 9 input to the inverting input portion 51a with a predetermined set value Vc, and supplies it to the discharge tube 9. An output voltage 52 corresponding to the applied voltage is output to the protect circuit 50 and the PWM circuit 8. The protect circuit 50 includes a comparator circuit (not shown) inside, and outputs from an output voltage 52 from the error amplifier 51 for voltage feedback and a resistor 57 provided in series with the secondary side of the transformer 1. The transformer output current signal 53 is input. The applied voltage signal 55 is a voltage obtained by dividing the voltage of the connection portion between the capacitors 31 and 32 provided in parallel on the output side of the transformer 1 by the resistors 58 and 59.
[0050]
When the applied voltage signal 55 of the discharge tube 9 is input to the inverting input portion 51a, the error amplifier 51 for voltage feedback compares the applied voltage signal 55 with a predetermined set value Vc and outputs the output voltage 52 to the PWM circuit 8. The voltage is output and feedback control of the voltage applied to the discharge tube 9 is performed. Therefore, for example, the open circuit voltage can be set to a set value when the discharge tube 9 is not connected or when there is a connection failure.
[0051]
Further, when the discharge tube 9 is not connected or when the connection is poor, the output voltage on the secondary side of the transformer 1 may become an abnormal value. In this case, the voltage feedback input to the protect circuit 50 is used. The output voltage 52 of the error amplifier 51 and the transformer output current signal 53 are compared with the reference voltage of the comparator circuit (not shown) of the protect circuit 50, and this reference voltage is output from the error amplifier 51 for voltage feedback or the transformer output. When the current signal 53 exceeds, the operation of the logic circuit 29 is stopped, and an overcurrent to the discharge tube 9 and an overvoltage to the transformer 1 can be prevented. The protect circuit 50 can also receive the output voltage 12 of the error amplifier 11 and prevent overcurrent to the discharge tube 9 and overvoltage to the transformer 1. Thus, the protect circuit 50 stops the operation of the logic circuit 29 and prevents the transformer 1 and each circuit from being damaged when detecting an abnormal situation on the discharge tube side of the transformer 1.
[0052]
In order to cope with an instantaneous overvoltage due to some cause, the protect circuit 50 stops the operation of the logic circuit 29 when it exceeds a predetermined value by a built-in timer, and erroneously stops the operation of the logic circuit 29. I don't want to do that.
[0053]
FIG. 7 is an operation explanatory diagram when the protection circuit in the discharge tube inverter circuit according to the embodiment of the present invention operates.
[0054]
As shown in FIG. 7, the power supply voltage Vcc is supplied to the booster circuit 100, the oscillation circuit 4, the PWM circuit 8, the error amplifiers 11, 51, the protect circuit 50, the reference voltage circuit 90, and the like. The power supply voltage Vcc is converted into a lower reference voltage Vc and a reference voltage Ve. The reference voltage Vc is input to the error amplifiers 11 and 51 and the protection circuit 50, and the reference voltage Ve is input to the booster circuit 100.
[0055]
When the protect circuit 50 detects an abnormal situation on the discharge tube side of the transformer 1, the operation of the logic circuit 29 is stopped to prevent the transformer 1 (see FIG. 1) and each circuit from being damaged. Since the circuit 17 is supplied with the power supply voltage Vb for lighting the 120V discharge tube, it is necessary to stop the operation reliably.
[0056]
When the protect circuit 50 detects an abnormal condition on the discharge tube side of the transformer 1, the protect circuit 50 stops the operation of the reference voltage circuit 90, sets the reference voltage Ve supplied to the booster circuit 100 to zero voltage, and starts from the booster circuit 100 to the logic circuit. The output of the power supply voltage 76 supplied to 29 is stopped, and the operation of the logic circuit 29 is surely stopped. Therefore, the operation of the H bridge circuit 17 can be stopped reliably.
[0057]
As described above, the discharge tube inverter circuit according to the embodiment of the present invention has a configuration in which the oscillation circuit is shared, so that a dedicated oscillation circuit is not required for the booster circuit, and the conciseness that reduces the number of parts and reduces the cost. With the configuration, it is possible to control the high breakdown voltage FET of the H bridge circuit. Therefore, the power supply voltage of the H-bridge circuit can be increased with a simple configuration, and the current flowing through the FET can be reduced to reduce the loss due to the on-resistance of the FET. In addition, the discharge tube inverter circuit according to the embodiment of the present invention can reduce the transformer primary current because the transformer has a small step-up ratio, thereby reducing the copper loss, improving the efficiency and consuming the liquid crystal display unit. Electric power can be reduced.
[0058]
In addition, since the oscillation circuit is shared, it is possible to avoid interference generated in the reference voltage, eliminate instability of circuit operation, and obtain stable circuit operation.
[0059]
In addition, since the reference voltage circuit that supplies the reference voltage to the circuit that requires the reference voltage is shared, it is possible to obtain a circuit with good stability without fear of malfunction.
[0060]
In addition, since the discharge tube inverter circuit according to the embodiment of the present invention operates the transformer at a frequency lower than the resonance frequency, it is difficult to be affected by higher-order frequencies, and the transformer design can be facilitated.
[0061]
In the discharge tube inverter circuit according to the embodiment of the present invention, a circuit excluding the H bridge circuit 17, the transformer 1, and the discharge tube 9 may be used as the inverter control IC.
[0062]
【The invention's effect】
The inverter circuit for a discharge tube according to the present invention has a minimum phase difference between a transformer in which a resonance circuit is formed by the parasitic capacitance of the discharge tube and a resonance frequency of the resonance circuit and a primary side voltage and current of the transformer. An H bridge circuit that drives the primary side of the transformer at a frequency within a predetermined range from a point; and a logic circuit that generates a gate signal for operating the H bridge circuit based on a power supply voltage based on an output signal of the oscillation circuit; A booster circuit that boosts a DC voltage based on the output signal from the oscillation circuit and supplies the boosted DC power supply voltage as the power supply voltage to the logic circuit. Therefore, the high-breakdown-voltage FET of the H-bridge circuit can be controlled with a simple configuration that reduces the number of parts and reduces the cost. Therefore, the power supply voltage of the H-bridge circuit can be increased with a simple configuration, and the current flowing through the FET can be reduced to reduce the loss due to the on-resistance of the FET. Further, since the transformer step-up ratio can be small, the current on the primary side of the transformer can be reduced, so that copper loss can be reduced, efficiency can be improved, and power consumption can be reduced. Further, since the oscillation circuit is shared, it is possible to avoid interference generated in the reference voltage and obtain a stable circuit operation.
[0063]
Further, since the resonance circuit is formed by the parasitic capacitance of the discharge tube and an auxiliary capacitor connected in parallel to the discharge tube, a desired resonance frequency can be easily obtained by the auxiliary capacitor.
[0064]
The booster circuit outputs an error amplifier that outputs a voltage corresponding to the output voltage of the booster circuit, and a pulse voltage having a pulse width corresponding to the output voltage of the error amplifier based on the output signal from the oscillation circuit. Since the output PWM circuit is provided, a stable constant voltage can be easily output.
[0065]
Further, since the booster circuit is provided with a slow start circuit connected to the PWM circuit, it is possible to prevent a transient excessive voltage from occurring in the output of the booster circuit.
[0066]
Also, since the slow start circuit provided in the booster circuit has a shorter rise time than the slow start circuit for slow starting the H bridge circuit, the logic circuit can be started up stably and connected to the logic circuit. The H bridge circuit can be started up stably.
[0067]
Further, since the protection circuit for stopping the operation of the booster circuit is provided when an abnormality on the discharge tube side of the transformer is detected, the operation of the logic circuit is surely stopped and the operation of the H bridge circuit is also surely performed. Can be stopped.
[Brief description of the drawings]
FIG. 1 is a block diagram of an inverter circuit for a discharge tube according to an embodiment of the present invention.
FIG. 2 shows the frequency characteristics of the admittance | Y | on the transformer primary side when the resonant circuit is formed on the secondary side and the phase difference θ between voltage and current in the inverter circuit for a discharge tube according to the embodiment of the present invention. It is a frequency characteristic.
FIG. 3 is a block diagram of a booster circuit in the discharge tube inverter circuit according to the embodiment of the present invention.
FIG. 4 is a waveform diagram of an output signal of a slow start circuit used in a booster circuit and a PWM circuit in the discharge tube inverter circuit according to the embodiment of the present invention.
FIG. 5 is an operation timing chart of the discharge tube inverter circuit according to the embodiment of the present invention.
FIG. 6 is a timing chart of gate signals in the discharge tube inverter circuit according to the embodiment of the present invention.
FIG. 7 is an operation explanatory diagram when the protect circuit is activated in the discharge tube inverter circuit according to the embodiment of the present invention;
[Explanation of symbols]
1 transformer
2 Liquid crystal display unit
4 Oscillator circuit
8, 72 PWM circuit
9 Discharge tube
10 Current-voltage conversion circuit
11, 51, 71 Error amplifier
17 H bridge circuit
18, 19, 20, 21 Gate signal
22 Burst circuit
29 Logic circuit
34, 75 Slow start circuit
50 Protection circuit
73 Transistor
77 Diode
90 Reference voltage circuit
100 Booster circuit

Claims (6)

放電管の持つ寄生容量により共振回路が形成されるトランスと、前記共振回路の共振周波数未満で、かつ前記トランスの一次側の電圧と電流との位相差が最小点より予め定めた範囲内にある周波数で前記トランスの一次側を駆動するＨブリッジ回路と、前記Ｈブリッジ回路を作動するゲート信号を発振回路の出力信号により電源電圧を基に作るロジック回路と、前記発振回路よりの前記出力信号に基づいて直流電圧を昇圧し、前記昇圧した直流電源電圧を前記ロジック回路に前記電源電圧として供給する昇圧回路とを備えたことを特徴とする放電管用インバータ回路。The phase difference between the transformer in which the resonance circuit is formed by the parasitic capacitance of the discharge tube, the resonance frequency of the resonance circuit, and the voltage and current on the primary side of the transformer is within a predetermined range from the minimum point. An H bridge circuit that drives the primary side of the transformer at a frequency, a logic circuit that generates a gate signal for operating the H bridge circuit based on a power supply voltage from an output signal of the oscillation circuit, and the output signal from the oscillation circuit An inverter circuit for a discharge tube, comprising: a booster circuit that boosts a DC voltage based on the booster and supplies the boosted DC power supply voltage to the logic circuit as the power supply voltage. 前記共振回路は、前記放電管の持つ前記寄生容量と、前記放電管に並列に接続する補助容量とにより形成することを特徴とする請求項１に記載の放電管用インバータ回路。2. The inverter circuit for a discharge tube according to claim 1, wherein the resonance circuit is formed by the parasitic capacitance of the discharge tube and an auxiliary capacitor connected in parallel to the discharge tube. 前記昇圧回路は、前記昇圧回路の出力電圧に応じた電圧を出力するエラーアンプと、前記発振回路よりの前記出力信号に基づき、前記エラーアンプの出力電圧に応じたパルス幅のパルス電圧を出力するＰＷＭ回路とを備えたことを特徴とする請求項１記載の放電管用インバータ回路。The booster circuit outputs an error amplifier that outputs a voltage corresponding to the output voltage of the booster circuit, and outputs a pulse voltage having a pulse width corresponding to the output voltage of the error amplifier based on the output signal from the oscillation circuit. The inverter circuit for a discharge tube according to claim 1, further comprising a PWM circuit. 前記昇圧回路は、前記ＰＷＭ回路に接続するスロースタート回路を設けたことを特徴とする請求項３記載の放電管用インバータ回路。4. The inverter circuit for a discharge tube according to claim 3, wherein the booster circuit is provided with a slow start circuit connected to the PWM circuit. 前記昇圧回路に設けたスロースタート回路は、前記Ｈブリッジ回路をスロースタートさせるスロースタート回路より短い立ち上がり時間とすることを特徴とする請求項４に記載の放電管用インバータ回路。5. The inverter circuit for a discharge tube according to claim 4, wherein the slow start circuit provided in the booster circuit has a shorter rise time than a slow start circuit for slow starting the H-bridge circuit. 前記トランスの前記放電管側の異常を検出したとき、前記昇圧回路の動作を停止するプロテクト回路を備えたことを特徴とする請求項１に記載の放電管用インバータ回路。2. The discharge tube inverter circuit according to claim 1, further comprising a protection circuit that stops the operation of the booster circuit when an abnormality is detected on the discharge tube side of the transformer.
JP2003199387A 2003-07-18 2003-07-18 Inverter circuit for discharge tube Expired - Fee Related JP3905868B2 (en)

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JP2003199387A JP3905868B2 (en) 2003-07-18 2003-07-18 Inverter circuit for discharge tube
EP04254206A EP1499166B1 (en) 2003-07-18 2004-07-14 Inverter circuit for discharge lamps with a voltage step-up circuit for supplying the gate driver of the inverter switches
DE602004007856T DE602004007856T2 (en) 2003-07-18 2004-07-14 Inverter for discharge lamps with voltage booster circuit for feeding the gate drivers of inverter switches
US10/891,578 US7067988B2 (en) 2003-07-18 2004-07-15 Inverter circuit for lighting discharge lamps with reduced power consumption
CNA2004100636954A CN1578577A (en) 2003-07-18 2004-07-16 Inverter circuit for lighting discharge lamps with reduced power consumption

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WO2008102703A1 (en) * 2007-02-19 2008-08-28 Panasonic Electric Works Co., Ltd. Discharge lamp operation device, illumination device, and liquid crystal display device
US7791283B2 (en) 2005-11-02 2010-09-07 Minebea Co., Ltd. Discharge lamp lighting apparatus
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WO2010034162A1 (en) * 2008-09-28 2010-04-01 Bosch Power Tools (China) Co., Ltd. Control device for controlling a motor in a low voltage dc power tool and control method thereof
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Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3329929B2 (en) * 1994-02-15 2002-09-30 松下電工株式会社 High pressure discharge lamp lighting device
JPH0992483A (en) * 1995-09-20 1997-04-04 Minebea Co Ltd High-intensity discharge lamp lighting device
US6114814A (en) * 1998-12-11 2000-09-05 Monolithic Power Systems, Inc. Apparatus for controlling a discharge lamp in a backlighted display
KR20000012429A (en) * 1999-12-03 2000-03-06 김중성 Electronic ballast for gas discharge lamp and operating method
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US7791283B2 (en) 2005-11-02 2010-09-07 Minebea Co., Ltd. Discharge lamp lighting apparatus
WO2008102703A1 (en) * 2007-02-19 2008-08-28 Panasonic Electric Works Co., Ltd. Discharge lamp operation device, illumination device, and liquid crystal display device
US8115421B2 (en) 2007-02-19 2012-02-14 Panasonic Electronic Works Co., Ltd. Discharge lamp lighting device, illumination device, and liquid crystal display device
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JP2015070108A (en) * 2013-09-30 2015-04-13 ミネベア株式会社 Light source drive device

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