JP2005038497A - Ferroelectric non-volatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory which is further increased in its bit capacity and is made non-volatile. <P>SOLUTION: A ferroelectric capacitor 1 and a paraelectric capacitor 2 are connected in series; a juncture FG of the ferroelectric capacitor 1 and the paraelectric capacitor 2 is connected to a gate section of a first field-effect transistor (FET) 3; and the juncture FG is connected to the source section or drain section of the FET 4, by which the ferroelectric non-volatile memory is constituted. The ferroelectric non-volatile memory puts the second FET 4 into a conducting state in a first step, puts the second FET 4 into a non-conducting state in a second step, applies a positive or negative voltage to each of the terminal of the ferroelectric capacitor 1 and the terminal of the paraelectric capacitor 2 or grounds the same in a third step and grounds the first terminal and the second terminal in a fourth step. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile memory device using a ferroelectric, and more particularly to a multi-value memory.

  As a conventional ferroelectric memory device equipped with a multi-value memory, there has been one using a multi-history ferroelectric capacitor (see, for example, Patent Document 1). FIG. 9 is a circuit diagram of a conventional ferroelectric memory device described in Patent Document 1.

  In FIG. 9, a multi-history ferroelectric capacitor 101 has a circuit configuration in which a paraelectric capacitor 102 is connected in series and a field effect transistor 103 is connected to a node FG. The charge amount of the paraelectric capacitor 102 induced by the polarization inversion of the ferroelectric is read out according to the magnitude of the drain current of the field effect transistor 103.

  The multiple history characteristic of the multiple history ferroelectric capacitor 101 is shown in FIG. FIG. 10A is a characteristic diagram of the electric field and polarization of the multi-history ferroelectric capacitor 101. As shown in FIG. 10A, since two different coercive electric fields exist, when the electric field increases, the polarization increases in two stages. That is, as shown in FIG. 10B, the multi-history ferroelectric capacitor 101 is equivalent to a parallel connection of two ferroelectric capacitors having different coercive electric fields.

  As shown in FIG. 10 (b1), when the polarization directions of the two ferroelectric capacitors are both downward, the state is P1 shown in FIG. 10 (a).

  As shown in FIG. 10 (b2), when the polarization directions of the two ferroelectric capacitors are both upward, the state of P2 shown in FIG. 10 (a) is obtained.

  As shown in FIG. 10B3, when the polarization directions of the two ferroelectric capacitors are different, the state of P0 shown in FIG.

  As described above, the multi-history ferroelectric capacitor 101 has three stable polarization states. The ternary state can be discriminated based on the charge amount of the paraelectric capacitor 102 induced in these three stable polarization states.

Further, when erasing the memory of the multi-history ferroelectric capacitor 101, the terminal IN2 is grounded, and a negative voltage capable of reversing the polarization of the ferroelectric capacitor is applied to the node IN1 to bring it into the state of P1. Thereafter, the terminals IN1 and IN2 are grounded, and the charge is discharged by the leakage current of the ferroelectric capacitor 101 and the paraelectric capacitor 102, so that the charge of the node FG is reduced to zero.
JP-A-6-58397 (page 3-4, FIG. 1-2)

  However, since the conventional configuration has three values (that is, P0, P1, and P2), an increase in bit capacity cannot be expected much compared to the conventional binary values. Further, since the ferroelectric memory is erased by the leakage current of the multi-history ferroelectric capacitor 101 and the paraelectric capacitor 102, the erasing time is long. Furthermore, since the charge induced in the paraelectric capacitor flows out due to the leak current, there is a problem that the memory state cannot be made non-volatile.

  An object of the present invention is to solve the above-described conventional problems, to further increase the bit capacity of a storage device, and to provide a nonvolatile memory device.

In order to solve the conventional problems, a ferroelectric multilevel nonvolatile memory device according to the present invention includes a ferroelectric capacitor and a paraelectric capacitor connected in series, and the ferroelectric capacitor, the paraelectric capacitor, Is connected to the gate part of the first field effect transistor, and the connection part is connected to the source part or the drain part of the second field effect transistor,
In the first step, the second field effect transistor is turned on,
In a second step following the first step, the second field effect transistor is turned off,
In the third step following the second step, a positive or negative voltage is applied to each of the first terminal on the ferroelectric capacitor side and the second terminal on the paraelectric capacitor side. Or ground,
In a fourth step subsequent to the third step, the voltages of the first terminal and the second terminal are grounded.

  In this configuration, a quinary state can be stored by using a minor loop, and the erasing time is shortened by using a reset field effect transistor for erasing the memory, and a leakage current other than at the time of erasing is used. The memory can be made almost non-volatile. Therefore, according to the ferroelectric nonvolatile memory device of the present invention, it has at least a five-value storage state and can be stored in a nonvolatile manner.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit configuration diagram of the ferroelectric nonvolatile memory device according to the first embodiment of the present invention. In FIG. 1, the same components as those in FIG.

  In FIG. 1, a ferroelectric capacitor 1 and a paraelectric capacitor 2 are connected in series. The node FG which is the connection portion is connected to the gate portion of the detection transistor 3 which is the first field effect transistor. The charge amount induced in the node FG is read by the detection transistor 3. Further, a node FG is connected to the drain portion of the resetting transistor 4 which is the second field effect transistor. By making the reset transistor 4 conductive, the charge induced in the node FG can flow out, and the memory state of the ferroelectric nonvolatile memory device can be erased at high speed.

  FIG. 2 is a diagram for explaining the operation principle of this embodiment. For simplicity, the terminal IN2 is grounded. Consider a case where the voltage Vpp1 is applied to the terminal IN1. As shown in FIG. 2A, the voltage Vf applied to the ferroelectric capacitor 1 is based on the node FG, and the voltage Vcc applied to the paraelectric capacitor 2 is based on the ground portion. Further, the charge induced in the ferroelectric capacitor 1 is Qf, and the charge induced in the paraelectric capacitor 2 is Qcc.

Now, assuming that the voltage Vpp1 is applied to the control terminal CG,
Vpp1 = Vf + Vcc ... (Formula 1)
It becomes. From the charge conservation law, the relationship between the charge induced in the lower electrode 1b of the ferroelectric capacitor 1 and the charge induced in the upper electrode 2a of the paraelectric capacitor 2 is
Qcc−Qf = 0… (Formula 2)
It becomes. The charge Qc induced in the paraelectric capacitor 2 is
Qcc = CccVcc ... (Formula 3)
It becomes. Here, if (Equation 1) and (Equation 2) are substituted into (Equation 3),
Qf = Ccc (Vpp1−Vf) (Equation 4)
It becomes. This corresponds to the straight line CC1 in FIG. On the other hand, the relationship between the charge Qf and the voltage Vf of the ferroelectric capacitor 1 shows a hysteresis characteristic as shown by a curve Ferro1 in FIG. The intersection A1 between the straight line CC1 and the curve Ferro1 is the charge Qf and the voltage Vf of the ferroelectric capacitor 1 when the voltage Vpp1 is applied to the terminal IN1.

  From this state, when the voltage at the terminal IN1 is returned to the ground, the straight line representing the paraelectric capacitor 2 becomes the straight line CC3 in FIG. The intersection B1 between the straight line CC3 and the curve Ferro1 is the charge Qf and the voltage Vf of the ferroelectric capacitor 1 when the voltage Vpp1 is applied to the terminal IN1 and then returned to the ground. From FIG. 2B, it can be seen that the voltage Vf is -Vh1. However, since the voltage Vf is based on the node FG, the voltage at the node FG becomes a positive value Vh1 when the ground portion is used as a reference.

  As described above, when the positive voltage Vpp1 is applied to the terminal IN1 and then returned to the ground, the positive voltage Vh1 is held at the node FG due to the polarization characteristics of the ferroelectric capacitor 1 and the hysteresis characteristics of the voltage. As can be seen from FIG. 2B, the magnitude of the holding voltage Vh1 varies depending on the shape of the curve Ferro1, the slope of the straight line CC1, that is, the capacitance value of the paraelectric capacitor 2, and the magnitude of the voltage applied to the control IN1. To do. Further, the charge Qf and the voltage Vf of the ferroelectric capacitor 1 when the negative voltage −Vpp1 is applied to the terminal IN1 and then returned to the ground are as indicated by a point B4. At this time, the negative voltage -Vh1 is held at the node FG.

  When the voltage Vpp1 is applied, the voltage Vf applied to the ferroelectric capacitor 1 is larger than the coercive voltage Vc of the ferroelectric capacitor 1. That is, the polarization of the ferroelectric capacitor 1 is sufficiently saturated.

  In the following example, the voltage Vpp2 is applied to the terminal IN1. At this time, the voltage Vf applied to the ferroelectric capacitor 1 is smaller than the coercive voltage Vc of the ferroelectric capacitor 1. That is, the polarization of the ferroelectric capacitor 1 is not saturated.

  When the voltage Vpp2 is applied to the terminal IN1, the relationship between the charge Qf of the ferroelectric capacitor 1 and the voltage Vf shows a hysteresis characteristic as shown by a curve Ferro2 in FIG. This is because the voltage Vf applied to the ferroelectric capacitor 1 is smaller than the coercive voltage Vc of the ferroelectric capacitor 1. Thereby, the hysteresis characteristic of the ferroelectric capacitor 1 becomes a minor loop. The intersection A2 between the straight line CC2 and the curve Ferro2 is the ferroelectric charge Qf and voltage Vf when the voltage Vpp2 is applied to the terminal IN1.

  From this state, when the voltage at the terminal IN1 is returned to the ground, the straight line representing the paraelectric capacitor 2 becomes the straight line CC3 in FIG. The intersection B2 between the straight line CC3 and the curve Ferro2 is the charge Qf and the voltage Vf of the ferroelectric capacitor 1 when the voltage Vpp2 is applied to the terminal IN1 and then returned to the ground. From FIG. 2B, it can be seen that the voltage Vf is -Vh2. However, similarly to B1, the voltage of the node FG has a positive value Vh2.

  As described above, when the positive voltage Vpp2 is applied to the terminal IN1 and then returned to the ground, the positive voltage Vh2 is held at the node FG due to the polarization characteristics of the ferroelectric capacitor 1 and the voltage hysteresis characteristics. Similarly, the charge Qf and the voltage Vf of the ferroelectric capacitor 1 when the negative voltage −Vpp1 is applied to the terminal IN2 and then returned to the ground are as indicated by a point B3. At this time, the negative voltage -Vh2 is held at the node FG.

  As described above, it has been shown that the value of the voltage held at the node FG can be changed by changing the value of the voltage applied to the terminal IN1. Next, a timing chart of voltages applied to each terminal for holding each state is shown.

  FIG. 3 is a timing chart of voltages applied to the terminals in order to set the charge Qf and the voltage Vf of the ferroelectric capacitor 1 to the point B1. In the period t1, which is the first step, the positive voltage Vdd is applied to the terminal CG. As a result, the reset transistor 4 becomes conductive, and the node FG is electrically connected to the terminal SS. Here, as shown in FIG. 3, a negative voltage −Vdd is applied to the terminal SS and a positive voltage Vdd is applied to the terminal IN2 by Δt. Thereby, the polarization of the ferroelectric capacitor 1 is aligned in a certain direction. Thereafter, both the terminal SS and the terminal IN2 are grounded. As a result, the charge of the node FG flows out and the previous state is erased.

  In the period t2, which is the second step after the period t1, the voltage of the terminal CG is returned to the ground. As a result, the node FG is disconnected from the ground portion.

  In a period t3 that is the third step after the period t2, a positive voltage Vdd is applied to the terminal IN1, and a negative voltage −Vdd is applied to the terminal IN2. As a result, the voltage 2 Vdd is applied to the series circuit of the ferroelectric capacitor 1 and the paraelectric capacitor 2. If 2Vdd is set to be equal to Vpp1, the polarization of the ferroelectric capacitor 1 is sufficiently saturated. For this reason, the state of the charge and voltage of the ferroelectric capacitor 1 is point A1 in FIG.

  In a period t4 that is a fourth step after the period t4, the voltages of the terminals IN1 and IN2 are returned to the ground, that is, 0 [V]. At this time, the state of the electric charge and voltage of the ferroelectric capacitor 1 is a point B1 in FIG. The voltage of Vh1 is held at the node FG. The held voltage is read by the detection transistor 4. A reading method will be described later. Since it is held by the polarization of the ferroelectric capacitor 1, it can be restored to its original state even when the power is turned off.

  FIG. 4 is a timing chart of voltages applied to the terminals in order to set the charge Qf and the voltage Vf of the ferroelectric capacitor 1 to the point B4. Except for the third step, the timing chart is the same as that of the point B1. The difference in the third step is described. In a period t3 as the third step, a positive voltage −Vdd is applied to the terminal IN1, and a negative voltage Vdd is applied to the terminal IN2. As a result, the voltage −2 Vdd is applied to the series circuit of the ferroelectric capacitor 1 and the paraelectric capacitor 2. In the period t4 that is the fourth step after the period t4, the state of the charge and voltage of the ferroelectric capacitor 1 is a point B4 in FIG. The voltage of −Vh1 is held at the node FG.

  FIG. 5 is a timing chart of voltages applied to the terminals in order to set the charge Qf and voltage Vf of the ferroelectric capacitor 1 to the point B2. Except for the third step, the timing chart is the same as that of the point B1. The difference in the third step is described. In the period t3 that is the third step, the positive voltage Vdd is applied to the terminal IN1. Terminal IN2 remains grounded. As a result, the voltage Vdd is applied to the series circuit of the ferroelectric capacitor 1 and the paraelectric capacitor 2. If Vdd is set to be equal to Vpp2, the polarization of the ferroelectric capacitor 1 is not sufficiently saturated. For this reason, the state of the electric charge and voltage of the ferroelectric capacitor 1 is a point A2 in FIG. In the period t4 that is the fourth step after the period t4, the state of the electric charge and voltage of the ferroelectric capacitor 1 is a point B2 in FIG. The voltage of Vh2 is held at the node FG.

  FIG. 6 is a timing chart of voltages applied to the terminals in order to set the charge Qf and the voltage Vf of the ferroelectric capacitor 1 to the point B3. Except for the third step, the timing chart is the same as that of the point B1. The difference in the third step is described. In the period t3 that is the third step, the positive voltage Vdd is applied to the terminal IN2. Terminal IN1 remains grounded. As a result, the voltage −Vdd is applied to the series circuit of the ferroelectric capacitor 1 and the paraelectric capacitor 2. If Vdd is set to be equal to Vpp2, the polarization of the ferroelectric capacitor 1 is not sufficiently saturated. In the period t4 that is the fourth step after the period t4, the state of the charge and voltage of the ferroelectric capacitor 1 is a point B3 in FIG. A voltage of −Vh2 is held at the node FG.

  FIG. 7 is a timing chart of voltages applied to the terminals in order to set the reset state. Except for the third step, the timing chart is the same as that of the point B1. The difference in the third step is described. In the period t3 that is the third step, the terminals IN1 and IN2 are kept in the ground state. In the period t4 which is the fourth step after the period t4, the state of the electric charge and voltage of the ferroelectric capacitor 1 becomes a point O in FIG. Thereby, this apparatus can be made into a reset state.

  Note that the voltage at the terminal BG of the substrate portion of the resetting transistor 4 is set to at least a voltage smaller than −Vh1 so that the forward current of the PN junction does not flow. The reset transistor 4 preferably has a positive threshold value in order to reduce the leakage current between the source and the drain. Furthermore, since a negative voltage is applied to the substrate portion of the reset transistor 4, the voltage between the gate and the substrate becomes higher than the power supply voltage. Therefore, it is more preferable that the gate oxide film is larger than the detection transistor 3. Next, a reading method will be described with reference to FIG.

  FIG. 8 is a diagram illustrating the relationship between Vfg, which is the voltage of the gate portion of the detection transistor 3, and the drain current Id. The threshold value of the detection transistor 3 is set to be smaller than -Vh1. Each point B1 to B4 shown in FIG. 2B is made to correspond to the relationship of Id-Vfg. In this way, by reading the drain current magnitudes Id0 to Id4 that differ from the drain current Id of the detection transistor 3 depending on the magnitude of Vfg, the storage state that is the voltage held at the node FG is read. Is possible. As can be seen from FIG. 8, when the points B1 to B4 and the reset state “0” are included, five states can be stored.

  As described above, in the ferroelectric nonvolatile memory device according to the first embodiment of the present invention, the ferroelectric capacitor 1 and the paraelectric capacitor are changed by changing the magnitude of the voltage applied to the terminal IN1 and the terminal IN2. 2 can be changed to the voltage of the node FG which is a series connection portion with 2, and at least a five-value storage state can be held. Further, by providing the reset transistor 4 at the node FG which is a serial connection portion and making the reset transistor 4 conductive, it is possible to erase the memory at high speed. Further, by making the reset transistor 4 non-conductive, it is possible to prevent the charge in the node FG, which is a series connection portion, from flowing out, so that the memory state can be held in a nonvolatile manner.

  In the present embodiment, it is possible to hold a five-value storage state, but the present invention is not limited to five values. As is clear from the principle of operation, by changing the magnitudes of the voltages Vpp1 and Vpp2 applied to the terminals IN1 and IN2, as long as the resolution of the detection transistor 3 allows, a storage state of five or more values can be maintained. Is possible.

  The ferroelectric nonvolatile memory device according to the present invention has nonvolatile and multivalued storage states and is useful as a semiconductor memory or the like. It can also be applied to applications such as reconfigurable LSI configuration memories.

1 is a circuit configuration diagram of a ferroelectric memory device according to a first embodiment of the present invention. The figure for demonstrating the principle of operation of the ferroelectric memory device in Embodiment 1 of this invention. Timing chart of voltage applied to each terminal for changing to the state “B1” Timing chart of voltage applied to each terminal for changing to state “B4” Timing chart of voltage applied to each terminal for changing to state “B2” Timing chart of voltage applied to each terminal for changing to state “B3” Timing chart of voltage applied to each terminal to set to reset state “O” The figure which shows the current-voltage characteristic of the transistor for a detection of the ferroelectric memory device in Embodiment 1 of this invention The figure which shows the circuit block diagram of the conventional ferroelectric memory device. The figure for demonstrating the principle of operation of the conventional ferroelectric memory device

Explanation of symbols

1 Ferroelectric Capacitor 1a Ferroelectric Capacitor Upper Electrode 1b Ferroelectric Capacitor Lower Electrode 2 Paraelectric Capacitor 2a Paraelectric Capacitor Upper Electrode 2b Paraelectric Capacitor Lower Electrode 3 Detection Transistor 4 Reset Transistor 101 Multi-History Ferroelectric Capacitor 102 Paraelectric Capacitor 103 Detection Transistor

Claims (9)

A ferroelectric capacitor and a paraelectric capacitor are connected in series,
A connection portion between the ferroelectric capacitor and the paraelectric capacitor is connected to a gate portion of a first field effect transistor;
The connection part is configured by being connected to a source part or a drain part of a second field effect transistor,
In the first step, the second field effect transistor is turned on,
In a second step following the first step, the second field effect transistor is turned off,
In the third step following the second step, a positive or negative voltage is applied to each of the first terminal on the ferroelectric capacitor side and the second terminal on the paraelectric capacitor side. Or ground,
A ferroelectric nonvolatile memory device, wherein a voltage of the first terminal and the second terminal is grounded in a fourth step following the third step. In the first step, a positive or negative voltage is applied to the first terminal, and a positive or negative voltage is applied to a third terminal that is not connected to the connection portion of the second field effect transistor. 2. The ferroelectric nonvolatile memory device according to claim 1, wherein a voltage is applied. 3. The ferroelectric nonvolatile memory device according to claim 2, wherein the first and second field effect transistors are N-type MOS transistors. 4. The ferroelectric nonvolatile memory device according to claim 3, wherein a threshold value of the first field effect transistor is negative. 4. The ferroelectric nonvolatile memory device according to claim 3, wherein the substrate portion of the second field effect transistor has a negative voltage. 6. The ferroelectric nonvolatile memory device according to claim 5, wherein a thickness of a gate oxide film of the second field effect transistor is larger than that of the first field effect transistor. In the first step,
While the second field effect transistor is non-conductive,
Applying a positive voltage to the first terminal and a negative voltage to the third terminal;
Alternatively, a negative voltage is applied to the first terminal, a positive voltage is applied to the third terminal,
3. The ferroelectric nonvolatile memory device according to claim 2, wherein a voltage applied to the ferroelectric capacitor is larger than a coercive voltage of the ferroelectric capacitor. In the third step,
Applying a positive voltage to the first terminal and a negative voltage to the second terminal;
Alternatively, a negative voltage is applied to the first terminal, a positive voltage is applied to the second terminal,
3. The ferroelectric nonvolatile memory device according to claim 2, wherein a voltage applied to the ferroelectric capacitor is larger than a coercive voltage of the ferroelectric capacitor. In the third step,
A positive or negative voltage is applied to the first terminal, and the second terminal is grounded;
Alternatively, the first terminal is in a state and a positive or negative voltage is applied to the second terminal,
3. The ferroelectric nonvolatile memory device according to claim 2, wherein a voltage applied to the ferroelectric capacitor is smaller than a coercive voltage of the ferroelectric capacitor.

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